Junctionless accumulation-mode devices on prominent architectures, and methods of making same

0001Disclosed embodiments relate to junctionless accumulation mode transistor devices and processes of making them.

BRIEF DESCRIPTION OF THE DRAWINGS

0002In order to understand the manner in which embodiments are obtained, a more particular description of various embodiments briefly described above will be rendered by reference to the appended drawings. These drawings depict embodiments that are not necessarily drawn to scale and are not to be considered to be limiting in scope. Some embodiments will be described and explained with additional specificity and detail through the use of the accompanying drawings in which:

0003<figref idref="DRAWINGS">FIG. 1</figref> is a cross-section and cut-away perspective elevation of a semiconductive device according to an example embodiment;

0004<figref idref="DRAWINGS">FIG. 1</figref><i>a </i>is a cross-section elevation of the semiconductive device depicted in <figref idref="DRAWINGS">FIG. 1</figref> during processing according to an example embodiment;

0005<figref idref="DRAWINGS">FIG. 1</figref><i>b </i>is a cross-section elevation of the semiconductive device depicted in <figref idref="DRAWINGS">FIG. 1</figref><i>a </i>after further processing according to an embodiment;

0006<figref idref="DRAWINGS">FIG. 1</figref><i>c </i>is a cross-section elevation of the semiconductive device depicted in <figref idref="DRAWINGS">FIG. 1</figref><i>b </i>after further processing according to an example embodiment;

0007<figref idref="DRAWINGS">FIG. 1</figref><i>d </i>is a cross-section elevation of the semiconductive device depicted in <figref idref="DRAWINGS">FIG. 1</figref><i>c </i>after further processing according to an embodiment;

0008<figref idref="DRAWINGS">FIG. 1</figref><i>e </i>is a cross-section elevation of the semiconductive device depicted in <figref idref="DRAWINGS">FIG. 1</figref><i>d </i>after further processing according to an embodiment;

0009<figref idref="DRAWINGS">FIG. 1</figref><i>f </i>is a cross-section elevation of the semiconductor device depicted in <figref idref="DRAWINGS">FIG. 1</figref><i>e </i>after further processing according to an embodiment;

0010<figref idref="DRAWINGS">FIG. 2</figref><i>a </i>is a cross-section elevation of a semiconductive device during processing according to an example embodiment;

0011<figref idref="DRAWINGS">FIG. 2</figref><i>b </i>is a cross-section elevation of the semiconductive device depicted in <figref idref="DRAWINGS">FIG. 2</figref><i>a </i>after further processing according to an example embodiment;

0012<figref idref="DRAWINGS">FIG. 3</figref><i>a </i>is a cross-section elevation of a semiconductive device during processing according to an example embodiment;

0013<figref idref="DRAWINGS">FIG. 3</figref><i>b </i>is a cross-section elevation of the semiconductor device depicted in <figref idref="DRAWINGS">FIG. 3</figref><i>a </i>after further processing according to an embodiment;

0014<figref idref="DRAWINGS">FIG. 4</figref> is a cross-section and cut-away perspective elevation of a semiconductive device according to an example embodiment;

0015<figref idref="DRAWINGS">FIG. 5</figref> is a cross-section and cut-away perspective elevation of a semiconductive device according to an example embodiment;

0016<figref idref="DRAWINGS">FIG. 6</figref> is a cross-section and cut-away perspective elevation of a semiconductive device according to an example embodiment;

0017<figref idref="DRAWINGS">FIG. 7</figref> is a cross-section and cut-away perspective elevation of a semiconductive device according to an example embodiment;

0018<figref idref="DRAWINGS">FIG. 8</figref> is a cross-section and cut-away perspective elevation of a semiconductive device according to an example embodiment;

0019<figref idref="DRAWINGS">FIG. 9</figref> is a process and method flow diagram according to an example embodiment; and

0020<figref idref="DRAWINGS">FIG. 10</figref> is a schematic of a computer system according to an embodiment.

DETAILED DESCRIPTION

0021Processes are disclosed where quantum wire and quantum fin transistors that operate in junctionless accumulation mode (JAM) are fabricated with a reverse-bias body that resists leakage or renders leakage negligible. The processes are described with wafer-level processing embodiments, but the processes may also be applied to die-level processing.

0022Reference will now be made to the drawings wherein like structures may be provided with like suffix reference designations. In order to show the structures of various embodiments more clearly, the drawings included herein are diagrammatic representations of integrated circuit structures. Thus, the actual appearance of the fabricated integrated circuit structures, for example in a photomicrograph, may appear different while still incorporating the claimed structures of the illustrated embodiments. Moreover, the drawings may only show the structures useful to understand the illustrated embodiments. Additional structures known in the art may not have been included to maintain the clarity of the drawings.

0023<figref idref="DRAWINGS">FIG. 1</figref> is a cross-section and cut-away perspective elevation of a semiconductive device <b>100</b> according to an example embodiment. The semiconductive device <b>100</b> includes a semiconductive substrate <b>110</b> which may be disposed above an SOI structure <b>108</b>. In an embodiment, the semiconductive substrate <b>110</b> is an epitixailly grown film. In an embodiment, the SOI structure <b>108</b> is a buried oxide layer. A prominence <b>112</b> includes a semiconductive first body <b>114</b>. The prominence <b>112</b> may also be referred to as a fin <b>112</b>. In an embodiment, the prominence <b>112</b> has an aspect ratio from greater than 1 (such as 1.1:1) to 16:1. In an embodiment, the aspect ratio is in a range from 6:1 to 10:1. Other aspect ratios may be useful depending up a given application. For example, the aspect ratios given are useful for fin prominences. Aspect ratios for quantum ribbons or quantum wires may each have different useful dimensions. In an embodiment, the source- and drain bodies <b>120</b> and <b>121</b>, respectively, are doped the same as the semiconductive first body <b>114</b>. In an embodiment, the source- and drain bodies <b>120</b> and <b>121</b>, respectively, are doped differently from that of the semiconductive first body <b>114</b>. For example, the source- and drain bodies <b>120</b> and <b>121</b>, respectively, are doped higher than that of the semiconductive first body <b>114</b>, but all are qualitatively doped the same.

0024In an example embodiment, the source- and drain bodies <b>120</b> and <b>121</b>, respectively, are doped the same as the semiconductive first body <b>114</b> such as they are each p-doped and function as a p-doped JAM semiconductor, and the reverse-bias second body <b>122</b> is n-doped. In an example embodiment, the source- and drain bodies <b>120</b> and <b>121</b>, respectively, are doped the same as the semiconductive first body <b>114</b> such as they are each n-doped and function as an n-doped JAM semiconductor, and the reverse-bias second body <b>122</b> is p-doped. The semiconductive first body <b>114</b> may also be delineated by a first side <b>126</b>, an edge <b>128</b>, and a second side (obscured from view) that is parallel planar to the first side <b>126</b>. It can now be seen that the semiconductive first body <b>114</b> extends (from left to right) from the source body <b>120</b>, through the gate electrode <b>116</b> and to the drain body <b>121</b>.

0025In an embodiment, the top substrate <b>110</b> is an epitaxially grown undoped semiconductor layer that has been formed upon the bottom substrate <b>108</b>, which is foundry-doped semiconductor. In a first example embodiment, the semiconductive first body <b>114</b> is n-doped silicon, the top substrate <b>110</b> is undoped silicon and the bottom substrate <b>108</b> is also n-doped silicon. In a second example embodiment, the semiconductive first body <b>114</b> is n-doped silicon, the top substrate <b>110</b> is undoped silicon and the bottom substrate <b>108</b> is p-doped silicon. In a third example embodiment, the semiconductive first body <b>114</b> is p-doped silicon, the top substrate <b>110</b> is undoped silicon, and the bottom substrate <b>108</b> is also p-doped silicon. In a fourth example embodiment, the semiconductive first body <b>114</b> is p-doped silicon, the top substrate <b>110</b> is undoped silicon, and the bottom substrate <b>108</b> is n-doped silicon.

0026In an embodiment, the top substrate <b>110</b> is a dielectric material and the band <b>122</b> is also a dielectric material. In this embodiment, the bottom substrate <b>108</b> is foundry-doped semiconductive material and may be referred to as the semiconductive second body <b>108</b> in contrast to the semiconductor first body <b>114</b> and in place of the structure <b>122</b> when it is reverse-biased instead of a dielectric material. Consequently, the dielectric <b>122</b> is part of the prominence <b>112</b>. In a fifth example embodiment, the semiconductive first body <b>114</b> is n-doped silicon, the band <b>122</b> is an oxide (that may be formed such as at a processing stage <b>322</b> depicted in <figref idref="DRAWINGS">FIG. 3</figref><i>a</i>), the top substrate is a dielectric such as a foundry-delivered dielectric layer <b>110</b>, and the bottom substrate <b>108</b> is foundry-delivered semiconductive material. In this fifth example embodiment, the bottom substrate <b>108</b> is also n-doped silicon. In a sixth example embodiment, all the conditions of the fifth example embodiment are the same with a difference that the bottom substrate <b>108</b> is p-doped silicon. In a seventh example embodiment, all the conditions of the sixth example embodiment are present with the difference that the semiconductive first body <b>114</b> is p-doped silicon.

0027The semiconductive first body <b>114</b> is a JAM device such as an n-channel junctionless source- channel- and drain device that operates in accumulation mode as a transistor. In an embodiment, the semiconductive first body <b>114</b> operates in quantum-well fashion due to the width in the X direction. In an embodiment, the semiconductive first body <b>114</b> has a width in a range from 1 nm to 100 nm. The semiconductive device <b>100</b> is displayed with at least one cut-away view. A cut-away view is seen with the Y-Z plane, which is cut into the semiconductive first body <b>114</b> such as to bifurcate it. A gate electrode <b>116</b> undulates over the semiconductive first body <b>114</b>. The gate electrode <b>116</b> is insulated from the semiconductive substrate <b>110</b> as well as the prominence <b>112</b> by a gate dielectric <b>118</b>. Shallow-trench isolations (STIs) <b>152</b> are also present and are at least partially depicted. The gate electrode <b>116</b> is also exposed by the cut-away plane Y-Z. The semiconductive first body <b>114</b> is coupled to a source body <b>120</b> and a drain body <b>121</b>. The source- and drain bodies <b>120</b> and <b>121</b>, respectively, may also be referred to as a contact pads to receive contacts for functioning of the semiconductive first body <b>114</b> in JAM operation. According to an embodiment, the prominence <b>112</b> also includes a reverse-bias band <b>122</b>. Formation of the prominence <b>112</b> includes an etching process. The semiconductive first body <b>114</b> may also be delineated by a first side <b>126</b>, an edge <b>128</b>, and a second side (obscured from view) that is parallel planar to the first side <b>126</b>. It can now be seen that the semiconductive first body <b>114</b> extends (from left to right) from the source body <b>120</b>, through the gate electrode <b>116</b> and to the drain body <b>121</b>. In an embodiment, doping levels of the S/D <b>120</b>/<b>121</b> are higher than that of the channel of the semiconductive first body <b>114</b>. In an example embodiment, the S/D areas <b>120</b>/<b>121</b> are doped at 1e21 and the semiconductive first body <b>114</b> is doped at 1e18 by contrast.

0028The entire structure of the semiconductive first body <b>114</b> is an n-channel that operates in junctionless accumulation mode according to an example embodiment. The reverse-bias band <b>122</b> is disposed opposite the edge <b>128</b> and runs the entire length of the semiconductive first body <b>114</b>.

0029In an embodiment, where the semiconductive first body <b>114</b> is an n-channel, the reverse-bias band <b>122</b> is a p-type semiconductive structure that extends beneath the entire length of the semiconductive first body <b>114</b>. In an embodiment, where the semiconductive first body <b>114</b> is an n-doped channel, the reverse-bias band <b>122</b> is differently doped, i.e. p-doped and the doping differential is sufficient to act as a reverse-bias junction.

0030As a consequence of the doping differential between the semiconductive first body <b>114</b> and the semiconductive second body <b>122</b>, the JAM semiconductive first body <b>114</b> may operate with minimal or even negligible leakage into the semiconductive substrate <b>110</b>.

0031Other prominences may be aligned adjacent or near the semiconductive first body and coupled to the gate diode <b>116</b> in order to make multiple gate devices.

0032It may now be appreciated that “reverse bias” may include an embodiment where the bias is different between the semiconductive first body <b>114</b> and the semiconductive second body <b>122</b>; it may therefore be called a differential bias so long as it is effective to restrict current leakage into the bulk semiconductive substrate <b>110</b>. For example, In an embodiment, the doping in the semiconductive first body <b>114</b> may be a first type such as n-type and the semiconductive second body <b>122</b> is opposite doped p-doped silicon or p-doped gallium arsenide, but the doping differential is significantly different such that leakage from the semiconductive first body <b>114</b> to the semiconductive second body is minimal or even negligible. In an example embodiment, the semiconductive first body <b>114</b> is n-doped to a range of 1e15 to 1e19 and the semiconductive second body <b>122</b> is p-doped to a level of 1e19.

0033As a consequence of the doping differential between the semiconductive first body <b>114</b> and the semiconductive second body <b>122</b>, the JAM semiconductive first body <b>114</b> may operate with minimal or even negligible leakage into the semiconductive substrate <b>110</b>.

0034In an example embodiment, the source- and drain bodies <b>120</b> and <b>121</b>, respectively, are doped the same as the semiconductive first body <b>114</b> such as they are each p-doped and function as a p-doped JAM semiconductor, and the reverse-bias second body <b>122</b> is n-doped. In an example embodiment, the source- and drain bodies <b>120</b> and <b>121</b>, respectively, are doped the same as the semiconductive first body <b>114</b> such as they are each n-doped and function as an n-doped JAM semiconductor, and the reverse-bias second body <b>122</b> is p-doped.

0035In an embodiment, band engineering techniques are used to achieve a low- or negligible leakage from the semiconductive first body <b>114</b> into the top substrate <b>110</b> when it is semiconductive. In this embodiment, the channel <b>114</b> is a material such as germanium (Ge) and the structure <b>122</b> is gallium arsenide (GaAs). The stack of GaAs <b>122</b> and Ge <b>114</b> will resist block subsurface leakage for a JAM device. In an embodiment, the GaAs band <b>122</b> is not doped and junction leakage issues are negligible or nonexistent. Band offsets between, e.g., a Ge channel <b>114</b> and a GaAs band <b>122</b> is useful for suppressing leakage for an nJAM. In an nJAM device, a lower Vcc is used because the band offset is small by comparison to a pJAM device. In an embodiment, band offsets between, e.g., a Ge channel <b>114</b> and a GaAs band <b>122</b> is useful for suppressing leakage for a pJAM device. Other materials may be used for band-engineering embodiments.

0036<figref idref="DRAWINGS">FIG. 1</figref><i>a </i>is a cross-section elevation of the semiconductive device depicted in <figref idref="DRAWINGS">FIG. 1</figref> during processing according to an example embodiment. The semiconductive device <b>101</b> includes the semiconductive substrate <b>110</b> that is depicted in <figref idref="DRAWINGS">FIG. 1</figref>. The semiconductive substrate <b>110</b> is depicted with a JAM channel body <b>114</b> that has been doped such as with phosphorus to make the channel body <b>114</b> an n-doped semiconductor. In an embodiment, an undoped semiconductive substrate <b>110</b> has been implanted to a depth of 500 Angstrom (Å) and to a doping concentration in a range from 1 e18 cm⁻³to 1 e20 cm⁻³. For example, arsenic (As) has been implanted before any patterning of the semiconductive substrate <b>110</b>. Thereafter, an anneal process has been carried out to heal dislocations and other crystal-lattice imperfections.

0037A hard mask <b>140</b> has been formed over the channel body <b>114</b> for further processing. In an embodiment, the hard mask <b>140</b> is an oxide and nitride such as a thermal oxide followed by nitridation to form an oxide- and oxynitride hard mask <b>140</b>. Other hard mask structures may be formed according to a given utility. After formation of the hard mask <b>140</b>, a polysilicon layer has been formed and patterned into a patterned polysilicon dummy layer <b>142</b>. The patterned polysilicon dummy layer <b>142</b> may also be referred to as a backbone <b>142</b>. The patterned polysilicon dummy layer <b>142</b> has further been blanketed with a spacer film and a spacer etch has been accomplished to leave spacers <b>144</b>. The spacers <b>144</b> along with the hard mask <b>140</b> are used as a composite hard mask for forming the prominences set forth in this disclosure according to an etching embodiment.

0038<figref idref="DRAWINGS">FIG. 1</figref><i>b </i>is a cross-section elevation of the semiconductive device depicted in <figref idref="DRAWINGS">FIG. 1</figref><i>a </i>after further processing according to an embodiment. The semiconductive device <b>102</b> has been processed after the spacer etch to form the spacers <b>144</b>. The polysilicon dummy layer <b>142</b> has been removed (backbone <b>142</b> removal) such as by a wet etch (or a dry etch or a combination of both) that is selective to leaving the hard mask <b>140</b> and the spacers <b>144</b>. In an embodiment, the spacers <b>144</b> as well as the hard mask <b>140</b> have a similar selectivity to remaining after a wet etch that is configured to remove the patterned dummy layer <b>142</b>.

0039It can be seen that three geometries remain after backbone <b>142</b> removal. A first geometry <b>146</b> is the gap <b>146</b> between two adjacent spacers that shared a common backbone. For example, critical-dimension (CD) patterning may be patterning on a 32 nanometer (nm), a 22 nm, or even a 15 nm geometry and the CD is reflected by the first geometry <b>146</b> from the patterned polysilicon dummy layer <b>142</b>. A second geometry <b>148</b> is the width of the spacer <b>144</b> after the spacer etch and the blanket etch. It may be appreciated that a spacer etch may leave the spacer <b>144</b> with a width <b>148</b> that is less than the CD of the process. A third geometry <b>150</b> is the gap <b>150</b> between two adjacent spacers that did not share a common backbone. It may be appreciated that this third geometry <b>150</b> may also be less than the CD of the process where two adjacent patterned polysilicon dummy layers <b>142</b> (e.g. see <figref idref="DRAWINGS">FIG. 1</figref><i>a</i>) may be more than the process CD, but their overall relative position may leave a gap <b>150</b> that is less than the CD <b>146</b> after the spacer etch.

0040<figref idref="DRAWINGS">FIG. 1</figref><i>c </i>is a cross-section elevation of the semiconductive device depicted in <figref idref="DRAWINGS">FIG. 1</figref><i>b </i>after further processing according to an example embodiment. The semiconductive device <b>103</b> has been processed with a directional etch through the hard mask <b>140</b> (and <b>144</b> depicted in <figref idref="DRAWINGS">FIG. 1</figref><i>b</i>) to form the prominence <b>112</b> that is seen at least dimensionally in <figref idref="DRAWINGS">FIG. 1</figref>. Etching has isolated the channel body <b>114</b> above the bulk of the semiconductive substrate <b>110</b>, but some leakage may occur into an unfinished region <b>123</b> that represents the area taken up by the reverse-bias band <b>122</b> and the undoped subprominence <b>124</b> depicted in <figref idref="DRAWINGS">FIG. 1</figref>.

0041<figref idref="DRAWINGS">FIG. 1</figref><i>d </i>is a cross-section elevation of the semiconductive device depicted in <figref idref="DRAWINGS">FIG. 1</figref><i>c </i>after further processing according to an embodiment. The semiconductive device <b>104</b> has been processed by filling shallow-trench isolation (STI) structures <b>152</b> between the several prominences <b>112</b>. The STI structures <b>152</b> (hereinafter STI <b>152</b>) act to isolate each prominence <b>112</b> for more useful accumulation-mode operation.

0042<figref idref="DRAWINGS">FIG. 1</figref><i>e </i>is a cross-section elevation of the semiconductive device depicted in <figref idref="DRAWINGS">FIG. 1</figref><i>d </i>after further processing according to an embodiment. The semiconductive device <b>105</b> has been processed by implanting the semiconductive second body <b>122</b> below the semiconductive first body <b>114</b>. As disclosed, the semiconductive second body <b>122</b> is reverse biased with respect to the semiconductive first body <b>114</b>. In an embodiment where the semiconductive first body <b>114</b> is a junctionless n- source- channel- and drain semiconductor that works in a JAM configuration, implantation (as indicated by the directional arrows <b>154</b>) of a p-source is carried out such as boron (B) doping. The implantation process causes the semiconductive second body <b>122</b> to form along the entire length (in the Y direction, see <figref idref="DRAWINGS">FIG. 1</figref>) opposite the edge <b>128</b> of the first semiconductive body <b>114</b>. As a result of the process of locating the semiconductive second body <b>122</b> below the semiconductive first body <b>114</b>, leakage during JAM transistor device operation is reduced or even made negligible.

0043<figref idref="DRAWINGS">FIG. 1</figref><i>f </i>is a cross-section elevation of the semiconductor device depicted in <figref idref="DRAWINGS">FIG. 1</figref><i>e </i>after further processing according to an embodiment. The semiconductor device <b>106</b> has been altered with an etch-back process that lowers the height of the STI <b>152</b> in order to expose at least some of the semiconductive first body <b>114</b> portion of the prominence <b>112</b>. Exposure of the semiconductive first body <b>114</b> enables further processing to lay down the gate dielectric <b>118</b> (see <figref idref="DRAWINGS">FIG. 1</figref>) followed by the gate electrode <b>116</b>.

0044Further processing includes formation of the source body <b>120</b> and the drain body <b>121</b> having a level of dopant that might differ from the channel.

0045<figref idref="DRAWINGS">FIG. 2</figref><i>a </i>is a cross-section elevation of a semiconductive device <b>200</b> during processing according to an example embodiment. Processing includes first implantation of the reverse-bias band <b>222</b> into the bulk form factor of the semiconductive substrate <b>210</b>. Thereafter, thermal processing may be done to heal imperfections and other crystal defects caused by the implanting process. By this embodiment, the thermal budget may be of lesser concern at the process stage because the prominence has not been formed.

0046<figref idref="DRAWINGS">FIG. 2</figref><i>b </i>is a cross-section elevation of the semiconductive device depicted in <figref idref="DRAWINGS">FIG. 2</figref><i>a </i>after further processing according to an example embodiment. The semiconductive device <b>210</b> has been processed by implanting a precursor to the semiconductive first body <b>214</b> into the section above the precursor to the semiconductive second body <b>222</b>. In an embodiment, thermal processing may be carried out to heal imperfections in the precursor to the semiconductive first body <b>214</b>. It may now be seen that thermal processing may be done once after formation of the precursor to the semiconductive first body <b>214</b> such that imperfections may be healed in the entire structure. It may now also be appreciated that the semiconductive first body <b>214</b> is pre-doped at the wafer-supplier stage of processing such that no additional doping may be needed to achieve the semiconductive first body <b>214</b> after implanting the reverse-bias band <b>222</b> as seen in <figref idref="DRAWINGS">FIG. 2</figref><i>a. </i>

0047Further processing may be carried out on the semiconductive device <b>210</b> according to the several embodiments set forth in this disclosure. For example, the precursor to the semiconductive first body <b>214</b> may be overlaid with a hard mask similar to the hard mask <b>140</b> depicted in <figref idref="DRAWINGS">FIG. 1</figref><i>a</i>, followed by a polysilicon dummy layer such as the patterned polysilicon dummy layer <b>142</b> also depicted in <figref idref="DRAWINGS">FIG. 1</figref><i>a</i>. It may now be understood that further processing may be done to form the prominence according to any prominence architecture embodiments set forth in this disclosure.

0048<figref idref="DRAWINGS">FIG. 3</figref><i>a </i>is a cross-section elevation of a semiconductive device <b>300</b> during processing according to an example embodiment. An epitaxial layer <b>322</b> is grown on a semiconductive substrate <b>310</b>. The epitaxial layer is a precursor of a reverse-bias film <b>322</b>. Thereafter, thermal processing may be carried out to heal crystal imperfections. In an embodiment, the layer <b>322</b> is an implanted layer that forms a precursor of the reverse-bias film <b>322</b>.

0049<figref idref="DRAWINGS">FIG. 3</figref><i>b </i>is a cross-section elevation of the semiconductor device depicted in <figref idref="DRAWINGS">FIG. 3</figref><i>a </i>after further processing according to an embodiment. The semiconductor device <b>301</b> has been processed with a second epitaxial film <b>314</b>, which is a precursor to a semiconductive first body <b>314</b> that will be located in a prominence. It may now be seen that other films may be grown epitaxially such as the architecture depicted in <figref idref="DRAWINGS">FIGS. 1</figref>, <b>4</b>, and <b>5</b> such that, for example, an n-doped and epitaxially grown InSb film (<figref idref="DRAWINGS">FIG. 4</figref>) forms the semiconductive first body <b>314</b>.

0050It may now be seen that thermal processing may be done only once after formation of both the precursor to the semiconductive second body <b>322</b> and the precursor to the semiconductive first body <b>314</b> such that imperfections may be healed in the entire structure.

0051Further processing may be carried out on the semiconductive device <b>310</b> according to the several embodiments set forth in this disclosure. For example, the precursor to the semiconductive first body <b>314</b> may be overlaid with a hard mask similar to the hard mask <b>140</b> depicted in <figref idref="DRAWINGS">FIG. 1</figref><i>a</i>, followed by a polysilicon dummy layer such as the patterned polysilicon dummy layer <b>142</b> also depicted in <figref idref="DRAWINGS">FIG. 1</figref><i>a</i>. It may now be understood that further processing may be done to form the prominence according to any prominence architecture embodiments set forth in this disclosure.

0052<figref idref="DRAWINGS">FIG. 4</figref> is a cross-section and cut-away perspective elevation of a semiconductive device <b>400</b> according to an example embodiment. The semiconductive substrate <b>410</b> may be undoped silicon and the semiconductive first body <b>414</b> is n-doped InSb.

0053The semiconductive device <b>400</b> includes a bulk semiconductive substrate <b>410</b> which may be disposed above an insulative structure <b>408</b> such as an SOI structure <b>408</b>. In an embodiment, the semiconductive substrate <b>410</b> has an epitixailly grown gallium arsenide (GaAs) <b>411</b> disposed on it that resolves dislocations, lattice mismatches and other imperfections. An aluminum indium antiminide (Al_yIn_1-ySb) film <b>413</b> surmounts the GaSb film <b>411</b> as well as an aluminum indium antiminide (Al_xIn_xSb) film <b>422</b> surmounts the Al_yIn_1-ySb film <b>413</b>. The films <b>411</b> and <b>413</b> have different chemistries from each other and they act as a buffer for the JAM channel <b>414</b>. Finally, the semiconductive first body <b>414</b> is an indium antiminide (InSb) film <b>414</b> that has been n-doped. In an embodiment, any or all of the previous films <b>422</b>, <b>413</b>, and <b>411</b> is reverse-bias doped with respect to the semiconductive first body <b>414</b> such that current leakage is minimized or made negligible. In an embodiment the AlSb film <b>422</b> is the semiconductive second body <b>422</b> and the InSb film <b>414</b> is the semiconductive first body <b>414</b>.

0054The prominence <b>412</b> as illustrated includes the semiconductive first body <b>414</b>. The semiconductive first body <b>414</b> is a JAM device such as an n-channel junctionless source- channel- and drain device that operates in accumulation mode as a transistor. A gate electrode <b>416</b> undulates over the semiconductive first body <b>414</b>. The gate electrode <b>416</b> is insulated from the semiconductive substrate <b>410</b> as well as the prominence <b>412</b> by a gate dielectric <b>418</b>. The semiconductive first body is coupled to a source body <b>420</b> and a drain body <b>421</b>. In an embodiment, the prominence <b>412</b> includes the reverse-bias band <b>422</b> or any of the other films <b>413</b> and <b>411</b>. In comparison to the semiconductive devices <b>100</b>, <b>200</b>, and <b>300</b> depicted in <figref idref="DRAWINGS">FIGS. 1</figref><b>2</b>, and <b>3</b>, the reverse-bias band <b>322</b> is supported by films <b>411</b> and <b>413</b> to resolve dislocations and to buffer the semiconductive first body <b>414</b> as well as the semiconductive second body <b>422</b>. The semiconductive first body <b>414</b> may also be delineated by a first side <b>426</b>, the edge <b>428</b>, and a second side (obscured from view). It can now be seen that the semiconductive first body <b>414</b> extends (from left to right) from the source body <b>420</b>, through the gate electrode <b>416</b> and to the drain body <b>421</b>. The entire structure of the semiconductive first body <b>414</b> is an n-channel that operates in junctionless accumulation mode according to an example embodiment. The reverse-bias band <b>422</b> is disposed opposite the edge <b>428</b> and runs the entire length of the semiconductive first body <b>414</b>.

0055In an embodiment, where the semiconductive first body <b>414</b> is an n-channel, the reverse-bias band <b>422</b> is a p-type semiconductive structure that extends beneath the entire length of the semiconductive first body <b>414</b>. In an embodiment, where the semiconductive first body <b>414</b> is an n- or p-doped channel, the reverse-bias band <b>422</b> is an undoped semiconductive structure where the doping differential is sufficient to act as a reverse-bias junction.

0056As a consequence of the doping differential between the semiconductive first body <b>414</b> and the semiconductive second body <b>422</b>, the JAM semiconductive first body <b>414</b> may operate with minimal or even negligible leakage into the semiconductive substrate <b>410</b>.

0057<figref idref="DRAWINGS">FIG. 5</figref> is a cross-section and cut-away perspective elevation of a semiconductive device <b>500</b> according to an example embodiment. The semiconductive device <b>500</b> includes a top substrate <b>510</b> that may be disposed upon a bottom substrate <b>508</b>. A prominence <b>512</b> includes a semiconductive first body <b>514</b> (indicated by a height section <b>514</b> of the prominence <b>512</b>). The prominence <b>512</b> also includes a reverse-bias band <b>522</b> that is set within a dielectric <b>509</b>. The semiconductive first body <b>514</b> is a JAM device such as an n-channel junctionless source- channel- and drain device that operates in accumulation mode as a transistor. In an embodiment, the semiconductive first body <b>514</b> operates in quantum-well fashion due to the width in the X direction. In an embodiment, the semiconductive first body <b>514</b> has a width in a range from 1 nm to 100 nm.

0058A gate electrode <b>516</b> is insulated from the substrate <b>510</b> by an STI <b>552</b>. The semiconductive first body <b>514</b> is coupled to a source body <b>520</b> and a drain body <b>521</b>. The source- and drain bodies <b>520</b> and <b>521</b>, respectively, may also be referred to as contact pads to receive a contact for functioning of the semiconductive first body <b>514</b> in JAM operation.

0059The semiconductive first body <b>514</b> has a first length <b>514</b>L and the source- and drain bodies <b>520</b> and <b>521</b> also have source- and drain body lengths <b>520</b>L and <b>521</b>L respectively. The gate electrode <b>516</b> also has a third length <b>516</b>L. The reverse bias band <b>522</b> also has a second length <b>522</b>L.

0060In an embodiment, the source- and drain bodies <b>510</b> and <b>521</b>, respectively, are formed of semiconductive material that is qualitatively doped the same as the semiconductive first body <b>114</b>, but they are formed at a different process stage as that of the semiconductive first body <b>114</b>.

0061In an embodiment, the first length <b>514</b>L is the same as the third length <b>516</b>L such that essentially the entire channel <b>514</b> is below (in the Z direction) the gate electrode <b>516</b>. In an embodiment, the first length <b>514</b>L is greater than the third length <b>516</b>L as illustrated in <figref idref="DRAWINGS">FIG. 5</figref>.

0062As illustrated, the reverse bias band length <b>522</b>L is the same as that of the first length <b>514</b>L. In an embodiment, however, the second length <b>522</b>L is greater than that of the first length <b>514</b>L such as where the entire channel <b>514</b> is below the gate electrode (the first length <b>514</b>L is essentially the same as that of the third length <b>516</b>L), but the second length <b>522</b>L is the length illustrated.

0063It may now be appreciated that band engineering embodiments disclosed with respect to <figref idref="DRAWINGS">FIG. 1</figref> may also be applied to channel- reverse bias band-, and gate length embodiments disclosed with respect to <figref idref="DRAWINGS">FIGS. 1</figref>, <b>4</b>, and <b>5</b>. In an example embodiment, the structure <b>522</b> is GaAs and has the second length <b>522</b>L as illustrated, and the channel <b>514</b> is Ge and has a length <b>514</b>L that is the same as that of the gate electrode length <b>516</b>L.

0064<figref idref="DRAWINGS">FIG. 6</figref> is a cross-section and cut-away perspective elevation of a semiconductive device <b>600</b> according to an example embodiment. The semiconductive device <b>600</b> includes a bulk semiconductive substrate <b>610</b> which may be disposed above an insulative structure <b>608</b> such as an SOI structure <b>608</b>. In an embodiment, the semiconductive substrate <b>610</b> is an epitaxially grown film. A prominence <b>612</b> includes a semiconductive first body <b>614</b> (indicated by a height section <b>614</b> of the prominence <b>612</b>). The semiconductive first body <b>614</b> is a JAM device such as an n-channel junctionless source- channel- and drain device that operates in accumulation mode as a transistor. The semiconductive device <b>600</b> is displayed with at least two cut-away views. A cut-away view is seen with the X₁Z₁plane, which is cut into a gate electrode <b>616</b> that undulates over the semiconductive first body <b>614</b>. The gate electrode <b>616</b> is insulated from the semiconductive substrate <b>610</b> by and STI <b>652</b>. The prominence <b>612</b> is insulated by a gate dielectric <b>618</b>. The gate electrode <b>616</b> is also exposed by a cut-away plane X₂Y₂. The semiconductive first body <b>614</b> is coupled to a source body <b>620</b> and a drain body (not illustrated). The source body <b>620</b> may also be referred to as a contact pad <b>620</b> to receive a contact for functioning of the semiconductive first body <b>614</b> in JAM operation. The semiconductive first body <b>614</b> is cut by a plane X₂Z₂before the drain body is reached.

0065The prominence <b>612</b> also includes a reverse-bias band <b>622</b>. The form factor of the semiconductive substrate <b>610</b> abuts the reverse-bias band <b>622</b>. The semiconductive first body <b>614</b> may also be delineated by a first side <b>626</b>, the edge <b>628</b>, and a second side (obscured from view). It can now be seen that the semiconductive first body <b>614</b> extends (from left to right) from the source body <b>620</b>, through the gate electrode <b>616</b> and toward the drain body. Another structure depicted in <figref idref="DRAWINGS">FIG. 6</figref> is a gate spacer <b>630</b> that has also been depicted in cut away perspective at the cut-away planes X₁Y₁and Y₂Z₂.

0066The entire structure of the semiconductive first body <b>614</b> is an n-channel that operates in junctionless accumulation mode according to an example embodiment. In an embodiment, the entire structure of the semiconductive first body <b>614</b> is a p-channel that operates in junctionless accumulation mode. The reverse-bias band <b>622</b> is disposed opposite the edge <b>628</b> and runs the entire length of the semiconductive first body <b>614</b>.

0067In an embodiment, where the semiconductive first body <b>614</b> is an n-channel, the reverse-bias band <b>622</b> is a p-type semiconductive structure that extends beneath the entire length of the semiconductive first body <b>614</b>. In an embodiment, where the semiconductive first body <b>614</b> is a p-channel, the reverse-bias band <b>622</b> is an n-type semiconductive structure that extends beneath the entire length of the semiconductive first body <b>614</b>. As a consequence of the doping differential between the semiconductive first body <b>614</b> and the semiconductive second body <b>622</b>, the JAM semiconductive first body <b>614</b> may operate with minimal or even negligible leakage into the semiconductive substrate <b>610</b>.

0068Other prominences <b>632</b>, <b>634</b>, and <b>636</b> are also illustrated but in not as much detail as the prominence <b>612</b> containing the semiconductive first body <b>614</b>. It can be seen that the semiconductive second body <b>622</b> has a height (in the Z direction) that begins upon the semiconductive substrate <b>610</b> and extends above the STI <b>652</b>.

0069<figref idref="DRAWINGS">FIG. 7</figref> is a cross-section and cut-away perspective elevation of a semiconductive device <b>700</b> according to an example embodiment. The semiconductive device <b>700</b> includes a bulk semiconductive substrate <b>710</b> which may be disposed above an insulative structure <b>708</b> such as an SOI structure <b>708</b>. A prominence <b>712</b> includes a semiconductive first body <b>714</b> (indicated by a height section <b>714</b> of the prominence <b>712</b>). The semiconductive first body <b>714</b> is a JAM device such as an n-channel junctionless source- channel- and drain device that operates in accumulation mode as a transistor according to an example embodiment. The semiconductive device <b>700</b> is displayed with at least two cut-away views. A cut-away view is seen with the X₁Z₁plane, which is cut into a gate electrode <b>716</b> that undulates over the semiconductive first body <b>714</b>. The gate electrode <b>716</b> is insulated from the semiconductive substrate <b>710</b> by an STI <b>752</b>. The prominence <b>712</b> is insulated by a gate dielectric <b>718</b>. The gate electrode <b>716</b> is also exposed by a cut-away plane X₂Y₂. The semiconductive first body is coupled to a source body <b>720</b> and a drain body (not illustrated). The semiconductive first body <b>714</b> is cut by a plane X₂Z₂before the drain body is reached.

0070The prominence <b>712</b> also includes a reverse-bias band <b>722</b>. Etching the prominence <b>712</b> to a height that stops at a level in the middle of the reverse-bias band <b>722</b> is done such that the reverse-bias band <b>722</b> completely overlies the semiconductive substrate <b>710</b>. The semiconductive first body <b>714</b> may also be delineated by a first side <b>726</b>, the edge <b>728</b>, and a second side (obscured from view). It can now be seen that the semiconductive first body <b>714</b> extends (from left to right) from the source body <b>720</b>, through the gate electrode <b>716</b> and toward the drain body. Another structure depicted in <figref idref="DRAWINGS">FIG. 7</figref> is a gate spacer <b>728</b> that has also been depicted in cut away perspective at the cut-away planes X₁Y₁and Y₂Z₂.

0071The entire structure of the semiconductive first body <b>714</b> is an n-channel that operates in junctionless accumulation mode according to an example embodiment. In an embodiment, the entire structure of the semiconductive first body <b>714</b> is a p-channel that operates in junctionless accumulation mode. The reverse-bias band <b>722</b> is disposed opposite the edge <b>728</b> and runs the entire length of the semiconductive first body <b>714</b>.

0072In an embodiment, where the semiconductive first body <b>714</b> is an n-channel, the reverse-bias band <b>722</b> is a p-type semiconductive structure that extends beneath the entire length of the semiconductive first body <b>714</b>. In an embodiment, where the semiconductive first body <b>714</b> is a p-channel, the reverse-bias band <b>622</b> is an n-type semiconductive structure that extends beneath the entire length of the semiconductive first body <b>714</b>. As a consequence of the doping differential between the semiconductive first body <b>714</b> and the semiconductive second body <b>722</b>, the JAM semiconductive first body <b>714</b> may operate with minimal or even negligible leakage into the semiconductive substrate <b>710</b>.

0073Other prominences <b>732</b>, <b>734</b>, and <b>736</b> are also illustrated but in not as much detail as the prominence <b>712</b> containing the semiconductive first body <b>714</b>.

0074<figref idref="DRAWINGS">FIG. 8</figref> is a cross-section and cut-away perspective elevation of a semiconductive device <b>800</b> according to an example embodiment. The semiconductive device <b>800</b> includes a bulk semiconductive substrate <b>810</b> which may be disposed above an insulative structure <b>808</b> such as an SOI structure <b>808</b>. In an embodiment, the semiconductive substrate <b>810</b> has an epitixailly grown gallium antiminide (GaSb) film <b>811</b> disposed on it that resolves dislocations, lattice mismatches and other imperfections. An aluminum arsenide (AlAs) film <b>813</b> surmounts the GaSb film <b>811</b>. An aluminum antiminide (AlSb) film <b>822</b> surmounts the AlAs film <b>813</b>. Finally, the semiconductive first body <b>814</b> is an indium antiminide (InSb) film <b>814</b> that has been n-doped. In an embodiment, any or all of the previous films <b>822</b>, <b>813</b>, and <b>811</b> is reverse-bias doped with respect to the semiconductive first body <b>814</b> such that current leakage is minimized or made negligible. In an embodiment the AlSb film <b>822</b> is the semiconductive second body <b>822</b> and the InSb film <b>814</b> is the semiconductive first body <b>814</b>.

0075The prominence <b>812</b> as illustrated includes the semiconductive first body <b>814</b>. The semiconductive first body <b>814</b> is a JAM device such as an n-channel junctionless source- channel- and drain device that operates in accumulation mode as a transistor. The semiconductive device <b>800</b> is displayed with at least two cut-away views. A cut-away view is seen with the X₁Z₁plane, which is cut into a gate electrode <b>816</b> that undulates over the semiconductive first body <b>814</b>. The gate electrode <b>816</b> is insulated from the semiconductive substrate <b>810</b> by an STI <b>852</b>. The prominence <b>812</b> is insulated by a gate dielectric <b>818</b>. The gate electrode <b>816</b> is also exposed by a cut-away plane X₂Y₂. The semiconductive first body is coupled to a source body <b>820</b> and a drain body (not illustrated). The semiconductive first body <b>814</b> is cut by a plane X₂Z₂before the drain body is reached.

0076The prominence <b>812</b> also includes a reverse-bias band <b>822</b> or any of the other films <b>813</b> and <b>811</b>. In comparison to the semiconductive device <b>100</b><figref idref="DRAWINGS">FIG. 1</figref>, the reverse-bias band <b>822</b> is supported by films <b>811</b> and <b>813</b> to resolve dislocations and to buffer the semiconductive first body <b>814</b> as well as the semiconductive second body <b>822</b>. The semiconductive first body <b>814</b> may also be delineated by a first side <b>826</b>, the edge <b>828</b>, and a second side (obscured from view). It can now be seen that the semiconductive first body <b>814</b> extends (from left to right) from the source body <b>820</b>, through the gate electrode <b>816</b> and toward the drain body. Another structure depicted in <figref idref="DRAWINGS">FIG. 8</figref> is a gate spacer <b>830</b> that has also been depicted in cut away perspective at the cut-away planes X₁Y₁and Y₂Z₂.

0077The entire structure of the semiconductive first body <b>814</b> is an n-channel that operates in junctionless accumulation mode according to an example embodiment. The reverse-bias band <b>822</b> is disposed opposite the edge <b>828</b> and runs the entire length of the semiconductive first body <b>814</b>.

0078In an embodiment, where the semiconductive first body <b>814</b> is an n-channel, the reverse-bias band <b>822</b> is a p-type semiconductive structure that extends beneath the entire length of the semiconductive first body <b>814</b>. In an embodiment, where the semiconductive first body <b>814</b> is an n- or p-doped channel, the reverse-bias band <b>822</b> is an undoped semiconductive structure where the doping differential is sufficient to act as a reverse-bias junction.

0079As a consequence of the doping differential between the semiconductive first body <b>814</b> and the semiconductive second body <b>822</b>, the JAM semiconductive first body <b>814</b> may operate with minimal or even negligible leakage into the semiconductive substrate <b>810</b>.

0080Other prominences <b>832</b>, <b>834</b>, and <b>836</b> are also illustrated but in not as much detail as the prominence <b>812</b> containing the semiconductive first body <b>814</b>.

0081<figref idref="DRAWINGS">FIG. 9</figref> is a process and method flow diagram <b>900</b> according to several embodiments.

0082At <b>910</b>, the process includes forming a reverse-biased semiconductive second body adjacent a prominent junctionless accumulation-mode semiconductive first body. In an non-limiting example embodiment, the semiconductive second body <b>122</b> is formed adjacent and abutting the semiconductive first body <b>114</b> by implanting a reverse-bias dopant through the semiconductive first body <b>114</b> as seen in <figref idref="DRAWINGS">FIG. 1</figref><i>e</i>. In a non-limiting example embodiment, the semiconductive second body <b>622</b> is formed adjacent and abutting the semiconductive first body <b>614</b> by implanting a reverse-bias dopant through the semiconductive first body <b>614</b> as seen in <figref idref="DRAWINGS">FIG. 6</figref><i>a</i>. In a non-limiting example embodiment, the semiconductive second body <b>622</b> is formed adjacent and abutting the semiconductive first body <b>614</b> by implanting a reverse-bias dopant through the semiconductive first body <b>614</b> as seen in <figref idref="DRAWINGS">FIG. 6</figref><i>b</i>. In a non-limiting example embodiment, the semiconductive second body <b>722</b> is formed adjacent and abutting the semiconductive first body <b>714</b> by growing two epitaxial layers <b>722</b> and <b>714</b>, respectively, as seen in <figref idref="DRAWINGS">FIGS. 7</figref><i>a </i>and <b>7</b><i>b. </i>

0083In a non-limiting example embodiment, the semiconductive second body is any one of films <b>411</b>, <b>413</b>, and <b>422</b> and is formed adjacent the semiconductive first body <b>414</b> as seen in <figref idref="DRAWINGS">FIG. 5</figref>.

0084At <b>906</b>, the process may begin by forming the prominence. In a non-limiting example embodiment, the prominence <b>112</b> is formed by etching through the hard mask <b>144</b> and the hard mask <b>140</b> to form the prominence <b>112</b> as seen in <figref idref="DRAWINGS">FIG. 1</figref><i>c. </i>

0085At <b>908</b>, the process may continue by isolating the prominence. In a non-limiting example embodiment, the STI <b>152</b> is first filled abutting the prominence <b>112</b> and then height-lowered by etching back to expose the semiconductive first body <b>114</b> and achieve a lowered STI <b>152</b> as seen in respective <figref idref="DRAWINGS">FIGS. 1</figref><i>d </i>and <b>1</b><i>f. </i>

0086At <b>920</b>, the process includes forming a gate dielectric on the prominence. In a non-limiting example embodiment, the gate dielectric <b>118</b> is patterned on the prominence <b>112</b> as seen in <figref idref="DRAWINGS">FIG. 1</figref>.

0087At <b>930</b>, the process includes forming a gate electrode on the prominence at the gate dielectric. In a non-limiting example embodiment, the gate electrode <b>116</b> is patterned to undulate over the prominences <b>112</b>, <b>132</b>, <b>134</b>, and <b>136</b>. Details of the gate electrode <b>116</b> below the gate dielectric <b>118</b> and on the prominences is shown only for the prominence <b>112</b>, but the gate electrode <b>116</b> extends over the prominences <b>132</b>, <b>134</b>, and <b>136</b> in a similar manner.

0088At <b>940</b>, a method embodiment includes installing the JAM device into a computer system.

0089<figref idref="DRAWINGS">FIG. 10</figref> is a schematic of a computer system <b>1000</b> according to an embodiment. The computer system <b>1000</b> (also referred to as the electronic system <b>1000</b>) as depicted can embody a JAM device according to any of the several disclosed embodiments and their equivalents as set forth in this disclosure. The computer system <b>1000</b> may be a mobile device such as a netbook computer. The computer system <b>1000</b> may be a mobile device such as a wireless smart phone

0090In an embodiment, the electronic system <b>1000</b> is a computer system that includes a system bus <b>1020</b> to electrically couple the various components of the electronic system <b>1000</b>. The system bus <b>1020</b> is a single bus or any combination of busses according to various embodiments. The electronic system <b>1000</b> includes a voltage source <b>1030</b> that provides power to the integrated circuit <b>1010</b>. In some embodiments, the voltage source <b>1030</b> supplies current to the integrated circuit <b>1010</b> through the system bus <b>1020</b>.

0091The integrated circuit <b>1010</b> is electrically coupled to the system bus <b>1020</b> and includes any circuit, or combination of circuits according to an embodiment. In an embodiment, the integrated circuit <b>1010</b> includes a processor <b>1012</b> that can be of any type. As used herein, the processor <b>1012</b> may mean any type of circuit such as, but not limited to, a microprocessor, a microcontroller, a graphics processor, a digital signal processor, or another processor. In an embodiment, the processor <b>1012</b> is the embedded die disclosed herein. In an embodiment, SRAM embodiments are found in memory caches of the processor. Other types of circuits that can be included in the integrated circuit <b>1010</b> are a custom circuit or an application-specific integrated circuit (ASIC), such as a communications circuit <b>1014</b> for use in wireless devices such as cellular telephones, smart phones, pagers, portable computers, two-way radios, and similar electronic systems. In an embodiment, the processor <b>1010</b> includes on-die memory <b>1016</b> such as static random-access memory (SRAM). In an embodiment, the processor <b>1010</b> includes embedded on-die memory <b>1016</b> such as embedded dynamic random-access memory (eDRAM). In an embodiment, the processor <b>1010</b> is a processor that is installed on a server blade.

0092In an embodiment, the integrated circuit <b>1010</b> is complemented with a subsequent integrated circuit <b>1011</b> such as an embedded subsequent die embodiment. The dual integrated circuit <b>1011</b> includes a dual processor <b>1013</b> and a dual communications circuit <b>1015</b> and dual on-die memory <b>1017</b> such as SRAM. In an embodiment, the dual integrated circuit <b>1010</b> includes embedded on-die memory <b>1017</b> such as eDRAM.

0093In an embodiment, the electronic system <b>1000</b> also includes an external memory <b>1040</b> that in turn may include one or more memory elements suitable to the particular application, such as a main memory <b>1042</b> in the form of RAM, one or more hard drives <b>1044</b>, and/or one or more drives that handle removable media <b>1046</b>, such as diskettes, compact disks (CDs), digital variable disks (DVDs), flash memory drives, and other removable media known in the art. The external memory <b>1040</b> may also be embedded memory <b>1048</b> such as a JAM device according to an embodiment.

0094In an embodiment, the electronic system <b>1000</b> also includes a display device <b>1090</b>, and an audio output <b>1060</b>. In an embodiment, the electronic system <b>1000</b> includes an input device such as a controller <b>1070</b> that may be a keyboard, mouse, trackball, game controller, microphone, voice-recognition device, or any other input device that inputs information into the electronic system <b>1000</b>. In an embodiment, an input device <b>1070</b> is a camera. In an embodiment, an input device <b>1070</b> is a digital sound recorder. In an embodiment, an input device <b>1070</b> is a camera and a digital sound recorder.

0095As shown herein, the integrated circuit <b>1010</b> can be implemented in a number of different embodiments, including a JAM device according to any of the several disclosed embodiments and their equivalents, an electronic system, a computer system, one or more methods of fabricating an integrated circuit, and one or more methods of fabricating an electronic assembly that a JAM device according to any of the several disclosed embodiments as set forth herein in the various embodiments and their art-recognized equivalents. The elements, materials, geometries, dimensions, and sequence of operations can all be varied to suit particular I/O coupling requirements including array contact count, array contact configuration a JAM device according to any of the several disclosed JAM device embodiments and their equivalents.

0096Although a die may refer to a processor chip, an RF chip or a memory chip may be mentioned in the same sentence, but it should not be construed that they are equivalent structures. Reference throughout this disclosure to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. The appearance of the phrases “in one embodiment” or “in an embodiment” in various places throughout this disclosure are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

0097Terms such as “upper” and “lower” “above” and “below” may be understood by reference to the illustrated X-Z coordinates, and terms such as “adjacent” may be understood by reference to X-Y coordinates or to non-Z coordinates.

0098The Abstract is provided to comply with 37 C.F.R. §1.72(b) requiring an abstract that will allow the reader to quickly ascertain the nature and gist of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

0099In the foregoing Detailed Description, various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments of the invention require more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate preferred embodiment.

0100It will be readily understood to those skilled in the art that various other changes in the details, material, and arrangements of the parts and method stages which have been described and illustrated in order to explain the nature of this invention may be made without departing from the principles and scope of the invention as expressed in the subjoined claims.