Multi-layer tsv insulation and methods of fabricating the same

CROSS-REFERENCE TO RELATED APPLICATIONS

0001This U.S. non-provisional patent application claims priority under 35 U.S.C. §119 of Korean Patent Application No. 10-2010-0093420, filed on Sep. 27, 2010, the entire contents of which are hereby incorporated herein by reference.

BACKGROUND

0002The present disclosure relates to a semiconductor device and a method of fabricating the same, and more particularly, to a semiconductor device having a Through Silicon Via (TSV) and a method of fabricating the same.

0003The current trend of electronics industry is to manufacture lightweight, small-sized, high-speed, multi-functioned, and high-performance products at a low cost. To achieve this object, a multi-chip stacked package technology or a system in package technology may be used. The multi-chip stacked package technology or the system in a package technology can use a TSV.

0004According to the multi-chip stacked package technology or the system in a package technology, functions of a plurality of unit semiconductor devices may be performed in a single semiconductor package. The multi-chip stacked package or the system in a package may be a little bit thicker than a typical single chip package. However, since their planar sizes are similar to that of the single chip package, they may be used for small-sized or mobile high-performance products such as cell phones, laptop computers, memory cards, and portable camcorders.

SUMMARY

0005The present disclosure provides a semiconductor device with improved electric characteristics by including a through silicon via (TSV) structure having a multi-layered insulation layer.

0006The present disclosure provides a method of fabricating a semiconductor device with improved electric characteristics by including a TSV structure having a multi-layered insulation layer.

0007The present disclosure also provides a semiconductor package including the semiconductor device.

0008Embodiments of the inventive concept provide semiconductor devices including a substrate and a stacked insulation layer on a sidewall of an opening which penetrates the substrate, wherein the stacked insulation layer includes at least one first insulation layer and at least one second insulation layer. The second insulation layer may have a dielectric constant lower than that of the first insulation layer, or vice versa, wherein the lower dielectric constant insulation layer may be a polymer and the other insulation layer may be a silicon based dielectric, with one insulation layer being between the sidewall of the opening and the other insulation layer.

0009In other embodiments of the inventive concept, methods for fabricating a semiconductor device include preparing a substrate, forming a via hole by selectively etching the substrate, forming a first insulation layer containing a polymer to cover a sidewall of the via hole, and forming a second insulation layer containing silicon on the first insulation layer, wherein the first insulation layer has a dielectric constant lower than that of the second insulation layer.

0010In still other embodiments of the inventive concept, methods for fabricating a semiconductor device include preparing a substrate, forming a via hole exposing a silicon oxide layer at a bottom surface of the via hole by selectively etching the substrate, forming a first insulation layer containing polymer to cover a sidewall of the via hole by etching the silicon oxide layer using CF-based gas, and forming a second insulation layer containing silicon on the first insulation layer to substantially cover the first insulation layer.

0011In still other embodiments of the inventive concept, methods for fabricating a semiconductor device include preparing a substrate, forming a via hole by selectively etching the substrate, forming a first insulation layer containing silicon along a profile of the via hole, and forming a second insulation layer containing a polymer to cover the first insulation layer by etching the first insulation layer using CF-based gas.

0012In still other embodiments of the inventive concept, semiconductor packages include a stacked first semiconductor device and second semiconductor device, wherein each of the first and second semiconductor devices includes a substrate, a stacked insulation layer on a sidewall of an opening which penetrates the substrate, and a metal layer which substantially fills the opening provided in the stacked insulation layer. The stacked insulation layer may include at least one first insulation layer and at least one second insulation layer whose dielectric constant is lower than that of the first insulation layer, wherein the second insulation layer may be a polymer and one of the first and second insulation layers is between the sidewall of the opening and the other insulation layer, wherein a first surface of the metal layer of the first semiconductor device faces a second surface of the metal layer of the second semiconductor device.

BRIEF DESCRIPTION OF THE DRAWINGS

0013The accompanying drawings are included to provide a further understanding of the inventive concept, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the inventive concept and, together with the description, serve to explain principles of the inventive concept. In the drawings:

0014<figref idref="DRAWINGS">FIG. 1</figref> is a cross-sectional view illustrating a semiconductor device according to an embodiment of the inventive concept;

0015<figref idref="DRAWINGS">FIG. 2</figref> is a cross-sectional view illustrating a semiconductor device according to another embodiment of the inventive concept;

0016<figref idref="DRAWINGS">FIG. 3</figref> is a cross-sectional view illustrating a semiconductor device according to still another embodiment of the inventive concept;

0017<figref idref="DRAWINGS">FIG. 4</figref> is a cross-sectional view illustrating a semiconductor device according to still another embodiment of the inventive concept;

0018<figref idref="DRAWINGS">FIG. 5</figref> is a cross-sectional view illustrating a semiconductor device according to still another embodiment of the inventive concept;

0019<figref idref="DRAWINGS">FIG. 6</figref> is a cross-sectional view illustrating a semiconductor device according to still another embodiment of the inventive concept;

0020<figref idref="DRAWINGS">FIG. 7</figref> is a cross-sectional view illustrating a semiconductor device according to still another embodiment of the inventive concept;

0021<figref idref="DRAWINGS">FIG. 8</figref> is a cross-sectional view illustrating a semiconductor device according to still another embodiment of the inventive concept;

0022<figref idref="DRAWINGS">FIG. 9</figref> is a cross-sectional view illustrating a semiconductor device according to still another embodiment of the inventive concept;

0023<figref idref="DRAWINGS">FIG. 10</figref> is a cross-sectional view illustrating a semiconductor device according to still another embodiment of the inventive concept;

0024<figref idref="DRAWINGS">FIGS. 11 to 21</figref> are cross-sectional views illustrating a method of fabricating the semiconductor device according to the embodiment of the inventive concept;

0025<figref idref="DRAWINGS">FIGS. 22 to 32</figref> are cross-sectional views illustrating a method of fabricating the semiconductor device according to another embodiment of the inventive concept;

0026<figref idref="DRAWINGS">FIG. 33</figref> is a cross-sectional view illustrating a semiconductor device according to still another embodiment of the inventive concept;

0027<figref idref="DRAWINGS">FIG. 34</figref> is a cross-sectional view illustrating an interposer according to the embodiments of the inventive concept and its exemplary application;

0028<figref idref="DRAWINGS">FIGS. 35 and 36</figref> are cross-sectional views illustrating a semiconductor package and its modification according to the embodiments of the inventive concept;

0029<figref idref="DRAWINGS">FIGS. 37 to 39</figref> are cross-sectional views illustrating a semiconductor package and its modifications according to the embodiments of the inventive concept;

0030<figref idref="DRAWINGS">FIG. 40</figref> is a cross-sectional view illustrating a semiconductor package according to the embodiments of the inventive concept;

0031<figref idref="DRAWINGS">FIGS. 41 and 42</figref> are cross-sectional views illustrating a semiconductor package and its modification according to the embodiments of the inventive concept;

0032<figref idref="DRAWINGS">FIG. 43</figref> is a cross-sectional view illustrating a semiconductor package according to the embodiments of the inventive concept;

0033<figref idref="DRAWINGS">FIGS. 44 and 45</figref> are diagrams for explaining a method of fabricating the semiconductor package according to the embodiments of the inventive concept;

0034<figref idref="DRAWINGS">FIG. 46</figref> is a plane view illustrating a package module according to the embodiments of the inventive concept;

0035<figref idref="DRAWINGS">FIG. 47</figref> is a block diagram illustrating a memory card according to the embodiments of the inventive concept;

0036<figref idref="DRAWINGS">FIG. 48</figref> is a block diagram illustrating an electronic system according to the embodiments of the inventive concept; and

0037<figref idref="DRAWINGS">FIG. 49</figref> is a perspective view illustrating an electronic device according to the embodiments of the inventive concept.

DETAILED DESCRIPTION OF THE EMBODIMENTS

0038Exemplary embodiments of the inventive concept will be described below in more detail with reference to the accompanying drawings. The inventive concept may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the inventive concept to those skilled in the art.

0039In the drawings, the dimensions of layers and regions are exaggerated for clarity of illustration. It will also be understood that when a layer (or film) is referred to as being ‘on’ another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Further, it will be understood that when a layer is referred to as being ‘under’ another layer, it can be directly under, and one or more intervening layers may also be present. In addition, it will also be understood that when a layer is referred to as being ‘between’ two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

0040The terms “first”, “second”, and the like may be used for explaining various elements; however, those elements should not be limited by the terms. The terms are used just for distinguishing one element from another. For instance, without departing the scope of the inventive concept, a first element may be named as a second element, and likewise, the second element may be named as the first element.

0041The terms of a singular form may include plural forms unless otherwise specified. Also, the meaning of “include,” “comprise,” “including,” or “comprising,” specifies a property, a region, a fixed number, a step, a process, an element and/or a component but does not exclude other properties, regions, fixed numbers, steps, processes, elements and/or components.

0042The terms used for the embodiments of the inventive concept may be interpreted as having the meanings typically known to those skilled in the art, unless they are differently defined. For instance, a low dielectric constant material layer indicates an insulation layer having a dielectric constant lower than that of silicon oxide, silicon nitride, and silicon oxinitride. The term “at least one” is used as having the meaning of one at a minimum and may selectively indicate one or more.

0043Hereinafter, exemplary embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

0044<figref idref="DRAWINGS">FIG. 1</figref> is a cross-sectional view illustrating a semiconductor device according to an embodiment of the inventive concept. For convenience, a region where a TSV is formed is focused on.

0045Referring to <figref idref="DRAWINGS">FIG. 1</figref>, a substrate <b>10</b> of a semiconductor device <b>101</b> includes a first surface <b>11</b> and a second surface <b>12</b> opposing the first surface <b>11</b>. The semiconductor device <b>101</b> may be a semiconductor chip including an integrated circuit <b>13</b>. The integrated circuit <b>13</b> is provided on the inside of the substrate <b>10</b>. The integrated circuit <b>13</b> may be formed close to the first surface <b>11</b> in the substrate <b>10</b>. The integrated circuit <b>13</b> may include a transistor or a memory device, and may be stacked with other circuits.

0046A pad <b>14</b> electrically connected to the integrated circuit <b>13</b> may be provided, and may be formed of aluminum (Al) or copper (Cu). Al pads may be provided on the integrated circuit <b>13</b>, while Cu pads may be part of the integrated circuit <b>13</b> as a damascene structure.

0047The substrate <b>10</b> may further include a passivation layer <b>15</b> partially exposing the pad <b>14</b> on the first surface <b>11</b>, which may protect the integrated circuit <b>13</b> from an external environment and may be formed of silicon oxide, silicon nitride, or their combination.

0048A via hole <b>16</b> for forming a TSV <b>20</b> penetrates the substrate <b>10</b> and may be separated from the integrated circuit <b>13</b>. The via hole <b>16</b> may be in a region of a peripheral circuit (not illustrated), or a scribe lane, or the via hole <b>16</b> may either penetrate or overlap the pad <b>14</b>.

0049A via hole insulation layer may be provided on a sidewall of the via hole <b>16</b>, and may include a first insulation layer <b>22</b><i>s </i>and a second insulation layer <b>22</b><i>p</i>. The first insulation layer <b>22</b><i>s </i>may include silicon oxide, silicon oxinitride, and silicon nitride. The second insulation layer <b>22</b><i>p </i>may include a polymer, preferably a CF-based polymer layer, and may be formed through a plasma process using at least one gas selected from C₄F₆, C₄F₈, C₅F₈, and CHF₃, and may have a dielectric constant lower than that of the first insulation layer <b>22</b><i>s. </i>A CF-based polymer has a dielectric constant of about 2.5 and a silicon oxide layer has a dielectric constant of about 3.6. The first insulation layer <b>22</b><i>s </i>may be extended from the sidewall of the via hole <b>16</b> onto the passivation layer <b>15</b>. In this illustrative embodiment, the first insulation layer <b>22</b><i>s </i>may expose a part of the pad <b>14</b>.

0050The TSV <b>20</b> is provided within the via hole <b>16</b> and the via hole insulation layers <b>22</b><i>s </i>and <b>22</b><i>p </i>may extend onto the first surface <b>11</b> of the substrate <b>10</b> so that the TSV <b>20</b> is electrically connected to the pad <b>14</b>. TSV <b>20</b> may include a barrier layer <b>24</b> on the via hole insulation layer and a via conductor <b>26</b> on the barrier layer <b>24</b>. The barrier layer <b>24</b> may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), and may serve to prevent conductive material of the via conductor <b>26</b> from being diffused into the substrate <b>10</b>. The via conductor <b>26</b> may include silver (Ag), gold (Au), copper (Cu), tungsten (W), and indium (In).

0051A connector <b>63</b> may be provided on the TSV <b>20</b>, and may be formed using a solder material. The connector <b>63</b> may be reflowed when semiconductor devices are stacked so that TSVs of the stacked semiconductor devices may be joined, and may be formed corresponding to a position where the via hole <b>16</b> is formed.

0052First and second sub insulation layers <b>32</b> and <b>34</b> may be sequentially provided on the second surface <b>12</b> of the substrate <b>10</b> and may serve to prevent the second surface <b>12</b> of the substrate <b>10</b> from being contaminated by the conductive material when a process of exposing the via conductor <b>26</b> is performed. The first sub insulation layer <b>32</b> may be a silicon oxide layer, and the second sub insulation layer <b>34</b> may be a silicon nitride layer. The first sub insulation layer <b>32</b> is provided directly on the second surface <b>12</b> of the substrate <b>10</b>, and the second sub insulation layer <b>34</b> is provided directly on the first sub insulation layer <b>32</b>.

0053The first sub insulation layer <b>32</b> may include a first part <b>32</b><i>a </i>provided on the second surface <b>12</b> of the substrate <b>10</b> and a second part <b>32</b><i>b </i>protruding from the second surface <b>12</b> of the substrate <b>10</b>. That is, the first sub insulation layer <b>32</b> may have a cross section having an L shape.

0054The first and second sub insulation layers <b>32</b> and <b>34</b> expose the TSV <b>20</b> and the via hole insulation layer. The TSV <b>20</b> may be exposed by planarizing the substrate <b>10</b> using the second sub insulation layer <b>34</b> as a planarization stop layer. Accordingly, the second sub insulation layer <b>34</b>, the via hole insulation layer, and the TSV <b>20</b> may have aligned surfaces.

0055By exposing the TSV <b>20</b> through the planarization process using the second sub insulation layer <b>34</b> as the planarization stop layer, a photolithography process for removing insulation layers on the TSV <b>20</b> may be omitted. When the TSV <b>20</b> is exposed using the photolithography process, if the TSV <b>20</b> has a narrow width (i.e., if the via hole <b>16</b> has a narrow width), the elimination of the first and second sub insulation layers <b>32</b> and <b>34</b> may not be easy due to a resolution limit of the photolithography process. According to the inventive concept, the TSV <b>20</b> may be easily exposed regardless of the width of the TSV <b>20</b>.

0056Hereinafter, referring to <figref idref="DRAWINGS">FIGS. 2 to 10</figref>, semiconductor devices according to other embodiments of the inventive concept will be described. <figref idref="DRAWINGS">FIGS. 2 to 10</figref> are cross-sectional views respectively illustrating the semiconductor devices according to the other embodiments of the inventive concept. For convenience, the region where the TSV is formed is focused on. For the structural elements already explained through the above-described embodiment of the inventive concept, the same reference numerals are used and descriptions for them are omitted.

0057A difference between a semiconductor device <b>102</b> according to another embodiment of the inventive concept illustrated in <figref idref="DRAWINGS">FIG. 2</figref> and the above-described semiconductor device <b>101</b> may include the via hole insulation layer having a different structure.

0058The via hole insulation layer on the sidewall of the via hole <b>16</b> may include a first insulation layer <b>22</b><i>p </i>and a second insulation layer <b>22</b><i>s </i>on the first insulation layer <b>22</b><i>p. </i>The first insulation layer <b>22</b><i>p </i>may include the polymer, preferably a CF-based polymer layer, which may be formed through a plasma process using at least one gas selected from C₄F₆, C₄F₈, C₅F₈, and CHF₃. The second insulation layer <b>22</b><i>s </i>may include silicon oxide, silicon oxinitride, and silicon nitride. The second insulation layer <b>22</b><i>s </i>may extend from the sidewall of the via hole <b>16</b> onto the passivation layer <b>15</b>, and the second insulation layer <b>22</b><i>s </i>may expose part of the pad <b>14</b>.

0059A difference between a semiconductor device <b>103</b> according to still another embodiment of the inventive concept illustrated in <figref idref="DRAWINGS">FIG. 3</figref> and the above-described semiconductor device <b>101</b> may include the via hole insulation layer having a different structure.

0060The via hole insulation layer on the sidewall of the via hole <b>16</b> may include sequentially stacked first insulation layer <b>22</b><i>s, </i>second insulation layer <b>22</b><i>p</i>, and third insulation layer <b>22</b><i>sa</i>. The first and third insulation layers <b>22</b><i>s </i>and <b>22</b><i>sa </i>may include silicon oxide, silicon oxinitride, and silicon nitride, preferably a silicon oxide layer. The second insulation layer <b>22</b><i>p </i>may include a polymer, preferably a CF-based polymer. The second insulation layer <b>22</b><i>p </i>may be formed through a plasma process using at least one gas selected from C₄F₆, C₄F₈, C₅F₈, and CHF₃. The first and third insulation layers <b>22</b><i>s </i>and <b>22</b><i>sa </i>may extend from the sidewall of the via hole <b>16</b> onto the passivation layer <b>15</b>, and may expose part of the pad <b>14</b>. A fourth insulation layer (not illustrated) including the polymer may be further provided on the third insulation layer <b>22</b><i>sa. </i>

0061A difference between a semiconductor device <b>104</b> according to still another embodiment of the inventive concept illustrated in <figref idref="DRAWINGS">FIG. 4</figref> and the above-described semiconductor device <b>101</b> may include the via hole insulation layer having a different structure. The via hole insulation layer provided to the sidewall of the via hole <b>16</b> may include sequentially stacked first insulation layer <b>22</b><i>p, </i>second insulation layer <b>22</b><i>s, </i>and third insulation layer <b>22</b><i>pa</i>. The first and third insulation layers <b>22</b><i>p </i>and <b>22</b><i>pa </i>may include a polymer. The second insulation layer <b>22</b><i>s </i>may include silicon oxide, silicon oxinitride, and silicon nitride, preferably a silicon oxide layer, which may extend from the sidewall of the via hole <b>16</b> onto the passivation layer <b>15</b>. A fourth insulation layer (not illustrated) including the silicon may be further provided on the third insulation layer <b>22</b><i>pa. </i>

0062A difference between a semiconductor device <b>105</b> according to still another embodiment of the inventive concept illustrated in <figref idref="DRAWINGS">FIG. 5</figref> and the above-described semiconductor device <b>101</b> may include the via hole insulation layer having a different structure, and may include a first insulation layer <b>22</b><i>s </i>and a second insulation layer <b>22</b><i>p </i>on the first insulation layer <b>22</b><i>s. </i>The first insulation layer <b>22</b><i>s </i>may include silicon oxide, silicon oxinitride, and silicon nitride, and preferably may be a silicon oxide layer. The first insulation layer <b>22</b><i>s </i>may have a larger thickness at a lower part of the via hole <b>16</b> than at an upper part of the via hole <b>16</b>. The second insulation layer <b>22</b><i>p </i>may include a polymer. The second insulation layer <b>22</b><i>s </i>may have a smaller thickness at a lower part of the via hole <b>16</b> than at an upper part of the via hole <b>16</b>. The first insulation layer <b>22</b><i>s </i>may extend from the sidewall of the via hole <b>16</b> onto the passivation layer <b>15</b> and may expose part of pad <b>14</b>.

0063A difference between a semiconductor device <b>106</b> according to still another embodiment of the inventive concept illustrated in <figref idref="DRAWINGS">FIG. 6</figref> and the above-described semiconductor device <b>101</b> may include the via hole insulation layer having a different structure, which may include a first insulation layer <b>22</b><i>s </i>and a second insulation layer <b>22</b><i>p </i>on the first insulation layer <b>22</b><i>s. </i>The first insulation layer <b>22</b><i>s </i>may have a smaller thickness at a lower part of the via hole <b>16</b> than at an upper part of the via hole <b>16</b>. The second insulation layer <b>22</b><i>p </i>may include a polymer. The second insulation layer <b>22</b><i>s </i>may have a larger thickness at a lower part of the via hole <b>16</b> than at an upper part of the via hole <b>16</b>. The first insulation layer <b>22</b><i>s </i>may extend from the sidewall of the via hole <b>16</b> onto the passivation layer <b>15</b>, and may expose part of the pad <b>14</b>.

0064In other embodiments, the first and second insulation layers <b>22</b><i>s </i>or <b>22</b><i>p </i>in the via hole insulation layer may not cover the whole sidewall of the via hole <b>16</b>.

0065A difference between a semiconductor device <b>107</b> according to still another embodiment of the inventive concept illustrated in <figref idref="DRAWINGS">FIG. 7</figref> and the above-described semiconductor device <b>101</b> may include the via hole insulation layer having a different structure, which may include a first insulation layer <b>22</b><i>p </i>and a second insulation layer <b>22</b><i>s, </i>where the first insulation layer <b>22</b><i>p </i>may include a polymer. The first insulation layer <b>22</b><i>p </i>may have a larger thickness at a lower part of the via hole <b>16</b> than at an upper part of the via hole <b>16</b>. The second insulation layer <b>22</b><i>s </i>may have a smaller thickness at a lower part of the via hole <b>16</b> than at an upper part of the via hole <b>16</b> and may extend from the sidewall of the via hole <b>16</b> onto the passivation layer <b>15</b>, and may expose part of the pad <b>14</b>.

0066A difference between a semiconductor device <b>108</b> according to still another embodiment of the inventive concept illustrated in <figref idref="DRAWINGS">FIG. 8</figref> and the above-described semiconductor device <b>101</b> may include the via hole insulation layer having a different structure, which may include a first insulation layer <b>22</b><i>p </i>and a second insulation layer <b>22</b><i>s </i>on the first insulation layer <b>22</b><i>p. </i>The first insulation layer <b>22</b><i>p </i>may have a smaller thickness at a lower part of the via hole <b>16</b> than at an upper part of the via hole <b>16</b>. The second insulation layer <b>22</b><i>s </i>may have a larger thickness at a lower part of the via hole <b>16</b> than at an upper part of the via hole <b>16</b>. In other embodiments, the first or second insulation layers <b>22</b><i>p </i>or <b>22</b><i>s </i>may not cover the whole sidewall of the via hole <b>16</b>.

0067A difference between a semiconductor device <b>109</b> according to still another embodiment of the inventive concept illustrated in <figref idref="DRAWINGS">FIG. 9</figref> and the above-described semiconductor device <b>101</b> may include the via hole insulation layer having a different structure, which may include a first insulation layer <b>22</b><i>s </i>and a second insulation layer <b>22</b><i>p </i>on the first insulation layer <b>22</b><i>s. </i>

0068The first insulation layer <b>22</b><i>s </i>may have a decreasing thickness at a lower part of the via hole <b>16</b> as a distance away from the second surface <b>12</b> of the substrate <b>10</b> increases, and may have a uniform thickness at an upper part of the via hole <b>16</b>. The second insulation layer <b>22</b><i>p </i>may have an increasing thickness at a lower part of the via hole <b>16</b> as the a distance away from the second surface <b>12</b> of the substrate <b>10</b> increases and may have a uniform thickness at an upper part of the via hole <b>16</b>.

0069A difference between a semiconductor device <b>110</b> according to still another embodiment of the inventive concept illustrated in <figref idref="DRAWINGS">FIG. 10</figref> and the above-described semiconductor device <b>101</b> may include the via hole insulation layer having a different structure, where the first insulation layer <b>22</b><i>s </i>may have a uniform thickness at the sidewall of the via hole <b>16</b>. The second insulation layer <b>22</b><i>p </i>may have an increasing thickness at a lower part of the via hole <b>16</b> as a distance from the second surface <b>12</b> of the substrate <b>10</b> increases and may have a uniform thickness at an upper part of the via hole <b>16</b>.

0070According to the above-described embodiments of the inventive concept, since the structure of the TSV has the multi-layered insulation layer, electric characteristics and reliability of the TSV structure may be improved.

0071An exemplary method of fabricating the semiconductor device according to the embodiment of the inventive concept described referring to <figref idref="DRAWINGS">FIG. 1</figref> will be described. <figref idref="DRAWINGS">FIGS. 11 to 18</figref> are cross-sectional views for explaining the exemplary method of fabricating the semiconductor device.

0072Referring to <figref idref="DRAWINGS">FIG. 11</figref>, the integrated circuit <b>13</b> is formed at the inside of the substrate <b>10</b> or at the first surface <b>11</b>. The pad <b>14</b> may be electrically connected to the integrated circuit <b>13</b> and formed on the integrated circuit <b>13</b>. If the pad <b>14</b> is formed of Al, the pad <b>14</b> may be formed on the integrated circuit <b>13</b> as illustrated in <figref idref="DRAWINGS">FIG. 11</figref>. If the pad <b>14</b> is formed of, Cu, the pad <b>14</b> may be formed to be included as part of the integrated circuit <b>13</b> as a damascene structure.

0073A passivation layer <b>15</b> exposing a part of pad <b>14</b> may be formed on the first surface <b>11</b> of the substrate <b>10</b>, and may protect the integrated circuit <b>13</b> from the external environment and may be formed of silicon oxide, silicon nitride, or their combination.

0074A via hole <b>16</b> may be recessed to a certain depth below the first surface <b>11</b> of the substrate <b>10</b>. The via hole <b>16</b> may be formed in a region of the peripheral circuit (not illustrated) or the scribe lane. Otherwise, the via hole <b>16</b> may be formed to penetrate or overlap the pad <b>14</b>. The via hole <b>16</b> may be formed using dry etching, wet etching, laser drilling, or mechanical drilling. The depth of the via hole <b>16</b> may be larger than a thickness of the integrated circuit <b>13</b> and smaller than a thickness of the substrate <b>10</b> so that the via hole <b>16</b> may be separated from an initial second surface <b>12</b>′.

0075Referring to <figref idref="DRAWINGS">FIG. 12</figref>, a first insulation layer <b>22</b><i>s </i>is formed on an inner surface of the via hole <b>16</b>. The first insulation layer <b>22</b><i>s </i>may extend from the inner surface of the via hole <b>16</b> onto the first surface <b>11</b> of the substrate <b>10</b>. Using a photolithography process, a part of the first insulation layer <b>22</b><i>s </i>on the pad <b>14</b> is removed so that part of the pad <b>14</b> is exposed.

0076Referring to <figref idref="DRAWINGS">FIG. 13</figref>, a second insulation layer <b>22</b><i>p </i>is formed on the sidewall of the via hole <b>16</b>. Due to CF_xcomponents generated during the plasma process using the CF-based gas, a CF-based polymer (CF₂)_nis generated so that the second insulation layer <b>22</b><i>p </i>may be formed substantially only on the portion of the first insulation layer <b>22</b><i>s </i>disposed on the sidewall of the via hole <b>16</b>. The second insulation layer <b>22</b><i>p </i>may be formed to have various forms referred to as the reference numerals <b>22</b><i>p </i>and <b>22</b><i>pa </i>of <figref idref="DRAWINGS">FIGS. 1 to 10</figref>.

0077Otherwise, the forming of second insulation layer <b>22</b><i>p </i>may include etching the portion of the first insulation layer <b>22</b><i>s </i>on a bottom surface of the via hole <b>16</b>. The CF-based gas may include at least one gas selected from C₄F₆, C₄F₈, C₅F₈, CHF₃, SF₆or/and O₂. Although not illustrated, the first insulation layer <b>22</b><i>s </i>on the bottom surface of the via hole <b>16</b> may be removed by the plasma process. The second insulation layer <b>22</b><i>p </i>may be formed to have various forms referred to as the reference numerals <b>22</b><i>p </i>and <b>22</b><i>pa </i>of <figref idref="DRAWINGS">FIGS. 1 to 10</figref>.

0078Although not illustrated, at least one additional insulation layer may be further formed on the sidewall of the via hole <b>16</b> where the second insulation layer <b>22</b><i>p </i>is formed. That is, a third insulation layer and a fourth insulation layer may be sequentially formed on the second insulation layer and may include similar materials as the first and second insulation layers.

0079Referring to <figref idref="DRAWINGS">FIG. 14</figref>, a barrier layer <b>24</b> may be formed on the top insulation layer. The barrier layer <b>24</b> may include Ti, TiN, Ta, and TaN, and may serve to prevent metal of a wiring pattern for the TSV from diffusing into the substrate <b>10</b>.

0080By filling the inside of the via hole <b>16</b> with the TSV wiring pattern and patterning it, the via conductor <b>26</b> is formed. The via conductor <b>26</b> may be formed in the inside of the via hole <b>16</b> by using an electroplating process, an electroless plating process, or a selective deposition process. The electroplating process may include forming a seed layer in the inside of the via hole <b>16</b> where the barrier layer <b>24</b> is formed and plating the wiring pattern using the seed layer. The seed layer may be formed in a vapor phase deposition, such as sputtering. The via conductor <b>26</b> may include Ag, Au, Cu, W, and In. The via conductor <b>26</b> may extend onto the first surface <b>11</b> of the substrate <b>10</b> to be electrically connected to the pad <b>14</b>, or may be formed to penetrate or to overlap the pad <b>14</b>.

0081According to the embodiment of the inventive concept, since the structure of the TSV has a multi-layered insulation layer including at least the first and second insulation layers <b>22</b><i>s </i>and <b>22</b><i>p, </i>electrical characteristics and reliability of the TSV structure may be improved.

0082Referring to <figref idref="DRAWINGS">FIG. 15</figref>, a part of the barrier layer <b>24</b> may be removed using the via conductor <b>26</b> as a mask. Removing the barrier layer <b>24</b> may be performed using dry etching or wet etching. Thereafter, a connector <b>63</b> may be formed on the via conductor <b>26</b>. The connector <b>63</b> may be a solder ball.

0083Referring to <figref idref="DRAWINGS">FIG. 16</figref>, a process of polishing the initial second surface <b>12</b>′ of the substrate <b>10</b> is performed. First, a carrier substrate <b>29</b> may adhere onto the first surface <b>11</b> of the substrate <b>10</b> by using an adhesive layer <b>27</b>. The carrier substrate <b>29</b> may relieve mechanical stress caused by the process of polishing the initial second surface <b>12</b>′ of the substrate <b>10</b> and may prevent the substrate <b>10</b> which is thinned after the polishing process from being bent. The carrier substrate <b>29</b> may include a glass substrate or a resin substrate, and the adhesive layer <b>27</b> may include ultraviolet adhesive or thermoplastic adhesive. Next, the initial second surface <b>12</b>′ of the substrate <b>10</b> is polished so that at least one of the first and second insulation layers <b>22</b><i>s </i>and <b>22</b><i>p </i>are exposed. The process of polishing the initial second surface <b>12</b>′ of the substrate <b>10</b> may be performed, e.g., by using a grinding method. The polished second surface <b>12</b>″ may be higher than or lower than the first and second insulation layers <b>22</b><i>s </i>and <b>22</b><i>p. </i>

0084Referring to <figref idref="DRAWINGS">FIG. 17</figref>, the polished second surface <b>12</b>″ is selectively etched so that the via conductor <b>26</b> surrounded by the first and second insulation layers <b>22</b><i>s </i>and <b>22</b><i>p </i>protrudes from the second surface <b>12</b> of the substrate <b>10</b>. The selective etching for the substrate <b>10</b> may be performed using wet or dry etching having a higher substrate <b>10</b> etch rate compared with the first and second insulation layers <b>22</b><i>s </i>and <b>22</b><i>p. </i>For instance, in the case that the first insulation layer <b>22</b><i>s </i>is silicon oxide, the substrate <b>10</b> may be selectively etched by using SF₆etch gas. An etched thickness d<b>1</b> of the substrate <b>10</b> may be equal to or larger than a sum of thicknesses of the first and second sub insulation layers (<b>32</b> and <b>34</b> in <figref idref="DRAWINGS">FIG. 18</figref>) which are formed later and the first and second insulation layers <b>22</b><i>s </i>and <b>22</b><i>p. </i>In the case where barrier layer <b>24</b> is formed, the etched thickness d<b>1</b> may be equal to or larger than a sum of thicknesses of the later formed first and second sub insulation layers (<b>32</b> and <b>34</b> in <figref idref="DRAWINGS">FIG. 18</figref>), the first and second insulation layers <b>22</b><i>s </i>and <b>22</b><i>p, </i>and the barrier layer <b>24</b>.

0085Referring to <figref idref="DRAWINGS">FIG. 18</figref>, the first and second sub insulation layers <b>32</b> and <b>34</b> are sequentially formed on the second surface <b>12</b> of the substrate <b>10</b> and the protruded first and second insulation layers <b>22</b><i>s </i>and <b>22</b><i>p. </i>The first sub insulation layer <b>32</b> may be formed of silicon oxide, and the second sub insulation layer <b>34</b> may be formed of silicon nitride. Since the carrier substrate <b>29</b> is adhered onto the first surface <b>11</b> of the substrate <b>10</b> by the adhesive layer <b>27</b>, the first and second sub insulation layers <b>32</b> and <b>34</b> may be formed by using Chemical Vapor Deposition (CVD) at a low temperature about 300° C. considering thermal stability of the adhesive layer <b>27</b>.

0086Referring to <figref idref="DRAWINGS">FIG. 1</figref> again, the planarization process is performed using the second sub insulation layer <b>34</b> as the planarization stop layer. The planarization process may be performed by using Chemical Mechanical Polishing (CMP). By the planarization process, parts of the second sub insulation layer <b>34</b>, the first sub insulation layer <b>32</b>, the first and second insulation layers <b>22</b><i>s </i>and <b>22</b><i>p, </i>the barrier layer <b>24</b>, and the via conductor <b>26</b> which protrude from the second sub insulation layer <b>34</b> on the second surface <b>12</b> of the substrate <b>10</b> are removed. After the planarization process, the carrier substrate <b>29</b> and the adhesive layer <b>27</b> may be removed. In the case of the barrier layer <b>24</b>, the planarization process may be performed so that the barrier layer <b>24</b> is not removed and still remains on an upper part of the via conductor <b>26</b>.

0087Meanwhile, although not illustrated, the remaining second sub insulation layer <b>34</b> may be eliminated. The second sub insulation layer <b>34</b> may be removed by using wet or dry etching having a high etch selectivity in comparison with the first sub insulation layer <b>32</b>. Particularly, in the case that the second sub insulation layer <b>34</b> is formed of silicon nitride layer (SiN), for reducing stress applied to the substrate <b>10</b>, the second sub insulation layer <b>34</b> may be removed.

0088In the embodiment of the inventive concept, by exposing the via conductor <b>26</b> through the planarization process using the second sub insulation layer <b>34</b> as the planarization stop layer, the photolithography process for removing the insulation layers on the via conductor <b>26</b> may be omitted. When the via conductor <b>26</b> is exposed by using a photolithography process, if the via conductor <b>26</b> has a narrow width, the elimination of the first and second insulation layers <b>32</b> and <b>34</b> may be not easy due to the resolution limit of the photolithography process. However, according to the embodiment of the inventive concept, the via conductor <b>26</b> may be easily exposed regardless of the width of the via conductor <b>26</b>.

0089According to the embodiment of the inventive concept, even if the via conductor <b>26</b> is exposed during the planarization process, the substrate <b>10</b> may not be contaminated by metal material because the second surface <b>12</b> of the substrate <b>10</b> is covered with the first and second sub insulation layers <b>32</b> and <b>34</b>.

0090<figref idref="DRAWINGS">FIGS. 19 to 21</figref> are cross-sectional views for explaining another exemplary method of fabricating the semiconductor device according to an embodiment of the inventive concept. For the structural elements already explained through the above-described exemplary method, the same reference numerals are used and descriptions for them are omitted.

0091Referring to <figref idref="DRAWINGS">FIG. 19</figref>, following the polishing process described referring to <figref idref="DRAWINGS">FIG. 16</figref>, parts of the substrate <b>10</b>, the first and second insulation layers <b>22</b><i>s </i>and <b>22</b><i>p, </i>the barrier layer <b>24</b>, and the via conductor <b>26</b> are removed by using a first planarization process so that the via conductor <b>26</b> is exposed. The first planarization process may be performed by using CMP. The polished second surface <b>12</b>″ may be higher than or lower than the exposed surface of the via conductor <b>26</b>.

0092Referring to <figref idref="DRAWINGS">FIG. 20</figref>, the polished second surface <b>12</b>″ of the substrate <b>10</b> is selectively etched so that the polished via conductor <b>26</b> is protruded from the second surface <b>12</b> of the substrate <b>10</b>. For instance, the substrate <b>10</b> may be selectively etched by using HBr etch gas. An etched thickness d<b>2</b> of the substrate <b>10</b> may be equal to or larger than a sum of thicknesses of the first and second sub insulation layers (<b>32</b> and <b>34</b> of <figref idref="DRAWINGS">FIG. 18</figref>).

0093Referring to <figref idref="DRAWINGS">FIG. 21</figref>, the first and second sub insulation layers <b>32</b> and <b>34</b> are sequentially formed on the protruded via conductor <b>26</b> and the second surface <b>12</b> of the substrate <b>10</b>. The first and second sub insulation layers <b>32</b> and <b>34</b> are also formed on the first and second insulation layers <b>22</b><i>s </i>and <b>22</b><i>p </i>and the barrier layer <b>24</b>. The first sub insulation layer <b>32</b> may be formed of silicon oxide, and the second sub insulation layer <b>34</b> may be formed of silicon nitride.

0094Referring to <figref idref="DRAWINGS">FIG. 1</figref> again, a second planarization process is performed using the second sub insulation layer <b>34</b> as the planarization stop layer. By the second planarization process, the via conductor <b>26</b> may be exposed remaining the first and second sub insulation layers <b>32</b> and <b>34</b> on the second surface <b>12</b> of the substrate <b>10</b>. Accordingly, the TSV <b>20</b> of the semiconductor device may be connected to that of another semiconductor device. After the second planarization process, the carrier substrate <b>29</b> and the adhesive layer <b>27</b> may be removed. Meanwhile, the remaining second sub insulation layer <b>34</b> may be removed.

0095An exemplary method of fabricating the semiconductor device according to the other embodiment of the inventive concept described referring to <figref idref="DRAWINGS">FIG. 2</figref> will be described. <figref idref="DRAWINGS">FIGS. 22 to 29</figref> are cross-sectional views for explaining the exemplary method of fabricating the semiconductor device according to another embodiment of the inventive concept. For the structural elements already explained above the same reference numerals are used and descriptions for them are omitted.

0096Referring to <figref idref="DRAWINGS">FIG. 22</figref>, the via hole <b>16</b> is formed in the manner described referring to <figref idref="DRAWINGS">FIG. 11</figref>.

0097Referring to <figref idref="DRAWINGS">FIG. 23</figref>, the first insulation layer <b>22</b><i>p </i>is formed on the sidewall of the via hole <b>16</b>. The first insulation layer <b>22</b><i>p </i>may include the polymer. Preferably, the first insulation layer <b>22</b><i>p </i>may be the CF-based polymer layer. The first insulation layer <b>22</b><i>p </i>may be formed through the plasma process using at least one selected from C₄F₆, C₄F₈, C₅F₈, and CHF₃.

0098The forming the first insulation layer <b>22</b><i>p </i>may expose the bottom of via hole <b>16</b>. The first insulation layer <b>22</b><i>p </i>may be formed to have various forms referred to as the reference numerals <b>22</b><i>p </i>and <b>22</b><i>pa </i>of <figref idref="DRAWINGS">FIGS. 1 to 10</figref>.

0099Otherwise, the via hole <b>16</b> may expose an interlayer dielectric (not illustrated) of the substrate <b>10</b>. The forming the first insulation layer <b>22</b><i>p </i>may etch the silicon oxide layer used as the interlayer dielectric exposed on a bottom surface of the via hole <b>16</b> using at least one selected from C₄F₆, C₄F₈, C₅F₈, CHF₃, SF₆and O₂.

0100Referring to <figref idref="DRAWINGS">FIG. 24</figref>, the second insulation layer <b>22</b><i>s </i>is formed on the inner surface of the via hole <b>16</b> where the first insulation layer <b>22</b><i>p </i>is formed. The second insulation layer <b>22</b><i>s </i>may extend from the inner surface of the via hole <b>16</b> onto the first surface <b>11</b> of the substrate <b>10</b>. By using a photolithography process, a part of the second insulation layer <b>22</b><i>s </i>on the pad <b>14</b> is removed so that the part of the pad <b>14</b> is exposed.

0101Referring to <figref idref="DRAWINGS">FIGS. 25 to 29</figref>, the via conductor <b>26</b> and the first and second sub insulation layers <b>32</b> and <b>34</b> are formed in the manner described referring to <figref idref="DRAWINGS">FIGS. 14 to 18</figref>. By performing the planarization process using the second sub insulation layer <b>34</b> as the planarization stop layer, the structure illustrated in <figref idref="DRAWINGS">FIG. 2</figref> may be formed.

0102Another exemplary method of fabricating the semiconductor device according to the other embodiment of the inventive concept described referring to <figref idref="DRAWINGS">FIG. 2</figref> will be described. <figref idref="DRAWINGS">FIGS. 30 to 32</figref> are cross-sectional views explaining the exemplary method of fabricating the semiconductor device. Structural elements already explained above use the same reference numerals and descriptions for them are omitted.

0103Referring to <figref idref="DRAWINGS">FIGS. 30 to 32</figref>, the first and second sub insulation layers <b>32</b> and <b>34</b> are formed in the manner described referring to <figref idref="DRAWINGS">FIGS. 19 to 21</figref>. By performing the planarization process using the second sub insulation layer <b>34</b> as the planarization stop layer, the structure illustrated in <figref idref="DRAWINGS">FIG. 2</figref> may be formed.

0104<figref idref="DRAWINGS">FIG. 33</figref> is a cross-sectional view illustrating a semiconductor device <b>111</b> according to still another embodiment of the inventive concept.

0105Referring to <figref idref="DRAWINGS">FIG. 33</figref>, a semiconductor substrate <b>10</b> is provided. For instance, the semiconductor substrate <b>10</b> may be a silicon substrate. The semiconductor substrate <b>10</b> may include a first surface <b>11</b>′ and a second surface <b>12</b> opposing the first surface <b>11</b>′. The semiconductor device <b>111</b> may include an integrated circuit <b>13</b> on the semiconductor substrate <b>10</b>. A type of the integrated circuit <b>13</b> may be different according to the type of semiconductor device <b>111</b>. For instance, the integrated circuit <b>13</b> may include at least one of a memory circuit, a logic circuit, and their combination. The integrated circuit <b>13</b> may include a passive device including a resistor or a capacitor.

0106The via hole <b>16</b> penetrates the semiconductor substrate <b>10</b> being separated from the integrated circuit <b>13</b>. The via hole <b>16</b> may have the same diameter from the first surface <b>11</b>′ to the second surface <b>12</b> of the semiconductor substrate <b>10</b>, may have different two or more diameters, or may have a tapered form where the diameter is gradually changed.

0107A TSV <b>20</b> may be provided to fill at least a part of the via hole <b>16</b>. The TSV <b>20</b> may be connected to the integrated circuit <b>13</b> of the semiconductor device <b>111</b>, may connect the semiconductor device <b>111</b> to another semiconductor device, or may connect the semiconductor device <b>111</b> to a package substrate or a module substrate. The TSV <b>20</b> may include a barrier layer <b>24</b> on an inner wall of the via hole <b>16</b> and a via conductor <b>26</b> on the barrier layer <b>24</b>. The conducive connection unit <b>26</b> may fill at least a part of the via hole <b>16</b>, and may have a part protruded from the second surface <b>12</b> of the semiconductor substrate <b>10</b>. A via hole insulation layer may be provided between the semiconductor substrate <b>10</b> exposed by the via hole <b>16</b> and the barrier layer <b>24</b>. The via hole insulation layer may be the structure described referring to <figref idref="DRAWINGS">FIGS. 1 to 10</figref>. The barrier layer <b>24</b> includes material capable of preventing conductive material included in the via conductor <b>26</b> from being diffused to the semiconductor substrate <b>10</b>. For instance, the barrier layer <b>24</b> may include Ti, TiN, Ta, or TaN, and may be formed by using sputtering. The via conductor <b>26</b> may include Cu, W, Al, Ag, Au, In, or polysilicon.

0108A surface insulation layer <b>30</b> may be provided on the second surface <b>12</b> of the semiconductor substrate <b>10</b>, and may extend from the second surface <b>12</b> of the semiconductor substrate <b>10</b> to a sidewall of the via hole <b>16</b>. The surface insulation layer <b>30</b> may include silicon oxide, silicon nitride, or silicon oxinitride. For instance, the surface insulation layer <b>30</b> may include a first sub insulation layer <b>32</b> on the second surface <b>12</b> of the semiconductor substrate <b>10</b> and a second sub insulation layer <b>34</b> on the first sub insulation layer <b>32</b>. The first sub insulation layer <b>32</b> may be a silicon oxide layer, and the second sub insulation layer <b>34</b> may be a silicon nitride layer.

0109A connection pad <b>60</b> covering the via conductor <b>26</b> and at least a part of the surface insulation layer <b>30</b> may be provided on the second surface <b>12</b> of the semiconductor substrate <b>10</b>. The connection pad <b>60</b> may be directly connected to the protruding part of the via conductor <b>26</b>.

0110An interlayer dielectric <b>33</b> covering the first surface <b>11</b>′ of the semiconductor substrate <b>10</b> and the integrated circuit <b>13</b>, and an internal wiring <b>41</b> connecting the integrated circuit <b>13</b> and the pad <b>14</b> may be provided. The interlayer dielectric <b>33</b> may include a plurality of insulation layers. For instance, the interlayer dielectric <b>33</b> may include a first interlayer dielectric <b>31</b> covering the first surface <b>11</b>′ of the semiconductor substrate <b>10</b> and a second interlayer dielectric <b>31</b>′ on the first interlayer dielectric <b>31</b> covering the integrated circuit <b>13</b>. A passivation layer <b>15</b> may be provided on the interlayer dielectric <b>33</b> exposing a part of the pad <b>14</b>. The internal wiring <b>41</b> may include first and second contact plugs <b>43</b> and <b>47</b> penetrating at least a part of the interlayer dielectric <b>33</b>, and a second wiring pattern <b>45</b> on or inside the interlayer dielectric <b>33</b>. For instance, the second wiring pattern <b>45</b> may be a first metal layer. The first and second contact plugs <b>43</b> and <b>47</b> and the second wiring pattern <b>45</b> may be formed by using the patterning or damascene method.

0111The semiconductor device <b>111</b> may be a semiconductor device of a via middle structure where the TSV <b>20</b> is formed after the integration circuit <b>13</b> is formed. For instance, after forming the integrated circuit <b>13</b>, the first interlay dielectric <b>31</b>, and the first contact plug <b>43</b> on the first surface <b>11</b>′ of the semiconductor substrate <b>10</b>, the TSV <b>20</b> penetrating the semiconductor substrate <b>10</b> and the first interlayer dielectric <b>31</b> is formed. Next, the second wiring pattern <b>45</b> connecting the first contact plug <b>43</b> and the via conductor <b>26</b>, the second contact plug <b>47</b>, and the pad <b>14</b> are formed.

0112The TSVs <b>20</b> described referring to <figref idref="DRAWINGS">FIGS. 1 to 10</figref> may be applied to an interposer (<b>120</b> of <figref idref="DRAWINGS">FIG. 34</figref>). In this case, the integrated circuit <b>13</b> described referring to <figref idref="DRAWINGS">FIG. 33</figref> may not be formed.

0113<figref idref="DRAWINGS">FIG. 34</figref> is a cross-sectional view illustrating an interposer according to the embodiments of the inventive concept and its exemplary application.

0114Referring to <figref idref="DRAWINGS">FIG. 34</figref>, a semiconductor substrate <b>10</b> may be a silicon or glass substrate. A second connection terminal <b>66</b> may be formed on a surface of the semiconductor substrate <b>10</b>. The second connection terminal <b>66</b> may be selected from a conductive bump, a solder ball, a conductive spacer, and a Pin Grid Array (PGA).

0115A first wiring layer <b>40</b> electrically connected to the TSV <b>20</b> and a second insulation layer <b>50</b> covering the first wiring layer <b>40</b> may be formed on a first surface <b>11</b> of the semiconductor substrate <b>10</b>. The first wiring layer <b>40</b> may be a rewiring for another semiconductor device stacked on an interposer <b>120</b>. The second insulation layer <b>50</b> may expose a part of the first wiring layer <b>40</b>. An electrode pad <b>62</b> electrically connected to the exposed part of the wiring layer <b>40</b> may be formed. In the case that a plurality of electrode pads <b>62</b> and a plurality of second connection terminals <b>66</b> are provided, the electrode pads <b>62</b> and the second connection terminals <b>66</b> may be formed to have different pitches.

0116The interposer <b>120</b> may be turned over to be mounted on a package substrate <b>200</b>. The package substrate <b>200</b> may be formed of a flexible printed circuit board, a rigid printed circuit board, or a combination where a circuit pattern <b>204</b> is formed in its inside. The circuit pattern <b>204</b> may be connected to a bonding pad <b>202</b> or a ball pad <b>206</b> exposed to the outside.

0117The interposer <b>120</b> may be electrically connected to the bonding pad <b>202</b> through the second connection terminal <b>66</b> and may be connected to an external connection terminal <b>208</b> through the circuit pattern <b>204</b> of the package substrate <b>200</b>.

0118Another semiconductor device <b>130</b> may be stacked on the interposer <b>120</b>. The other semiconductor device <b>130</b> may be electrically connected to the electrode pad <b>62</b> of the interposer <b>120</b> through a first connection terminal <b>64</b>. For instance, the other semiconductor device <b>130</b> may be a semiconductor chip, and the first connection terminal <b>64</b> may be a flip-chip bump. In the case that multiple first connection terminals <b>64</b> and TSVs <b>20</b> are formed, a distance between the first connection terminals <b>64</b> may be smaller than that between the TSVs <b>20</b>. In the case that the distance between the first connection terminals <b>64</b> is so small that the other semiconductor device <b>130</b> cannot be directly connected to the bonding pad <b>202</b> of the package substrate <b>200</b>, the interposer <b>120</b> including the first wiring layer <b>40</b> may be disposed between the other semiconductor device <b>130</b> and the package substrate <b>200</b>.

0119A protector <b>80</b> covering parts of or all of the package substrate <b>200</b>, the interposer <b>120</b>, and the other semiconductor device <b>130</b> may be further included. For instance, the protector <b>80</b> may be an underfill filling at least a portion of a space between the interposer <b>120</b> and the package substrate <b>200</b> or a space between the interposer <b>120</b> and the other semiconductor device <b>130</b>, or it may be a molding structure covering the interposer <b>120</b> and the other semiconductor device <b>130</b>. The molding structure may include epoxy molding compound.

0120<figref idref="DRAWINGS">FIGS. 35 and 36</figref> are cross-sectional views illustrating a semiconductor package and its modification according to the embodiments of the inventive concept.

0121Referring to <figref idref="DRAWINGS">FIG. 35</figref>, the semiconductor package according to the inventive concept is described. The embodiment described referring to <figref idref="DRAWINGS">FIG. 33</figref> may be applied to a semiconductor chip <b>310</b>. The semiconductor chip <b>310</b> may include the integrated circuit <b>13</b> inside of the semiconductor substrate <b>10</b> or on the first surface <b>11</b> of the semiconductor substrate <b>10</b>. The integrated circuit <b>13</b> may be electrically connected to the TSV <b>20</b> through the internal wiring <b>41</b> and a first wiring layer <b>40</b>′.

0122The second insulation layer <b>50</b> may be formed on the first wiring layer <b>40</b>′. The first wiring layer <b>40</b>′ and the second insulation layer <b>50</b> may have the same structures as above-described referring to <figref idref="DRAWINGS">FIG. 33</figref>.

0123The package substrate <b>200</b> may be formed of flexible printed circuit board, rigid printed circuit board, or combination where the circuit pattern <b>204</b> is formed in its inside. The package substrate <b>200</b> may include the bonding pad <b>202</b> and the ball pad <b>206</b> exposed to the outside from both surfaces of the package substrate <b>200</b>. The circuit pattern <b>204</b> may be connected to the exposed bonding pad <b>202</b> and/or the ball pad <b>206</b>. The semiconductor chip <b>310</b> may be mounted on the package substrate <b>200</b> so that the second surface <b>12</b> of the semiconductor substrate <b>10</b> faces the package substrate <b>200</b>. The semiconductor chip <b>310</b> may be electrically connected to the bonding pad <b>202</b> through the second connection terminal <b>66</b> and may be connected to the external connection terminal <b>208</b> through the circuit pattern <b>204</b> and the ball pad <b>206</b> of the package substrate <b>200</b>.

0124The semiconductor chip <b>310</b> may be mounted on the package substrate <b>200</b> so that the first surface <b>11</b> of the semiconductor substrate <b>10</b> faces the package substrate <b>200</b>. The second insulation layer <b>50</b> may be formed so that at least a part of the first wiring layer <b>40</b>′ is exposed. The exposed part of the first wiring layer <b>40</b>′ may be electrically connected to the circuit pattern <b>204</b> of the package substrate <b>200</b> through a connection terminal (not illustrated).

0125Referring to <figref idref="DRAWINGS">FIG. 36</figref>, the modification of the semiconductor package described referring to <figref idref="DRAWINGS">FIG. 35</figref> will be described. For convenience, explanations for the same structures as <figref idref="DRAWINGS">FIG. 35</figref> are omitted and differences will be described in detail. The package substrate <b>200</b> may include a second circuit pattern <b>205</b> in its inside, a second bonding pad <b>203</b> and a second ball pad <b>207</b> exposed to the outside from both surfaces of the package substrate <b>200</b>, The second circuit pad <b>205</b> may be connected to the exposed second bonding pad <b>203</b> and/or the second ball pad <b>207</b>.

0126A part of the integrated circuit <b>13</b> of a semiconductor chip <b>320</b> may be electrically connected to the TSV <b>20</b> through the internal wiring <b>41</b> and the first wiring layer <b>40</b>′. Another part of the integrated circuit <b>13</b> of the semiconductor chip <b>320</b> may be electrically connected to a bonding wire <b>67</b> through the internal wiring <b>41</b> and a second wiring layer <b>48</b>. The first and second wiring layers <b>40</b>′ and <b>48</b> and the second insulation layer <b>50</b> may have the same structures as above-described referring to <figref idref="DRAWINGS">FIG. 33</figref>. A part of the second wiring layer <b>48</b> may be exposed by the second insulation layer <b>50</b> to be connected to the bonding wire <b>67</b>. The semiconductor chip <b>320</b> may be electrically connected to the second circuit pattern <b>205</b> of the package substrate <b>200</b> through the bonding wire <b>67</b> and may be connected to the external connection terminal <b>208</b> through the second ball pad <b>207</b>.

0127A signal transferred through the TSV <b>20</b> may be different from a signal transferred through the bonding wire <b>67</b>. For instance, the TSV <b>20</b> may transfer a power or ground signal, and the bonding wire <b>67</b> may transfer a data signal. On the contrary, the TSV <b>20</b> may transfer the data signal, and the bonding wire <b>67</b> may transfer the power or ground signal. Accordingly, the semiconductor chip <b>320</b> may have more signal transfer paths.

0128<figref idref="DRAWINGS">FIGS. 37 to 39</figref> are cross-sectional views illustrating a semiconductor package and its modifications according to the embodiments of the inventive concept. For convenience, explanations for the same structures as <figref idref="DRAWINGS">FIGS. 35 and 36</figref> are omitted and differences will be described in detail.

0129Referring to <figref idref="DRAWINGS">FIG. 37</figref>, a multi-chip package <b>400</b> according to the inventive concept will be described. The embodiment described referring to <figref idref="DRAWINGS">FIG. 33</figref> may be applied to semiconductor chips <b>410</b> and <b>420</b> of the multi-chip package <b>400</b>. The multi-chip package <b>400</b> may include a package substrate <b>200</b>, a first semiconductor chip <b>410</b> on the package substrate <b>200</b>, and at least one second semiconductor chip <b>420</b> on the first semiconductor chip <b>410</b>. The first semiconductor chip <b>410</b> and the second semiconductor chip <b>420</b> may be the same kind of semiconductor chip. For instance, the first semiconductor chip <b>410</b> and the second semiconductor chip <b>420</b> may be fabricated through the same process. Each of the first semiconductor chip <b>410</b> and the second semiconductor chip <b>420</b> may include an integrated circuit <b>13</b> where the memory circuit is formed. The first semiconductor chip <b>410</b> and the second semiconductor chip <b>420</b> may include a first TSV <b>20</b> and a second TSV <b>21</b> respectively. The first TSV <b>20</b> and the second TSV <b>21</b> may be overlapped with each other to be connected. The second TSV <b>21</b> may be directly connected to the first TSV <b>20</b>. Otherwise, the first TSV <b>20</b> and the second TSV <b>21</b> may be connected to each other through the first wiring layer <b>40</b>, the connection pad (<b>62</b> of <figref idref="DRAWINGS">FIG. 34</figref>), and/or the second connection terminal <b>66</b> between them.

0130Referring to <figref idref="DRAWINGS">FIG. 38</figref>, a semiconductor package <b>400</b>′ according to a modification of the semiconductor package <b>400</b> described referring to <figref idref="DRAWINGS">FIG. 37</figref> will be described. For convenience, explanations for the same structures as <figref idref="DRAWINGS">FIG. 37</figref> are omitted and differences will be described in detail.

0131The first semiconductor chip <b>410</b> and the second semiconductor chip <b>410</b> may respectively include the first TSV <b>20</b> and the second TSV <b>21</b>. The first TSV <b>20</b> and the second TSV <b>21</b> may be overlapped with each other to be connected. A part of the integrated circuit <b>13</b> of the second semiconductor chip <b>420</b> may be electrically connected to the second TSV <b>21</b> through the internal wiring and the first wiring layer <b>40</b>′. Another part of the integrated circuit <b>13</b> of the second semiconductor chip <b>420</b> may be electrically connected to the bonding wire <b>67</b> through the internal wiring and the second wiring layer <b>48</b>. The first wiring layer <b>40</b>′ and the second insulation layer <b>50</b> may have the same or similar structures as above-described referring to <figref idref="DRAWINGS">FIG. 33</figref>. A part of the second wiring layer <b>48</b> may be exposed by the second insulation layer <b>50</b> to be connected to the bonding wire <b>67</b>. The second semiconductor chip <b>420</b> may be electrically connected to the second circuit pattern <b>205</b> of the package substrate <b>200</b> through the bonding wire <b>67</b>.

0132The signal transferred through the TSVs <b>20</b> and <b>21</b> may be different from the signal transferred through the bonding wire <b>67</b>. For instance, the TSVs <b>20</b> and <b>21</b> may transfer the power or ground signal, and the bonding wire <b>67</b> may transfer the data signal. On the contrary, the TSVs <b>20</b> and <b>21</b> may transfer the data signal, and the boding wire <b>67</b> may transfer the power or ground signal. Therefore, the semiconductor chips <b>410</b> and <b>420</b> may have more signal transfer paths.

0133Referring to <figref idref="DRAWINGS">FIG. 39</figref>, a semiconductor package <b>400</b>″ according to another modification of the semiconductor package <b>400</b> described referring to <figref idref="DRAWINGS">FIG. 37</figref> will be described. For convenience, explanations for the same structures as <figref idref="DRAWINGS">FIG. 37</figref> are omitted and differences will be described in detail. The first semiconductor chip <b>410</b> and the second semiconductor chip <b>420</b> may be mounted on the package substrate <b>200</b> so that their first surfaces <b>11</b> face the package substrate <b>200</b>. The first semiconductor chip <b>410</b> may be connected to the bonding pad <b>202</b> of the package substrate <b>200</b> through the connection terminal <b>64</b> on the first surface <b>11</b> of the first semiconductor chip <b>410</b>.

0134<figref idref="DRAWINGS">FIG. 40</figref> is a cross-sectional view illustrating a semiconductor package where the semiconductor devices according to the embodiments of the inventive concept are stacked.

0135Referring to <figref idref="DRAWINGS">FIG. 40</figref>, a first semiconductor device <b>100</b>A and a second semiconductor device <b>100</b>B are stacked so that their TSVs <b>20</b> are vertically aligned. The TSV <b>20</b> of the first semiconductor device <b>100</b>A and the TSV <b>20</b> of the second semiconductor device <b>100</b>B may be joined through the connector <b>63</b>. A gap between the first semiconductor device <b>100</b>A and the second semiconductor device <b>100</b>B may be filled with an insulating filler (not illustrated).

0136The stacked semiconductor devices may be mounted on the package substrate (<b>200</b> of <figref idref="DRAWINGS">FIG. 39</figref>). For the package substrate (<b>200</b> of <figref idref="DRAWINGS">FIG. 39</figref>), the printed circuit board, tape wiring board, ceramic wiring board, or silicon wiring board may be used. The package substrate (<b>200</b> of <figref idref="DRAWINGS">FIG. 39</figref>) may include the wiring pattern (<b>204</b> of <figref idref="DRAWINGS">FIG. 39</figref>) extended onto one surface of the package substrate (<b>200</b> of <figref idref="DRAWINGS">FIG. 39</figref>) penetrating the package substrate (<b>200</b> of <figref idref="DRAWINGS">FIG. 39</figref>), the bonding pad (<b>202</b> of <figref idref="DRAWINGS">FIG. 39</figref>) formed on the one surface of the package substrate (<b>200</b> of <figref idref="DRAWINGS">FIG. 39</figref>) and electrically connected to the wiring pattern (<b>204</b> of <figref idref="DRAWINGS">FIG. 39</figref>), and the ball pad (<b>206</b> of <figref idref="DRAWINGS">FIG. 39</figref>) formed on the other surface of the package substrate (<b>200</b> of <figref idref="DRAWINGS">FIG. 39</figref>) and electrically connected to the wiring pattern (<b>204</b> of <figref idref="DRAWINGS">FIG. 39</figref>). For mounting the semiconductor device <b>100</b>A or <b>100</b>B or semiconductor devices where they are stacked on the package substrate (<b>200</b> of <figref idref="DRAWINGS">FIG. 39</figref>), the connector <b>63</b> of the semiconductor device <b>100</b>A may be joined with the bonding pad (<b>202</b> of <figref idref="DRAWINGS">FIG. 39</figref>) of the package substrate (<b>200</b> of <figref idref="DRAWINGS">FIG. 39</figref>).

0137<figref idref="DRAWINGS">FIGS. 41 and 42</figref> are cross-sectional views illustrating a semiconductor package and its modification according to the embodiments of the inventive concept. For convenience, explanations for the same structures as <figref idref="DRAWINGS">FIGS. 35 and 36</figref> are omitted and differences will be described in detail.

0138Referring to <figref idref="DRAWINGS">FIG. 41</figref>, a semiconductor package <b>500</b> according to the embodiment may be a system in package <b>500</b>. The embodiment described referring to <figref idref="DRAWINGS">FIG. 33</figref> may be applied to a first semiconductor chip <b>510</b> of the system in package <b>500</b>. A second semiconductor chip <b>520</b> may be stacked on the first semiconductor chip <b>510</b>. The second semiconductor chip <b>520</b> may be a different kind of semiconductor chip from the first semiconductor chip <b>510</b>. For instance, the first semiconductor chip <b>510</b> may include the logic circuit, and the second semiconductor chip <b>520</b> may include the memory circuit. The second semiconductor chip <b>520</b> may be a high-performance memory chip for helping operations of the first semiconductor chip <b>510</b>.

0139The first semiconductor chip <b>510</b> may be mounted on the package substrate <b>200</b> so that its first surface <b>11</b> faces the package substrate <b>200</b>. The first semiconductor chip <b>510</b> may further include a plurality of first connection terminals <b>64</b> on its first surface <b>11</b>. Some of the first connection terminals <b>64</b> may be connected to the TSV <b>20</b> and the others may be connected to the integrated circuit <b>13</b> formed at the first semiconductor chip <b>510</b>. The integrated circuit <b>13</b> may be directly connected to the package substrate <b>200</b> through the first connection terminal <b>64</b>. The integrated circuit <b>13</b> may be connected to the second semiconductor chip <b>520</b> through the TSV <b>20</b>.

0140The second semiconductor chip <b>520</b> may be connected to the package substrate <b>200</b> through the TSV <b>20</b> and the first connection terminal <b>64</b>. The second semiconductor chip <b>520</b> may be connected to the first semiconductor chip <b>510</b> through the second connection terminal <b>66</b> on one surface of the second semiconductor chip <b>520</b>. The second connection terminal <b>66</b> may be selected from the list including a conductive bump, solder ball, conductive spacer, and PGA. The second connection terminal <b>66</b> and the TSV <b>20</b> may be connected to each other through a fifth wiring pattern <b>74</b> for rewiring. For instance, when a distance between the second connection terminals <b>66</b> is different from that between the TSVs <b>20</b>, the fifth wiring pattern <b>74</b> may be used for connecting them.

0141Referring to <figref idref="DRAWINGS">FIG. 42</figref>, a semiconductor package <b>500</b>′ according to a modification of the semiconductor package <b>500</b> described referring to <figref idref="DRAWINGS">FIG. 41</figref> will be described. For convenience, explanations for the same structures as <figref idref="DRAWINGS">FIG. 41</figref> are omitted and differences will be described in detail.

0142A part of the fifth wiring pattern <b>74</b> may be exposed by the second insulation layer <b>50</b>. The second semiconductor chip <b>520</b> may be electrically connected to the fifth wiring pattern <b>74</b> through the bonding wire <b>67</b>. The first semiconductor chip <b>510</b> and the second semiconductor chip <b>520</b> may be connected to each other through the bonding wire <b>67</b>. The bonding wire <b>67</b> may be directly connected to the TSV <b>20</b> or may be connected to the TSV <b>20</b> through the fifth wiring pattern <b>74</b> for rewiring.

0143<figref idref="DRAWINGS">FIG. 43</figref> is a cross-sectional view illustrating a semiconductor package according to the embodiments of the inventive concept.

0144Referring to <figref idref="DRAWINGS">FIG. 43</figref>, the embodiments described referring to <figref idref="DRAWINGS">FIGS. 34 to 42</figref> may be applied to a first semiconductor package <b>610</b> and/or a second semiconductor package <b>620</b> of a stacked package <b>600</b>.

0145The first semiconductor package <b>610</b> may include a first semiconductor chip <b>602</b> on a first package substrate <b>200</b>. The embodiment described referring to <figref idref="DRAWINGS">FIG. 33</figref> may be applied to the first semiconductor chip <b>602</b>. The first semiconductor package <b>610</b> may further include a protector <b>612</b> covering the first semiconductor chip <b>602</b> and at least a part of the first package substrate <b>200</b>. For instance, the protector <b>612</b> may be an underfill between the first surface <b>11</b> of the first semiconductor chip <b>602</b> and the first package substrate <b>200</b>, or it may be a molding structure further covering other surfaces of the first semiconductor chip <b>602</b>, and may include an epoxy molding compound. In the case that the protector <b>612</b> is a molding structure, the first semiconductor package <b>610</b> may further include a molding electrode <b>614</b> penetrating the molding structure. One end of the molding electrode <b>614</b> may be connected to the second circuit pattern <b>205</b> of the first package substrate <b>200</b>, and the other end may be exposed to the outside of the protector <b>612</b>. The first semiconductor package <b>610</b> may further include a second semiconductor chip <b>604</b> on the first semiconductor chip <b>602</b>.

0146The second semiconductor package <b>620</b> may be stacked on the first semiconductor package <b>610</b>. The second semiconductor package <b>620</b> may include a second package substrate <b>210</b> and at least one third semiconductor chip <b>606</b> on the second package substrate <b>210</b>. For instance, the at least one third semiconductor chip <b>606</b> may be a high-capacity memory chip and may be connected to each other through each TSV <b>20</b>. The second package substrate <b>210</b> may include an external connection terminal <b>218</b> on a surface facing the first semiconductor package <b>610</b>. The external connection terminal <b>218</b> may be connected to the exposed surface of the molding electrode <b>614</b>. The second semiconductor package <b>620</b> may be connected to the outside through a third circuit pattern <b>214</b> of the second package substrate <b>210</b>, the external connection terminal <b>218</b>, the molding electrode <b>614</b> and the second circuit pattern <b>205</b> of the first package substrate <b>200</b>. The second circuit pattern <b>205</b> of the first package substrate <b>200</b> may be electrically separated from the first circuit pattern <b>204</b> connected to the first semiconductor chip <b>602</b>. Since the first semiconductor package <b>610</b> and the second semiconductor package <b>620</b> which function differently may be vertically stacked, a mounting size may be reduced compared to individually mounting them on a module board (<b>702</b> of <figref idref="DRAWINGS">FIG. 46</figref>) at the following process. The second semiconductor package <b>620</b> may further include a protector <b>622</b> covering the second package substrate <b>210</b> and at least a part of the third semiconductor chip <b>606</b>. For instance, the protector <b>622</b> may mold the at least one third semiconductor chip <b>606</b> or may be underfills between a lowermost third semiconductor chip <b>606</b> and the second package substrate <b>210</b>.

0147<figref idref="DRAWINGS">FIGS. 44 and 45</figref> are diagrams for explaining a method of fabricating the semiconductor package according to the embodiments of the inventive concept.

0148Referring to <figref idref="DRAWINGS">FIG. 44</figref>, semiconductor wafers <b>100</b> where the semiconductor devices obtained through the fabricating methods illustrated in <figref idref="DRAWINGS">FIGS. 11 to 32</figref> may be provided. A plurality of semiconductor wafers <b>100</b> may be stacked. By stacking the plurality of semiconductor wafers <b>100</b> and cutting the plurality of semiconductor wafers <b>100</b> along the scribe lane, they may be separated into individual semiconductor packages. The cutting may be performed by using a cutter <b>120</b> or laser.

0149Otherwise, as illustrated in <figref idref="DRAWINGS">FIG. 45</figref>, the semiconductor package may be formed by stacking individual semiconductor devices <b>100</b><i>a, </i><b>100</b><i>b </i>and so forth on the semiconductor wafer <b>100</b>. Or, after the individual semiconductor devices <b>100</b><i>a</i>, <b>100</b><i>b </i>and so forth are separated by cutting along the scribe lane, the semiconductor package may be formed by stacking the plurality of semiconductor devices <b>100</b><i>a </i><b>100</b><i>b </i>and so forth.

0150<figref idref="DRAWINGS">FIG. 46</figref> is a plane view illustrating a package module <b>700</b> according to the embodiments of the inventive concept.

0151Referring to <figref idref="DRAWINGS">FIG. 46</figref>, the package module <b>700</b> may include a module substrate <b>702</b> provided with an external connection terminal <b>708</b>, a semiconductor chip <b>704</b> mounted on the module substrate <b>702</b>, and a semiconductor package <b>706</b> which is Quad Flat Packaged (QFP). The semiconductor chip <b>704</b> and/or the semiconductor package <b>706</b> may include the semiconductor device according to the embodiment of the inventive concept. The package module <b>700</b> may be connected to an external electronic device through the external connection terminal <b>708</b>.

0152<figref idref="DRAWINGS">FIG. 47</figref> is a schematic diagram illustrating a memory card <b>800</b> according to the embodiments of the inventive concept.

0153Referring to <figref idref="DRAWINGS">FIG. 47</figref>, the memory card <b>800</b> may include a controller <b>820</b> and a memory <b>830</b> within a housing <b>810</b>. The controller <b>820</b> and the memory <b>830</b> may exchange electric signals. For instance, according to a command of the controller <b>820</b>, the memory <b>830</b> and the controller <b>820</b> may exchange data. Accordingly, the memory card <b>800</b> may store the data into the memory <b>830</b> or outputs the data to the outside from the memory <b>830</b>.

0154The controller <b>820</b> and/or the memory <b>830</b> may include at least one of the semiconductor device or the semiconductor package according to the embodiments of the inventive concept. For instance, the controller <b>820</b> may include the system in package (<b>500</b> of <figref idref="DRAWINGS">FIG. 41</figref> or <b>500</b>′ of <figref idref="DRAWINGS">FIG. 42</figref>), and memory <b>830</b> may include the multi-chip package (<b>400</b> of <figref idref="DRAWINGS">FIG. 37</figref>, <b>400</b>′ of <figref idref="DRAWINGS">FIG. 38</figref>, or <b>400</b>″ of <figref idref="DRAWINGS">FIG. 39</figref>). Or, the controller <b>820</b> and/or the memory <b>830</b> may be provided as the stacked package (<b>600</b> of <figref idref="DRAWINGS">FIG. 43</figref>). The memory card <b>830</b> may be used as a storage medium of various portable devices. For instance, the memory card <b>830</b> may include a Multi Media Card (MMC) or a Secure Card (SD).

0155<figref idref="DRAWINGS">FIG. 48</figref> is a block diagram illustrating an electronic system <b>900</b> according to the embodiments of the inventive concept.

0156Referring to <figref idref="DRAWINGS">FIG. 48</figref>, the electronic system <b>900</b> may include at least one of the semiconductor device or the semiconductor package according to the embodiments of the inventive concept. The electronic system <b>900</b> may include a mobile device, a computer or the like. For instance, the electronic system <b>900</b> may include a memory system <b>912</b>, a processor <b>914</b>, a RAM <b>916</b>, and a user interface <b>918</b>. Herein, they may perform data communication by using a bus <b>920</b>. The processor <b>914</b> may serve to run a program and control the electronic system <b>900</b>. The RAM <b>916</b> may be used an operating memory of the processor <b>914</b>. For instance, each of the processor <b>914</b> and the RAM <b>914</b> may include the semiconductor devices or the semiconductor package according to the embodiments of the inventive concept. Or, the processor <b>914</b> and the RAM <b>916</b> may be included one package. The user interface <b>918</b> may be used for inputting or outputting data to or from the electronic system <b>900</b>. The memory system <b>912</b> may store a code for operating the processor <b>914</b>, data processed by the processor <b>914</b> or data inputted from the outside. The memory system <b>912</b> may include the controller and the memory and may be configured as the same as the memory card <b>800</b> of <figref idref="DRAWINGS">FIG. 47</figref> substantially.

0157The electronic system <b>900</b> may be applied to an electronic control device of various electronic devices. <figref idref="DRAWINGS">FIG. 49</figref> illustrates that the electronic system <b>900</b> is applied to a mobile phone <b>1000</b>. Besides, the electronic system <b>900</b> may be applied to portable laptops, MP3 players, navigations, Solid State Disks (SSDs), cars, or household appliances.

0158As above-described, according to the inventive concept, since the structure of the TSV of the semiconductor device has the multi-layered insulation layer, electric characteristics and reliability of the semiconductor device may be improved.

0159The above-disclosed subject matter is to be considered illustrative and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments, which fall within the true spirit and scope of the inventive concept. Thus, to the maximum extent allowed by law, the scope of the inventive concept is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.