Method of forming through silicon via with dummy structure

CROSS-REFERENCE TO RELATED APPLICATIONS

0001The present application is a divisional application of U.S. patent application Ser. No. 12/791,978, filed on Jun. 2, 2010, which claims priority of U.S. Provisional Patent Application Ser. No. 61/254,043, filed on Oct. 22, 2009, the entire disclosures of which are incorporated herein by reference.

TECHNICAL

0002The present disclosure relates generally to the field of semiconductor circuits, and more particularly, to a through-silicon-via. (TSV) structure for integrated circuits.

BACKGROUND

0003A through-silicon via (TSV) is a vertical electrical connection passing through a silicon wafer or die. TSV technology is important in creating 3-dimensional (3D) packages and 3D integrated circuits. A 3D package, e.g. system in package, chip stack multi-chip module (MCM), etc., contains two or more chips (integrated circuits) stacked vertically so that they occupy less space.

0004In most 3D packages, the stacked chips arc wired together along their edges; this edge wiring slightly increases the length and width of the package and usually requires an extra interposer layer between the chips. In some new 3D packages, through-silicon vias replace edge wiring by creating vertical connections through the body of the chips. The resulting package has no added length or width. Because no interposer is required, a TSV 3D package can also be flatter than an edge-wired 3D package.

0005A 3D integrated circuit is a single integrated circuit built by stacking silicon wafers and/or dies and interconnecting them vertically so that they are packaged as a single device. By using TSV technology, 3D ICs can pack a great deal of functionality into a small footprint. In addition, critical electrical paths through the device can be drastically shortened, leading to faster operation.

0006However, interface failure between TSV and interconnect pad is problematic. For example, copper TSV connected to an aluminum interconnect pad suffers high thermal stress because of temperature coefficient difference and the large thickness of copper. The failure location is typically at an interface between Cu and Al/AlCu, The cause of the failure is Cu delamination induced by Joule heating or higher temperature.

BRIEF DESCRIPTION OF THE DRAWINGS

0007For a more complete understanding of the present disclosure, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

0008<figref idref="DRAWINGS">FIG. 1A-FIG</figref>. <b>1</b>B are a top view and a cross-sectional view of a through silicon via (TSV) structure including one or more dummy structure according to sonic embodiments;

0009<figref idref="DRAWINGS">FIG. 2A-FIG</figref>. <b>2</b>C are top views of a through silicon via (TSV) structure including one or more dummy structure according to some embodiments; and

0010<figref idref="DRAWINGS">FIG. 3A-FIG</figref>. <b>3</b>L are cross-sectional views of a through silicon via (TSV) structure including one or more dummy structure at various manufacturing stages.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

0011The making and using of various embodiments are discussed in detail below. It should he appreciated, however, that the present disclosure provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use, and do not limit the scope of the invention.

0012A structure of through silicon via (TSV) using one or more dummy structure to improve adhesion to the interconnect pad and a method to fabricate the same are provided. <figref idref="DRAWINGS">FIG. 1A-FIG</figref>. <b>1</b>B are a top view and a cross-sectional view of a through silicon via (TSV) structure including one or more dummy structure according to some embodiments. <figref idref="DRAWINGS">FIG. 1A</figref> shows a top view of the TSV structure <b>100</b>, including a top pad <b>102</b>, an interconnect pad <b>104</b> and dummy structures <b>106</b>. The through silicon via structure <b>100</b> further includes a vertical conductive post <b>105</b> that is connected to the top pad <b>102</b>. The top pad <b>102</b> covers a wider area than the cross section of the vertical conductive post <b>105</b>. An interconnect pad <b>104</b> is located at least partially below the top pad <b>102</b>. An under layer <b>107</b> is also located at least partially below the top pad <b>102</b>. At least one dummy structure <b>106</b> connects the top pad <b>102</b> and the under layer <b>107</b>, fastening the top pad <b>102</b> and the interconnect pad <b>104</b>, The dummy structures <b>106</b> are distributed circularly around the vertical conductive post <b>105</b> in one embodiment.

0013<figref idref="DRAWINGS">FIG. 1B</figref> shows a cross section view of the TSV structure <b>100</b> along the cross section line <b>1</b>B according to one embodiment. The top pad <b>102</b> is connected to the vertical conductive post <b>105</b> to form a TSV. The interconnect pad <b>104</b> is also shown under the top pad <b>102</b>. The dummy structure <b>106</b> connects the top pad <b>102</b> and the under layer <b>107</b> (in <figref idref="DRAWINGS">FIG. 1A</figref>). Depending on implementations, in some embodiments, the under layer <b>107</b> can include a seed layer <b>118</b>, an isolation layer <b>116</b>, the second passivation layer <b>114</b>, any other suitable layer (e.g. dummy interconnect layer), or any combinations thereof.

0014The vertical conductive post <b>105</b> is connected to a backside interconnect layer <b>120</b> through a substrate <b>108</b>. The backside interconnect layer <b>120</b> is shown on top of an electroless nickel/immersion gold (ENIG) layer <b>122</b> and the dicing tape <b>124</b>, On the substrate <b>108</b>, the first passivation layer <b>110</b>, the second passivation layers <b>112</b> and <b>114</b> are also shown.

0015The dummy structures <b>106</b> fasten the top pad <b>102</b> and interconnect pad <b>104</b> to improve the reliability and interconnection performance. The dummy structures <b>106</b> increase the thermal tolerance of the structure and improve the adhesion between the top pad <b>102</b> and the interconnect pad <b>104</b>. The top pad <b>102</b> and the vertical conductive post <b>105</b> can comprise copper, tungsten, or any other suitable material. The top pad <b>102</b> can have a diameter about 15 μm-about 50 μm in some embodiments. The interconnect pad <b>104</b> can comprise Al, AlCu, Cu, or any other suitable material. The interconnect pad <b>104</b> can have a length/width about 5 μm-about 60 μm. The vertical conductive post <b>105</b> can have a depth about 50 μm-about 200 μm in some embodiments, The TSV structure <b>100</b> may have different geometries and dimensions for enhanced performance in various embodiments.

0016The dummy structures <b>106</b> can also comprise copper, tungsten, or any other suitable material. The dummy structures <b>106</b> can have a diameter about 0.5 μm-about 10 μm and a depth about 0.5 μm-about 2 μm in some embodiments. The area ratio between the dummy structure <b>106</b> and the top pad <b>102</b> can be about 5%-about 40% in some embodiments. The interconnect pad <b>104</b> can have a length or a width about 5 μm-about 60 μm in some embodiments. The isolation layer <b>116</b> can comprise dielectric material, and have a thickness of about 0.5 μm-about 2 μm in some embodiments.

0017<figref idref="DRAWINGS">FIG. 2A-FIG</figref>. <b>2</b>C are top views of a through silicon via (TSV) structure including one or more dummy structure according to some embodiments. In <figref idref="DRAWINGS">FIG. 2A</figref>, dummy structures <b>202</b> have, for example, a circular shape, and they are distributed around the vertical conductive post <b>105</b>. The dummy structures <b>202</b> can be distributed uniformly under the top pad <b>102</b> except an area where the top pad <b>102</b> is connected to the vertical conductive post <b>105</b>. The dummy structures <b>202</b> can be distributed in a square grid pattern. In <figref idref="DRAWINGS">FIG. 2B</figref>, the dummy structures <b>204</b> have a linear shape. The linear shape can be a straight line. The dummy structures <b>204</b> can be evenly spaced from each other. The dummy structures <b>204</b> can have at least two different lengths. In <figref idref="DRAWINGS">FIG. 2C</figref>, the dummy structures <b>206</b> also have a linear shape and aligned in a different direction compared to <figref idref="DRAWINGS">FIG. 2B</figref>.

0018<figref idref="DRAWINGS">FIG. 3A-FIG</figref>. <b>3</b>L are cross-sectional views of a through silicon via (TSV) structure including one or more dummy structure at various manufacturing stages. In general, the process includes TSV etching to provide space for TSV, TSV isolation to prevent undesired contact, creating openings for TSV connection with interconnect pad, and TSV plating (e.g., Cu).

0019Referring to <figref idref="DRAWINGS">FIG. 3A</figref>, a substrate <b>108</b> is shown. In one example, the substrate <b>108</b> is a semiconductor wafer. in another example, the substrate <b>108</b> includes a semiconductor chip. In at least one embodiment, the substrate <b>108</b> includes silicon. In some other embodiments, the substrate <b>108</b> may alternatively or additionally include other elementary semiconductor, such as germanium. The substrate <b>108</b> may also include a compound semiconductor, such as silicon carbide, gallium arsenic, indium arsenide, and indium phosphide.

0020The substrate <b>108</b> may include an epitaxial layer. For example, the substrate <b>108</b> may have an epitaxial layer overlying a bulk semiconductor. Further, the substrate <b>108</b> may be strained for performance enhancement. For example, the epitaxial layer may include semiconductor materials different from those of the bulk semiconductor such as a layer of silicon germanium overlying bulk silicon, or a layer of silicon overlying a bulk silicon germanium formed by a process including selective epitaxial growth (SEG). Furthermore, the substrate <b>108</b> may include a semiconductor-on-insulator (SOI) structure. In various examples, the substrate <b>108</b> includes a buried oxide (BOX) layer formed by a process such as separation by implanted oxygen (SIMOX).

0021In some embodiments, the substrate <b>108</b> can include various doped wells and other doped features configured and coupled to form various microelectronic devices such as metal-insulator-semiconductor field effect transistor (MOSFET) including complementary MOSFET (CMOS), imaging sensor including CMOS imaging sensor (CIS), micro-electro-mechanical system (MEMS), and/or other suitable active and/or passive devices, The doped wells and other doped features include p-type doped region and/or an n-type doped region, formed by a doping process such as ion implantation.

0022Other structures such as gate dielectric and polysilicon gate electrodes may be additionally formed on the substrate <b>108</b> for devices such as MOSFET devices. The substrate <b>108</b> also includes various isolation features configured to separate various devices from each other for proper isolation. The isolation features may include different structures and can be formed by certain particular processing technologies. In one example, the isolation features include dielectric isolation such as shallow trench isolation (STI). The STI can be fabricated by etching the substrate to form a trench and filling the trench with a dielectric material.

0023Also, an interconnect structure can formed on the substrate <b>108</b> and configured to properly connect various doped regions in the substrate, resulting in the integrated circuit with designed functions. The interconnect structure can include multilayer interconnect (MLI) having horizontal conductive features (metal lines) disposed at multiple metal layers and vertical conductive features, such as contacts and vias. A via is configured to connect two metal lines at different metal layers. A contact is configured to connect a metal line and the substrate <b>108</b>. The multi layer interconnect may include conductive materials such as aluminum, aluminum/silicon/copper alloy, titanium, titanium nitride, tungsten, polysilicon, metal silicide, or combinations thereof.

0024Aluminum interconnect can be formed by a process including physical vapor deposition (PVD such as PVD by sputtering), chemical vapor deposition (CVD), or combinations thereof. Other manufacturing techniques to form the aluminum interconnect may include photolithography processing and etching to pattern the conductive materials for vertical (via and contact) and horizontal connects (conductive line). In some embodiments, still other manufacturing processes such as thermal annealing may be used to form metal silicide to reduce contact resistance.

0025In some alternative embodiments, a copper or other interconnect may be used. Copper or other interconnect may include copper, copper alloy, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, polysilicon, metal silicide, or combinations thereof. The copper or other interconnect may be formed by a technique such as CVD, sputtering, plating, and/or other suitable processes. The metal silicide used in multilayer interconnects may include nickel silicide, cobalt silicide, tungsten silicide, tantalum silicide, titanium silicide, platinum silicide, erbium silicide, palladium silicide, or combinations thereof.

0026In addition, dielectric material features can be disposed on the substrate <b>108</b> to isolate various conductive elements. The dielectric material features include an interlayer dielectric (ILD) disposed between the substrate and the first metal layer. The dielectric material features also include inter-metal dielectric (IMD) disposed between adjacent metal layers. The dielectric material features include a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or spin-on glass (SOG). The dielectric material, in some alternative embodiments, includes a material of a low dielectric constant (low k) such as a dielectric constant less than about 3.5. in various examples, the dielectric material may include silicon dioxide, silicon nitride, silicon oxynitride, spin-on glass (SOG), fluoride-doped silicate glass (FSG), carbon doped silicon oxide, BLACK DIAMOND® (Applied Materials of Santa Clara, Calif.), Xerogel, Aerogel, amorphous fluorinated carbon, Parylene, BCC (bis-benzocyclobutenes), SILK (Dow Chemical, Midland, Mich.), polyimide, and/or other suitable materials. The dielectric material features can be formed by a technique including spin-on coating, CVD, or other suitable processes.

0027In <figref idref="DRAWINGS">FIG. 3A</figref>, a first passivation layer <b>110</b> is formed on the substrate <b>108</b> and second passivation layers <b>112</b> and <b>114</b> are formed on the e first passivation layer <b>110</b>, The first and second passivation layers each may include various passivation materials. In one embodiment, the first passivation layer <b>110</b> includes silicon oxide. In one example, the silicon oxide passivation layer may have a thickness ranging between about 0.2 μm. and about 2 μm, in another example, the silicon oxide passivation layer may be formed by a high density plasma CVD process. In another embodiment, the second passivation layers <b>112</b> and <b>114</b> comprise silicon nitride and/or silicon oxynitride. In one example, the second passivation layers <b>112</b> and <b>114</b> may have a thickness ranging between about 2 μm and about 6 μm. In one example, a silicon nitride passivation layer is formed by a plasma enhanced CVD (MOM) process. The precursors used to form silicon nitride in CVD include Hexachlorodisilane (Si₂Cl₆), Dichlorosilane (SiH₂Cl₂), Bis(TertiaryButylAmino)Silane (C₈H₂₂N₂Si), and/or Disilane (Si₂H₆).

0028The interconnect pads <b>104</b> are also formed over the substrate <b>108</b>. The interconnect pads <b>104</b> can have a thickness about 1 μm-about 4 μm in some embodiments. The interconnect pads <b>104</b> are disposed on the first passivation layer <b>110</b> and positioned at least partially within the openings of the second passivation layers <b>112</b> and <b>114</b>. In one example, the interconnect pads <b>104</b> include aluminum. In one embodiment of the interconnect pad formation, an aluminum layer is deposited on the first passivation layer <b>110</b> and within the openings of the second passivation layers <b>112</b> and <b>114</b> to connect to interconnect structures. The aluminum layer is then patterned to form the various interconnect pads <b>104</b>. The second passivation layer <b>112</b> and <b>114</b> are deposited on the first passivation layer <b>110</b>. The second passivation layer <b>114</b> deposited on the interconnect pads <b>104</b> is then patterned to expose the interconnect pads <b>104</b>.

0029Interconnect pads <b>104</b> can include conductive materials such as aluminum, aluminum/silicon/copper alloy, titanium, titanium nitride, tungsten, polysilicon, metal silicide, or combinations thereof. Aluminum interconnect pads can be formed by a process including physical vapor deposition (PVD such as PVD by sputtering), chemical vapor deposition (CVD), or combinations thereof. Other manufacturing techniques to form the aluminum interconnect pad may include photolithography processing and etching to pattern the conductive materials for vertical (via and contact) and horizontal connects (conductive line). Still other manufacturing processes such as thermal annealing may be used to form metal silicide to reduce contact resistance. In some alternative embodiments, a copper or other interconnect pad may be used. Copper or other interconnect pad may include copper, copper alloy, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, polysilicon, metal silicide, or combinations. The copper or other interconnect may be formed by a technique such as CVD, sputtering, plating, or other suitable processes. The metal suicide used in multilayer interconnects may include nickel silicide, cobalt suicide, tungsten silicide, tantalum silicide, titanium silicide, platinum silicide, erbium silicide, palladium silicide, or combinations thereof.

0030In <figref idref="DRAWINGS">FIG. 3A</figref>, TSV etching such as a dry plasma etching process is performed to form the TSV opening <b>302</b> through the first passivation layer <b>110</b>, the second passivation layers <b>112</b> and <b>114</b>. Plasma etch can be performed in several modes by adjusting the parameters of the plasma. Ordinary plasma etching operates between 0.1 and 5 torr. The plasma produces energetic free radicals, neutrally charged, that react at the surface of the wafer. Since neutral particles attack the wafer from all angles, this process is isotropic. The source gas for the plasma usually contains small molecules rich in chlorine or fluorine. For instance, in some embodiments, carbon tetrachloride (CC14) can be used to etch silicon and aluminum, and trifluoromethane can be used to etch silicon dioxide and silicon nitride.

0031In <figref idref="DRAWINGS">FIG. 3B</figref>, additional TSV etching such as a dry plasma etching process is performed to form a deeper TSV opening <b>302</b> partially through the substrate <b>108</b>. In some embodiments, the TSV opening <b>302</b> does not extend all the way through the substrate <b>108</b>, but the rest of the substrate <b>108</b> can be removed later. For example, backside polishing at a later stage can be performed.

0032In <figref idref="DRAWINGS">FIG. 3C</figref>, the isolation layer <b>116</b> is deposited over the interconnect pads <b>104</b> and the second passivation layer <b>114</b>. The isolation layer <b>116</b> may comprise silicon oxide layer, tetraethoxysilane (TEOS), silica glass, or any other suitable material. The isolation layer <b>116</b> may have a thickness about 0.5 μm-about 2 μm in one embodiment.

0033In <figref idref="DRAWINGS">FIG. 3D</figref>, photo resist (PR) layer <b>304</b> can be deposited by spray coating or spin coating, and then openings <b>303</b> for dummy structures are etched out. In one embodiment, the thickness of PR layer <b>304</b> can be about 1 μm-about 5 μm. In one example, spin coating is used to form thin films with uniform thickness over flat substrates. An excess amount of a solution is placed on the substrate, which is then rotated at high speed in order to spread the fluid by centrifugal force. Rotation is continued while the fluid spins off the edges of the substrate, until the desired thickness of the film is achieved. Photoresist is typically spun at 20 to 80 revolutions per second for 30 to 60 seconds.

0034In <figref idref="DRAWINGS">FIG. 3E</figref>, PR layer <b>304</b> is removed and seed layer <b>118</b> is deposited. The seed layer <b>118</b> can comprise Cu, Ti, TiN, W, any other suitable material, or any combinations thereof in some embodiments. In one example, a copper seed layer can be formed by physical vapor deposition (PVD) such as PVD by sputtering. In one embodiment, the seed layer <b>118</b> can have a thickness ranging between about 10 nm and about 600 nm.

0035In <figref idref="DRAWINGS">FIG. 3F</figref>, another PR layer <b>306</b> is formed. The PR layer <b>306</b> can be either liquid PR or dry film PR. The PR layer <b>306</b> prevents metal deposit in undesired areas in the next stage.

0036In <figref idref="DRAWINGS">FIG. 3G</figref>, a TSV including top pad <b>102</b> and vertical conductive post <b>105</b> is formed as well as dummy structures <b>106</b> over the seed layer <b>118</b> by a suitable method such as plating a metal layer (e.g. copper, tungsten, any other suitable material). Other process may be further followed. For example, a chemical mechanic polishing (CMP) process may he applied thereafter to planarize the surface. The metal layer may be further patterned to form the TSV. For example, if a copper layer is implemented, then a damascene process can be used to form patterned copper features including TSV. In one embodiment, the top pad <b>102</b> of the TSV is connected to one of the interconnect pads <b>104</b>. In some embodiments, wafers and/or chips can be stacked vertically and coupled through TSV features. Such TSV 3D package creates vertical connections through chip body and eliminates additional wire. The top pad <b>102</b> may have a diameter about 15 μm-50 μm and the vertical conductive post <b>105</b> may have a depth about 50 μm-200 μm in embodiments. The top pad <b>102</b> and the vertical conductive post <b>105</b> of the TSV may have different geometries and dimensions for enhanced performance in various embodiments.

0037In <figref idref="DRAWINGS">FIG. 3H</figref>, the PR film <b>306</b> is removed and seed layer <b>118</b> outside the top pad <b>102</b> area is etched out. In one embodiment, a liquid resist stripper can be used, which chemically alters the resist so that it no longer adheres to the layer below. In some alternative embodiments, photoresist may be removed by ashing, i.e. a plasma containing oxygen that oxidizes the photoresist.

0038In <figref idref="DRAWINGS">FIG. 3I</figref>, a carrier <b>308</b> is placed over the substrate <b>108</b> so that the backside processing of the substrate <b>108</b> can be performed.

0039In <figref idref="DRAWINGS">FIG. 3J</figref>, the backside of the substrate <b>108</b> is ground and polished. The backside polishing process thins the substrate <b>108</b> and exposes the vertical conductive post <b>105</b> of the TSV from the backside of the substrate <b>108</b> for 3-D packaging, For example, the TSV can be coupled to other wafer/chip in embodiments.

0040In <figref idref="DRAWINGS">FIG. 3K</figref>, interconnect layer <b>120</b> and electroless nickel/immersion gold (ENIG) layer <b>122</b> can be formed. In one example, aluminum sputtering can be performed to form the interconnect layer <b>120</b> with a thickness of about 1 μm to about 5 μm. The ENIG layer <b>122</b> can have a thickness of about 100 nm-about 4 μm.

0041In <figref idref="DRAWINGS">FIG. 3L</figref>, the carrier <b>308</b> is debonded and dicing tape <b>124</b> is put on under the substrate <b>108</b>. In one example, the dicing tape <b>124</b> can comprise a polymer tape. The dicing tape <b>124</b> has a sticky backing that holds the wafer on a thin sheet metal frame. Once a wafer has been diced, the remaining components that are left on the dicing tape <b>124</b> are referred to as die, dice or dies. The die will stay on the dicing tape <b>124</b> until they are extracted by die handling equipment, like a die bonder or die sorter, further in the electronics assembly process.

0042The TSV structure <b>100</b> disclosed herein can improve its temperature tolerance. For example, a conventional structure contact resistance shifted significantly within one day under one stress test. In comparison, the TSV structure <b>100</b> using one or more dummy structure <b>106</b> as described above can keep the same performance more than 2000 hrs under the same stress test. A skilled person in the art will appreciate that there can be many embodiment variations of this invention.

0043Although exemplary embodiments of the present invention and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims, Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, and composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure herein, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.