Random number generator

PRIORITY STATEMENT

p-0002This application claims the benefit of Korean Patent Application No. 10-2007-0105768, filed on Oct. 19, 2007, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

BACKGROUND

p-00031. Field

p-0004Example embodiments relate to a random number generator, and more particularly, to a random number generator capable of increasing its performance without an increase in a circuit area and/or circuit manufacturing costs.

p-00052. Description of the Related Art

p-0006As information and communication based technologies have developed, encryption and decryption have become important as a way to protect the confidentiality of information. Random numbers are used in many applications such as the generation of secret keys for security systems. Accordingly, systems in which security is important use random number generators. Random number generators necessarily generate unpredictable random numbers.

p-0007In systems in which security is important, random numbers are not permitted to have periodicity or be regular. In more detail, security systems need to generate perfect random numbers that are unpredictable and have no periodicity. True random numbers (TRNs) are generated from physical noise sources, are unpredictable, and have no periodicity.

p-0008In order to generate TRNs, conventional random number generators have used thermal noise or shot noise as a noise source. Alternatively, conventional random number generators have generated clock signals having irregular periods using ring oscillators.

p-0009<figref idrefs="DRAWINGS">FIG. 1A</figref> is a diagram of a related art random number generator. <figref idrefs="DRAWINGS">FIG. 1B</figref> is a diagram of signals that are input into and output from the related art random number generator of <figref idrefs="DRAWINGS">FIG. 1A</figref>. The related art random number generator will now be described with reference to <figref idrefs="DRAWINGS">FIGS. 1A and 1B</figref>.

p-0010Referring to <figref idrefs="DRAWINGS">FIG. 1A</figref>, a related art random number generator <b>100</b> may comprise a signal terminal <b>103</b> that receives a signal clock S_in, a clock terminal <b>105</b> that receives a clock signal S_CLK, and a sampling block <b>101</b>.

p-0011The signal clock S_in that is input into the signal terminal <b>103</b> may be a high frequency clock signal may have a regular and short period.

p-0012The clock signal S_CLK that is input into the clock terminal <b>105</b> may be a low frequency clock signal has irregular period and duty cycle. The clock signal S_CLK may have a period longer than the signal clock S_in.

p-0013The sampling block <b>101</b> may be synchronized with the clock signal S_CLK and sample the signal clock S_in in accordance with a rising edge of the clock signal S_CLK.

p-0014Referring to <figref idrefs="DRAWINGS">FIG. 1B</figref>, the signal clock S_in <b>110</b> may be a signal having regular periods each having the same duty cycle. The clock signal S_CLK <b>115</b> may be a signal having irregular periods, some or all having a different duty cycle.

p-0015The sampling block <b>101</b> may perform a sampling operation and output a random number signal S_RN <b>120</b>.

p-0016The random number signal S_RN <b>120</b> may sample a value of the signal clock S_in <b>110</b> every rising edge of the clock signal S_CLK <b>115</b> and generate the random number signal S_RN. Therefore, the sampling block <b>101</b> may sample the value of the signal clock S_in at a point a, outputs the value “1”, and generate the value “0” at a point b, the value “0” at a point c, the value “0” at a point d, and the value “1” at a point f.

p-0017As described above, the clock signal S_CLK must have irregular period and duty cycle. A related art random number generator may use a ring oscillator (RO) in order to generate the clock signal S_CLK.

p-0018The RO performs an oscillation operation and outputs an oscillation signal having a jitter in order to produce an irregular period.

p-0019The oscillation signal that is output from the RO will now be described with reference to <figref idrefs="DRAWINGS">FIG. 2</figref>.

p-0020<figref idrefs="DRAWINGS">FIG. 2</figref> is a waveform diagram of the generation of an oscillation signal. Referring to <figref idrefs="DRAWINGS">FIG. 2</figref>, an RO (not shown) performs an inversion operation for inverting a logic level at an initial duration <X>, so that a sine waveform signal having a predetermined or given period Tosc is output. A signal <b>210</b> that is output at the duration <X> may be a stabilized oscillation signal.

p-0021The RO continuously performs an oscillation operation. After a period of time of a duration <Y> further passes, the RO outputs an oscillation signal having jitter. Jitter is a shake of a signal on a temporal axis (a coordinate at an axis x) due to accumulated noise.

p-0022Therefore, a curve signal may shake and its real value lies between <b>215</b> and <b>220</b> at a duration <Z>. So, at the duration <Z>, a period and its duty cycle are irregular.

p-0023The related art random number generator must perform a sampling operation according to a signal having an irregular signal in order to generate a true random number. The signal having the irregular signal must be generated after passing the durations <X> and <Y>. Therefore, the related art random number generator cannot output a random number immediately after the RO starts its operation but after at least a period of time of the durations <X> and <Y> elapses.

p-0024The related art random number generator may output random number data after an oscillation signal having the jitter is generated, which reduces throughput.

p-0025The related art random number generator additionally may contain a circuit for generating and providing noise in order to artificially provide physical noise and generate the oscillation signal having jitter. This circuit may increase an area and/or manufacturing cost of the conventional random number generator.

SUMMARY

p-0026Example embodiments provide a random number generator capable of increasing throughput without an increase in circuit area or manufacturing cost.

p-0027Example embodiments provide a random number generator that performs an oscillation operation using a meta stable voltage.

p-0028According to example embodiments, there is provided a random number generator comprising: a clock generator outputting first and second control signals; a ring oscillator (RO) block receiving a meta stable voltage and/or performing an oscillation operation using the meta stable voltage in response to the first control signal; and a sampling unit sampling an output signal according to the oscillation operation in response to the second control signal.

p-0029The RO block may generate or receive the meta stable voltage in response to one logic level of the first control signals and perform an RO operation using the meta stable voltage in response to another logic level of the first control signal.

p-0030The meta stable voltage may have an intermediate (for example, close to mean) value between a voltage value of a logic low signal and a voltage value of a logic high signal.

p-0031According to example embodiments, there is provided a random number generator comprising: a clock generator outputting first and second control signals; an RO block receiving a meta stable voltage in response to one logic level of the first control signals and/or for performing an RO operation using the meta stable voltage in response to another logic level of the first control signal; and a sampling unit sampling an output signal according to the oscillation operation in response to the second control signal.

p-0032The RO block may comprise: a variable delay unit varying a delay amount in response to the first control signal; and an inverting element connected in series with an output end of the variable delay unit and comprising one or odd number of inverting elements performing the RO operation, wherein an output end of the inverting element and an input end of the variable delay unit are connected via a feedback path.

p-0033According to example embodiments, a physical or intrinsic noise, for example, noise generated by heat, by one or more components of a random number generator may be used to introduce non-periodicity, irregularity, and/or and unpredictability.

BRIEF DESCRIPTION OF THE DRAWINGS

p-0034The above and other features and advantages of example embodiments will become more apparent by describing them in detail with reference to the attached drawings in which:

p-0035<figref idrefs="DRAWINGS">FIG. 1A</figref> is a diagram of a related art random number generator;

p-0036<figref idrefs="DRAWINGS">FIG. 1B</figref> is a diagram of signals that are input into and output from the related art random number generator of <figref idrefs="DRAWINGS">FIG. 1A</figref>;

p-0037<figref idrefs="DRAWINGS">FIG. 2</figref> is a waveform diagram of the generation of an oscillation signal;

p-0038<figref idrefs="DRAWINGS">FIG. 3A</figref> is a diagram of a random number generator according to example embodiments;

p-0039<figref idrefs="DRAWINGS">FIG. 3B</figref> is an example diagram of a signal that is input into and output from the random number generator of <figref idrefs="DRAWINGS">FIG. 3A</figref>;

p-0040<figref idrefs="DRAWINGS">FIG. 3C</figref> is an example waveform diagram for explaining the generation of a signal oscillated in the random number generator of <figref idrefs="DRAWINGS">FIG. 3A</figref>;

p-0041<figref idrefs="DRAWINGS">FIG. 3D</figref> is an example waveform diagram for explaining the operation of the random number generator of <figref idrefs="DRAWINGS">FIG. 3A</figref>;

p-0042<figref idrefs="DRAWINGS">FIG. 4</figref> is a diagram of a random number generator according to example embodiments;

p-0043<figref idrefs="DRAWINGS">FIG. 5</figref> is a diagram of a random number generator according to example embodiments;

p-0044<figref idrefs="DRAWINGS">FIG. 6</figref> is a diagram of a random number generator according to example embodiments;

p-0045<figref idrefs="DRAWINGS">FIG. 7A</figref> is a diagram of a random number generator according to example embodiments;

p-0046<figref idrefs="DRAWINGS">FIG. 7B</figref> is an example diagram of an operation of the random number generator of <figref idrefs="DRAWINGS">FIG. 7A</figref>;

p-0047<figref idrefs="DRAWINGS">FIG. 8</figref> is a diagram of a random number generator according to example embodiments; and

p-0048<figref idrefs="DRAWINGS">FIG. 9</figref> is a diagram of a random number generator according to example embodiments.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

p-0049Example embodiments will be more clearly understood from the detailed description taken in conjunction with the accompanying drawings.

p-0050Various example embodiments will now be described more fully with reference to the accompanying drawings in which some example embodiments are shown. In the drawings, the thicknesses of layers and regions may be exaggerated for clarity.

p-0051Detailed illustrative embodiments are disclosed herein. However, specific structural and functional details disclosed herein are merely representative for purposes of describing example embodiments. This invention may, however, may be embodied in many alternate forms and should not be construed as limited to only example embodiments set forth herein.

p-0052Accordingly, while example embodiments are capable of various modifications and alternative forms, embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that there is no intent to limit example embodiments to the particular forms disclosed, but on the contrary, example embodiments are to cover all modifications, equivalents, and alternatives falling within the scope of the invention. Like numbers refer to like elements throughout the description of the figures.

p-0053It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of example embodiments. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

p-0054It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. Other words used to describe the relationship between elements should be interpreted in a like fashion (e.g., “between” versus “directly between”, “adjacent” versus “directly adjacent”, etc.).

p-0055The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises”, “comprising”, “includes” and/or “including”, when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

p-0056It should also be noted that in some alternative implementations, the functions/acts noted may occur out of the order noted in the FIGS. For example, two FIGS. shown in succession may in fact be executed substantially concurrently or may sometimes be executed in the reverse order, depending upon the functionality/acts involved.

p-0057Also, the use of the words “compound,” “compounds,” or “compound(s),” refer to either a single compound or to a plurality of compounds. These words are used to denote one or more compounds but may also just indicate a single compound.

p-0058Now, in order to more specifically describe example embodiments, various embodiments will be described in detail with reference to the attached drawings. However, the present invention is not limited to example embodiments, but may be embodied in various forms. In the figures, if a layer is formed on another layer or a substrate, it means that the layer is directly formed on another layer or a substrate, or that a third layer is interposed therebetween. In the following description, the same reference numerals denote the same elements.

p-0059Although example embodiments have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.

p-0060Example embodiments will be described in detail with reference to the attached drawings. Throughout the drawings, like reference numerals refer to like elements.

p-0061<figref idrefs="DRAWINGS">FIG. 3A</figref> is a diagram of a random number generator <b>300</b> according to example embodiments. Referring to <figref idrefs="DRAWINGS">FIG. 3A</figref>, the random number generator <b>300</b> may comprise a ring oscillator (RO) block <b>310</b>, a clock generator <b>330</b>, and/or a sampling unit <b>340</b>.

p-0062The RO block <b>310</b> may comprise a meta stable voltage offering unit <b>312</b>, an odd number of inverting elements <b>315</b>, <b>316</b>, and <b>317</b>, and/or a plurality of switching units <b>321</b>, <b>322</b>, and <b>323</b>.

p-0063The odd number (including one) of inverting elements may be inverters <b>315</b>, <b>316</b>, and <b>317</b>. Hereinafter, inverting elements are the inverters <b>315</b>, <b>316</b>, and <b>317</b>.

p-0064Alternatively, the inverting elements may be NAND gates, NOR gates, or XNOR gates, instead of inverters. The input part of NAND gates, NOR gates, or XNOR gates may receive a common input signal.

p-0065The meta stable voltage offering unit <b>312</b> may generate and output a meta stable voltage. The meta stable voltage is a voltage having an intermediate value of a logic low voltage value and a logic high voltage value. For example, a CMOS outputting 0V and 2V as logic low and logic high may use 0.753V as an example of a meta stable voltage.

p-0066The odd number of inverters <b>315</b>, <b>316</b>, and <b>317</b> and the plurality of switching units <b>321</b>, <b>322</b>, and <b>323</b> having the same number as the inverters (for example), may alternatively be connected in series with each other.

p-0067Each of the plurality of switching units <b>321</b>, <b>322</b>, and <b>323</b> may perform a switching operation in response to a first control signal CLK_con. For example, each of the plurality of switching units <b>321</b>, <b>322</b>, and <b>323</b> may connect a switching terminal to a terminal S<b>1</b> in response to one logic level (hereinafter referred to as a first logic level) of the first control signal CLK_con, and the switching terminal to a terminal S<b>2</b> in response to another logic level (hereinafter referred to as a second logic level) of the first control signal CLK_con. A representative switching unit may be a multiplexer MUX or any other element capable of performing a switching operation.

p-0068The clock generator <b>330</b> may comprise a control clock generator <b>331</b> and a delay unit <b>333</b>. The control clock generator <b>331</b> may generate and output the first control signal CLK_con.

p-0069The delay unit <b>333</b> may receive the first control signal CLK_con, delay the received first control signal CLK_con for a predetermined or desired period of time, and output a second control signal CLK_sp. The first control signal CLK_con and the second control signal CLK_sp may be clock signals.

p-0070The sampling unit <b>340</b> may receive the second control signal CLK_sp as a clock terminal and an output signal D of the RO block <b>310</b> as a data input terminal. The sampling unit <b>340</b> may sample the output signal D that is synchronized with the second control signal CLK_sp. The sampling unit <b>340</b> may use a flip-flop or any other elements capable of performing a sampling operation. The sampling operation of the sampling unit <b>340</b> may output random number data S_out.

p-0071<figref idrefs="DRAWINGS">FIG. 3B</figref> is an example diagram of a signal that is input into and output from the random number generator <b>300</b> of <figref idrefs="DRAWINGS">FIG. 3A</figref>. <figref idrefs="DRAWINGS">FIG. 3C</figref> is an example waveform diagram for explaining the generation of a signal oscillated in the random number generator <b>300</b> of <figref idrefs="DRAWINGS">FIG. 3A</figref>. <figref idrefs="DRAWINGS">FIG. 3D</figref> is an example waveform diagram for explaining the operation of the random number generator <b>300</b> of <figref idrefs="DRAWINGS">FIG. 3A</figref>.

p-0072The operation of the random number generator <b>300</b> of <figref idrefs="DRAWINGS">FIG. 3A</figref> will now be described with reference to <figref idrefs="DRAWINGS">FIGS. 3B through 3D</figref>.

p-0073Referring to <figref idrefs="DRAWINGS">FIG. 3A</figref>, the random number generator <b>300</b> may output the first control signal CLK_con that is a clock signal having a predetermined or desired period.

p-0074The operation of the random number generator <b>300</b> of example embodiments may be divided into two operation modes. In a first operation mode, the first control signal CLK_con has a first logic level (for example, a logic low level). In a second operation mode, the first control signal CLK_con has a second logic level (for example, a logic high level).

p-0075In the first operation mode indicated as “MS” of a diagram <b>353</b>, the switching terminals of the switching units <b>321</b>, <b>322</b>, and <b>323</b> may be connected to the terminal S<b>1</b>, so that each of the inverters <b>315</b>, <b>316</b>, and <b>317</b> receives the meta stable voltage that is output from the meta stable voltage offering unit <b>312</b>.

p-0076In the second operation mode indicated as “Gener” of the diagram <b>353</b>, the switching terminals of the switching units <b>321</b>, <b>322</b>, and <b>323</b> may be connected to the terminal S<b>2</b>, so that the RO block <b>310</b> forms an inverter chain and performs an RO operation.

p-0077Referring to <figref idrefs="DRAWINGS">FIG. 3B</figref>, the first and second operation modes may be alternately performed. After the first operation mode is performed, the meta stable voltage may be applied to an input end of each of the inverters <b>315</b>, <b>316</b>, and <b>317</b>. Thereafter, the second operation mode is performed, so that the RO block <b>310</b> formed as the inverter chain may perform the RO operation using the meta stable voltage. In the second operation mode, data D generated by the RO operation may be output. The oscillation operation is an operation of a circuit that repeatedly varies between high and low logic levels.

p-0078Referring to <figref idrefs="DRAWINGS">FIG. 3C</figref>, the RO block <b>310</b> may generate and output a signal. In the first operation mode in which the first control signal CLK_con has the first logic level, meta stable voltages MS are applied to the input end of each of the inverters <b>315</b>, <b>316</b>, and <b>317</b>. The meta stable voltages MS are points <b>361</b> and <b>362</b>.

p-0079In the second operation mode in which the first control signal CLK_con has the second logic level, the switching terminals are connected to the terminal S<b>2</b> to start the RO operation. Signals that are output by the oscillation operation are curves <b>363</b> and <b>365</b>.

p-0080Inverters (for example, <b>315</b>) may generate heat due to circuit operation. The heat may be a source of an irreversible noise. For example, the inverter <b>315</b> itself has a thermal noise. Inverting elements other than the inverter <b>315</b> generate some heat by their own circuit operations. For example, a circuit element included in the RO block <b>310</b> has a thermal noise.

p-0081The meta stable voltages MS <b>361</b> and <b>362</b> toggle up or down due to the thermal noise of the inverting elements. Because irregular thermal noise is applied when the RO block <b>310</b> outputs data D, it is not informed of whether the meta stable voltages MS <b>361</b> and <b>362</b> starts toggling up or down.

p-0082The curve <b>363</b> indicating a signal output from the RO block <b>310</b> starts toggling up due to the thermal noise.

p-0083The curve <b>365</b> indicating another signal output from the RO block <b>310</b> starts toggling down at first due to the thermal noise.

p-0084A sampling value changes according to the direction the curves <b>363</b> and <b>365</b> start toggling. For example, at a section A<b>1</b>, a logic low value is sampled in the curve <b>363</b>, whereas a logic high value is sampled in the curve <b>365</b>. At a section A<b>2</b>, a logic high value is sampled in the curve <b>363</b>, whereas a logic low value is sampled in the curve <b>365</b>. For example, the random number generator <b>300</b> has non-periodicity and unpredictability.

p-0085The sampling unit <b>340</b> may perform the sampling operation at a section t<b>2</b> in which a stable oscillation is carried out.

p-0086At a section t<b>1</b>, a transition process is carried out. For example, if the oscillation starts, amplitude increases and converges to a predetermined or given value. The section t<b>1</b> between the start and end of the oscillation is referred to as a transition process section. A period of time taken for the transition process section t<b>1</b> has a very small value (generally, a nano sec. value) within several periods generally.

p-0087Because the sampling operation of the sampling unit <b>340</b> is carried out after the transition process section t<b>1</b> elapses, the second control signal CLK_sp that is a sampling clock is a phase delayed signal by a predetermined or given delay amount compared to the first control signal CLK_con. The predetermined or given delay amount may be determined according to the period of time taken for the transition process section t<b>1</b>. The time taken for the transition process section t<b>1</b> is a value that may be changed according to maximum voltage amplitude, or specification of inverting elements (for example, inverters). Therefore, the predetermined or given delay amount may be set to a different value, depending on the situation.

p-0088The random number generator <b>300</b> may perform the RO operation after applying the meta stable voltage (the first operation mode), and has irregularity and non-periodicity. Therefore, the random number generator <b>300</b> may output the random number data D having irregularity and non-periodicity without waiting for the generation of an oscillation signal having a jitter. For example, in comparison with the random number generator <b>300</b> and the conventional random number generator, the random number generator <b>300</b> does not need to wait until time taken for the sections <X> and <Y> shown in <figref idrefs="DRAWINGS">FIG. 2</figref>, which increases throughput per hour compared to the conventional random number generator.

p-0089Further, the random number generator <b>300</b> does not need additional circuits for generating and providing a separate noise source or increasing throughput per hour, thereby reducing a circuit area and circuit manufacturing cost.

p-0090When the oscillation signal having the jitter (between <b>215</b> and <b>220</b> of <figref idrefs="DRAWINGS">FIG. 2</figref>) is similarly synchronized with a sampling clock signal (corresponding to the second clock signal of example embodiments), it is difficult for the related art random number generator to generate a true random number having non-periodicity, and security of a system is suspect. However, the random number generator <b>300</b> may perform an oscillation operation by applying a thermal noise of the circuit to the metal stable voltage signal, thereby generating a true random number having regular non-periodicity and irregularity. Therefore, the random number generator <b>300</b> may maintain the security of the system compared to the related art random number generator.

p-0091Referring to <figref idrefs="DRAWINGS">FIG. 3D</figref> illustrating the operation of the RO block <b>310</b>, an axis y is an output end signal D of the RO block <b>310</b>, and is a voltage value. An axis x is a period of time elapsed. A signal <b>381</b> is a waveform of the first control signal to divide the first and second operation modes.

p-0092At sections <a<b>2</b>> and <a<b>4</b>>, the second operation mode is carried out. At sections <a<b>3</b>> and <a<b>5</b>>, the first operation mode is carried out. At the section <a<b>2</b>>, toggling starts up (toward a logic low level) at a duration <b>371</b>. The first operation mode is carried out at the section <a<b>3</b>>. A voltage level is the meta stable voltage level. Toggling starts up at a duration <b>373</b>. Toggling having an amplitude value that cannot be recognized as a signal is disregarded. At a duration <b>375</b>, toggling starts down. Toggling starts up at a duration <b>377</b>.

p-0093As described above, because a different thermal noise is applied to the RO block <b>310</b>, the RO block <b>310</b> has an irregular toggling direction. Therefore, the data D that is output in the table <b>355</b> of <figref idrefs="DRAWINGS">FIG. 3B</figref> includes 1, 1, 0, and 1 at random.

p-0094<figref idrefs="DRAWINGS">FIG. 4</figref> is a diagram of a random number generator <b>400</b> according to example embodiments. A switching unit is used as a MUX in <figref idrefs="DRAWINGS">FIGS. 4</figref>, <b>5</b>, and <b>6</b>.

p-0095Referring to <figref idrefs="DRAWINGS">FIG. 4</figref>, the random number generator <b>400</b> may comprise a single switching unit <b>421</b> compared to the random number generator <b>300</b> of <figref idrefs="DRAWINGS">FIG. 3A</figref>. A control clock generator <b>431</b> may output a first control signal CLK_con that is applied to the switching unit <b>431</b> only.

p-0096In example embodiments, the switching unit <b>421</b> is connected in series with an output end of a first arranged inverter <b>415</b>. However, the switching unit <b>421</b> may be connected in series with one of output ends of a plurality of inverters.

p-0097The operation and configuration of the random number generator <b>400</b> are the same as those of the random number generator <b>300</b> of <figref idrefs="DRAWINGS">FIG. 3A</figref>.

p-0098<figref idrefs="DRAWINGS">FIG. 5</figref> is a diagram of a random number generator <b>500</b> according to example embodiments. Referring to <figref idrefs="DRAWINGS">FIG. 5</figref>, the random number generator <b>500</b> is different from the random number generator <b>300</b> of <figref idrefs="DRAWINGS">FIG. 3A</figref> in the configuration of a clock generator <b>530</b>.

p-0099The clock generator <b>530</b> of the random number generator <b>500</b> may comprise a control clock generator <b>531</b> and a sampling clock generator <b>533</b>. The control clock generator <b>531</b> may generate and outputs a first control signal CLM_con. The sampling clock generator <b>533</b> may output a second control signal CLK_sp.

p-0100The operation and configuration of the random number generator <b>500</b> are the same as those of the random number generator <b>300</b> of <figref idrefs="DRAWINGS">FIG. 3A</figref>.

p-0101<figref idrefs="DRAWINGS">FIG. 6</figref> is a diagram of a random number generator <b>600</b> according to example embodiments. Referring to <figref idrefs="DRAWINGS">FIG. 6</figref>, the random number generator <b>600</b> may comprise an RO block <b>610</b>, a clock signal generator <b>630</b>, and/or a sampling unit <b>640</b>.

p-0102The RO block <b>610</b> may comprise a delay unit <b>620</b>, a switching unit <b>614</b>, a meta stable voltage offering unit <b>612</b>, and/or a single inverting element <b>616</b>. In example embodiments, the switching unit <b>614</b> is a MUX, and the inverting element <b>616</b> is an inverter. A logic element may be used as the switching unit <b>614</b> and the inverting element <b>616</b> as shown in <figref idrefs="DRAWINGS">FIG. 3A</figref>.

p-0103The delay unit <b>620</b> may receive a feedback signal D that is output from the RO block <b>610</b>. The delay unit <b>620</b> may have a predetermined or given delay amount, delay an input signal by the predetermined or given delay amount, and output the delayed signal to a terminal S<b>2</b> that is one input terminal of the switching unit <b>614</b>.

p-0104The switching unit <b>614</b> may connect a first node N<b>1</b> to one of terminals S<b>1</b> and S<b>2</b> in response to the first control signal CLK_con.

p-0105The switching unit <b>614</b>, the meta stable voltage offering unit <b>612</b>, and the single inverting element <b>616</b> of the RO block <b>610</b> may correspond to the switching unit <b>321</b>, the meta stable voltage offering unit <b>312</b>, and the single inverting element <b>315</b> of <figref idrefs="DRAWINGS">FIG. 3A</figref>, respectively, and each corresponding constituent may perform the same operation.

p-0106The random number generator <b>600</b> may have an odd number of inverting elements <b>616</b> that are connected in series with each other as shown in <figref idrefs="DRAWINGS">FIG. 3A</figref>.

p-0107The clock signal generator <b>630</b> may correspond to the clock generator <b>330</b> of <figref idrefs="DRAWINGS">FIG. 3A</figref>. Therefore, the clock signal generator <b>630</b> may comprise a control clock generator (not shown) (corresponding to the control clock generator <b>331</b> of <figref idrefs="DRAWINGS">FIG. 3A</figref>) and a delay unit (not shown) (corresponding to the delay unit <b>333</b> of <figref idrefs="DRAWINGS">FIG. 3A</figref>).

p-0108The clock signal generator <b>630</b> may generate and output a first control signal CLk-con and a second control signal CLK_sp.

p-0109With regard to the operation of the random number generator <b>600</b> shown in <figref idrefs="DRAWINGS">FIG. 6</figref>, the clock signal generator <b>630</b> may output the first control signal CLK_con to a first logic level (that is a logic level for entering the RO block <b>610</b> into an MS mode). A switching terminal may connect the first node N<b>1</b> and a terminal S<b>1</b>, so that a meta stable voltage is supplied to an input terminal of the inverter <b>616</b>.

p-0110The clock signal generator <b>630</b> may output the first control signal CLK_con to a second logic level (that is a logic level for entering the RO block <b>610</b> into a Gener. operation mode). The switching terminal may connect the first node N<b>1</b> to a terminal S<b>2</b>. Therefore, the inverter <b>616</b> and the delay unit <b>620</b> may be connected in series with each other and generate a single feedback loop. The feedback loop performs an RO operation using the meta stable voltage applied to the first node N<b>1</b>.

p-0111The operation and configuration of the sampling unit <b>640</b> are the same as those of the sampling unit <b>340</b> of <figref idrefs="DRAWINGS">FIG. 3A</figref>. The second control signal CLK_sp may be the same as that of <figref idrefs="DRAWINGS">FIG. 3A</figref>.

p-0112<figref idrefs="DRAWINGS">FIG. 7A</figref> is a diagram of a random number generator <b>700</b> according to example embodiments. <figref idrefs="DRAWINGS">FIG. 7B</figref> is a diagram of an operation of the random number generator <b>700</b> of <figref idrefs="DRAWINGS">FIG. 7A</figref>.

p-0113The operation and configuration of the random number generator <b>700</b> will now be described with reference to <figref idrefs="DRAWINGS">FIGS. 7A and 7B</figref>.

p-0114Referring to <figref idrefs="DRAWINGS">FIG. 7A</figref>, the random number generator <b>700</b> may comprise an RO block <b>710</b>, a clock signal generator <b>730</b>, and/or a sampling unit <b>740</b>.

p-0115The RO block <b>710</b> may comprise a variable delay unit <b>712</b> and an inverting element <b>714</b>. The inverting element <b>714</b> may be singular as shown or an even number of inverting elements <b>714</b> may be connected in series with each other. In example embodiments, the inverting element <b>714</b> is an inverter.

p-0116The configuration and operation of the inverting element <b>714</b>, the clock generator <b>730</b>, and the sampling unit <b>740</b> are the same as those of the inverting element <b>315</b>, the clock generator <b>330</b> (or the clock generator <b>630</b> of <figref idrefs="DRAWINGS">FIG. 6</figref>), and the sampling unit <b>340</b> of <figref idrefs="DRAWINGS">FIG. 3A</figref>, respectively.

p-0117The variable delay unit <b>712</b> may vary a delay amount in response to a first control signal CLK_con. The varied delay amount will now be described.

p-0118The delay amount of the variable delay unit <b>712</b> is <img id="CUSTOM-CHARACTER-00001" he="3.13mm" wi="2.46mm" file="US20090106339A1-20090423-P00001.TIF" img-content="character" img-format="tif" orientation="portrait" inline="no" />_VD. A delay amount of the inverting element <b>714</b> is <img id="CUSTOM-CHARACTER-00002" he="3.13mm" wi="2.46mm" file="US20090106339A1-20090423-P00001.TIF" img-content="character" img-format="tif" orientation="portrait" inline="no" />_INV. A parasitic RC (resistance and capacitance) characteristics of a feedback loop that connects an output end of the RO block <b>710</b> and an input end of the variable delay unit <b>712</b> is <img id="CUSTOM-CHARACTER-00003" he="3.13mm" wi="2.46mm" file="US20090106339A1-20090423-P00001.TIF" img-content="character" img-format="tif" orientation="portrait" inline="no" />_RCsince all conductors include a resistance and capacitance of a metal line.

p-0119The delay amount of the inverter may change according to a type or specifications of the inverter. Therefore, the delay amount of the inverter may not be a variable value according to the setting of a control signal but be a fixed value. The RC characteristics of the feedback loop is determined according to capacitance and inductance, length, and/or diameter of a metal conductor. Further, the RC characteristics of the feedback loop may not be a variable value according to the setting of a control signal but be a fixed value.

p-0120The operation mode of the random number generator <b>700</b> may be divided into a first operation mode (an MS operation mode) and a second operation mode (a Gener. operation mode) as shown in <figref idrefs="DRAWINGS">FIG. 3A</figref>.

p-0121A first control signal CLK_con generated by the clock generator <b>730</b> may have a first logic level (for example, logic low) and a second logic level (for example, logic high).

p-0122When the first control signal CLK_con has the first logic level, the condition of Inequality 1 below is satisfied. If the first control signal CLK_con is applied to the RO block <b>710</b> as the first logic level, the variable delay unit <b>712</b> may set the variable delay amount as a value much smaller than the delay value caused by parasitic RC characteristics of the feedback loop.

p-0123<br />(<img id="CUSTOM-CHARACTER-00004" he="3.13mm" wi="2.46mm" file="US20090106339A1-20090423-P00001.TIF" img-content="character" img-format="tif" orientation="portrait" inline="no" />_VD+<img id="CUSTOM-CHARACTER-00005" he="3.13mm" wi="2.46mm" file="US20090106339A1-20090423-P00001.TIF" img-content="character" img-format="tif" orientation="portrait" inline="no" />_INV)&lt;&lt;<img id="CUSTOM-CHARACTER-00006" he="3.13mm" wi="2.46mm" file="US20090106339A1-20090423-P00001.TIF" img-content="character" img-format="tif" orientation="portrait" inline="no" />_RC  1)

p-0124For example, when the sum of the delay amounts of the variable delay unit <b>712</b> and the inverter <b>714</b> is small compared to those of the feedback loop, the RO block <b>710</b> may be operated at the first operation mode.

p-0125As described above, a delay amount of the inverter and a delay amount of the feedback loop have a fixed value per device. Therefore, in order to satisfy Inequality 1 above, the delay amount of the variable delay unit <b>712</b> must have a smaller value.

p-0126The operation of the RO block <b>710</b> in the first operation mode to which Equation 1 is applied is described with reference to <figref idrefs="DRAWINGS">FIG. 7B</figref>.

p-0127Referring to <figref idrefs="DRAWINGS">FIG. 7B</figref>, as described above, the delay amount of the variable delay unit <b>712</b> may have a value close to 0. Therefore, the variable delay unit <b>712</b> is assumed to no longer exist.

p-0128An inverter <b>751</b> that is a simple logic element has a small delay amount and usually delay amount caused by parasitic RC characteristics of the feedback loop is bigger. Therefore, the Inequality 1 is satisfied and after a while, any signal converges to some stable level with a meta stable voltage value.

p-0129According to the first operation mode, the meta stable voltage value is applied to the first node N<b>1</b>.

p-0130When the first control signal CLK_con has the second logic level, Equation 2 is established. If the first control signal CLK_con is applied to the RO block <b>710</b> as the second logic level, the variable delay unit <b>712</b> may set the variable delay amount as a very larger value than the delay value caused by parasitic RC characteristics of the feedback loop.

p-0131<br />(<img id="CUSTOM-CHARACTER-00007" he="3.13mm" wi="2.46mm" file="US20090106339A1-20090423-P00001.TIF" img-content="character" img-format="tif" orientation="portrait" inline="no" />_VD+<img id="CUSTOM-CHARACTER-00008" he="3.13mm" wi="2.46mm" file="US20090106339A1-20090423-P00001.TIF" img-content="character" img-format="tif" orientation="portrait" inline="no" />_INV)>><img id="CUSTOM-CHARACTER-00009" he="3.13mm" wi="2.46mm" file="US20090106339A1-20090423-P00001.TIF" img-content="character" img-format="tif" orientation="portrait" inline="no" />_RC  2)

p-0132For example, when the sum of the delay amounts of the variable delay unit <b>712</b> and the inverter <b>714</b> is large compared to those of the feedback loop, the RO block <b>710</b> is operated at the second operation mode.

p-0133As described above, a resistance amount of the inverter and a resistance amount of the feedback loop may have a fixed value per device. Therefore, in order to satisfy Inequality 2 above, the delay amount of the variable delay unit <b>712</b> may be set to be larger than the resistor of the feedback loop. The configuration and the operation of the random number generator <b>700</b> may correspond to those of the random number generator <b>600</b> of <figref idrefs="DRAWINGS">FIG. 6</figref> in the second operation mode. For example, the random number generator <b>700</b> may perform an oscillation operation using the meta stable voltage applied to the first node N<b>1</b> at the first operation mode.

p-0134<figref idrefs="DRAWINGS">FIG. 8</figref> is a diagram of a random number generator according to example embodiments. <figref idrefs="DRAWINGS">FIG. 8</figref> is a diagram of a random number generator <b>800</b> according to example embodiments. Referring to <figref idrefs="DRAWINGS">FIG. 8</figref>, the random number generator <b>800</b> may comprise an RO block <b>810</b>, a clock signal generator <b>830</b>, and/or a sampling unit <b>840</b>. The RO block <b>810</b> may comprise inverting elements <b>815</b>, <b>816</b>, and <b>817</b>, and/or a plurality of switching units <b>821</b>, <b>822</b>, and <b>823</b>.

p-0135The clock generator <b>830</b> may comprise a control clock generator <b>831</b> and a delay unit <b>833</b>. The control clock generator <b>331</b> may generate and output the first control signal CLK_con.

p-0136The delay unit <b>833</b> may receive the first control signal CLK_con, delay the received first control signal CLK_con for a predetermined or desired period of time, and output a second control signal CLK_sp. The first control signal CLK_con and the second control signal CLK_sp may be clock signals.

p-0137Referring to <figref idrefs="DRAWINGS">FIG. 3</figref>, a MUX may be used as a switching unit and an inverter may be used as an inverting element.

p-0138A first input end S<b>1</b> of the MUX (for example, <b>821</b>) receives an output signal of the inverter <b>815</b> that is serially connected to an output end of the MUX <b>821</b>. For example, the serially connected MUX <b>821</b> and the inverter <b>815</b> are connected via a feedback loop. If the terminal S<b>1</b> of the MUX <b>821</b> is connected to a MUX output terminal, the inverter <b>815</b> has the same shape as the inverter <b>751</b> shown in <figref idrefs="DRAWINGS">FIG. 7B</figref>.

p-0139Therefore, as described with reference to <figref idrefs="DRAWINGS">FIG. 7B</figref>, if the terminal S<b>1</b> of the MUX <b>821</b> is connected to the MUX output terminal, a meta stable voltage can be applied to the inverter <b>815</b>. Thus, the inverter <b>815</b> may perform the same operation as the RO <b>300</b> shown in <figref idrefs="DRAWINGS">FIG. 3A</figref> without an additional meta stable voltage offering unit.

p-0140<figref idrefs="DRAWINGS">FIG. 9</figref> is a diagram of a random number generator <b>900</b> according to example embodiments. Referring to <figref idrefs="DRAWINGS">FIG. 9</figref>, the random number generator <b>900</b> may comprise switching units <b>321</b>, <b>322</b>, and <b>323</b> having each output end is connected to an input end D of the sampling unit <b>340</b>. For example, the output end of the switching unit <b>321</b> may be connected to the input end of the sampling unit <b>340</b> via a signal line <b>911</b>, and the output end of the switching unit <b>323</b> may be connected to the input end of the sampling unit <b>340</b> via a signal line <b>913</b>.

p-0141The sampling unit <b>340</b> may select any one of output signals of the plurality of switching units <b>321</b>, <b>322</b>, and <b>323</b> and sample the selected output signal in response to the control signal CLK_con that is output from the control clock generating unit <b>331</b>.

p-0142The configuration and operation of the random number generator <b>900</b> are the same as the random number generator shown in <figref idrefs="DRAWINGS">FIG. 3A</figref> and thus the detailed description thereof is not repeated.

p-0143The random number generator of example embodiments may perform an oscillation operation using a meta stable voltage, thereby reducing time taken to perform an oscillation operation without an increase in a circuit area and/or manufacturing cost. Further, the random number generator of example embodiments may reduce time taken to generate a random number, thereby increasing throughput.

p-0144While example embodiments have been particularly shown and described, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. Example embodiments should be considered in a descriptive sense only and not for purposes of limitation. Therefore, the scope of the invention is defined not by the detailed description but by the appended claims.