Method of fabricating semiconductor device
Claim Score by NHIP
Abstract
A method of forming a semiconductor device that includes heating a wafer on which an Al—Cu sputtering thin film is formed before patterning the Al—Cu sputtering thin film. The heating is performed at a temperature no less than a solid solution temperature of copper or at a temperature between 300° C. and 600° C. The process temperature in heating the process wafer is not higher than the flow temperature of aluminum or is the temperature at which a reflow process can be performed.

Term
Projected expiry 9 July 2028.
- Priority
- Filed
- Published
- Today
- Projected expiry
20 claims: 3 independent, 17 dependent
- 1A method comprising:forming a wafer having a partially laminated metal film formed as a wiring line;and then heating the wafer in a sputtering chamber at a first predetermined temperature;and then performing a process which completely laminates the wiring line on the wafer;and then heating the wafer a second time including the wiring line layer at a second predetermined temperature;and then patterning the wiring line layer.
- 10A method comprising:forming a partially laminated metal wiring line on a wafer;and then performing a first heating process on the wafer;and then performing a process which completely laminates the metal wiring line on the wafer;and then performing a second heating process on the wafer including the metal wiring line;and then performing a cooling process on the wafer;and then patterning the metal wiring line.
- 19Broadest claimClaim Score 89, very broad(NHIP)A method comprising:partially laminating an aluminum-copper wiring on a wafer;and then performing a first heating process on the wafer;and then completely laminating the aluminum-copper wiring on the wafer;and then performing a second heating process on the wafer while simultaneously reflowing an aluminum component in the aluminum-copper wiring;and then performing a cooling process on the wafer;and then patterning the aluminum-copper wiring.
Independent claims3
17 paragraphs in 4 sections, as filed
0001The present application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2007-000070037 (filed on Jul. 12, 2007), which is hereby incorporated by reference in its entirety.
BACKGROUND
0002In fabricating a semiconductor device, the width of a metal wiring line may be reduced as the element of the semiconductor device becomes highly integrated. In order to increase the conductivity of the wiring line, a material such as copper (Cu) may be used. However, it is sometimes difficult to form copper using a present patterning process. Therefore, in many cases, a wiring line process of depositing aluminum by sputtering to perform patterning may be used. In order to increase the conductivity of the wiring line, copper can be partially included in the aluminum. When a target obtained by including copper from about 0.1% to about 0.5% in aluminum may be used in a sputtering process, a patterning process can be performed in the above containing amount of copper. The sputtering can be performed at a temperature between a range of 120° C. and 200° C., which is lower than in another layer deposition process such as chemical vapor deposition (CVD). When an Al—Cu sputtering deposition layer is left at a relatively low temperature for a long time, an Al—Cu thin film changes from a GP zone to a 0 phase due to an aging effect so that the copper component in the Al—Cu thin film is extracted in the form of a particle. The copper extracted material may serve as an etching stop layer that prevents aluminum positioned under the particle from being etched when the Al—Cu thin film is reactive ion etched to form process defect in the form of a micro bridge between metal lines.
0003As illustrated in example <figref idref="DRAWINGS">FIG. 1</figref>, an enlarged side section and plane of a photograph is shown of a process defect in the form of a micro bridge caused by extracting copper in an Al—Cu sputtering thin film. As a result, since the defect deteriorates the function of the semiconductor device and reliability, when the defect is generated, a large number of process wafers are scraped. When process yield deteriorates due to an increase in a reject ratio, process cost and chip production cost increase.
SUMMARY
0004Embodiments relate to a method of forming a wiring line by aluminum partially including copper.
0005Embodiments relate to a method of forming a semiconductor device in order to solve problems caused by extracting copper when an Al—Cu sputtering layer is left in a sputtering process environment for a long time.
0006In accordance with embodiments, a method of forming a semiconductor device may include at least one of the following steps: heating a wafer on which an Al—Cu sputtering thin film is formed at a temperature no less than a solid solution temperature for copper in an Al thin film before patterning the Al—Cu sputtering thin film.
0007In accordance with embodiments, a method of forming a semiconductor device may include at least one of the following steps: forming a process wafer on which an Al—Cu thin film serving as a wiring line layer is at least partially laminated by sputtering; and then leaving the process wafer in a sputtering chamber at a process temperature; and then completely laminating the wiring line layer on the process wafer; and then heating the process wafer on which the wiring line layer is completely laminated at a set temperature; and then patterning the wiring line layer.
0008In accordance with embodiments, when the process temperature in heating the process wafer is higher than 500° C., since problems can be caused by the flow of the formed Al thin film, the process temperature is not preferably higher than the flow temperature of the Al thin film even when the process time is short. In addition, the process temperature can be determined in consideration of the phase of a solid solution. However, when the reflow process is performed after forming the wiring line layer on the wafer where a contact hole is formed, heating the process wafer can be further provided together with the reflow process.
0009Although all of the extracted copper is not in a solid phase, a certain amount of effect can be expected by reducing particles or the size of the particles. Therefore, the thin film can be processed for a short time at the process temperature. In accordance with embodiments, a difference in the solid solution temperature can be generated by the density of Al—Cu. However, the effect of heating the process wafer can be obtained when the amount of copper is within 3% and when the process wafer is heated at the temperature no less than 300° C. In accordance with embodiments, the time for which the Al—Cu thin film is left at the process temperature of the sputtering chamber can be determined in accordance with the degree of the process and needs not be limited. In accordance with embodiments, when copper is segregated in the wiring line forming process due to the aging effect, the extracted copper is turned to a solid solved through simple thermal treatment. Therefore, it is possible to prevent the extracted copper from prohibiting the etching of a pattern in the patterning process so that it is possible to prevent the formation of the pattern from being deteriorated. In accordance with embodiments, it is possible to reduce the reject ratio in the wiring line process. The thermal treatment may be previously performed on the left process wafer so that it is possible to rework problems caused by leaving the process wafer in the process chamber and to improve yield.
DRAWINGS
0010Example <figref idref="DRAWINGS">FIG. 1</figref> illustrates the enlarged side section and plane of a photograph of process defect in the form of a micro bridge that is caused by extracting Cu in an Al—Cu sputtering thin film.
0011Example <figref idref="DRAWINGS">FIG. 2</figref> is a graph illustrating a state in which copper is solidified in accordance with the temperature of aluminum, in accordance with embodiments.
DESCRIPTION
0012Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that they can be readily implemented by those skilled in the art.
0013In accordance with embodiments, Al—Cu or Ti/TiN laminated on and/or over Al—Cu used as a reflection preventing layer may be left in a deposition chamber in an Al deposition process performed by sputtering at a process chamber temperature between a range of 120° C. and 200° C. so that an aging effect is generated.
0014After depositing a liner titanium (Ti) or Ti/TiN (a bottom layer) in order to form a wiring line, the Al—Cu and the Ti/TiN used as the reflection preventing layer may be sequentially deposited by sputtering. However, when the deposition of the Al—Cu or the Ti/TiN thin film is stopped due to errors generated in the semiconductor device during the above-described processes, after depositing the target thickness of remaining deposition layers, the deposition process may be stopped.
0015After forming a wiring line layer on an impact wafer, the wafer is positioned in a process chamber that can heat the wafer to a temperature no less than 300° C. It may be generally difficult to heat a sputtering device to a temperature no less than 300° C. Since the sputtering device is a vacuum device, in terms of efficiency, processes of heating the wafer in a sputtering chamber may be performed in another device. In the process chamber, thermal treatment may be performed at an annealing temperature between a range of 300° C. and 600° C. for a time in a range between 100 to 300 seconds. The heated wafer is then cooled at room temperature. When the wafer is too slowly cooled, copper can be extracted again. However, the re-extraction of copper does not matter when the wafer is cooled at room temperature. Then, a wiring line patterning process may be performed simultaneously with the other normal wafers (i.e., the wafers that are not left in the sputtering chamber). Meaning, the wiring line layer may be coated with photoresist and exposed and developed to form an etching mask pattern. The wiring line layer may then be etched using the etching mask pattern. The etching can be performed by a reactive ion etching (RIE) method that can improve etching efficiency. Since the temperature and time of the thermal treatment can affect each other to a certain degree, the temperature and time can be determined in consideration of each other. For example, when the thermal treatment is performed at a high temperature, i.e., no less than 600° C., the process time may be reduced. On the other hand, when the thermal treatment is performed at a relatively low temperature of 300° C., the thermal treatment can be performed for several minutes so that extracted copper can sufficiently change to a solid phase.
0016As illustrated in example <figref idref="DRAWINGS">FIG. 2</figref>, a graph illustrating a state in which copper is in a solid phase in accordance with the temperature of aluminum. When the thermal treatment is performed at a temperature no less than 300° C., a copper extracted material is not found and a bridge or a lock-in phenomenon is not found between wiring lines obtained by patterning.
0017Although embodiments have been described with reference to a number of illustrative embodiments thereof, it should be understood that numerous other modifications and embodiments can be devised by those skilled in the art that will fall within the spirit and scope of the principles of this disclosure. More particularly, various variations and modifications are possible in the component parts and/or arrangements of the subject combination arrangement within the scope of the disclosure, the drawings and the appended claims. In addition to variations and modifications in the component parts and/or arrangements, alternative uses will also be apparent to those skilled in the art.
Contents4
3 sheets
Sheet 1 Sheet 2 Sheet 3
Every citation, both ways
| Document | Relation | Office | Cited during |
|---|---|---|---|
| US9910126B2 | Cited by | United States of America | Applicant |
| US10481237B2 | Cited by | United States of America | Applicant |
| US9684055B2 | Cited by | United States of America | Applicant |
| WO2017151196A1 | Cited by | World Intellectual Property Organization (WIPO) | Applicant |
| WO2016073208A1 | Cited by | World Intellectual Property Organization (WIPO) | Applicant |
| US9618602B2 | Cited by | United States of America | Applicant |
| US2001053596A1 | Cites | United States of America | Pre-grant |
| US5300307A | Cites | United States of America | Pre-grant |
| US6140236A | Cites | United States of America | Pre-grant |
| US6372645B1 | Cites | United States of America | Pre-grant |
| US6440841B2 | Cites | United States of America | Pre-grant |
| US6468908B1 | Cites | United States of America | Pre-grant |
| US6774035B2 | Cites | United States of America | Pre-grant |
| US6977221B2 | Cites | United States of America | Pre-grant |
| US7037836B2 | Cites | United States of America | Pre-grant |
3 members in 2 offices
Priority claims5
| Document | Office | Kind | Date |
|---|---|---|---|
| 1020070070037 | Republic of Korea | – | |
| 20070070037 | Republic of Korea | A | |
| 20070070037 | Republic of Korea | A | |
| 1020070070037 | – | – | – |
| KR20070070037 | – | – | – |
Members3
| Document | Office | Kind | |
|---|---|---|---|
| KR100875822B1 | Republic of Korea | B1 | |
| US2009017618A1 | United States of America | A1 | |
| US7682969B2 | United States of America | B2 |
31 transactions on the USPTO file
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Numbers
- Publication
- 20090017618
- Publication, DOCDB
- 2009017618
- Publication, EPODOC
- US2009017618
- Application
- 12170261
- Application, DOCDB
- 17026108
- Application, EPODOC
- US20080170261
Titles
- English
- METHOD OF FABRICATING SEMICONDUCTOR DEVICE
Classification
- CPC, 4
- H01L21/32051
- H01L21/28
- H01L23/53219
- H01L2924/0002
- IPC, 1
- H01L21 285
- USPC, 2
- 438660000
- 257E21169