Assertion Tester

BACKGROUND

0001In the field of microchip design, chip designers and programmers can write complex algorithms to represent desired logic. Depending on the particular project and the particular chip designer, the algorithm can be written in any of a plurality of programming languages, including but not limited to Very High Speed Integrated Circuit Hardware Description Language (abbreviated as VHSIC-HDL or VHDL), Verilog, C++, etc. Additionally, as the algorithms become more complex, the chip designer or programmer can implement various techniques to ensure the accuracy of the algorithm. Oftentimes, the chip designer can include comments into the program, such that when debugging or improving the algorithm, the chip designer can more clearly understand the workings of the algorithm without having to simulate or synthesize the algorithm.

0002Another technique that programmers and chip designers use for ensuring the accuracy of an algorithm is an assertion function inserted within the program itself. While some programming and hardware description languages (HDLs) include an assertion function within their libraries, there are other, more specific assertion programs that can operate as part of the simulation program (computer, synthesizer, etc.) to more concisely and easily perform assertions within the programming languages. More specifically System Verilog Assertion (SVA), Property Specification Language (PSL) and Open Vera Assertion (OVA) can be used as part of an HDL to provide a more comprehensive assertion function.

0003While these programs can assist the programmer or chip designer in developing the desired logic and ensuring its accuracy, there can be problems in current techniques. More specifically, as the complexity of algorithms (and thus the logic program that describes the logic) increases, assertions can become more valuable. However, as the algorithms become more complex and the number of inputs and other variables increases, the assertions become more difficult to implement. Depending on the particular programming language and configuration, the programmer or chip designer may desire to individually determine the value for each input. Additionally, there may not be a simple way for the programmer to test internal variables within the algorithm to determine if an assertion is operating as desired. More specifically, when a programmer or chip designer creates a program that includes assertion, the programmer or chip designer generally will manually determine each value for each input and will run a simulation. From the values generated in the simulation, the programmer or chip designer can determine whether the program is operating properly, and whether the assertion is operating properly. One problem that programmers encounter is that there may not be a way to easily determine whether the assertion is operating properly, and thus whether the program is operating properly.

0004Thus, a heretofore unaddressed need exists in the industry to address the aforementioned deficiencies and inadequacies.

SUMMARY

0005Included in this disclosure are embodiments of an assertion program for testing an assertion that is written for a logic program. At least one embodiment of the assertion program includes logic configured to determine at least one variable in the assertion and logic configured to determine values for the at least one variable in the assertion. Other embodiments include logic configured to determine at least one of value of the variable that corresponds to a violation of the assertion and logic configured to display at least one determined value related to the violation of the assertion.

0006Also included herein are embodiments of a method for testing an assertion written for a logic program that can be simulated in a simulation program. Embodiments of the method include receiving the assertion independent from the logic program and independent from the simulation program, where the assertion includes at least one variable from the simulation program. Embodiments of the method also include determining the at least one variable in the assertion. The assertion is tested, independent from the logic program and the simulation program. Testing the assertion, in this nonlimiting example, includes testing the assertion with at least one value for the at least one variable and determining at least one violation of the assertion.

0007Also included herein are embodiments of a computer readable medium that includes an assertion program for testing an assertion written for a logic program, where the logic program can be executed in a simulation program, where the assertion program is different than the simulation program, and where the assertion program is different than the logic program. Embodiments of the assertion program include logic configured to receive the assertion independent from the logic program and independent from the simulation program, wherein the assertion includes at least one variable from the logic program and logic configured to determine the at least one variable in the assertion. Embodiments of the assertion program also include logic configured to test the assertion independent from the logic program, wherein testing the assertion includes testing the assertion with at least one value for the at least one variable and logic configured to determine at least one violation of the assertion from the testing of the assertion.

0008Other systems, methods, features, and advantages of this disclosure will be or become apparent to one with skill in the art upon examination of the following drawings and detailed description. It is intended that all such additional systems, methods, features, and advantages be included within this description, be within the scope of the present disclosure.

BRIEF DESCRIPTION

0009Many aspects of the disclosure can be better understood with reference to the following drawings. The components in the drawings are not necessarily to scale, emphasis instead being placed upon clearly illustrating the principles of the present disclosure. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views.

0010<figref idref="DRAWINGS">FIG. 1</figref> is a functional diagram illustrating exemplary digital logic that can be implemented using a programming language.

0011<figref idref="DRAWINGS">FIG. 2</figref> is a functional diagram illustrating exemplary components of a client device that may include a programming language that can describe the logic from <figref idref="DRAWINGS">FIG. 1</figref>.

0012<figref idref="DRAWINGS">FIG. 3</figref> is a screenshot of an exemplary VHDL program that can be used to implement the logic from <figref idref="DRAWINGS">FIG. 1</figref>.

0013<figref idref="DRAWINGS">FIG. 4</figref> is a screenshot of an exemplary VHDL program with an assertion that can be used to determine whether the VHDL program is an accurate representation of the logic from <figref idref="DRAWINGS">FIG. 1</figref>.

0014<figref idref="DRAWINGS">FIG. 5</figref> is a screenshot of an exemplary test sequence of the program from <figref idref="DRAWINGS">FIG. 4</figref>.

0015<figref idref="DRAWINGS">FIG. 6</figref> is a screenshot of an exemplary technique for testing the assertion from <figref idref="DRAWINGS">FIG. 4</figref>.

0016<figref idref="DRAWINGS">FIG. 7</figref> is a screenshot of exemplary logic for determining the operation of the assertion from <figref idref="DRAWINGS">FIG. 4</figref>.

0017<figref idref="DRAWINGS">FIG. 8</figref> is a screenshot of exemplary logic for manually testing an assertion that can be inserted into the VHDL program from <figref idref="DRAWINGS">FIG. 4</figref>.

0018<figref idref="DRAWINGS">FIG. 9</figref> is a screenshot of an exemplary display for determining various options for testing the assertion from <figref idref="DRAWINGS">FIG. 8</figref>.

0019<figref idref="DRAWINGS">FIG. 10</figref> is a screenshot of an exemplary test sequence for testing the assertion from <figref idref="DRAWINGS">FIG. 8</figref>.

0020<figref idref="DRAWINGS">FIG. 11</figref> is a screenshot of an exemplary display for inserting the assertion from <figref idref="DRAWINGS">FIG. 8</figref> into a program.

0021<figref idref="DRAWINGS">FIG. 12</figref> is a flowchart illustrating exemplary steps that can be taken for testing the assertion from <figref idref="DRAWINGS">FIG. 4</figref>.

DETAILED DESCRIPTION

0022Many aspects of the disclosure can be better understood with reference to the following drawings. The components in the drawings are not necessarily to scale, emphasis instead being placed upon clearly illustrating the principles of the present disclosure. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views. While several embodiments are described in connection with these drawings, there is no intent to limit the disclosure to the embodiment or embodiments disclosed herein. On the contrary, the intent is to cover all alternatives, modifications, and equivalents.

0023<figref idref="DRAWINGS">FIG. 1</figref> is a functional diagram illustrating exemplary digital logic that can be implemented using a programming language. More specifically, the logic in <figref idref="DRAWINGS">FIG. 1</figref> includes three “NAND” gates <b>102</b>, <b>104</b>, <b>106</b> and a “NOT” gate <b>108</b>. Inputs Z<b>0</b> and Z<b>1</b> are input into NAND gate <b>102</b> and inputs Z<b>2</b> and Z<b>3</b> are input into NAND gate <b>104</b>. These gates produce the internal signals A<b>0</b> and A<b>2</b>, which can be input into NAND gate <b>106</b>. NAND gate <b>106</b> can then produce output R<b>0</b>. R<b>0</b> can also be input into NOT gate <b>108</b> to produce output signal R<b>1</b>.

0024One should note that while the above described logic can be implemented using NAND gates, the same results can be obtained using different gates, such as “AND” gates and “OR” gates, or by using a computer programming language, such as an HDL. Additionally, while the logic described herein with respect to <figref idref="DRAWINGS">FIG. 1</figref> illustrates single bit inputs and outputs, this is also a nonlimiting example. Any kind of logic with any of a plurality of different types of inputs and outputs can be implemented for purposes of this discussion.

0025<figref idref="DRAWINGS">FIG. 2</figref> is a functional diagram illustrating exemplary components of a client device that may include a programming language that can describe the logic from <figref idref="DRAWINGS">FIG. 1</figref>. More specifically, client device <b>206</b> can take the form of a personal computer (PC), a mobile or cellular telephone) a personal digital assistant (PDA), or other device capable of executing logic. Generally, in terms of hardware architecture, as shown in <figref idref="DRAWINGS">FIG. 2</figref>, the client device <b>206</b> includes a processor <b>282</b>, volatile and nonvolatile memory <b>284</b>, and one or more input and/or output (I/O) device interface(s) <b>296</b> that are communicatively coupled via a local interface <b>292</b>. The local interface <b>292</b> can be, for example but not limited to, one or more buses or other wired or wireless connections. The local interface <b>292</b> may have additional elements, which are omitted for simplicity, such as controllers, buffers (caches), drivers, repeaters, and receivers to enable communications. Further, the local interface <b>292</b> may include address, control, and/or data connections to enable appropriate communications among the aforementioned components. The processor <b>282</b> is a hardware device for executing software, particularly software stored in volatile and nonvolatile memory <b>284</b>.

0026The processor <b>282</b> can be any custom made or commercially available processor, a central processing unit (CPU), an auxiliary processor among several processors associated with the client device <b>206</b>, a semiconductor based microprocessor (in the form of a microchip or chip set), a macroprocessor, or generally any device for executing software instructions. Examples of suitable commercially available microprocessors are as follows: a PA-RISC series microprocessor from Hewlett-Packard® Company, an 80x86 or Pentium® series microprocessor from Intel® Corporation, a PowerPC® microprocessor from IBM®, a Sparc® microprocessor from Sun Microsystems®, Inc, or a 68xxx series microprocessor from Motorola® Corporation.

0027The volatile and nonvolatile memory <b>284</b> can include any one or combination of volatile memory elements (e.g., random access memory (RAM, such as DRAM, SRAM, SDRAM, etc.)) and nonvolatile memory elements (e.g., ROM, hard drive, tape, CDROM, etc.). Moreover, the memory <b>214</b> can incorporate electronic, magnetic, optical, and/or other types of storage media. Note that the volatile and nonvolatile memory <b>284</b> can have a distributed architecture, where various components are situated remotely from one another, but can be accessed by the processor <b>282</b>.

0028The software in volatile and nonvolatile memory <b>284</b> may include one or more separate programs, each of which includes an ordered listing of executable instructions for implementing logical functions. In the nonlimiting example of <figref idref="DRAWINGS">FIG. 2</figref>, the software in the volatile and nonvolatile memory <b>284</b> may include assertion testing software <b>288</b> and a program simulator (or compiler) <b>290</b>, as well as an operating system <b>286</b>. A nonexhaustive list of examples of suitable commercially available operating systems is as follows: (a) a Windows® operating system available from Microsoft® Corporation; (b) a Netware® operating system available from Novell®, Inc.; (c) a Macintosh® operating system available from Apple® Computer, Inc.; (d) a UNIX operating system, which is available for purchase from many vendors, such as the Hewlett-Packard® Company, Sun Microsystems®, Inc., and AT&amp;T® Corporation; (e) a LINUX operating system, which is freeware that is readily available on the Internet; (f) a run time Vxworks® operating system from WindRiver® Systems, Inc.; or (g) an appliance-based operating system, such as that implemented in handheld computers or personal data assistants (PDAs) (e.g., PalmOS® available from Palm® Computing, Inc., and Windows CE® available from Microsoft® Corporation). The operating system essentially controls the execution of other computer programs and provides scheduling, input-output control, file and data management, memory management, and communication control and related services.

0029A system component embodied as software may also be construed as a source program, executable program (object code), script, or any other entity comprising a set of instructions to be performed. When constructed as a source program, the program is translated via a compiler, assembler, interpreter, or the like, which may or may not be included within the volatile and nonvolatile memory <b>284</b>, so as to operate properly in connection with the Operating System <b>286</b>.

0030Input/Output devices that may be coupled to system I/O Interface(s) <b>296</b> may include input devices, for example but not limited to, a keyboard, mouse, scanner, microphone, etc. Further, the Input/Output devices may also include output devices, for example but not limited to, a printer, display, etc. Finally, the Input/Output devices may further include devices that communicate both as inputs and outputs, for instance but not limited to, a modulator/demodulator (modem; for accessing another device, system, or network), a radio frequency (RF) or other transceiver, a telephonic interface, a bridge, a router, etc.

0031If the client device <b>206</b> is a Personal Computer, workstation, or the like, the software in the volatile and nonvolatile memory <b>284</b> may further include a basic input output system (BIOS) (omitted for simplicity). The BIOS is a set of essential software routines that initialize and test hardware at startup, start the Operating System, and support the transfer of data among the hardware devices. The BIOS can be stored in ROM so that the BIOS can be executed when the client device <b>206</b> is activated.

0032When the client device <b>206</b> is in operation, the processor <b>282</b> is configured to execute software stored within the volatile and nonvolatile memory <b>284</b>, to communicate data to and from the volatile and nonvolatile memory <b>284</b>, and to generally control operations of the client device <b>206</b> pursuant to the software. Software in memory, in whole or in part, can be read by the processor <b>282</b>, perhaps buffered within the processor <b>282</b>, and then executed.

0033One should note that while the above description with respect to <figref idref="DRAWINGS">FIG. 2</figref> refers to components of a client device <b>206</b>, some or all of these components may also be present in a server, to which the client device <b>206</b> is coupled. More specifically, while the assertion testing software <b>288</b> (and programming language software) can be located in volatile and nonvolatile memory <b>284</b> of client device <b>206</b>, in some embodiments assertion testing software <b>288</b> can be located externally of client device log. Thus the components described with reference to <figref idref="DRAWINGS">FIG. 2</figref> can be applied to a client device <b>206</b>, a server, other device, or any permutation of these, depending on the desired configuration.

0034<figref idref="DRAWINGS">FIG. 3</figref> is a screenshot of an exemplary VHDL program that can be used to implement logic from <figref idref="DRAWINGS">FIG. 1</figref>. More specifically, the display window <b>300</b> can be associated with a VHDL simulation program. As such, the display window <b>300</b> can be configured to facilitate creation and display of a VHDL program. More specifically, the VHDL simulation program of <figref idref="DRAWINGS">FIG. 3</figref> includes a logic program for describing a piece of logic. The logic program includes inputs Z<b>0</b>, Z<b>1</b>, Z<b>2</b>, and Z<b>3</b> at <b>302</b>, and outputs R<b>0</b> and R<b>1</b> at <b>304</b>. Additionally included in the VHDL logic program of <figref idref="DRAWINGS">FIG. 3</figref> is an indication of internal signals A<b>0</b> and A<b>2</b> at <b>306</b>. One should note that while the inputs <b>302</b>, outputs <b>304</b>, and internal signals <b>306</b> are defined as standard logic, this is a nonlimiting example, as any type of data can be provided for the inputs, outputs and internal signals.

0035Also included in the log program of <figref idref="DRAWINGS">FIG. 3</figref> is an assignment of Z<b>0</b> AND Z<b>1</b> as internal signal A<b>0</b>. More specifically, referring back to <figref idref="DRAWINGS">FIG. 1</figref>, the inputs Z<b>0</b> and Z<b>1</b> can be input into NAND gate <b>102</b>. While <figref idref="DRAWINGS">FIG. 1</figref> discusses logic with NAND gates, the use of logical AND and logical OR can be substituted for the NAND gates of <figref idref="DRAWINGS">FIG. 1</figref>. As also illustrated in <figref idref="DRAWINGS">FIG. 3</figref>, the internal signal A<b>2</b> is assigned a value equal to the logical expression (Z<b>2</b> AND Z<b>3</b>). The output R<b>0</b> is defined as being equal to the logical expression of internal signals (A<b>0</b> OR A<b>2</b>). The output R<b>1</b> is defined as being the logical NOT of R<b>0</b>.

0036<figref idref="DRAWINGS">FIG. 4</figref> is a screenshot if an exemplary VHDL simulator program with an assertion that can be used to determine whether the VHDL logic program is an accurate representation of the logic from <figref idref="DRAWINGS">FIG. 1</figref>. Similar to the VHDL logic program from <figref idref="DRAWINGS">FIG. 3</figref>, this VHDL logic program includes inputs Z<b>0</b>, Z<b>1</b>, Z<b>2</b>, and Z<b>3</b>, shown as element <b>402</b>. Additionally, element <b>404</b> introduces the outputs R<b>0</b> and R<b>1</b>. Element <b>406</b> introduces internal signals A<b>0</b> and A<b>2</b>. Similar to the VHDL logic program from <figref idref="DRAWINGS">FIG. 3</figref>, the internal signal A<b>0</b> is assigned a value equal to (Z<b>0</b> AND Z<b>1</b>). Internal signal A<b>2</b> is assigned a value equal to (Z<b>2</b> AND Z<b>3</b>). R<b>0</b> is assigned a value equal to (A<b>0</b> OR A<b>2</b>). R<b>1</b> is assigned a value equal to (NOT R<b>0</b>).

0037Additionally included in this nonlimiting example is an assertion <b>408</b>. The assertion <b>408</b> states that R<b>1</b> should always equal (NOT R<b>0</b>). If R<b>1</b> is not equal to (NOT R<b>0</b>) then the assertion will report “Test Failed” and the severity of this violation will be an error. Assertions like this can be used as a programming tool to determine whether a program is operating properly. More specifically, by using an assertion the programmer can determine whether the logic program variables are operating correctly. As R<b>0</b> should always equal (NOT R<b>1</b>), the programmer will know there is a problem if the assertion is violated.

0038Assertions can be used to determine if or when illegal operations occur in a program. Additionally, while the assertion <b>408</b> indicates a violation with respect to outputs, assertions can be used to determine errors in any of the variables of the program. When the program of <figref idref="DRAWINGS">FIG. 4</figref> is simulated, the programmer can determine various inputs for the simulation and simulate the outputs according to the inputs provided. While the assertion can provide the programmer with an indication as to whether the assertion is violated, the programmer may not have a way to determine whether the assertion is written properly. More specifically, if the programmer accidentally included a typographical or other error in the assertion, the programmer may be provided with incorrect information related to the operation of the program. Additionally, because the programmer has limited resources in determining whether the assertion is operating correctly, the programmer may have limited resources in determining whether the program is operating correctly.

0039<figref idref="DRAWINGS">FIG. 5</figref> is a screenshot of an exemplary test sequence of the logic program from <figref idref="DRAWINGS">FIG. 4</figref>. As illustrated in display window <b>500</b>, the inputs Z<b>3</b>, Z<b>2</b>, Z<b>1</b>, and Z<b>0</b> (Z<b>0</b> not shown) are associated with a plurality of logical values, as shown with waveforms <b>506</b>, <b>508</b>, and <b>510</b>, respectively. Additionally, outputs R<b>0</b> and R<b>1</b> are displayed with their values that correspond to the displayed inputs. More specifically, R<b>1</b> and R<b>0</b> are associated with waveforms <b>502</b> and <b>504</b> respectively. Additionally, as displayed with dotted circle <b>512</b> and corresponding dotted vertical lines, there is a portion of the waveforms associated with R<b>1</b> and R<b>0</b> that violates the assertion of <figref idref="DRAWINGS">FIG. 4</figref>. More specifically, as shown in circle <b>512</b>, there is a time when R<b>1</b>=R<b>0</b>=0. The assertion from <figref idref="DRAWINGS">FIG. 4</figref> states that R<b>1</b> must be equal to (NOT R<b>0</b>), so when R<b>1</b> equals R<b>0</b>, error window <b>514</b> is displayed with the text “Test Failed.”

0040As stated above, the display of a violation of the assertion can be beneficial to a programmer for determining whether the program is operating correctly, and if not, where an error occurs. However, as also described above, the use of assertions can be deterred by the inability of the programmer to determine whether the assertion is operating properly. More specifically, when an assertion incorporates a plurality of variables and a plurality of operations, the likelihood of error with respect to the assertion logic can be jeopardized. Additionally, as the complexity of the insertion increases, the likelihood of an error in inputting the assertion can also increase.

0041<figref idref="DRAWINGS">FIG. 6</figref> is a screenshot of an exemplary technique for testing the assertion from <figref idref="DRAWINGS">FIG. 4</figref>. More specifically, as illustrated in <figref idref="DRAWINGS">FIG. 4</figref>, display window <b>400</b> for an exemplary simulator program includes inputs Z<b>0</b>, Z<b>1</b>, Z<b>2</b>, and Z<b>3</b> at element <b>402</b>. Outputs R<b>0</b> and R<b>1</b> are indicated at element <b>404</b>. A logic program with internal signals A<b>0</b> and A<b>2</b> are indicated at element <b>406</b>. Assertion <b>408</b> is indicated as in <figref idref="DRAWINGS">FIG. 4</figref>, except that in this nonlimiting example, the programmer can highlight the text of the assertion with the mouse cursor <b>610</b>. Additionally, by “right clicking” on the highlighted text, the programmer can facilitate display of options box <b>612</b>, which can include one or more options that may include “copy,” “cut,” “paste,” and “run in assertion software.” The “copy” option can provide the programmer with the ability to copy the highlighted text to a virtual notepad for insertion at a different locale, without disturbing the highlighted text. The “cut” option can provide the programmer with the ability to cut the highlighted text from its current location for insertion at a different location. The paste option can provide the programmer with the ability to insert the cut or copied text at a position of the programmer's choice.

0042Additionally included in the options box <b>610</b> is a “run in assertion software” option. The “run in assertion software” option can provide the programmer with the ability to automatically copy and execute the highlighted assertion in an assertion testing software. More specifically, if the programmer does not know whether the assertion is correctly written, the programmer can highlight the desired assertion and choose the “run in assertion software” option. The assertion can then be copied from its current location and inserted into an assertion testing software. The assertion testing software can then execute the assertion to provide the programmer with information related to the operation of the assertion.

0043<figref idref="DRAWINGS">FIG. 7</figref> is a screenshot of exemplary logic for determining the operation of the assertion from <figref idref="DRAWINGS">FIG. 4</figref>. As illustrated in the display window <b>770</b>, the assertion software can be configured to display a text window <b>772</b> and a graphical window <b>774</b>. In the text window <b>772</b> the assertion can be displayed. The assertion <b>408</b> can be manually entered into the text window <b>772</b> (as discussed below), or the assertion software can retrieve the assertion via the programmer selecting the “run in assertion software” option from <figref idref="DRAWINGS">FIG. 6</figref> (or via other techniques). In some embodiments the assertion software can be linked with the simulator software, compiler, and/or other programming software (in this disclosure the term “simulator software”, “simulator program”, and “simulator logic” can be construed to include simulators, synthesizers, computers, or any permutation thereof), depending on the configuration such that when the simulator software is opened, the assertion software can also be opened to a state that permits communication of data between the assertion program. When the programmer selects the “run in assertion software” option from <figref idref="DRAWINGS">FIG. 6</figref>, the assertion software can be configured to receive the assertion in text window <b>772</b>. Additionally, upon selecting this option, the assertion software can be configured to execute the assertion for all possible scenarios associated with the variables included in the assertion. This information can be displayed in a graphical representation with indicators that denote when the assertion is violated. As illustrated in graphical window <b>774</b>, the waveform <b>706</b> can represent R<b>0</b> and the waveform <b>708</b> can represent R<b>1</b>. The violation indicators <b>710</b><i>a </i>denote that there is a violation when R<b>0</b>=R<b>1</b>=0. Violation indicators <b>710</b><i>b </i>denote that there is a violation in the assertion when R<b>0</b>=R<b>1</b>=1. Additionally, included in the graphical window <b>774</b> is an error window <b>712</b>, that can indicate to the programmer the values at which the assertion is violated (in this nonlimiting example when R<b>0</b>R<b>1</b>=00 and 11).

0044One should also note that while the depiction of display window <b>770</b> includes a graphical representation of the assertion data, this is a nonlimiting example. While some embodiments can include a graphical display of the data, other embodiments can provide the programmer with the desired assertion data in other manners as well.

0045Additionally, while the nonlimiting example described above indicates that the assertion software can be configured to run the assertion for all possible permutations of the variables included in the assertion, this is also not a requirement. In at least one embodiment the assertion software can include logic that is configured to provide the programmer with the ability to determine the variables and values of those variables that the programmer desires tested.

0046<figref idref="DRAWINGS">FIG. 8</figref> is a screenshot of exemplary logic for manually testing an assertion that can be inserted into the VHDL logic program from <figref idref="DRAWINGS">FIG. 4</figref>. Included in this nonlimiting example is display window <b>770</b>, which includes text window <b>772</b> and graphical window <b>774</b>. As discussed above, text window can be configured to provide the programmer with the ability to manually enter an assertion, without the use of the simulator or compiler. Additionally, the assertion software can be configured to provide a programmer with the ability to modify assertions that are input in the text window <b>772</b> (either manually or via the “run in assertion software” option, discussed above). Once the programmer has entered or amended the assertion to his or her specifications, the programmer can select a “run” option, which can be located on the menu toolbar of display window <b>770</b>.

0047<figref idref="DRAWINGS">FIG. 9</figref> is a screenshot of an exemplary display for determining various options for testing the assertion from <figref idref="DRAWINGS">FIG. 8</figref>. In this nonlimiting example, the programmer has selected an option, such as the “run” option. In response to this programmer selection, the assertion software can be configured to provide display window <b>970</b> that can provide the programmer with supplemental options related to the entered assertion.

0048More specifically, the programmer can be provided with a “language” option <b>984</b>, which can allow the programmer to select the programming language of the assertion. While some embodiments can be configured to automatically determine the programming language of the assertion, other embodiments can be configured to provide the programmer with the ability to determine the programming language.

0049Additionally included the display window <b>970</b> is a “test sequence” option <b>988</b>. The “test sequence” option <b>988</b> can be configured to allow the programmer to determine whether the assertion software tests all possible permutations of the variables, or whether the user decides the values to be tested.

0050While the second option of the “test sequence” option <b>988</b> illustrates the ability for the programmer to provide a range of values, this is a nonlimiting example. Other embodiments can include providing the programmer with the ability to individually select the values to be tested. When the programmer has selected the desired options, the programmer can select the “test” option <b>990</b>, to run the assertion test.

0051One should also note that although the language option <b>984</b> and the test sequence option <b>988</b> are illustrated, other options can also be provided. More specifically, other embodiments can include options to more fully customize the assertion for implementation in the desired program.

0052<figref idref="DRAWINGS">FIG. 10</figref> is a screenshot of an exemplary test sequence for testing the assertion from <figref idref="DRAWINGS">FIG. 8</figref>. As illustrated, the assertion has been run and the assertion software is displaying violations in the assertion. Additionally, in at least one embodiment, the programmer can insert the assertion into a simulator by first highlighting the assertion <b>408</b> and “right clicking” the highlighted text. Upon “right clicking” the highlighted assertion, an options window <b>1002</b> may be displayed to provide the user with various options including “cut,” “copy,” “paste,” and “run in programming software.” As discussed above with respect to <figref idref="DRAWINGS">FIG. 6</figref>, the user can select the “cut” and “paste options” and/or the “copy” and “paste” options for inserting the assertion into the programming software. Additionally, by selecting the “run in programming software” option, the assertion software can automatically copy highlighted text for insertion into a program, as discussed with respect to <figref idref="DRAWINGS">FIG. 11</figref>.

0053<figref idref="DRAWINGS">FIG. 11</figref> is a screenshot of an exemplary display for inserting the assertion from <figref idref="DRAWINGS">FIG. 8</figref> into a program. As illustrated in <figref idref="DRAWINGS">FIG. 10</figref>, the programmer can select a “run in programming software” option. In response to selecting this option, the assertion software can display the insert window <b>1102</b> for providing the desired location of the assertion. The insert window <b>1102</b> can include a file path prompt for providing the destination (or destinations) for the assertion. As also illustrated, the programmer can select the line number that the programmer wishes to insert the assertion.

0054Additionally, while not illustrated in <figref idref="DRAWINGS">FIG. 11</figref>, the assertion software can also be configured to provide the ability to open a program for the programmer to select the desired location for inserting the assertion. More specifically, a programmer may not know the exact line number or file path of the program that the programmer wants to access. In such a scenario, the programmer can open the desired program and select the line that the programmer wants to insert the assertion. Additionally, other techniques can also be implemented for sending an assertion from the assertion software to the simulator and/or compiler (or other program).

0055One should note that in at least one embodiment, the assertion software can be configured to prompt the user for the desired outputs of the assertion. Upon receiving the desired outputs and executing the assertion, the assertion software may then compare the actual outputs of the assertion with the desired outputs of the assertions to determine whether the assertion is operating properly. Other techniques for determining the operation of an assertion are also contemplated.

0056<figref idref="DRAWINGS">FIG. 12</figref> is a flowchart illustrating exemplary steps that can be taken for testing the assertion from <figref idref="DRAWINGS">FIG. 4</figref>. As illustrated, the first step in the flowchart of <figref idref="DRAWINGS">FIG. 12</figref> is to receive an assertion (block <b>1230</b>). The assertion can be received from a simulator, compiler, etc, however this is not a requirement. As discussed above, at least one embodiment can include receiving the assertion via direct user input. Regardless of the source of the assertion, the assertion software can determine the assertion variables (block <b>1232</b>). As the assertion can implement one or more variable, the assertion software can be configured to automatically determine the variables that are to be tested. Additionally, some embodiments can be configured to receive user input regarding the variables and values of those variables to test.

0057The next step in the flowchart of <figref idref="DRAWINGS">FIG. 12</figref> is to run the assertion (block <b>1234</b>). As stated above, the assertion can automatically run (and/or be tested) when the assertion is received at the assertion software. Other embodiments can provide for the programmer to determine when the assertion software is run. Once the assertion is run, a determination of whether the assertion is correct can be performed (block <b>1236</b>). The programmer can perform the determination, however this is not a requirement. In some embodiments the assertion software <b>408</b> can be configured to receive data related to the desired violations, in addition to the assertion <b>408</b>. The assertion software can then compare the assertion <b>408</b> with the desired violations to determine whether the assertion is written correctly.

0058If the assertion <b>408</b> is not correct, the assertion software can facilitate amending the assertion <b>408</b> (block <b>1240</b>). In at least one embodiment, the assertion software can facilitate amending the assertion <b>408</b> by providing an option for the programmer to change assertion <b>408</b>. Once the assertion has been amended, the flowchart returns to block <b>1232</b> to determine the assertion variables. From this point, the flowchart proceeds as before. If, on the other hand, the assertion is correct (at block <b>1236</b>), the flowchart can facilitate inserting the assertion into the simulator, compiler, etc. (block <b>1238</b>). One should note that, in some situations, the programmer may not desire to insert the assertion back into the program. More specifically, in some embodiments the programmer may determine that the assertion is correct, and thus does not need to be changed in the simulator. In these situations, the flowchart may not include this step.

0059One should note that the flowcharts included herein show the architecture, functionality, and operation of a possible implementation of software. In this regard, each block can be interpreted to represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that in some alternative implementations, the functions noted in the blocks may occur out of the order. For example, two blocks shown in succession may in fact be executed substantially concurrently or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved.

0060It should be emphasized that the above-described embodiments are merely possible examples of implementations, merely set forth for a clear understanding of the principles of this disclosure. Many variations and modifications may be made to the above-described embodiment(s) without departing substantially from the spirit and principles of the disclosure. All such modifications and variations are intended to be included herein within the scope of this disclosure.