Power controller, a method of operating the power controller and a semiconductor memory system employing the same

CROSS-REFERENCE TO PROVISIONAL APPLICATION

0001This application claims the benefit of U.S. Provisional Application No. 60/862,705 entitled “Leakage Reduction Modes for Semiconductor Memories” to Michael P. Clinton, et al., filed on Oct. 24, 2006, which is incorporated herein by reference in its entirety.

TECHNICAL FIELD

0002The present disclosure is directed, in general, to memory systems and, more specifically, to a power controller, a method of operating a power controller and a semiconductor memory system employing the controller or the method.

BACKGROUND

0003Portable electronic devices are increasingly more feature-rich, often requiring wireless communications and multimedia processing. These devices are also trending toward smaller physical size and increased computing power. CMOS circuits can play a dominant role in such devices, which are often integrated to the point of having a complete system on a chip (SoC). Even though these devices are smaller in size, power requirements typically have not diminished due to the demand for increased functionality. Additionally, applications require memories that can offer low leakage currents while still providing fast access and cycle times. Although current devices are providing acceptable performance, further improvements would prove beneficial in the art.

SUMMARY

0004Embodiments of the present disclosure provide a power controller, a method of operating a power controller and a semiconductor memory system. In one embodiment, the power controller is for use with a memory and includes an access module configured to provide an active state of the memory to allow memory access. The power controller also includes a retain-till-access module configured to cycle a portion of the memory between the active state and a low leakage data retention state of the memory. The power controller further includes an expanded retain-till-access module configured to extend the active state of the memory for a specified period of time before returning the memory to the low leakage data retention state.

0005In another aspect, the present disclosure provides a method of operating a power controller for use with a memory. The method includes providing an active state of the memory that allows memory access and cycling a portion of the memory between the active state and a low leakage data retention state of the memory. The method also includes extending the active state of the memory for a specified period of time before returning the memory to the low leakage data retention state.

0006The present disclosure also provides, in yet another aspect, a semiconductor memory system. The semiconductor memory system includes a plurality of memory blocks, a power supply coupled to the plurality of memory blocks and a power controller coupled to the power supply. The power controller has an input module that receives first and second memory mode signals and provides mutually exclusive access, retain-till-access and expanded retain-till-access control signals. The power controller also has an access module, coupled to the access output control signal, which provides an active state of the memory to allow memory access. The power controller additionally has a retain-till-access module, coupled to the retain-till-access control signal, which cycles a portion of the memory between the active state and a low leakage data retention state of the memory. The power controller further has an expanded retain-till-access module, coupled to the expanded retain-till-access control signal, which extends the active state of the memory for a specified period of time before returning the memory to the low leakage data retention state. The power controller still further has an output module that provides an output status signal corresponding to extending the active state.

0007The foregoing has outlined preferred and alternative features of the present disclosure so that those skilled in the art may better understand the detailed description of the disclosure that follows. Additional features of the disclosure will be described hereinafter that form the subject of the claims of the disclosure. Those skilled in the art will appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

0008For a more complete understanding of the present disclosure, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

0009<figref idref="DRAWINGS">FIG. 1</figref> illustrates a block diagram of a semiconductor memory system as provided by one embodiment of the disclosure;

0010<figref idref="DRAWINGS">FIG. 2</figref> illustrates a diagram of memory power states as provided by one embodiment of the disclosure; and

0011<figref idref="DRAWINGS">FIG. 3</figref> illustrates a flow diagram of a method of operating a power controller carried out according to the principles of the present disclosure.

DETAILED DESCRIPTION

0012In systems, including SoC designs, there are often many memories that are used in varied ways. Some require fast access and cycle time and do not need low leakage current. Others may need a low leakage current and can suffer slightly lower access and cycle times that are required to get the low leakage current. Still other memories need good leakage current reduction with the fastest possible access and cycle time. Embodiments of the present disclosure provide solutions that address these various memory requirements.

0013<figref idref="DRAWINGS">FIG. 1</figref> illustrates a block diagram of a semiconductor memory system <b>100</b> as provided by one embodiment of the disclosure. The semiconductor memory system <b>100</b> includes a plurality of memory blocks <b>105</b>, a power supply <b>110</b> coupled to the plurality of memory blocks <b>105</b>, and a power controller <b>120</b> coupled to the power supply <b>110</b>. The semiconductor memory system <b>100</b> also includes first and second input memory mode signals <b>101</b><i>a</i>, <b>101</b><i>b </i>and an output status signal <b>103</b>. The power controller <b>120</b> includes an input module <b>121</b>, an access module <b>122</b>, a retain-till-access module <b>123</b>, an expanded retain-till-access module <b>124</b> and an output module <b>125</b>.

0014The plurality of memory blocks <b>105</b> employ static random access memory (SRAM) cells, in the illustrated embodiment. The power supply provides each memory block with positive and negative supply voltages. The positive and negative supply voltages are scalable in voltage value as directed by the power controller <b>120</b>. This scalability allows each of the memory blocks to range between a fully powered supply voltage that is needed for memory access and a retention supply voltage employed to retain data storage while reducing active leakage current in the plurality of memory blocks <b>105</b>.

0015The input module <b>121</b> receives the first and second input memory mode signals <b>101</b><i>a</i>, <b>101</b><i>b</i>, which determine an operating mode for the memory blocks <b>105</b>. The input module <b>121</b> then provides mutually exclusive access, retain-till-access and expanded retain-till-access control signals for the power controller <b>120</b>. The access module <b>122</b> is controlled by the access control signal and provides an active state of the memory blocks <b>105</b> that allows memory access, when enabled by the access control signal. In this operating mode, all of the memory blocks <b>105</b> are fully powered allowing minimum access and cycle times for memory reading and writing.

0016The retain-till-access module <b>123</b> is controlled by the retain-till-access control signal and, when enabled, cycles a memory block <b>105</b><i>a </i>between the active state and a low leakage data retention state that is employed for all of the memory blocks <b>105</b>. In this operating mode, only the memory block <b>105</b><i>a </i>is allowed to be fully powered to provide minimum access and cycle times for memory reading and writing. The low leakage data retention state provides a minimum powered leakage for all of the memory blocks <b>105</b>. The memory block <b>105</b><i>a </i>is a representative portion of the memory blocks <b>105</b> wherein it corresponds to a memory block controlled by a group of 32 word lines, in the illustrated embodiment. Of course, any grouping of word lines may define a memory block as deemed appropriate to a particular memory application.

0017The expanded retain-till-access module <b>124</b> is controlled by the expanded retain-till-access control signal. This operating mode extends the active state of all of the memory blocks <b>105</b> for a specified period of time before returning all of them to the low leakage data retention state. In one embodiment, the specified period of time restarts after each memory access that occurs during the extended active state. The specified period of time may correspond to a selected number of clock cycles employing a control counter. Alternatively, the specified period of time may be determined independent of the number of clock cycles. In either case, the specified period of time may be programmable. The output module <b>125</b> provides an output status signal that corresponds to extending the active state. This indicates that the memory blocks <b>105</b> are still in the active state that allows minimum access and cycle times for memory reading and writing.

0018<figref idref="DRAWINGS">FIG. 2</figref> illustrates a diagram of memory power states <b>200</b> as provided by one embodiment of the disclosure. The memory power states <b>200</b> include a low leakage data retention state <b>205</b>, an active state <b>210</b> and an extended active state <b>215</b>. These states may be determined by a power controller such as the power controller <b>120</b> for a memory such as the plurality of memory blocks <b>105</b> of <figref idref="DRAWINGS">FIG. 1</figref>. The low leakage data retention state <b>205</b> is applied to the entire memory when at least a portion of the memory is not residing in another state. In the low leakage data retention state <b>205</b>, the supply voltage across the memory is reduced to provide the smallest powered or active leakage current for the memory. Alternatively, the active state <b>210</b> corresponds to the largest leakage current of the memory.

0019A cycle of operating states for the entire memory is different than one employed when only a portion of the memory is accessed. A cycle path <b>206</b>, <b>211</b>, <b>216</b> is employed for the entire memory. Transitioning from the low leakage data retention state <b>205</b> to the active state <b>210</b> for the entire memory typically produces an access latency period of at least one clock cycle. This allows time for the entire memory to become fully active from its having been in a retention mode or “sleep mode”. After this latency period, the entire memory may be accessed at minimum access and cycle times for reading or writing. At the completion of a memory access, the entire memory transitions to the extended active state <b>215</b>.

0020In the extended active state <b>215</b>, the entire memory may still be accessed at minimum access and cycle times, without latency. The extended active state <b>215</b> continues until either another memory access occurs within a pre-selected, specified period of time, or the time period expires without memory access. When the time period expires without memory access, the entire memory returns to the low leakage data retention state <b>205</b>, thereby completing a memory cycle.

0021A cycle path <b>206</b>, <b>207</b> is employed when only a portion of the memory is activated for reading or writing. Transitioning the portion of the memory from the low leakage data retention state <b>205</b> to the active state <b>210</b> typically does not produce an access latency period large enough to prohibit the memory portion from being accessed during the same clock cycle. This occurs since the capacitances associated with the memory portion selected are typically small enough to allow recovery to full power quickly. The memory portion is returned to the low leakage data retention state <b>205</b> after each memory access. This allows the entire memory or a portion of the memory to be activated for another memory access.

0022<figref idref="DRAWINGS">FIG. 3</figref> illustrates a flow diagram of a method of operating a power controller <b>300</b> carried out according to the principles of the present disclosure. The method <b>300</b> is for use with a memory in a powered state and starts in a step <b>305</b>. Then, in a first decisional step <b>310</b>, it is determined if an access mode of the memory has been selected by an enabling access control signal. If the access mode has been selected, a fully active state is provided that allows access for reading from and writing to all of the memory, in a step <b>315</b>. After each memory access in the step <b>315</b>, a second decisional step <b>320</b> determines if the memory is still in the powered state. If the memory is still in the powered state and the access mode of the first decisional step <b>310</b> is still enabled, the method <b>300</b> returns to the step <b>315</b> for the next memory access.

0023If the first decisional step <b>310</b> determines that the access mode is not enabled, the method <b>300</b> continues to the third decisional step <b>325</b> wherein it is determined if a retain-till-access mode of the memory has been selected by an enabling retain-till-access control signal. If the retain-till-access mode has been selected, the fully active state is provided for a portion of the memory thereby allowing the memory portion to be accessed, in a step <b>330</b>. Correspondingly, the remainder of the memory resides in a low leakage data retention state, which provides a minimum active leakage current for the remainder of the memory. In the fully active state, the portion of the memory is accessed only once before it cycles to the low leakage data retention state. This places all of the memory in the low leakage data retention state.

0024As before, the second decisional step <b>320</b> determines if the memory is still in the powered state. If the memory is still powered, and the first and third decisional steps <b>310</b>, <b>325</b> determine that the access mode is not enabled and the retain-till-access mode is still enabled, the method <b>300</b> returns to the step <b>330</b> for the next access of the portion of the memory.

0025If the first and third decisional steps <b>310</b>, <b>325</b> determine that the access and retain-till-access modes are not enabled, the method <b>300</b> continues to a step <b>335</b>, which is an expanded retain-till-access mode. An expanded retain-till-access control signal enables the expanded retain-till-access mode, wherein all of the memory is initially placed in the low leakage data retention state thereby providing the minimum active leakage current for the memory. The fully active state is provided for all of the memory when it is accessed.

0026In this mode, the fully active state of the memory is extended for a specified period of time before the memory is returned to the low leakage data retention state. In one embodiment, extending the fully active state restarts after each memory access during the specified period of time. Additionally, the specified period of time may correspond to a preset timer or to a selected number of clock cycles that may be measured by a control counter. In either of these cases, the specified period of time may be programmable. A fully active state status signal is provided during the specified period of time to indicate that memory access is immediately available.

0027After the memory is returned to the low leakage data retention state, the second decisional step <b>320</b> again determines if the memory is still in the powered state. If the memory is still powered, and the first and third decisional steps <b>310</b>, <b>325</b> determine that the access and the retain-till-access modes are not enabled, the method <b>300</b> returns to the step <b>335</b> for the next memory access. In this manner, the method <b>300</b> continues to select an appropriate mode as long as the memory remains in the powered state. If the second decisional step <b>320</b> determines that the memory is not in the powered state, the method <b>300</b> ends in a step <b>340</b>.

0028While the method disclosed herein has been described and shown with reference to particular steps performed in a particular order, it will be understood that these steps may be combined, subdivided, or reordered to form an equivalent method without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order or the grouping of the steps is not a limitation of the present disclosure.

0029Those skilled in the art to which the disclosure relates will appreciate that other and further additions, deletions, substitutions and modifications may be made to the described example embodiments without departing from the disclosure.