Reconfigurable integrated circuit, circuit reconfiguration method and circuit reconfiguration apparatus

0001This application is based on application No. 2006-288579 filed in Japan, the contents of which are hereby incorporated by reference.

BACKGROUND OF THE INVENTION

0002[1] Field of the Invention

0003The present invention relates to a dynamic reconfigurable arithmetic circuit capable of dynamically changing a logical configuration, especially to hardware resources required for changing the configuration of the dynamic reconfigurable arithmetic circuit.

0004[2] Description of the Related Art

0005In late years, a dynamic reconfigurable arithmetic circuit (generally referred to as “dynamic reconfigurable logic”) capable of changing its logical configuration according to a program has been proposed for the purpose of enabling both flexibility in software processing and high-speed capability of hardware processing.

0006As of now, FPGA (Field Programmable Gate Array) and PLD (Programmable Logic Device) are well known as devices whose logical configuration can be changed according to a program. FPGAs and PLDs are capable of changing, for example, connections between internal transistors dynamically to some extent in accordance with a program, to thereby restructure a circuit having a different function on the whole.

0007However, simple FPGAs and PLDs require many hardware resources for changing the configuration, resulting in an increase in area. Hardware resources required for changing the configuration are, specifically speaking, a storage unit for storing configuration information that defines the configuration of FPGA and the like, and a wiring group for appropriately distributing configuration information to each reconfiguration element, for example.

0008[Patent Reference 1] Published Japanese Translation of PCT International Publication for Patent Applications 2004-505488

SUMMARY OF THE INVENTION

0009The present invention aims at providing a circuit reconfiguration apparatus, a circuit reconfiguration method, and an integrated circuit, all of which are capable of reducing, within a dynamic reconfiguration arithmetic circuit, an area occupied by hardware resources required for configuration change.

0010In order to achieve the objective, the present invention is an integrated circuit capable of changing an internal configuration thereof, comprising: a reconfiguration arithmetic block (i) including a plurality of reconfigurable arithmetic cells and a plurality of cell storage units each of which corresponds to a different one of the arithmetic cells and stores therein a piece of original configuration information indicating all or part of a configuration of the corresponding arithmetic cell, (ii) outputting an output set including therein pieces of original configuration information stored in the cell storage units, (iii) receiving an input set including therein one or some of the pieces of original configuration information included in the output set and one or more pieces of alternative configuration information, each of which is to replace a corresponding one of remaining pieces of original configuration information included in the output set and indicates all or part of a new configuration of a corresponding arithmetic cell whose configuration needs to be changed, and (iv) reconfiguring the arithmetic cells according to the one or some of the pieces of original configuration information and the one or more pieces of alternative configuration information included in the received input set; a storage unit storing therein the one or more pieces of alternative configuration information; and a control unit operable to (i) control the reconfiguration arithmetic block to obtain the output set therefrom, (ii) for each arithmetic cell whose configuration needs not to be changed, select a corresponding piece of original configuration information from the output set, and for each arithmetic cell whose configuration needs to be changed, select a corresponding piece of alternative configuration information stored in the storage unit in place of the corresponding piece of original configuration information in the output set, and (iii) output, to the reconfiguration arithmetic block, the input set in which the one or some of the pieces of original configuration information are the selected pieces of original configuration information and the one or more pieces of alternative configuration information are the selected pieces of alternative configuration information.

0011Here, the “reconfiguration arithmetic block” above corresponds to a dynamic reconfiguration arithmetic block <b>2010</b> shown in <figref idref="DRAWINGS">FIG. 1</figref> of Embodiment 1. In addition, the function of the “storage unit” is fulfilled by a configuration information storage unit <b>3000</b> of Embodiment 1. The function of the “control unit” is fulfilled by a configuration information selector <b>3400</b>, a cell address comparator <b>4000</b>, a cell address counter <b>5000</b>, a reconfiguration cell address storage unit <b>6000</b> and a storage unit address counter <b>8000</b>.

0012According to the structure, the control unit (i) selects a piece of alternative configuration information for each of the arithmetic cells whose configuration needs to be changed while selecting a piece of original configuration information for each of the arithmetic cells whose configuration needs not to be changed, and (ii) outputs an output set made up of the selected pieces of alternative and original configuration information. The reconfiguration arithmetic block reconfigures each arithmetic cell according to the pieces of the original and alternative configuration information included in the output set.

0013Therefore, in the case of changing the configuration of the reconfiguration arithmetic block, the storage unit only has to store pieces of alternative configuration information corresponding to arithmetic cells whose configuration needs to be changed. Accordingly, a reduction in the capacity of the storage unit can be realized.

0014Further, in the present invention, the control unit may repeat (i) outputting a timing signal to the reconfiguration arithmetic block, (ii) obtaining apiece of original configuration information included in the output set, and (iii) selecting one of the obtained piece of original configuration information and a piece of alternative configuration information based on whether the obtained piece of original configuration information corresponds to an arithmetic cell whose configuration needs to be changed and outputting the selected piece to the reconfiguration arithmetic block. Further, the arithmetic cells may be respectively connected to the corresponding cell storage units. Here, the cell storage units are connected in series together to form a shift register. At each time when the timing signal is received from the control unit, (i) a cell storage unit located at a last end of the shift register outputs the piece of original configuration information stored therein, (ii) each of remaining storage units other than the cell storage unit located at the last end shifts the piece of original configuration information or a piece of alternative information, whichever is stored therein, to a neighboring cell storage unit in a direction of the last end, and (iii) a cell storage unit located at a first end of the shift register stores therein a piece of original configuration information included in the output set or a piece of alternative configuration information.

0015The above-mentioned Patent Reference 1 discloses a technology for reducing the capacity of the storage unit required for changing the configuration of the reconfiguration arithmetic block. According to the technology, the reconfiguration arithmetic block includes therein a shift register for transmitting configuration data, data lines for transmitting configuration data in the direction perpendicular to the shift register, and a mask register for preventing new configuration information (which corresponds to alternative configuration information of the present invention) from being transmitted to arithmetic cells whose configuration will not be changed. One data line is provided for each row while one mask register is provided for each column. Therefore, if the reconfiguration arithmetic block increases in size, the area occupied by the data lines and mask registers also increases.

0016In comparison, according to the integrated circuit of the present invention, a piece of original configuration information is output to the control unit from the cell storage unit located at the last end of the shift register in response to the timing signal functioning as a trigger. Each of the remaining cell storage units shifts a piece of original configuration information or a piece of alternative information, whichever is stored therein, and the cell storage unit located at the first end of the shift register stores therein a piece of original configuration information or a piece of alternative configuration information output from the control unit.

0017That is, within the reconfiguration arithmetic block, the shift register is the only component relating to configuration change. In addition, the circuit size of the control unit is substantially not influenced by the size of the reconfiguration arithmetic block. Accordingly, when the size of the reconfiguration arithmetic block increases—i.e. when the total number of arithmetic cells increases, the shift register is the only component whose area increases. Therefore, in comparison to the above-mentioned patent reference, the present invention is able to inhibit an increase in the total area of the circuit associated with size expansion of the reconfiguration arithmetic block.

0018In the present invention, the arithmetic cells may be respectively identified by different identification numbers that are assigned serially in an order of the corresponding arithmetic cells being connected to the shift register. Here, the control unit (i) stores therein at least one reconfiguration target identification number which indicates an arithmetic cell whose configuration needs to be changed, (ii) holds a counter value, (iii) repeatedly outputs the timing signal, and (iv) performs repetition of, for each output of the timing signal, adding a constant value to the holding counter value, making a comparison between the added counter value and the reconfiguration target identification number, and selecting the piece of alternative configuration information when the comparison shows agreement and selecting the output piece of original configuration information when the comparison shows disagreement.

0019According to the structure, each of the arithmetic cells is identified by a different identification number. Here, the control unit compares the added counter value against the stored reconfiguration target identification number, and selects the piece of alternative configuration information when the comparison shows agreement and selects the output piece of original configuration information when the comparison shows disagreement.

0020Therefore, according to the present invention, the control unit is able to make such a selection by a simple process, comparison.

0021In the present invention, the control unit may include: a reconfiguration cell address storage unit sequentially storing therein the at least one reconfiguration target identification number, a cell address counter operable holding the counter value and operable to repeatedly output the timing signal and add the constant value to the counter value at each output of the timing signal, an address counter operable to determine a read address in the storage unit and in the reconfiguration cell address storage unit; a cell address comparison unit operable to make a comparison, at each time when the timing signal is output, between the added counter value and an identification number stored at the determined read address in the reconfiguration cell address storage unit; and an information selection unit operable to repeat, for each comparison, (i) selecting the piece of alternative configuration information stored at a location indicated by the determined read address in the storage unit when the comparison shows agreement and selecting the output piece of original configuration information when the comparison shows disagreement, and (ii) outputting the selected piece to the cell storage unit located at the first end. Here, the storage unit stores therein at least one piece of alternative configuration information in association with at least one piece of reconfiguration target identification number.

0022According to the structure, the control unit can be realized by combining simple circuits, such as a counter, a comparator and an adder.

0023In the present invention, when the comparison made by the cell address comparison unit shows agreement, the address counter may set, as a new read address, a value obtained by adding 1 to the read address.

0024According to the structure, the address counter is able to update the read address by a simple arithmetic operation, addition.

0025In the present invention, the address counter may store therein an initial address of the reconfiguration cell address storage unit, externally obtain a reconfiguration instruction requesting reconfiguration of the reconfiguration arithmetic block, and set the initial address as the read address when obtaining the reconfiguration instruction.

0026Since storing therein the initial address of the reconfiguration cell address storage unit, the address counter is able to quickly determine an initial read address when receiving the reconfiguration instruction.

0027In the present invention, the address counter may store an end address of the reconfiguration cell address storage unit, and stop adding 1 to the read address when the read address is equal to the end address.

0028According to the structure, the address counter stops updating the read address when the read address is equal to the end address. The cell address storage unit may be realized by a region within a large capacity memory.

0029According to the structure, since the address counter stops updating the read address when the read address is equal to the end address, data is not referred to if it has no relevance to configuration change. Accordingly, the integrated circuit of the present invention is capable of reconfiguring the reconfiguration arithmetic block in a reliable manner.

0030In the present invention, the control unit may stop the repetition when the counter value is equal to an identification number which indicates an arithmetic cell corresponding to the cell storage unit located at the first end.

0031According to the structure, the control unit stops the repetition when the counter value is equal to the identification number which indicates an arithmetic cell corresponding to the cell storage unit located at the first end. Therefore, for each cell storage unit corresponding to an arithmetic cell whose configuration is not to be changed, a piece of original configuration information originally stored therein before the configuration change is started is returned; for each cell storage unit corresponding to an arithmetic cell whose configuration needs to be changed, a piece of alternative configuration information is stored therein. Thus, the present invention is capable of completing the configuration change of the reconfiguration arithmetic block in a reliable manner.

0032In the present invention, each of the cell storage units may store therein, as the piece of original configuration information, an original arithmetic parameter indicating part of the configuration of the corresponding arithmetic cell. Here, the storage unit stores therein, as the piece of alternative configuration information, an alternative arithmetic parameter indicating part of the configuration of the corresponding arithmetic cell. The reconfiguration arithmetic block rewrites an arithmetic parameter configuring each of the arithmetic cells according to one of the original arithmetic parameter included in the input set and the alternative arithmetic parameter.

0033According to the structure, within the information indicating the configuration of each arithmetic cell, only the arithmetic parameter is changed. This results in a further reduction in the storage capacity of the storage unit.

0034In the present invention, the reconfiguration arithmetic block and the control unit may be connected by a 1^stwiring and a 2^ndwiring, and the storage unit and the control unit are connected by a 3^rdwiring. Here, the reconfiguration arithmetic block outputs the output set to the control unit via the 1^stwiring. The control unit obtains the output set via the 1^stwiring, obtains the one or more pieces of alternative configuration information via the 3^rdwiring, and outputs the input set to the reconfiguration arithmetic block via the 2^ndwiring. Further, the present invention may be an image processing apparatus having thereon the above-mentioned integrated circuit and causing the circuit reconfiguration apparatus to reconfigure the reconfiguration arithmetic block during one of a vertical blanking period and a horizontal blanking period. Further, the present invention may be an information processing apparatus having thereon the above-mentioned integrated circuit and causing the circuit reconfiguration apparatus to reconfigure the reconfiguration arithmetic block during a period in which a process by a circuit established on the reconfiguration arithmetic block does not have to be performed.

0035According to the structure, an apparatus having thereon the integrated circuit is able to make efficient use of time for changing the configuration of the reconfiguration arithmetic block.

0036The present invention may be an integrated circuit capable of changing an internal configuration thereof, comprising: a reconfiguration arithmetic block (i) including a plurality of reconfigurable arithmetic cells and a plurality of cell storage units each of which corresponds to a different one of the arithmetic cells and stores therein a piece of original configuration information indicating all or part of a configuration of the corresponding arithmetic cell, (ii) outputting an output set including therein pieces of original configuration information stored in the cell storage units, (iii) receiving an input set including therein one or some of the pieces of original configuration information included in the output set and one or more pieces of alternative configuration information, each of which is to replace a corresponding one of remaining pieces of original configuration information included in the output set and indicates all or part of a new configuration of a corresponding arithmetic cell whose configuration needs to be changed, and (iv) reconfiguring the arithmetic cells according to the one or some of the pieces of original configuration information and the one or more pieces of alternative configuration information included in the received input set; an obtaining unit operable to obtain the one or more pieces of alternative configuration information; and a control unit operable to (i) control the reconfiguration arithmetic block to obtain the output set therefrom, (ii) for each arithmetic cell whose configuration needs not to be changed, select a corresponding piece of original configuration information from the output set, and for each arithmetic cell whose configuration needs to be changed, select a corresponding piece of alternative configuration information obtained by the obtaining unit in place of the corresponding piece of original configuration information in the output set, and (iii) output, to the reconfiguration arithmetic block, the input set in which the one or some of the pieces of original configuration information are the selected pieces of original configuration information and the one or more pieces of alternative configuration information are the selected pieces of alternative configuration information. Further, the present invention may be a circuit reconfiguration method used in an integrated circuit capable of changing an internal configuration thereof. Here, the integrated circuit includes: a reconfiguration arithmetic block (i) including a plurality of reconfigurable arithmetic cells and a plurality of cell storage units each of which corresponds to a different one of the arithmetic cells and stores therein a piece of original configuration information indicating all or part of a configuration of the corresponding arithmetic cell, (ii) outputting an output set including therein pieces of original configuration information stored in the cell storage units, (iii) receiving an input set including therein one or some of the pieces of original configuration information included in the output set and one or more pieces of alternative configuration information, each of which is to replace a corresponding one of remaining pieces of original configuration information included in the output set and indicates all or part of a new configuration of a corresponding arithmetic cell whose configuration needs to be changed, and (iv) reconfiguring the arithmetic cells according to the one or some of the pieces of original configuration information and the one or more pieces of alternative configuration information included in the received input set. The circuit reconfiguration method includes: an obtaining step of obtaining the one or more pieces of alternative configuration information; and a control step of (i) controlling the reconfiguration arithmetic block to obtain the output set therefrom, (ii) for each arithmetic cell whose configuration needs not to be changed, selecting a corresponding piece of original configuration information from the output set, and for each arithmetic cell whose configuration needs to be changed, selecting a corresponding piece of alternative configuration information obtained in the obtaining step in place of the corresponding piece of original configuration information in the output set, and (iii) outputting, to the reconfiguration arithmetic block, the input set in which the one or some of the pieces of original configuration information are the selected pieces of original configuration information and the one or more pieces of alternative configuration information are the selected pieces of alternative configuration information. Further, the present invention may be a circuit reconfiguration apparatus comprising: a reconfiguration arithmetic block (i) including a plurality of reconfigurable arithmetic cells and a plurality of cell storage units each of which corresponds to a different one of the arithmetic cells and stores therein a piece of original configuration information indicating all or part of a configuration of the corresponding arithmetic cell, (ii) outputting an output set including therein pieces of original configuration information stored in the cell storage units, (iii) receiving an input set including therein one or some of the pieces of original configuration information included in the output set and one or more pieces of alternative configuration information, each of which is to replace a corresponding one of remaining pieces of original configuration information included in the output set and indicates all or part of a new configuration of a corresponding arithmetic cell whose configuration needs to be changed, and (iv) reconfiguring the arithmetic cells according to the one or some of the pieces of original configuration information and the one or more pieces of alternative configuration information included in the received input set; an obtaining unit operable to obtain the one or more pieces of alternative configuration information; and a control unit operable to (i) control the reconfiguration arithmetic block to obtain the output set therefrom, (ii) for each arithmetic cell whose configuration needs not to be changed, select a corresponding piece of original configuration information from the output set, and for each arithmetic cell whose configuration needs to be changed, select a corresponding piece of alternative configuration information obtained by the obtaining unit in place of the corresponding piece of original configuration information in the output set, and (iii) output, to the reconfiguration arithmetic block, the input set in which the one or some of the pieces of original configuration information are the selected pieces of original configuration information and the one or more pieces of alternative configuration information are the selected pieces of alternative configuration information.

0037According to the structure, original configuration information, in the output set, corresponding to arithmetic cells whose configuration needs not to be changed can be reused.

BRIEF DESCRIPTION OF THE DRAWINGS

0038These and other objects, advantageous effects and features of the invention will become apparent from the following description thereof taken in conjunction with the accompanying drawings which illustrate specific embodiments of the invention. In the drawings:

0039<figref idref="DRAWINGS">FIG. 1</figref> is a block diagram showing a structure of a dynamic reconfiguration arithmetic circuit <b>110</b> according to Embodiment 1 of the present invention;

0040<figref idref="DRAWINGS">FIG. 2</figref> is a block diagram showing a structure of a shift register <b>2300</b> of Embodiment 1 of the present invention;

0041<figref idref="DRAWINGS">FIG. 3</figref> is an operation scheduling diagram for configuration change in the dynamic reconfiguration arithmetic circuit <b>110</b> of Embodiment 1 of the present invention;

0042<figref idref="DRAWINGS">FIG. 4</figref> shows a list of numbers of operation cells <b>2100</b> whose configuration has to be changed according to Embodiment 1 of the present invention;

0043<figref idref="DRAWINGS">FIG. 5</figref> shows a list of configuration information data values of the dynamic reconfiguration arithmetic block <b>2010</b> in individual configurations according to Embodiment 1 of the present invention;

0044<figref idref="DRAWINGS">FIG. 6</figref> shows a reconfiguration cell address setting of each configuration area in a reconfiguration cell address storage unit <b>6000</b> according to Embodiment 1 of the present invention;

0045<figref idref="DRAWINGS">FIG. 7</figref> shows a configuration information data setting of each configuration area in a configuration information storage unit <b>3000</b> according to Embodiment 1 of the present invention;

0046<figref idref="DRAWINGS">FIG. 8</figref> shows a control flow for configuration change according to Embodiment 1 of the present invention;

0047<figref idref="DRAWINGS">FIG. 9</figref> shows relationship among individual configuration elements on a cycle basis for the time when the configuration is changed from Configuration A to Configuration B, according to Embodiment 1 of the present invention;

0048<figref idref="DRAWINGS">FIG. 10</figref> is a block diagram showing a quality enhancing apparatus <b>18001</b> using a dynamic reconfiguration arithmetic circuit <b>110</b> of Embodiment 2 of the present invention;

0049<figref idref="DRAWINGS">FIG. 11</figref> shows a calculation formula 1 of a filtering process performed by a video quality enhancing circuit <b>19000</b> according to Embodiment 2 of the present invention;

0050<figref idref="DRAWINGS">FIG. 12</figref> shows a calculation formula 2 of a filtering process performed by the video quality enhancing circuit <b>19000</b> according to Embodiment 2 of the present invention;

0051<figref idref="DRAWINGS">FIG. 13</figref> shows the processing order of video images according to Embodiment 2 of the present invention;

0052<figref idref="DRAWINGS">FIG. 14</figref> shows relationship between a vertical blanking area and a valid area for video image transmission according to Embodiment 2 of the present invention;

0053<figref idref="DRAWINGS">FIG. 15</figref> shows an external appearance of a mobile communication apparatus <b>10000</b> using the dynamic reconfiguration arithmetic circuit <b>110</b> of Embodiment 3 of the present invention;

0054<figref idref="DRAWINGS">FIG. 16</figref> shows a modification of the dynamic reconfiguration arithmetic circuit of the present invention;

0055<figref idref="DRAWINGS">FIG. 17</figref> is a block diagram showing a specific example of Modification (18);

0056<figref idref="DRAWINGS">FIG. 18</figref> is a block diagram showing a specific example of Modification (19); and

0057<figref idref="DRAWINGS">FIG. 19</figref> is a schematic diagram of a dynamic reconfiguration arithmetic circuit apparatus of Patent Reference 1.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

1. Embodiment 1

0058The following describes Embodiment 1 of the present invention in reference to drawings.

00591.1 Structure

0060<figref idref="DRAWINGS">FIG. 1</figref> is a functional block diagram showing a structure of a dynamic reconfiguration arithmetic circuit <b>110</b> according to Embodiment 1 of the present invention.

0061The circuit is composed of a dynamic reconfiguration arithmetic block <b>2010</b>, a configuration information storage unit <b>3000</b>, a configuration information selector <b>3400</b>, a cell address comparator <b>4000</b>, a cell address counter <b>5000</b>, a reconfiguration cell address storage unit <b>6000</b>, a storage unit address counter <b>8000</b>, a configuration information input bus <b>3100</b>, a configuration information output bus <b>3200</b>, a configuration information transmission bus <b>3300</b>, a cell address comparator output line <b>4100</b>, a cell address counter output line <b>5100</b>, a reconfiguration cell address storage unit output line <b>6100</b>, and a storage unit address counter output line <b>8100</b>.

0062The dynamic reconfiguration arithmetic block <b>2010</b> includes sixteen dynamic reconfiguration arithmetic cells <b>2100</b>-<b>10</b>, <b>2100</b>-<b>02</b>, <b>2100</b>-<b>03</b>, . . . , and <b>2100</b>-<b>16</b>. The type of arithmetic operation performed by each arithmetic cell and a connection configuration for arithmetic operation data can be changed. To the operation cells <b>2100</b>, cell addresses <b>16</b> to <b>01</b> are assigned sequentially in descending order from one closest to the input terminal of a shift register <b>2300</b>. Note that, in the present specification, the dynamic reconfiguration arithmetic cells are sometimes simply referred to as “arithmetic cells” for ease of explanation.

0063In the following description, the arithmetic cells <b>2100</b>-<b>01</b>, <b>2100</b>-<b>02</b>, <b>2100</b>-<b>03</b>, . . . , and <b>2100</b>-<b>16</b> are denoted simply as <b>2100</b> in the case where they do not have to be particularly distinguished.

0064The next describes details of the shift register <b>2300</b> in reference to <figref idref="DRAWINGS">FIG. 2</figref>.

0065The shift register <b>2300</b> includes sixteen storage units <b>2301</b>, <b>2302</b>, <b>2303</b>, <b>2304</b>, <b>2305</b>, <b>2306</b>, <b>2307</b>, <b>2308</b>, <b>2309</b>, <b>2310</b>, <b>2311</b>, <b>2312</b>, <b>2313</b>, <b>2314</b>, <b>2315</b> and <b>2316</b>. The storage units are respectively connected to the corresponding arithmetic cells <b>2100</b>-<b>01</b>, <b>2100</b>-<b>02</b>, <b>2100</b>-<b>03</b>, . . . , and <b>2100</b>-<b>16</b>.

0066Each storage unit stores therein configuration information of a corresponding arithmetic cell. The configuration information includes information regarding the type of arithmetic operation performed by a corresponding arithmetic cell, an arithmetic parameter, and connections between arithmetic cells <b>2100</b>. For example, the storage unit <b>2303</b> corresponding to a cell address <b>03</b> stores therein wiring information that indicates to obtain a result of arithmetic operation performed by an arithmetic cell with “cell address 01” and information that indicates to “add” an arithmetic parameter “+3” to the obtained arithmetic result.

0067The sixteen storage units are cascade-connected in descending order of the cell addresses of the corresponding arithmetic cells <b>2100</b> to thereby make up the shift register <b>2300</b>. In addition, the input terminal of the shift register <b>2300</b> is connected to the configuration information input bus <b>3100</b>, and the output terminal of the shift register <b>2300</b> is connected to the configuration information output bus <b>3200</b>.

0068In addition, the storage units <b>2301</b>-<b>2316</b> making up the shift register <b>2300</b> are connected to the cell address counter <b>5000</b>, and receive a pulse signal from the cell address counter <b>5000</b>. When receiving the pulse signal, the storage unit <b>2301</b> outputs the configuration information stored therein to the configuration information output bus <b>3200</b>. At the same time, the storage unit <b>2302</b> outputs the configuration information stored therein to the storage unit <b>2301</b>, and the storage unit <b>2303</b> outputs the configuration information stored thereinto the storage unit <b>2302</b>. Each storage unit outputs the configuration information stored in itself to the neighboring storage unit, and thereby the configuration information is sequentially shifted within the shift register <b>2300</b>. At this time also, configuration information corresponding to one arithmetic cell is input from the configuration information input bus <b>3100</b> and then stored in the storage unit <b>2316</b>.

0069The following describes a mechanism for inputting configuration information planned to be changed to the shift register <b>2300</b> as the configuration of the dynamic reconfiguration arithmetic block <b>2010</b> is changed. The configuration information indicating a new configuration of arithmetic cells <b>2100</b> planned to be changed is stored in the configuration information storage unit <b>3000</b>. The change of the configuration of the arithmetic cells <b>2100</b> is realized by writing the configuration information stored in the configuration information storage unit <b>3000</b> to the shift register <b>2300</b>.

0070The configuration information is transmitted to the shift register <b>2300</b> via the configuration information selector <b>3400</b>, the configuration information transmission bus <b>3300</b>, the configuration information output bus <b>3200</b> and the configuration information input bus <b>3100</b>.

0071The configuration information output from the configuration information storage unit <b>3000</b> is transmitted to the configuration information selector <b>3400</b> via the configuration information transmission bus <b>3300</b>. In addition, the configuration information output from the shift register <b>2300</b> is transmitted to the configuration information selector <b>3400</b> through the configuration information output bus <b>3200</b>.

0072The input terminal of the shift register <b>2300</b> is connected to the configuration information input bus <b>3100</b>, which is connected to the output of the configuration information selector <b>3400</b>. The configuration information selector <b>3400</b> is controlled by the cell address comparator <b>4000</b> via the cell address comparator output line <b>4100</b>.

0073The cell address comparator <b>4000</b> is a function part controlling the configuration information selector <b>3400</b> and the storage unit address counter <b>8000</b> using its output value.

0074The cell address comparator <b>4000</b> receives an output value (a counter value that will be described later) from the cell address counter <b>5000</b> via the cell address counter output line <b>5100</b>, receives an output value from the reconfiguration cell address storage unit <b>6000</b> via the reconfiguration cell address output line <b>6100</b>, and then compares the received two values. When the two values are equal to each other, the cell address comparator <b>4000</b> sets a value output to the cell address comparator output line <b>4100</b> to 1; otherwise, the cell address comparator <b>4000</b> sets the value to 0.

0075In the case of outputting 1, the cell address comparator <b>4000</b> outputs 1 only during the time period of Δs, and sets the output value to 0 after the time period As has elapsed. Here, Δs is shorter than an interval time Δt of counting up by the cell address counter <b>5000</b> (the details will be described later with the aid of <figref idref="DRAWINGS">FIG. 9</figref>).

0076The cell address counter <b>5000</b> is initialized to 0 by the storage unit address counter <b>8000</b>. After the initialization, the cell address counter <b>5000</b> counts up the counter value by one at regular intervals (Δt). The cell address counter <b>5000</b> outputs the counter value to the cell address comparator <b>4000</b> via the cell address counter output line <b>5100</b>.

0077Additionally, the cell address counter <b>5000</b> outputs the pulse signal to the shift register <b>2300</b> making up the dynamic reconfiguration arithmetic block <b>2010</b> at each time of counting up.

0078The configuration information selector <b>3400</b> selects data on the configuration information transmission bus <b>3300</b> when the output value of the cell address comparator output line <b>4100</b> is 1, and selects data on the configuration information output bus <b>3200</b> when the output value of the cell address comparator output line <b>4100</b> is 0. Then, the configuration information selector <b>3400</b> outputs the selected data to the configuration information input bus <b>3100</b>.

0079The configuration information storage unit <b>3000</b> stores therein the configuration information of arithmetic cells <b>2100</b> planned to be changed in ascending order of the cell addresses. The reconfiguration cell address storage unit <b>6000</b> stores therein cell addresses of the arithmetic cells <b>2100</b> planned to be changed in ascending order. Within the reconfiguration cell address storage unit <b>6000</b> and the configuration information storage unit <b>3000</b>, each cell address and each piece of configuration information corresponding to the cell address, respectively, are stored in areas identified by the same memory address.

0080<figref idref="DRAWINGS">FIGS. 6 and 7</figref> show examples of the structures of the reconfiguration cell address storage unit <b>6000</b> and configuration information storage unit <b>3000</b>, respectively.

0081For example, in an area <b>3001</b>/<b>6001</b> of memory addresses 0×00-0×01 of each storage unit, data for changing the configuration of the dynamic reconfiguration arithmetic block <b>2010</b> from Configuration A to Configuration B is stored.

0082An area <b>6001</b> of the reconfiguration cell address storage unit <b>6000</b> stores therein cell addresses “10” and “11” of arithmetic cells in ascending order whose configuration information has to be changed in order to change from Configuration A to Configuration B. Specifically speaking, the cell address “10” is stored in the memory address 0×00 and the cell address “11” is stored in the memory address 0×01.

0083On the other hand, an area <b>3001</b> of the configuration information storage unit <b>3000</b> stores therein pieces of configuration information required to change from Configuration A to Configuration B in ascending order of the cell addresses corresponding to the respective pieces of the configuration information.

0084Specifically speaking, in the area of the memory address 0×00, configuration information “2315” of the arithmetic cell <b>2100</b>-<b>10</b> identified by the cell address “10” is stored. In the area of the memory address 0×01, configuration information “5778” of the arithmetic cell “11” is stored.

0085Note that each piece of the configuration information here is expressed in a four-digit decimal number, however, this is merely an example. For instance, the configuration information may be expressed in a 64-bit binary or a 128-bit binary. Or it may be more complicated or simpler configuration information.

0086The reconfiguration cell address storage unit <b>6000</b> and configuration information storage unit <b>3000</b> receive an address output from the storage unit address counter <b>8000</b> via the storage unit address counter output line <b>8100</b>. When receiving the address, these storage units <b>6000</b> and <b>3000</b> respectively read data stored in the received address, and then output each piece of the read data to the reconfiguration cell address output line <b>6100</b> and the configuration information transmission bus <b>3300</b>, respectively.

0087The storage unit address counter <b>8000</b> is a function part controlling addresses to be read by the configuration information storage unit <b>3000</b> and the reconfiguration cell address storage unit <b>6000</b>.

0088The storage unit address counter <b>8000</b> stores therein multiple pairs of initial and end addresses of an area, within the reconfiguration cell address storage unit <b>6000</b> and the configuration information storage unit <b>3000</b>, which stores therein data necessary for changing the configuration of the dynamic reconfiguration arithmetic block <b>2010</b>.

0089Specifically speaking, the storage unit address counter <b>8000</b> stores therein an initial address “0×00” and an end address “0×01” of the areas <b>3001</b> and <b>6001</b> in which data necessary for changing the dynamic reconfiguration arithmetic block <b>2010</b> from Configuration A to Configuration B is stored. In a similar manner, the storage unit address counter <b>8000</b> stores therein an initial address “0×02” and an end address “0×04” of the areas <b>3002</b> and <b>6002</b> in which data necessary for changing from Configuration B to Configuration C is stored. Also, the storage unit address counter <b>8000</b> stores therein an initial address “0×05” and an end address “0×06” of the areas <b>3003</b> and <b>6003</b> in which data necessary for changing from Configuration C to Configuration A is stored.

0090The storage unit address counter <b>8000</b> receives an instruction for starting configuration change of the dynamic reconfiguration arithmetic block <b>2010</b> from a control mechanism of the apparatus having thereon the dynamic reconfiguration arithmetic circuit <b>110</b>. Here, the received instruction includes information indicating the current configuration of the dynamic reconfiguration arithmetic block <b>2010</b> and information indicating a configuration required next. For example, information indicating “change from Configuration A to Configuration B” is included.

0091Further, the storage unit address counter <b>8000</b> may store therein information indicating the current configuration of the dynamic reconfiguration arithmetic block <b>2010</b>, and the instruction from the control mechanism may include only information indicating the configuration required next.

0092When receiving the instruction of configuration change, the storage unit address counter <b>8000</b> selects a pair of initial and end addresses based on the information indicating the current state of the dynamic reconfiguration arithmetic cells and the configuration required next.

0093Note that, instead of the storage unit address counter <b>8000</b> selecting a pair of initial and end addresses, the instruction from the control mechanism may include therein the initial and end addresses.

0094Subsequently, the storage unit address counter <b>8000</b> outputs the selected initial address to the reconfiguration cell address storage unit <b>6000</b> and the configuration information storage unit <b>3000</b> via the storage unit address counter output line <b>8100</b>. The storage unit address counter <b>8000</b> also initializes the counter value of the cell address counter <b>5000</b> to 0.

0095In addition, the storage unit address counter <b>8000</b> receives 0 and 1 from the cell address comparator output line <b>4100</b> in process of the configuration change. When the output value from the cell address comparator output line <b>4100</b> is 1, the storage unit address counter <b>8000</b> adds 1 to the value output to the storage unit address counter output line <b>8100</b>. Herewith, the address to be read by the configuration information storage unit <b>3000</b> and the reconfiguration cell address storage unit <b>6000</b> is changed.

0096Note however that, even when the output value from the cell address comparator output line <b>4100</b> is 1, if the value currently being output to the storage unit address counter output line <b>8100</b> is equal to the end address, the storage unit address counter <b>8000</b> does not increment the output value.

0097The configuration change of the dynamic reconfiguration arithmetic block <b>2010</b> is described next in detail.

00981.2 Time-lapse Configuration Change

0099<figref idref="DRAWINGS">FIG. 3</figref> is an operation scheduling diagram of configuration changes of the dynamic reconfiguration arithmetic block <b>2010</b> of the present embodiment. The dynamic reconfiguration arithmetic block <b>2010</b> is able to change the configuration in the order from Configurations A, B to C. Hereinafter, in drawings, the dynamic reconfiguration arithmetic cells are abbreviated to arithmetic cells, if necessary.

0100Regarding the changes, a list of cell addresses of the arithmetic cells <b>2100</b> whose configuration has to be changed is shown in <figref idref="DRAWINGS">FIG. 4</figref>. Also, <figref idref="DRAWINGS">FIG. 5</figref> shows a list of data values of configuration information of the dynamic reconfiguration arithmetic cells <b>2100</b>-<b>01</b>-<b>2100</b>-<b>16</b> making up the dynamic reconfiguration arithmetic block <b>2010</b> for each configuration. In addition, cell address setting values in the reconfiguration cell address storage unit <b>6000</b> for each of the configuration changes are shown in <figref idref="DRAWINGS">FIG. 6</figref>. Configuration information data setting values in the configuration information storage unit <b>3000</b> for each of the configuration changes are shown in <figref idref="DRAWINGS">FIG. 7</figref>.

0101The configuration changes are explained in temporal order. In a period <b>9000</b>, the dynamic reconfiguration arithmetic block <b>2010</b> is set in Configuration A. The configuration information of each dynamic reconfiguration arithmetic cell <b>2100</b> in Configuration A is as shown in the column of “CONFIGURATION A” of <figref idref="DRAWINGS">FIG. 5</figref>.

0102Then, in a period <b>9011</b>, the configuration of the dynamic reconfiguration arithmetic block <b>2010</b> is changed from Configuration A to Configuration B. With this change, the configuration information of the dynamic reconfiguration arithmetic cells <b>2100</b>-<b>10</b> and <b>2100</b>-<b>11</b> is changed.

0103In a period <b>9001</b>, the configuration of the dynamic reconfiguration arithmetic block <b>2010</b> is in Configuration B. The configuration information of each dynamic reconfiguration arithmetic cell in Configuration B is as shown in the column of “CONFIGURATION B” of <figref idref="DRAWINGS">FIG. 5</figref>.

0104In a period <b>9012</b>, the configuration of dynamic reconfiguration arithmetic block <b>2010</b> is changed from Configuration B to Configuration C. With this change, the configuration information of the dynamic reconfiguration arithmetic cells <b>2100</b>-<b>10</b>, <b>2100</b>-<b>11</b> and <b>2100</b>-<b>12</b> is changed.

0105In a period <b>9002</b>, the configuration of the dynamic reconfiguration arithmetic block <b>2010</b> is in Configuration C. The configuration information of each dynamic reconfiguration arithmetic cell in Configuration C is as shown in the column of “CONFIGURATION C” of <figref idref="DRAWINGS">FIG. 5</figref>.

0106Next, in a period <b>9013</b>, the configuration of the dynamic reconfiguration arithmetic block <b>2010</b> is changed from Configuration C to Configuration A. With this change, the configuration information of the dynamic reconfiguration arithmetic cells <b>2100</b>-<b>11</b> and <b>2100</b>-<b>12</b> is changed.

0107In the following period <b>9003</b>, the dynamic reconfiguration arithmetic block <b>2010</b> is in Configuration A.

0108Thus, in the case where the configuration of the dynamic reconfiguration arithmetic block <b>2010</b> is cyclically changed from Configurations A, B to C, the configurations of the dynamic reconfiguration arithmetic cells <b>2100</b>-<b>01</b>, <b>2100</b>-<b>02</b>, <b>2100</b>-<b>03</b>, <b>2100</b>-<b>04</b>, <b>2100</b>-<b>05</b>, <b>2100</b>-<b>06</b>, <b>2100</b>-<b>07</b>, <b>2100</b>-<b>08</b>, <b>2100</b>-<b>09</b>, <b>2100</b>-<b>13</b>, <b>2100</b>-<b>14</b>, <b>2100</b>-<b>15</b> and <b>2100</b>-<b>16</b> are not changed. The configurations of only the arithmetic cells <b>2100</b>-<b>10</b>, <b>2100</b>-<b>11</b> and <b>2100</b>-<b>12</b> are changed.

0109Therefore, as shown in <figref idref="DRAWINGS">FIGS. 6 and 7</figref>, only data regarding the arithmetic cells <b>2100</b>-<b>10</b>, <b>2100</b>-<b>11</b> and <b>2100</b>-<b>12</b> is stored in the reconfiguration cell address storage unit <b>6000</b> and the configuration information storage unit <b>3000</b>.

01101.3 Operation

0111<figref idref="DRAWINGS">FIG. 8</figref> is a flowchart showing operation of the configuration change. The following describes the operation of the configuration change with the aid of <figref idref="DRAWINGS">FIG. 8</figref>.

0112In the change operation form Configurations A to B in the period <b>9011</b>, first the storage unit address counter <b>8000</b> outputs the initial address “0×00” (Step S<b>9501</b>).

0113Also, the storage unit address counter <b>8000</b> initializes the counter value of the cell address counter <b>5000</b> to 0 (Step S<b>9502</b>).

0114Next, the cell address counter <b>5000</b> adds 1 to the counter value (Step S<b>9503</b>).

0115The cell address comparator <b>4000</b> compares the output value of the cell address counter <b>5000</b> with that of the reconfiguration cell address storage unit <b>6000</b> (Step S<b>9504</b>).

0116In the result of the comparison, if the two values are equal to each other (S<b>9504</b>: Y) the cell address comparator <b>4000</b> outputs <b>1</b> during the predetermined time period As (Step S<b>9506</b>).

0117The configuration information selector <b>3400</b> receives 1 via the cell address comparator output line <b>4100</b>. When receiving 1, the configuration information selector <b>3400</b> connects the configuration information transmission bus <b>3300</b> to the configuration information input bus <b>3100</b> (Step S<b>9507</b>).

0118Also, the storage unit address counter <b>8000</b> after receiving 1 via the cell address comparator output line <b>4100</b> compares the data currently being output to the storage unit address counter output line <b>8100</b> with an end address corresponding to the initial address output in Step S<b>9501</b> (Step S<b>9509</b>). When they do not match each other (Step S<b>9509</b>: N), the storage unit address counter <b>8000</b> adds 1 to the data being output (Step S<b>9510</b>).

0119In the result of the comparison, if they match each other (Step S<b>9509</b>: Y), the storage unit address counter <b>8000</b> does not perform the increment in Step S<b>9510</b>, and the process moves to Step S<b>9513</b>.

0120If they do not match each other in Step S<b>9504</b> (Step <b>59504</b>: N), the cell address comparator <b>4000</b> outputs <b>0</b> to the cell address comparator output line <b>4100</b> (Step S<b>9511</b>).

0121The configuration information selector <b>3400</b> after receiving 0 connects the configuration information output bus <b>3200</b> to the configuration information input bus <b>3100</b> (Step S<b>9512</b>).

0122Subsequently, the configuration data on the configuration information input bus <b>3100</b> is input to the shift register <b>2300</b> (Step S<b>9513</b>).

0123Next, the cell address counter <b>5000</b> compares the counter value with the number of the dynamic reconfiguration arithmetic cells <b>2100</b> (in this case, 16). When the counter value indicates 16 or more (Step S<b>9514</b>: Y), the operation of the configuration change is ended.

0124If the counter value indicates less than 16 (N in Step S<b>9514</b>), the process returns to Step S<b>9503</b>, and then Steps S<b>9503</b>-S<b>9514</b> are repeated until the counter value indicates 16 or more.

0125In the case of the configuration change from Configurations A to B, the configuration information in the dynamic reconfiguration arithmetic cells <b>2100</b>-<b>01</b>, <b>2100</b>-<b>02</b>, <b>2100</b>-<b>03</b>, <b>2100</b>-<b>04</b>, <b>2100</b>-<b>05</b>, <b>2100</b>-<b>06</b>, <b>2100</b>-<b>07</b>, <b>2100</b>-<b>08</b>, <b>2100</b>-<b>09</b>, <b>2100</b>-<b>12</b>, <b>2100</b>-<b>13</b>, <b>2100</b>-<b>14</b>, <b>2100</b>-<b>15</b> and <b>2100</b>-<b>16</b> whose configuration is not changed is reused in the process depicted by <figref idref="DRAWINGS">FIG. 8</figref>.

0126The configuration information of only the dynamic reconfiguration arithmetic cells <b>2100</b>-<b>10</b> and <b>2100</b>-<b>11</b> is changed with that stored in the configuration information storage unit <b>3000</b>.

0127In relation to the configuration changes from Configurations B to C and from Configurations C to A, the configuration information of arithmetic cells whose configuration is not changed is reused in a similar manner.

01281.4 Detailed Pipelines

0129Pipelines of configuration elements for the change from Configurations A to B are shown in <figref idref="DRAWINGS">FIG. 9</figref>. The detailed data transition during the configuration change is described below with the aid of <figref idref="DRAWINGS">FIG. 9</figref>.

0130At the time t<b>0</b>, the storage unit address counter <b>8000</b> initializes the counter value of the cell address counter <b>5000</b> to 0. Along with this, the output value of the cell address counter output line <b>5100</b> becomes 0. After the initialization, the cell address counter <b>5000</b> counts up the counter value by one every period of Δt (times t<b>1</b>, t<b>2</b>, t<b>3</b>, . . . ).

0131In addition, the storage unit address counter <b>8000</b> starts outputting the initial address “0×00” to the storage unit address counter output line <b>8100</b>.

0132When receiving the output of “0×00”, the reconfiguration cell address output line <b>6100</b> starts outputting the cell address “10”, and the configuration information transmission bus <b>3300</b> starts outputting the configuration information “2315”.

0133At the time t<b>0</b>, the configuration of the dynamic reconfiguration arithmetic block <b>2010</b> is Configuration A, and therefore the configuration information of the arithmetic cells <b>2100</b>-<b>16</b>, <b>2100</b>-<b>12</b>, <b>2100</b>-<b>11</b>, <b>2100</b>-<b>10</b> and <b>2100</b>-<b>01</b> is “2222”, “4500”, “5678”, “3333” and “5000”, respectively (see Configuration A of <figref idref="DRAWINGS">FIG. 5</figref>).

0134At the time t<b>1</b>, the cell address counter <b>5000</b> counts up the counter value to “1”. The cell address counter <b>5000</b> outputs the pulse signal to the shift register <b>2300</b>.

0135When the pulse signal is received, the storage unit <b>2301</b> (corresponding to the arithmetic cell <b>2100</b>-<b>01</b>), which is a constituent of the shift register <b>2300</b>, outputs the configuration information “5000” stored therein to the configuration information output bus <b>3200</b>, and the remaining storage units <b>2302</b>-<b>2316</b> shift the configuration information they hold to the neighboring storage units. Each of the arithmetic cells <b>2100</b> lodes the configuration information written to the corresponding one of the storage units <b>2301</b>-<b>2315</b>.

0136Since the output value “1” of the cell address counter output line <b>5100</b> and the output value “10” of the reconfiguration cell address output line <b>6100</b> do not match each other, the cell address comparator <b>4000</b> outputs 0 to the cell address comparator output line <b>4100</b>.

0137Since the configuration information selector <b>3400</b> after receiving the signal <b>0</b> connects the configuration information output bus <b>3200</b> to the configuration information input bus <b>3100</b>, the configuration information “5000” is input to the shift register <b>2300</b> and then stored in the storage unit <b>2316</b>. The configuration information “5000” stored in the storage unit <b>2316</b> is loaded to the arithmetic cell <b>2100</b>-<b>16</b>.

0138Accordingly, at this point, the configuration information of the arithmetic cells <b>2100</b>-<b>16</b>, <b>2100</b>-<b>12</b>, <b>2100</b>-<b>11</b>, <b>2100</b>-<b>10</b> and <b>2100</b>-<b>01</b> is “5000”, “7843”, “4500”, “5678” and “0010”, respectively.

0139At the time t<b>2</b>, the cell address counter <b>5000</b> counts up the counter value to “2”, and the output value of the cell address counter output line <b>5100</b> becomes “2”. Here, again, since the output values of the cell address counter output line <b>5100</b> and the reconfiguration cell address output line <b>6100</b> do not match each other, the configuration information stored in the storage unit <b>2301</b> constituting the shift register <b>2300</b> is shifted to the storage unit <b>2316</b>, and the configuration information stored in the storage units <b>2302</b>-<b>2316</b> is shifted to the neighboring storage units as in the same case with the time t<b>1</b>. Each arithmetic cell <b>2100</b> loads configuration information stored in its corresponding storage unit.

0140Similar processing is repeated until the time t<b>9</b>.

0141At the time t<b>10</b>, the cell address counter <b>5000</b> counts up the counter value to “10” and outputs the pulse signal to the shift register <b>2300</b>.

0142The shift register <b>2300</b> outputs the configuration information stored in the storage unit <b>2301</b> (corresponding to the arithmetic cell <b>2100</b>-<b>01</b>), and internally shifts configuration information among the storage units.

0143At this point, since the output values of the cell address counter output line <b>5100</b> and the reconfiguration cell address output line <b>6100</b> are both “10”, the cell address comparator <b>4000</b> outputs 1 to the cell address comparator output line <b>4100</b> during the time period Δs.

0144The configuration information selector <b>3400</b> after receiving the signal <b>1</b> connects the configuration information transmission bus <b>3300</b> to the configuration information input bus <b>3100</b>. Accordingly, the configuration information “2315” output from the configuration information storage unit <b>3000</b> is input to the shift register <b>2300</b>, and then written to the storage unit <b>2316</b>. The arithmetic cell <b>2100</b>-<b>16</b> loads the configuration information “2315” written to the storage unit <b>2316</b>.

0145In addition, the storage unit address counter <b>8000</b> after receiving 1 from the cell address comparator output line <b>4100</b> increases the output value by one and starts outputting “0×01”.

0146The reconfiguration cell address storage unit <b>6000</b> after receiving “0×01” via the storage unit address counter output line <b>8100</b> outputs the cell address “11” stored in the address “0×01” to the reconfiguration cell address output line <b>6100</b>.

0147Similarly, the configuration information storage unit <b>3000</b> after receiving “0×01” starts outputting the configuration information “5778” stored in the address “0×01”.

0148At the time t<b>11</b>, the output value of the cell address counter output line <b>5100</b> is “11”, which matches the output value of the reconfiguration cell address output line <b>6100</b>. Accordingly, the cell address comparator <b>4000</b> outputs 1 via the cell address comparator output line <b>4100</b>.

0149The configuration information selector <b>3400</b> after receiving the signal <b>1</b> connects the configuration information transmission bus <b>3300</b> to the configuration information input bus <b>3100</b>. Accordingly, the configuration information “5778” is input to the shift register <b>2300</b>, and then written to the storage unit <b>2316</b>. The arithmetic cell <b>2100</b>-<b>16</b> loads the configuration information “5778” written to the storage unit <b>2316</b>.

0150At this point, the storage unit address counter <b>8000</b>, although receiving <b>1</b> via the cell address comparator output line <b>4100</b>, does not increment the output value since the value currently being output “0×01” and the end address match each other.

0151Accordingly, since from the time t<b>12</b> onwards, the output value of the reconfiguration cell address output line <b>6100</b> remains as “11”, the output values of the cell address counter output line <b>5100</b> and the reconfiguration cell address output line <b>6100</b> do not match. Accordingly, from the time t<b>12</b> to the time t<b>16</b>, the cell address counter <b>5000</b> continues counting up of the counter value, and the shift register <b>2300</b> cyclically shifts the configuration information stored in the storage units <b>2301</b>-<b>2316</b> at each time of the counting up.

0152At the time t<b>17</b>, the counter value of the cell address counter <b>5000</b> is already 16, which is the number of the arithmetic cells. Therefore, the cell address counter <b>5000</b> stops counting up, and ends the operation of the configuration change.

0153At this point, although the configuration information of the arithmetic cells <b>2100</b> of the cell addresses “10” and “11” has been changed, the configuration information of the rest of the arithmetic cells <b>2100</b> is the same as before the start of the configuration change.

01541.5 Conclusions

0155As has been explained, according to the present invention, the dynamic reconfiguration arithmetic block includes the shift register, which is made up of storage units connected in series, and the configuration information of each dynamic reconfiguration arithmetic cell is cyclically shifted by control of the control unit. Here, only configuration information needed to be changed is replaced with new configuration information, and the remaining configuration information is reused.

0156Accordingly, it is necessary for the configuration information storage unit to store therein only new configuration information of dynamic reconfiguration arithmetic cells requiring configuration change, and thus the memory capacity in the circuit can be reduced.

0157The above-mentioned Patent Reference 1 discloses a technology for realizing a reduction of configuration information to be stored.

0158<figref idref="DRAWINGS">FIG. 19</figref> is a schematic diagram of a dynamic reconfigurable arithmetic circuit disclosed by Patent Reference 1. The dynamic reconfigurable arithmetic block <b>200</b> can change, in accordance with arithmetic operation to be processed, the operational contents and connection configuration of the arithmetic cells <b>210</b>. The change of operation contents and connections by the dynamic reconfiguration arithmetic block <b>200</b> is realized by that configuration information input from the shift register <b>230</b> is transmitted to each of the arithmetic cells <b>210</b>. The configuration information input from the shift register <b>230</b> is distributed by each data line <b>250</b>. The configuration of the arithmetic cells <b>210</b> in the region specified by the address line <b>220</b> and not masked by the mask register <b>240</b> is changed by the distributed configuration information.

0159Thus, by specifying the region to be changed, the configuration information of the arithmetic cells <b>210</b> whose configuration is not to be changed can be used again.

0160As a result, it is necessary to prepare only the configuration information for a part that requires a change, whereby being able to reduce the data size of the configuration information and therefore to decrease the capacity required for the configuration information storage unit <b>300</b>.

0161However, with the structure of Patent Reference <b>1</b>, the hardware resources for changing the configuration increase according to the number of the arithmetic cells <b>210</b>. As a result, when the reconfigurable logic circuit is of large scale, the area occupied by the hardware resources becomes large. Specifically speaking, assume that the total number of the arithmetic cells <b>210</b> is N pieces, the area occupied by one arithmetic cell <b>210</b> of the data line <b>250</b> is a, the number of arithmetic cells disposed in the vertical direction is β, the area occupied by one arithmetic cell <b>210</b> of the mask register <b>240</b> is b, and the area occupied by one arithmetic cell <b>210</b> of the address line <b>220</b> is c. In this case, the area of (a+c)×N+b×β is occupied by the hardware resources required for changing the configuration. Thus, a large-scale reconfiguration logic circuit having a large number of arithmetic cells <b>210</b> has a problem regarding the area for the configuration change.

0162Compared to this technology, according to the present invention, even when the number of dynamic reconfiguration arithmetic cells in the dynamic reconfiguration arithmetic block increases, the circuit of the control unit does not substantially change in size. Further, in the dynamic reconfiguration arithmetic block, the shift register is the only hardware resource for configuration change, and therefore even if the number of the dynamic reconfiguration arithmetic cells increases, an increase in the overall area of the dynamic reconfiguration arithmetic block can be reduced as compared to the technology of Patent Reference 1. Accordingly, the present invention can inhibit an increase in the area required for configuration change of the dynamic reconfiguration arithmetic block.

01631.6 Additional Remarks

0164Embodiment 1 has been explained above, however, it is merely an example, and the following cases are also within the scope of the present invention.

0165(1) The storage unit address counter <b>8000</b> has been described as it prestores therein pairs of initial and end addresses of an area, within the reconfiguration cell address storage unit <b>6000</b> and the configuration information storage unit <b>3000</b>, which stores therein data necessary for configuration change. Instead of this case, the initial and end addresses may be indicated by a control mechanism of the apparatus having thereon the dynamic reconfiguration arithmetic circuit <b>110</b> at each time of the configuration change.

0166(2) In addition, the storage unit address counter <b>8000</b> has been described as it initializes the cell address counter <b>5000</b>. Instead, the control mechanism of the apparatus having the dynamic reconfiguration arithmetic circuit <b>110</b> may perform the initialization.

0167(3) In Embodiment 1 above, every time when configuration information stored in each storage unit is changed, a corresponding arithmetic cell is rewritten according to new configuration information. That is, regarding the configuration change of the dynamic reconfiguration arithmetic block including sixteen arithmetic cells, the arithmetic cells are reconfigured every time when configuration information is shifted in the shift register, and thus reconfiguration is performed sixteen times in total. However, the present invention is not limited to this case.

0168For example, after configuration information is appropriately written to all the storage units—i.e. when the counter value of the cell address counter <b>5000</b> reaches 16, reconfiguration of sixteen arithmetic cells all together may be performed.

2. Embodiment 2

0169The following describes Embodiment 2 of the present invention with the aid of drawings.

01702.2 Structure and Operation

0171<figref idref="DRAWINGS">FIG. 10</figref> shows a video quality enhancing apparatus <b>18001</b> of Embodiment 2.

0172The video quality enhancing apparatus <b>18001</b> includes a video data generation unit <b>18000</b>, a video quality enhancing circuit <b>19000</b>, an image feature quantity data line <b>19100</b> and a display <b>11000</b>.

0173The video quality enhancing apparatus <b>18001</b> has functions of inputting video data generated by the video data generation unit <b>18000</b> to the video quality enhancing circuit <b>19000</b> and displaying the video data with enhanced quality on the display <b>11000</b>.

0174The video quality enhancing circuit <b>19000</b> includes video frame buffers <b>17000</b><i>a </i>and <b>17000</b><i>b </i>and a dynamic reconfiguration arithmetic circuit <b>110</b>.

0175The structure of the dynamic reconfiguration arithmetic circuit <b>110</b> is the same as in the case of Embodiment 1 and is shown in <figref idref="DRAWINGS">FIG. 1</figref>. The components identical to those in Embodiment 1 are given the same reference numerals, and the explanation for these components is omitted.

0176The video data input from the video data generation unit <b>18000</b> is stored in the video frame buffer <b>17000</b><i>a, </i>then becomes subject to video quality enhancing processing performed by the dynamic reconfiguration arithmetic circuit <b>110</b>, and is subsequently stored in the video frame buffer <b>17000</b><i>b. </i>Then, the video data is transmitted to the display <b>11000</b> by the video frame buffer <b>17000</b><i>b. </i>

0177<figref idref="DRAWINGS">FIGS. 11 and 12</figref> show examples of calculation formulae of a filtering process performed by the dynamic reconfiguration arithmetic circuit <b>110</b> for enhancing video quality.

0178In addition, the order of video images processed by the dynamic reconfiguration arithmetic circuit is shown in <figref idref="DRAWINGS">FIG. 13</figref>. As shown in <figref idref="DRAWINGS">FIG. 13</figref>, the video quality enhancing processing is performed in the order of image data <b>20000</b>, <b>20100</b> and <b>20200</b>.

0179The video quality enhancing apparatus <b>18001</b> performs, on video data, a filtering process based on the calculation shown in <figref idref="DRAWINGS">FIG. 11</figref> or <figref idref="DRAWINGS">FIG. 12</figref> in accordance with the feature of the video data.

0180Specifically speaking, when video data has the amount of noise less than a predetermined threshold, the filtering process is performed using the calculation formula of <figref idref="DRAWINGS">FIG. 11</figref>:

0000<br /><i>X</i>2′=(1*<i>X</i>1+1*<i>X</i>3)/2,

0181X<b>1</b>: data of a pixel to the immediate left of X<b>2</b>,

0182X<b>2</b>: data of a pixel for correction,

0183X<b>3</b>: data of a pixel to the immediate right of X<b>2</b>, and

0184X<b>2</b>′: data of a pixel after corrected.

0185When video data has the amount of noise exceeding the predetermined threshold, the filtering process is performed using the calculation formula of <figref idref="DRAWINGS">FIG. 12</figref>:

0000<br /><i>X</i>2′=(1*<i>X</i>1+2*<i>X</i>2+1*<i>X</i>3)/4,

0186X<b>1</b>: data of a pixel to the immediate left of X<b>2</b>,

0187X<b>2</b>: data of a pixel for correction,

0188X<b>3</b>: data of a pixel to the immediate right of X<b>2</b>, and

0189X<b>2</b>′: data of a pixel after corrected.

0190The video data generation unit <b>18000</b> has a function of detecting the amount of noise of each piece of video data. For example, assume that there are pieces of video data <b>20000</b>, <b>20100</b> and <b>20200</b>. Of them, if the video data generation unit <b>18000</b> detects the noise of video data <b>20100</b> exceeding the predetermined threshold, then the video data generation unit <b>18000</b> transmits information indicating that the video data <b>20100</b> has a high noise level to the dynamic reconfiguration arithmetic circuit <b>110</b> via the image feature quantity data line <b>19100</b>.

0191When receiving the information, the dynamic reconfiguration arithmetic circuit <b>110</b> performs, on the video data <b>20000</b> and <b>20200</b>, the filtering process using the calculation shown in <figref idref="DRAWINGS">FIG. 11</figref> and performs, on the video data <b>20100</b>, the filtering process using the calculation shown in <figref idref="DRAWINGS">FIG. 12</figref>.

0192In order to realize this, the dynamic reconfiguration arithmetic circuit <b>110</b> performs the configuration change between the process of the video data <b>20000</b> and the process of the video data <b>20100</b> and between the process of the video data <b>20100</b> and the process of the video data <b>20200</b>.

0193Regarding the configuration change, the configuration information for only dynamic reconfiguration arithmetic cells requiring configuration change is changed, and the configuration information before the configuration change is used for the remaining dynamic reconfiguration arithmetic cells, as described in Embodiment 1.

0194The respective pieces of video data are input to the dynamic reconfiguration arithmetic circuit <b>110</b> in order starting from the top horizontal line data. In each piece of video data, there is a time period—called a vertical blanking area <b>20010</b>—during which invalid data is transmitted, as shown in <figref idref="DRAWINGS">FIG. 14</figref>.

0195The dynamic reconfiguration arithmetic circuit <b>110</b> detects the blanking area and starts the configuration change. The configuration change is completed within the period of the vertical blanking area <b>20010</b>.

3. Embodiment 3

0196<figref idref="DRAWINGS">FIG. 15</figref> shows an external appearance of a mobile communication apparatus <b>10000</b> according to Embodiment 3 of the present invention.

0197As the mobile communication apparatus <b>10000</b>, various types of apparatuses can be considered—for example, a mobile telephone, a PDA, a mobile video playback apparatus, a mobile music playback apparatus and a digital camera.

0198As shown in <figref idref="DRAWINGS">FIG. 15</figref>, the mobile communication apparatus <b>10000</b> includes a display <b>11000</b>, an imaging unit <b>12000</b>, an audio output unit <b>13000</b>, an audio input unit <b>14000</b>, a command input unit <b>15000</b>, and an antenna <b>16000</b>. In addition, the mobile communication apparatus <b>10000</b> has therein the dynamic reconfiguration arithmetic circuit <b>110</b> described in Embodiment 1.

0199The structure of the dynamic reconfiguration arithmetic circuit <b>110</b> is the same as in the case of Embodiment 1 and is shown in <figref idref="DRAWINGS">FIG. 1</figref>. The components identical to those in Embodiment 1 are given the same reference numerals, and the explanation for these components is omitted.

02003.1 Functions of Mobile Communication Apparatus <b>10000</b>

0201The following provides specific examples regarding functions of the mobile communication apparatus <b>10000</b>.

0202Note that the following functions are merely examples, and the mobile communication apparatus <b>10000</b> may also have other functions.

0203(1) Image Playback Function

0204The dynamic reconfiguration arithmetic circuit <b>110</b> is connected to the display <b>11000</b> via a video frame buffer. The dynamic reconfiguration arithmetic circuit <b>110</b> performs a decoding process of still images such as JPEG, a decoding process of video such as MPEG, a three-dimensional graphics process for games and the like, and a text drawing process. The dynamic reconfiguration arithmetic circuit <b>110</b> also performs a process of superimposing respective images. Subsequently, the dynamic reconfiguration arithmetic circuit <b>110</b> writes processed image data to the frame buffer.

0205The display <b>11000</b> obtains the processed image data from the frame buffer and displays video based on the obtained image data.

0206(2) Imaging Function

0207The dynamic reconfiguration arithmetic circuit <b>110</b> is also connected to the imaging unit <b>12000</b> via the video frame buffer.

0208The imaging unit <b>12000</b> writes captured image data to the video frame buffer.

0209The dynamic reconfiguration arithmetic circuit <b>110</b> obtains the image data from the video frame buffer, and performs an encoding process on the obtained image data. Specific examples of the encoding process include an encoding process of still images, such as JPEG, and an encoding process of video, such as MPEG.

0210(3) Audio Playback Function

0211Furthermore, the dynamic reconfiguration arithmetic circuit <b>110</b> is connected to the audio output unit <b>13000</b> via an audio frame buffer. The dynamic reconfiguration arithmetic circuit <b>110</b> performs an MPEG and other audio decoding processes, and writes decoded audio data to the audio frame buffer. The audio output unit <b>13000</b> reads audio data from the audio frame buffer, generates audio based on the read audio data, and outputs the audio.

0212(4) Recording Function

0213The dynamic reconfiguration arithmetic circuit <b>110</b> is also connected to the audio input unit <b>14000</b> via the audio frame buffer.

0214The audio input unit <b>14000</b> including a microphone or the like picks up audio and generates audio data, and writes the generated audio data to the audio frame buffer.

0215The dynamic reconfiguration arithmetic circuit <b>110</b> reads the audio data from the audio frame buffer, and performs an MPEG audio encoding process, for example, on the read audio data.

0216In the above (1)-(4), the dynamic reconfiguration arithmetic circuit <b>110</b> performs decoding and encoding processes in conformity with JPEG, MPEG or the like. However, there are various types of video and audio processing standards, and contents of processes are respectively different. By causing the dynamic reconfiguration arithmetic block <b>2010</b> to process parts which have the different process contents and would impose a heavy load on the processor, it is possible to flexibly conform to processes of various standards.

0217(5) Communication Function

0218The dynamic reconfiguration arithmetic circuit <b>110</b> is connected to the antenna <b>16000</b> and a radio frequency circuit block (not shown). These three form a radio network when the dynamic reconfiguration arithmetic circuit <b>110</b> performs a communication process. The dynamic reconfiguration arithmetic circuit <b>110</b> also performs encrypting and decrypting processes of transmitting and receiving data.

0219There are various types of communication and encryption standards, and contents of processes are respectively different. By causing the dynamic reconfiguration arithmetic block <b>2010</b> to process parts which have the different process contents and would impose a heavy load on the processor, it is possible to flexibly respond to processes of various standards.

0220(6) Reception of User Operation

0221The command input unit <b>15000</b> includes a number of buttons as shown in <figref idref="DRAWINGS">FIG. 15</figref>. For example, a playback button, a stop button, direction keys and an enter button are provided. The command input unit <b>15000</b> receives a button operation made by the user, and outputs an instruction to each function part, including the dynamic reconfiguration arithmetic circuit <b>110</b>, in accordance with the received operation to thereby realize the individual functions described in the above sections (1)-(5).

02223.2 Conclusions

0223Many communication systems, image processing systems and security process systems are designed to conform to multiple standards. Therefore, as the mobile communication apparatus <b>10000</b> of the present invention, by providing the dynamic reconfiguration arithmetic circuit <b>110</b> thereon and causing the configuration of the circuit to change according to need, it is possible to perform processes in conformity with each standard without requiring to equip a number of hardware circuits.

0224Further, the dynamic reconfiguration arithmetic circuit <b>110</b> can be applied not only to the mobile communication apparatus described in the present embodiment but also to image display apparatuses (e.g. TVs, DVD players and car navigation systems), image recording apparatuses (e.g. DVD recorders, video cameras, DSCs, and security cameras), audio players, and communication systems and security processing systems in communication apparatuses.

4. Other Modifications

0225The embodiments of the dynamic reconfiguration arithmetic circuit <b>110</b> of the present invention have been explained, however, the present invention is not limited to the above embodiments. The dynamic reconfiguration arithmetic circuit <b>110</b> shown in the respective embodiments may be partially modified in the following manners.

0226(1) Although, in Embodiment 1, the arithmetic cells of the dynamic reconfiguration arithmetic block <b>2010</b> are arranged in a 4-by-4 matrix, it may be a 10-by-4 rectangular matrix. Alternatively, the arithmetic cells may be arranged in a line, and thus the present invention is not subject to the arrangements of the arithmetic cells.

0227Functions performed by the dynamic reconfiguration arithmetic cells <b>2100</b> conceivably include multiplication, shifting, addition, logic operation, division, subtraction and rotation. The kinds of functions that can be performed by the arithmetic cells <b>2100</b> making up the dynamic reconfiguration arithmetic block <b>2010</b> are not particularly limited, and each arithmetic cell <b>2100</b> may perform various kinds of functions, or may perform only limited kinds of functions. Further, the arithmetic cells <b>2100</b> making up the dynamic reconfiguration arithmetic block <b>2010</b> may all have the same structure. Or alternatively, arithmetic cells each having a different function may be included—e.g. only particular arithmetic cells can perform a division calculation.

0228In the above embodiments, all the dynamic reconfiguration arithmetic cells <b>2100</b> are reconfigurable; however, nonreconfigurable arithmetic cells <b>2100</b> may be included.

0229The dynamic reconfiguration arithmetic cells <b>2100</b> may be, for example, single-input and single-output cells, or three-input and two-output cells. Thus, the number of inputs and outputs may be varied. Such variation can be adjusted by increasing the number of inputs and outputs of the arithmetic cells <b>2100</b>.

0230Note that the dynamic reconfiguration arithmetic cells <b>2100</b> may operate on the same clock. Instead, multiple clock lines may be provided and each arithmetic cell may operate on a different arithmetic operation clock.

0231(2) In Embodiment 1, all arithmetic cells <b>2100</b> are connected to one shift register <b>2300</b>; however, there may be multiple shift registers <b>2300</b>. In the case, the number of arithmetic cells connected to each shift register can be and the bit count of the configuration information may be different. Additionally, multiple shift registers may be connected to a single configuration information selector <b>3400</b>, or may be connected to different configuration information selector <b>3400</b> and configuration information storage unit <b>3000</b>.

0232(3) Reuse of the configuration information is realized in Embodiment 1. As has mentioned above, configuration information includes the type of arithmetic operation performed by a corresponding arithmetic cell, an arithmetic parameter and wiring information. Accordingly, not the entire configuration information but only the arithmetic parameter may be reused. In the case, each configuration element uses the arithmetic parameter instead of the configuration information. Note that a different means may be used for changing the type of arithmetic operation and wiring information, or another set of hardware resources for changing the type of arithmetic operation and wiring information may be provided where the change is performed as in the same manner as in Embodiment 1.

0233Further, in the case of changing the arithmetic parameter, configuration information stored by the individual storage units making up the shift register <b>2300</b> may be cyclically shifted as in the case of Embodiment 1. In this case, the configuration information storage unit <b>3000</b> stores a new arithmetic parameter for each dynamic reconfiguration arithmetic cell whose parameter needs to be changed. The control unit <b>2000</b> cyclically shifts configuration information held by the individual storage units making up the shift register <b>2300</b> in the same procedure as in Embodiment 1.

0234When configuration information corresponding to a dynamic reconfiguration arithmetic cell whose parameter needs to be changed is output (specifically speaking, when the cell address comparator <b>4000</b> outputs 1), the configuration information selector <b>3400</b> rewrites the arithmetic parameter included in the configuration information output from the shift register <b>2300</b> with configuration information stored in the configuration information storage unit <b>3000</b>, and inputs the result to the shift register <b>2300</b>.

0235(4) In Embodiment 1, the dynamic reconfiguration arithmetic circuit <b>110</b> includes the configuration information storage unit <b>3000</b> and the reconfiguration cell address storage unit <b>6000</b> separately; however, they may be integrated into one storage unit. In the case, within the storage unit, configuration information and its corresponding cell address are stored in the same address, and among output data, a cell address is input to the cell address comparator <b>4000</b> while configuration information is input to the configuration information selector <b>3400</b>.

0236(5) In Embodiment 2, the configuration is changed in the vertical blanking area; however, the configuration may be changed in a horizontal blanking area instead.

0237The video quality enhancing circuit <b>19000</b> includes two video frame buffers; however, it may not include them therein.

0238The video data generation unit <b>18000</b> detects a feature of video; however, this may be done by the dynamic reconfiguration arithmetic circuit <b>110</b> instead.

0239(6) The dynamic reconfiguration arithmetic circuit <b>110</b> described in Embodiment 1 above includes one dynamic reconfiguration arithmetic block <b>2010</b>; however, it may include two or more dynamic reconfiguration arithmetic blocks.

0240In this case, the control unit and the configuration information storage unit (hereinafter, these are collectively referred to as the “reconfiguration mechanism”) may be provided for each dynamic reconfiguration arithmetic block. Alternatively, the configuration change of the multiple dynamic reconfiguration arithmetic blocks may be performed by a single reconfiguration mechanism.

0241The following explains an example in which one reconfiguration mechanism performs configuration change of two dynamic reconfiguration arithmetic blocks.

0242<figref idref="DRAWINGS">FIG. 16</figref> is a block diagram showing a part of the dynamic reconfiguration arithmetic circuit of the present modification.

0243The components identical to those in Embodiment 1 are given the same reference numerals.

0244The dynamic reconfiguration arithmetic circuit includes new dynamic reconfiguration arithmetic block <b>2020</b> and switches <b>1001</b> and <b>1002</b>.

0245The dynamic reconfiguration arithmetic block <b>2020</b> includes twenty dynamic reconfiguration arithmetic cells <b>2400</b>-<b>17</b> to <b>2400</b>-<b>36</b> arranged in a 4 by 5 matrix. The dynamic reconfiguration arithmetic cells are individually connected to the shift register <b>2500</b>, and the cell addresses “17”, “18”, “19”, . . . , and “36” are assigned to them in order of the closest to the output terminal of the shift register to the furthest.

0246Similar to the shift register <b>2300</b>, the shift register <b>2500</b> is structured by connecting in series twenty storage units corresponding to the individual arithmetic cells. Each storage unit stores configuration information of a corresponding arithmetic cell.

0247The cell address counter <b>5000</b> counts up the counter value at regular intervals (Δt), as in Embodiment 1. Here, the cell address counter <b>5000</b> outputs the counter value and pulse signal to the switch <b>1002</b>.

0248The switch <b>1002</b> receives the pulse signal and counter value from the cell address counter <b>5000</b>. When the received counter value indicates “16”—which is the total number of the arithmetic cells <b>2100</b> making up the dynamic reconfiguration arithmetic block <b>2010</b>—or less, the switch <b>1002</b> connects a signal line <b>5200</b> to a signal line <b>5400</b> to allow the pulse signal to be input to the dynamic reconfiguration arithmetic block <b>2010</b>.

0249When the received counter value indicates “17” or more, the switch <b>1002</b> connects the signal line <b>5200</b> and a signal line <b>5300</b> to allow the pulse signal to be input to the dynamic reconfiguration arithmetic block <b>2020</b>.

0250According to this structure, the pulse signal is input to only one of the two dynamic reconfiguration arithmetic blocks. The shift register in one of the dynamic reconfiguration arithmetic blocks, to which the pulse signal has been input, outputs configuration information stored by the storage unit closest to the output terminal to the configuration information output bus <b>3200</b>, and the remaining storage units shift the configuration information to the neighboring storage units.

0251The cell address counter <b>5000</b> also outputs the counter value to the switch <b>1001</b> via the cell address counter output line <b>5100</b>.

0252The switch <b>1001</b> receives the configuration information from the configuration information selector <b>3400</b> via a configuration information interchange bus <b>3500</b>. Here, if the counter value received from the cell address counter <b>5000</b> indicates “16” or less, the switch <b>1001</b> connects the configuration information interchange bus <b>3500</b> and the configuration information input bus <b>3100</b>.

0253When the received counter value indicates “17” or more, the switch <b>1001</b> connects the configuration information interchange bus <b>3500</b> to the configuration information input bus <b>3600</b>.

0254Although not being shown, the storage unit address counter initializes the cell address counter <b>5000</b> to 0 at the start of the configuration change, and stops the cell address counter <b>5000</b> when the counter value thereof reaches 36.

0255According to the above structure, it is possible to build, in two dynamic reconfiguration arithmetic blocks, circuits having different functions.

0256In addition, the storage unit address counter <b>8000</b> has a control to set the initial value of the cell address counter <b>5000</b> to “0” and the end value to “16”, and herewith it is possible to change the configuration of only the dynamic reconfiguration arithmetic block <b>2010</b> without giving no influence to the dynamic reconfiguration arithmetic block <b>2020</b>.

0257Further, by setting the initial value of the cell address counter <b>5000</b> to “17” and the end value to “36”, it is possible to change the configuration of only the dynamic reconfiguration arithmetic block <b>2020</b> without giving no influence to the dynamic reconfiguration arithmetic block <b>2010</b>.

0258(7) Assume an example of, in the above modification, mounting multiple dynamic reconfiguration arithmetic blocks made up of dynamic reconfiguration arithmetic cells.

0259Here, the storage unit address counter has a control so that the switch <b>1001</b> connects the configuration information interchange bus <b>3500</b> to all the configuration information input buses regardless of the counter value of the cell address counter, and that the cell address comparator <b>4000</b> always outputs 0.

0260Further, by setting the initial value of the cell address counter to “0” and the end value to “16”, it is possible to allow all the dynamic reconfiguration arithmetic blocks to have the same structure.

0261(8) In the above embodiments, each dynamic reconfiguration arithmetic block consists of sixteen dynamic reconfiguration arithmetic cells and a shift register, and the configuration information of each arithmetic block includes a type of arithmetic operation performed by the arithmetic block, an arithmetic parameter, and an arithmetic block from which data subject to the arithmetic operation is obtained.

0262However, the structure of the dynamic reconfiguration arithmetic block is not limited to this case. For example, it may consist of wiring resources that connect and disconnect wiring between arithmetic cells performing arithmetic operation.

0263In this case also, similar to Embodiment 1, the shift register structured by connecting in series storage units corresponding to arithmetic cells and wiring resources may shift configuration information and change only configuration information of arithmetic cells and wiring resources requiring change.

0264(9) The dynamic reconfiguration arithmetic circuit <b>110</b> of the present invention only needs to have configuration information of dynamic reconfiguration arithmetic cells <b>2100</b> requiring change. As a result, the capacity required for the configuration information storage unit <b>3000</b> can be reduced.

0265Further, regarding the hardware resources for the configuration change, address lines and a mask register whose areas increase depending on the number of the arithmetic cells <b>2100</b> are not required.

0266According to the structure, the number of arithmetic cells <b>2100</b> to be updated is small, and thus the dynamic reconfiguration arithmetic circuit <b>110</b> is useful in media processing apparatuses using a large-scale reconfiguration arithmetic circuit having a large number of arithmetic cells <b>2100</b>. In addition, the dynamic reconfiguration arithmetic circuit <b>110</b> is applicable to communication and security usage. (10) Further, the present invention is a dynamic reconfiguration arithmetic circuit apparatus comprising: a dynamic reconfiguration arithmetic block changeable to at least two different configurations; a 1^stwiring connected to an output terminal of the dynamic reconfiguration arithmetic block; a 2^ndwiring connected to an input terminal of the dynamic reconfiguration arithmetic block; a 1^ststorage unit; a 3^rdwiring connected to an output terminal of the 1^ststorage unit; and a selector operable to select either data on the 1^stwiring or data on the 3^rdwiring and transmit the selected data to the 2^ndwiring.

0267(11) In the dynamic reconfiguration arithmetic circuit apparatus according to the modification (10), the dynamic reconfiguration arithmetic block may include: a plurality of dynamic reconfiguration arithmetic cells changeable to at least two different configurations; and a plurality of 2^ndstorage units connected to the dynamic reconfiguration arithmetic cells. Here, the plurality of 2^ndstorage units are linked together in a chain, an output terminal of the chain is connected to the 1^stwiring, and an input terminal of the chain is connected to the 2^ndwiring.

0268(12) Further, in the dynamic reconfiguration arithmetic circuit apparatus according to the modification (11), addresses may be uniquely assigned to the plurality of 2^ndstorage units. Here, the dynamic reconfiguration arithmetic circuit apparatus further comprises: a cell address counter operable to change the addresses in order; a 3^rdstorage unit storing, among the addresses assigned to the 2^ndstorage units, addresses of 2^ndstorage units whose data held therein is to be changed; a cell address comparator operable to compare an output of the cell address counter and an output of the 3^rdstorage unit. The selector determines, based on an output of the cell address comparator, to select either the data on the 1^stwiring or the data on the 3^rdwiring.

0269(13) The dynamic reconfiguration arithmetic circuit apparatus according to the modification (12) may further comprise: a storage unit address counter operable to calculate read addresses of the 1^stand 3^rdstorage units; a 3^rdwiring connected to an output terminal of the storage unit address counter; and a 4^thwiring connected to an output terminal of the storage unit address counter. Here, the 3^rdwiring is connected to an input terminal of a read address input of the 1^ststorage unit and the 4^thwiring is connected to an input terminal of a read address input of the 3^rdstorage unit.

0270(14) In the dynamic reconfiguration arithmetic circuit apparatus according to the above modifications (10)-(13), the 1^ststorage unit may store therein configuration information of the dynamic reconfiguration arithmetic block. Here, the 1^stand 2^ndwirings transmit the configuration information and the selector selects the configuration information.

0271(15) In the dynamic reconfiguration arithmetic circuit apparatus according to the above modifications (10)-(13), the 1^ststorage unit may store therein arithmetic data of the dynamic reconfiguration arithmetic block. Here, the 1^stand 2^ndwirings transmit the arithmetic data and the selector selects the arithmetic data.

0272(16) The dynamic reconfiguration arithmetic circuit apparatus according to the above modifications (10)-(15) may have thereon a dynamic reconfiguration arithmetic circuit recited in one of Claims <b>1</b> to <b>6</b>. Here, the configuration of the dynamic reconfiguration arithmetic block is changed during the time when arithmetic data requiring no processing is being transmitted.

0273(17) Further, the present invention is an information processing apparatus having thereon the dynamic reconfiguration arithmetic circuit apparatus recited in one of the above modifications (10)-(15).

0274(18) Further, the configuration information storage unit <b>3000</b> and the reconfiguration cell address storage unit <b>6000</b> shown in <figref idref="DRAWINGS">FIG. 1</figref> do not have to be provided inside the dynamic reconfiguration arithmetic circuit <b>110</b>. It is only necessary to provide a storage mechanism serving the same function within an apparatus having thereon the dynamic reconfiguration arithmetic circuit <b>110</b>.

0275<figref idref="DRAWINGS">FIG. 17</figref> is a block diagram showing an example of a structure of such an apparatus, an information processing apparatus <b>1200</b>. Here, there are various apparatuses to be examples of the information processing apparatus <b>1200</b>, including an image processing apparatus, a mobile telephone, and a game console, and each apparatus conceivably has other function units necessary for itself. For example, in the case of a mobile telephone, it is considered to have a microphone, a speaker, an antenna, and input keys. However, these parts not directly related to the features of the present invention are not shown in the figure.

0276The information processing apparatus <b>1200</b> includes a dynamic reconfiguration arithmetic circuit <b>120</b>, a main control unit <b>1000</b>, the configuration information storage unit <b>3000</b>, and the reconfiguration cell address storage unit <b>6000</b>. The configuration information storage unit <b>3000</b> is connected to the main control unit <b>1000</b> via a configuration information storage unit output line <b>3550</b>, and the reconfiguration cell address storage unit <b>6000</b> is connected to the main control unit <b>1000</b> via a reconfiguration cell address storage unit output line <b>6300</b>. The dynamic reconfiguration arithmetic circuit <b>120</b> is connected to the main control unit <b>1000</b> via a control line <b>1100</b>.

0277The configuration information storage unit <b>3000</b> and the reconfiguration cell address storage unit <b>6000</b> respectively store therein information necessary for changing the configuration of the dynamic reconfiguration arithmetic block <b>2010</b>, as in Embodiment 1.

0278When the configuration of the dynamic reconfiguration arithmetic block <b>2010</b> needs to be changed, the main control unit <b>1000</b> reads corresponding information from the configuration information storage unit <b>3000</b> and the reconfiguration cell address storage unit <b>6000</b>. For example, when the configuration is changed from Configuration A to Configuration B, the main control unit <b>1000</b> reads the cell addresses “10” and “11” stored in the area <b>6001</b> of the reconfiguration cell address storage unit <b>6000</b>, and the configuration information “2315” and “5778” stored in the area <b>3001</b> of the configuration information storage unit <b>3000</b>.

0279Then, the main control unit <b>1000</b> outputs reconfiguration information including the read cell addresses and configuration information to the dynamic reconfiguration arithmetic circuit <b>120</b>.

0280The structure of the dynamic reconfiguration arithmetic circuit <b>120</b> is that of the dynamic reconfiguration arithmetic circuit <b>110</b> described in Embodiment 1 without the configuration information storage unit <b>3000</b> and reconfiguration cell address storage unit <b>6000</b>.

0281Further, a storage unit address counter <b>8200</b>, different from the storage unit address counter <b>8000</b> of Embodiment 1, receives the reconfiguration instruction from the main control unit <b>1000</b>, temporarily stores the cell addresses and configuration information included in the received reconfiguration instruction, and outputs the cell addresses stored therein to the cell address comparator <b>4000</b> via a cell address output line <b>6200</b>. Similarly, the storage unit address counter <b>8200</b> outputs the configuration information stored therein to the configuration information selector <b>3400</b> via a configuration information transmission bus <b>3450</b>. During the period of receiving 0 from the cell address comparator <b>4000</b>, the storage unit address counter <b>8200</b> keeps outputting the same cell address and configuration information; when receiving 1, the storage unit address counter <b>8200</b> changes the cell address and configuration information to be output.

0282The following describes the case in which the dynamic reconfiguration arithmetic block <b>2010</b> is changed from Configuration A to Configuration B.

0283The storage unit address counter <b>8200</b> receives, from the main control unit <b>1000</b>, a reconfiguration instruction including the cell addresses “10” and “11” and configuration information “2315” and “5778”. Upon receiving the reconfiguration instruction, the storage unit address counter <b>8200</b> initializes the counter value of the cell address counter <b>5000</b> to 0. Then, the storage unit address counter <b>8200</b> outputs the received cell address “10” to the cell address comparator <b>4000</b> via the cell address output line <b>6200</b>, and outputs the configuration information “2315” to the configuration information selector <b>3400</b> via the configuration information transmission bus <b>3450</b>.

0284During the period when the output value from the cell address comparator <b>4000</b> remains <b>0</b>, the storage unit address counter <b>8200</b> continues the output.

0285When receiving <b>1</b> from the cell address comparator <b>4000</b>, the storage unit address counter <b>8200</b> changes the cell address to be output to the cell address comparator <b>4000</b> to “11” and also changed the configuration information to be output to the configuration information selector <b>3400</b> to “5778”.

0286The remaining components of the dynamic reconfiguration arithmetic circuit <b>120</b> have the same functions as those in Embodiment 1.

0287(19) Each of the above-mentioned apparatuses and circuits may be, specifically speaking, a computer system composed of a microprocessor, a ROM, a RAM, a hard disk unit, a display unit, a keyboard, a mouse and the like. A computer program is stored in the RAM or the hard disk unit. The microprocessor operates according to the computer program, and thereby the apparatus fulfills its functions. Here, the computer program is structured by combining multiple instruction codes indicating commands to the computer to achieve predetermined functions.

0288<figref idref="DRAWINGS">FIG. 18</figref> is a block diagram showing an example of an information processing apparatus <b>1700</b> that performs the configuration change of the dynamic reconfiguration arithmetic block <b>2010</b> using a program.

0289Although the information processing apparatus <b>1700</b> conceivably has various components besides the ones shown in the figure, the figure shows only components relating to the configuration change of the dynamic reconfiguration arithmetic block <b>2010</b>.

0290As shown in <figref idref="DRAWINGS">FIG. 18</figref>, the information processing apparatus <b>1700</b> includes the configuration information storage unit <b>3000</b>, the reconfiguration cell address storage unit <b>6000</b>, a main control unit <b>1300</b>, and the dynamic reconfiguration arithmetic block <b>2010</b>. The configuration information storage unit <b>3000</b> is connected to the main control unit <b>1300</b> via the configuration information storage unit output line <b>3550</b>, and the reconfiguration cell address storage unit <b>6000</b> is connected to the main control unit <b>1300</b> via the reconfiguration cell address storage unit output line <b>6300</b>. The dynamic reconfiguration arithmetic block <b>2010</b> is connected to the main control unit <b>1300</b> via the configuration information output bus <b>3200</b> and the configuration information input bus <b>3100</b>. The shift register in the dynamic reconfiguration arithmetic block <b>2010</b> receives a pulse signal from the main control unit <b>1300</b> via a pulse output line <b>5150</b>.

0291The structures of the configuration information storage unit <b>3000</b> and the reconfiguration cell address storage unit <b>6000</b> are the same as those of the configuration information storage unit <b>3000</b> and the reconfiguration cell address storage unit <b>6000</b> described in Embodiment 1.

0292The main control unit <b>1300</b> is a computer system including composed of a processor <b>1500</b> and a memory <b>1400</b>. The memory <b>1400</b> stores therein various computer programs including a circuit reconfiguration program <b>1600</b>. The processor <b>1500</b> operates according to a computer program stored in the memory <b>1400</b>, and thereby the information processing apparatus <b>1700</b> fulfills part of its functions.

0293The circuit reconfiguration program <b>1600</b> stored in the memory <b>1400</b> is, specifically speaking, a procedure of the configuration change of the dynamic reconfiguration arithmetic block <b>2010</b>, as one shown in <figref idref="DRAWINGS">FIG. 8</figref>, written in machine language readable by the processor <b>1500</b>.

0294By the processor <b>1500</b> operating according to the circuit reconfiguration program <b>1600</b>, the main control unit <b>1300</b> periodically outputs a pulse signal, reads configuration information stored in each storage unit in the dynamic reconfiguration arithmetic block <b>2010</b> via the configuration information output bus <b>3200</b>, inputs configuration information corresponding to arithmetic cells whose configuration needs not to be changed straight to the dynamic reconfiguration arithmetic block <b>2010</b> via the configuration information input bus <b>3100</b>, and replaces configuration information corresponding to arithmetic cells whose configuration needs to be changed with configuration information stored in the configuration information storage unit <b>3000</b> and inputs the replaced configuration information to the dynamic reconfiguration arithmetic block <b>2010</b>. Herewith, the configuration change of the dynamic reconfiguration arithmetic block <b>2010</b> can be realized as in Embodiment 1.

0295(20) Part or all of the components making up the above individual apparatuses may be assembled as a single system LSI (Large Scale Integration). The system LSI is an ultra-multifunctional LSI produced by integrating multiple components on one chip, and more specifically, is a computer system composed of a microprocessor, ROM, RAM, and the like. A computer program is stored in the RAM. The microprocessor operates according to the computer program, and thereby the system LSI accomplishes its function.

0296(21) Each element, part or all of the components making up the above individual apparatuses and circuits may be assembled as an IC card detachable from a device, or as a single module. The IC card/module is a computer system composed of a microprocessor, ROM, RAM, and the like. The IC card/module may include therein the above-mentioned ultra-multifunctional LSI. The microprocessor operates according to a computer program, and thereby the IC card/module accomplishes its function. The IC card/module may be tamper resistant.

0297(22) The present invention may be a method of accomplishing the above-described system. The present invention may be a computer program that achieves the method by a computer, or may be a digital signal representing the computer program.

0298The present invention may also be achieved by a computer-readable recording medium, such as a flexible disk, a hard disk, a CD-ROM, an MO disk, a DVD, a DVD-ROM, a DVD-RAM, a BD (Blu-ray Disc), or a semiconductor memory, on which the above-mentioned computer program or digital signal is recorded. The present invention may also be the computer program or the digital signal recorded on such a storage medium.

0299The present invention may also be the computer program or digital signal to be transmitted via networks, as represented by telecommunications, wire/wireless communications, and the Internet, or via data broadcasting.

0300The present invention may also be a computer system having a microprocessor and memory, wherein the memory stores the computer program and the microprocessor operates according to the computer program.

0301The computer program or digital signal may be recorded on the above storage medium and transferred to an independent computer system, or alternatively, may be transferred to an independent computer system via the above network. Then, the independent computer system may execute the computer program or digital signal.

0302(23) Assembling only a part, not all, of the functional blocks with an LSI is also within the scope of the present invention. Each of the functional blocks may be assembled on one chip, or part or all of the functional blocks are integrated on one chip. Although referred to here as LSI, it may be also referred to as IC, system LSI, super LSI, and ultra LSI, depending on the degree of integration.

0303In addition, the method for assembling integrated circuits is not limited to LSI, and a dedicated communication circuit or a general-purpose processor may be used to achieve this.

0304(24) In the above embodiments and modifications, FPGA and PLD are used as specific examples of the dynamic reconfiguration arithmetic block; however, the present invention is not limited to them. Further, if technology for forming integrated circuits that replaces LSIs is introduced, owing to advance in semiconductor technology or different technology derived therefrom, the integration of functional blocks may naturally be accomplished using such technology. There is also a possibility of application of biotechnology to the integrated circuit technology.

0305(25) The present invention includes a structure in which two or more of the above embodiments and modifications are combined.

0306(26) The present invention is applicable operationally and repeatedly in industries that manufacture and sell dynamic reconfiguration arithmetic circuits, industries that manufacture and sell various electrical apparatuses having thereon dynamic reconfiguration arithmetic circuits, and industries that offer services using the electrical apparatuses.

0307Although the present invention has been fully described by way of examples with reference to the accompanying drawings, it is to be noted that various changes and modifications will be apparent to those skilled in the art. Therefore, unless otherwise such changes and modifications depart from the scope of the present invention, they should be constructed as being included therein.