Information processing device, data transfer method, and information storage medium

BACKGROUND OF THE INVENTION

0001The present invention relates to an information processing device, a data transfer method, and an information storage medium.

0002In the event of a processor transferring data in a main memory to an I/O device such as an NIC (Network Interface Card), if the processor is already executing another program, there is a potential problem that it will not be possible to demonstrate sufficient transfer performance such as latency and transfer rate. It has therefore, been considered to provide dedicated hardware for data transfer at the I/O device side, so that it is made possible to stably exhibit transfer performance.

0003However, in order for the above-described dedicated hardware to directly access data in the main memory, it is necessary for an address translation table, for translating the logical address of the data to a physical address, to be set beforehand. With the above-described structure therefore, it is necessary to create a new address translation table in the dedicated hardware before data transfer, and there is a problem in that it is not possible to execute data transfer immediately the need arises.

SUMMARY OF THE INVENTION

0004The present invention has been conceived in view of the above-described situation, and an object of the invention is to provide an information processing device, data transfer method and information storage medium that can commence data transfer to an I/O device immediately, and can stably exhibit data transfer performance.

0005In order to solve the above described problems, an information processing device of the present invention comprises a memory, a main processor, at least one sub-processor, an I/O device, and address translation table sharing means, for sharing an address translation table, for translating logical addresses of the memory to physical addresses, between the main processor and the at least one sub-processor, wherein the one sub-processors is provided with request receiving means for receiving a transfer request designating a logical address of the memory, address translation means for translating the logical address designated by the transfer request to a physical address using the shared address translation table, and transfer process execution means for executing transfer process for data stored in the memory to the I/O device in accordance with the translated physical address.

0006It is also possible for the one sub-processor to be provided with a local memory. In this case, it is possible for the transfer process execution means to include means for reading out data from the physical address translated by the address translation means, and storing data in the local memory based on the data, and means for sending a transfer request designating the physical address of data stored in the local memory to the I/O device, and for the I/O device to read out data from the local memory in accordance with a physical address designated by the transfer request received from the one sub processor.

0007Also, a data transfer method of the present invention is performed by a computer comprising a memory, a main processor, at least one sub-processor, an I/O device, and address translation table sharing means, for sharing an address translation table, for translating logical addresses of the memory to physical addresses, between the main processor and the at least one sub-processor, and executes, in the one sub-processor, a step of receiving a transfer request designating a logical address of the memory, a step of translating the logical address designated by the transfer request to a physical address using the shared address translation table, and a step of executing a transfer process for data stored in the memory in accordance with the translated physical address.

0008Also, an information storage medium of the resent invention stores a program, executed by a computer comprising a memory, a main processor, at least one sub-processor, an I/O device, and address translation table sharing means, for sharing an address translation table, for translating logical addresses of the memory to physical addresses, between the main processor and the at least one sub-processor, and the program cause the at least one sub-processor to function as means for receiving a transfer request designating a logical address of the memory, means for translating the logical address designated by the transfer request to a physical address using the shared address translation table, and means for executing a transfer process for data stored in the memory in accordance with the translated physical address. This program can be stored in an information storage medium capable of being read by various types of computer.

BRIEF DESCRIPTION OF THE DRAWINGS

0009<figref idref="DRAWINGS">FIG. 1</figref> is a structural drawing of an information processing device of one embodiment of the present invention.

0010<figref idref="DRAWINGS">FIG. 2</figref> is a drawing showing stored content of the local memory and the main memory.

0011<figref idref="DRAWINGS">FIG. 3</figref> is a sequence drawing showing a data transfer process.

DESCRIPTION OF PREFERRED EMBODIMENTS

0012One embodiment of the present invention will be described in the following based on the drawings.

0013<figref idref="DRAWINGS">FIG. 1</figref> is a structural drawing of an information processing device of the present invention. As shown in <figref idref="DRAWINGS">FIG. 1</figref>, this information processing device <b>10</b> includes a main processor <b>12</b> and a plurality of sub-processors <b>24</b>-<b>1</b> to <b>24</b>-<i>n</i>, and is constructed as an asymmetric multi-core processor. The main processor <b>12</b> and the plurality of sub-processors <b>24</b>-<b>1</b> to <b>24</b>-<i>n </i>are all connected to a bus <b>22</b>, and data can be mutually sent and received among the processors via this bus <b>22</b>. A main memory <b>14</b> is connected to the bus <b>22</b> via a memory interface <b>16</b>, and an NIC <b>20</b> as an I/O device is connected to the bus <b>22</b> via an input output interface <b>18</b>.

0014The main processor <b>12</b> is program execution means for executing programs, such as an operating system and performing task allocation to the sub-processors <b>24</b>-<b>1</b> to <b>24</b>-<i>n</i>, and contains a memory management unit <b>12</b><i>a </i>and a cache memory <b>12</b><i>b</i>. The memory management unit <b>12</b><i>a </i>is hardware for executing processing for translating a logical address, that is generated by the main processor <b>12</b> or received externally, into a physical address of the main memory <b>14</b> and carries out this translation processing in accordance with an address translation table stored in the main memory <b>14</b>. The address translation table is a table which associates logical addresses with physical addresses, and is made up of page groups of a specified size such as 4 KB. Therefore, the memory management section <b>12</b><i>a </i>is provided with a memory for storing the necessary pages, of these pages, and when a logical address generated by the main processor <b>12</b> does not exist in a page stored in the memory, another page is read out from the main memory <b>14</b> and the memory contents updated. Also, the cache memory <b>12</b><i>b </i>is a memory for temporarily storing commands and data to be processed by the main processor <b>12</b>.

0015The sub-processors <b>24</b> (<b>24</b>-<b>1</b> to <b>24</b>-<i>n</i>) are ancillary program execution means containing local memory <b>24</b><i>a</i>, a memory management section <b>24</b><i>b </i>and a DMAC (Direct Memory Access Controller). The local memory <b>24</b><i>a</i>, as shown in <figref idref="DRAWINGS">FIG. 2</figref>(<i>a</i>) is used to store a program <b>24</b><i>a</i>′ executed by the sub processor <b>24</b>, and temporarily stored data that is the object of processing. The memory control section <b>24</b><i>b </i>also provides the same functions as the memory management section <b>12</b><i>a</i>. More specifically, the memory management unit <b>24</b><i>b </i>is hardware for executing processing for translating a logical address, that is generated by the sub processor <b>24</b> or received externally, into a physical address of the main memory <b>14</b> and carries out this translation processing in accordance with an address translation table stored in the main memory <b>14</b>. The memory management section <b>24</b><i>b </i>is provided with a memory for storing the necessary pages of the address translation table, and when a logical address that requires translation does not exist in a page stored in the memory, another page is read out from the main memory <b>14</b> and the memory contents updated. The DMAC <b>24</b><i>c </i>is also a control unit for direct access to the main memory <b>14</b>, without going via the main processor <b>12</b>. With this embodiment, in particular, of the sub-processors <b>24</b>-<b>1</b> to <b>24</b>-<i>n</i>, a transfer task for transferring transfer data stored in the main memory <b>14</b> to the NIC <b>20</b> is allocated to the sub-processor <b>24</b>-<b>1</b>, and in this way it is possible to execute high speed data transfer without imposing a processing load on the main processor <b>12</b>. Therefore, processing to transfer the transfer data stored in the main memory <b>14</b> to the NIC <b>20</b> is implemented by storing a data transfer program in the local memory <b>24</b><i>a</i>-<b>1</b> as a sub-processor program <b>24</b><i>a</i>′, and having the sub-processor <b>24</b>-<b>1</b> execute this data transfer program. Also, at the time of this transfer task, as shown in <figref idref="DRAWINGS">FIG. 2</figref>(<i>a</i>), data to be transferred to the NIC <b>20</b> that is stored in the main memory <b>14</b>, that is, transfer data <b>24</b><i>a</i>″, is temporarily stored in the local memory <b>24</b><i>a</i>-<b>1</b> of the sib-processor <b>24</b>-<b>1</b> (described in detail later).

0016As shown in <figref idref="DRAWINGS">FIG. 2</figref>(<i>b</i>), a system program <b>14</b><i>a</i>, such as an OS (operating system) executed by the main processor <b>12</b>, a user program <b>14</b><i>b </i>executed by the main processor <b>12</b>, and an address translation table <b>14</b><i>c </i>are stored in the main memory <b>14</b>. The address translation table <b>14</b><i>c </i>is updated by the main processor system program <b>14</b><i>a</i>, and when the table has been updated this fact is also notified to the sub-processors <b>24</b>-<b>1</b> to <b>24</b>-<i>n</i>, and the latest address translation table <b>14</b><i>c </i>is shared by the main processor <b>12</b> and the sub-processors <b>24</b>-<b>1</b> to <b>24</b>-<i>n</i>. Data generated by the main processor <b>12</b> and the sub-processors <b>24</b>-<b>1</b> to <b>24</b>-<i>n </i>that is to be transferred to the NIC <b>20</b>, namely transfer data <b>14</b><i>d</i>, is also stored in the main memory <b>14</b>. As has been described above, this transfer data <b>14</b><i>d </i>is temporarily transferred to the sub-processor <b>24</b>-<b>1</b> at the time of transfer to the NIC <b>20</b>, and is stored in the local memory <b>24</b><i>a</i>-<b>1</b>.

0017The NIC <b>20</b> is an interface for connecting this information processing device <b>10</b> to a data communication network such as a LAN (Local Area Network), and contains a DMAC <b>20</b><i>a </i>and a buffer memory <b>20</b><i>b</i>. The DMAC <b>20</b><i>a </i>is a control unit for direct access to the main memory <b>14</b> and the local memory <b>24</b><i>a </i>of each sub-processor <b>24</b>, and stores received data in the buffer memory <b>20</b><i>b</i>. The buffer memory <b>2</b><i>b </i>is a FIFO (First In First Out) buffer, and data stored in the buffer memory <b>20</b><i>b </i>are sequentially sent to the network.

0018Here, data transfer processing of the information processing device <b>10</b> will be described. <figref idref="DRAWINGS">FIG. 3</figref> is a sequence diagram for data transfer processing when data transfer to the sub-processor <b>24</b>-<b>1</b>, which is a processor for data transfer, is carried out after transfer data <b>14</b><i>d </i>has been stored in the main memory <b>14</b> by a sub-processor N. As shown in <figref idref="DRAWINGS">FIG. 3</figref>, if a data transfer request designating of logical address (here made “a”) of transfer data <b>14</b><i>d </i>is transmitted by the sub-processor <b>24</b>-<i>n </i>via the bus <b>22</b> to the sub-processor <b>24</b>-<b>1</b> (S<b>101</b>), the sub-processor <b>24</b>-<b>1</b> receives this data transfer request. The memory management section <b>24</b><i>b</i>-<b>1</b> of the sub-processor <b>24</b>-<b>1</b> translates the logical address “a” designated in the data transfer request to a physical address “A” based on some pages of the address translation table <b>14</b><i>c </i>stored in the internal memory (S<b>102</b>). This physical address “A” is then transmitted to the memory interface <b>16</b> (S<b>103</b>), and transfer data <b>14</b><i>d </i>stored at the physical address “A” of the main memory <b>14</b> is received (S<b>104</b>). Next, the sub-processor <b>24</b>-<b>1</b> stores the received transfer data <b>14</b><i>d </i>in the local memory <b>24</b><i>a</i>-<b>1</b> (S<b>105</b>). Then, a data transfer instruction designating a physical address (here made “B”) for a storage destination us transmitted via the bus <b>22</b> to the NIC <b>20</b> (S<b>106</b>). The NIC <b>20</b> transits the physical address “B” to the sub-processor <b>24</b>-<b>1</b> in response to this instruction (S<b>107</b>), and receives transfer data <b>24</b><i>a</i>″ (namely transfer data <b>14</b><i>d</i>) returned from the sub-processor <b>24</b>-<b>1</b> (S<b>108</b>). The thus received transfer data <b>24</b><i>a</i>″ is then stored in the buffer memory <b>20</b><i>b </i>and used in communication processing (S<b>109</b>).

0019According to the above described information processing device <b>10</b>, since a single sub-processor <b>24</b>-<b>1</b> constituting a multi-core processor is allocated solely to data transfer, it is possible to implement data transfer at high speed and with low latency regardless of the operating state of the main processor <b>12</b>. Also, since data transfer is implemented using an address translation table <b>14</b><i>c </i>that is shared between the main processor <b>12</b> and the sub-processor <b>24</b> due to the hardware architecture of the information processing device <b>10</b>, it is possible to carry out data transfer immediately the need arises.

0020Incidentally, the present invention is not limited to the above described embodiment, and various modifications are possible. For example, with the above described embodiment an NIC <b>20</b> has been adopted as the I/O device, but it is also possible to have another I/O device such as a hard disk storage device. Also, with the above described embodiment transfer data <b>14</b><i>d </i>stored in the main memory is stored as it is in the local memory <b>24</b><i>a</i>-<b>1</b> of the sub-processor <b>24</b>-<b>1</b>, but it is also possible, for example, to perform carious translation processes such as encryption in the sub-processor <b>24</b>-<b>1</b>, and after that store as transfer data <b>24</b><i>a</i>″, and transfer this translated data <b>24</b><i>a</i>″ to the NIC <b>20</b>.