Data Processing System and Method for Efficient L3 Cache Directory Management

CROSS-REFERENCE TO RELATED APPLICATIONS

0001The present application is a continuation of U.S. patent application Ser. No. 11/055,301 (AUS920040916US1), filed on Feb. 10, 2005, and entitled “Data Processing System and Method for Efficient L3 Cache Directory Management,” which is also related to U.S. patent application Ser. No. 11/055,483 (AUS920040802US1), which is assigned to the assignee of the present invention and incorporated herein by reference in its entirety.

BACKGROUND OF THE INVENTION

00021. Technical Field

0003The present invention relates in general to data processing systems, and more particularly to an improved multi-processor data processing system. Still more particularly, the present invention relates to improved management of a hierarchical cache system within a multi-processor data processing system.

00042. Description of the Related Art

0005A conventional symmetric multiprocessor (SMP) computer system, such as a server computer system, includes multiple processing units all coupled to a system interconnect, which typically comprises one or more address, data and control buses. Coupled to the system interconnect is a system memory, which represents the lowest level of volatile memory in the multiprocessor computer system and generally is accessible for read and write access by all processing units. In order to reduce access latency to instructions and data residing in the system memory, each processing unit is typically further supported by a respective multi-level cache hierarchy, the lower level(s) of which may be shared by one or more processor cores.

0006Because multiple processor cores may request write access to a same cache line of data and because modified cache lines are not immediately synchronized with system memory, the cache hierarchies of multiprocessor computer systems typically implement a cache coherency protocol to ensure at least a minimum level of coherence among the various processor core's “views” of the contents of system memory. In particular, cache coherency requires, at a minimum, that after a processing unit accesses a copy of a memory block and subsequently accesses an updated copy of the memory block, the processing unit cannot again access the old copy of the memory block.

0007A cache coherency protocol typically defines a set of cache states stored in association with the cache lines stored at each level of the cache hierarchy, as well as a set of coherency messages utilized to communicate the cache state information between cache hierarchies. In a typical implementation, the cache state information takes the form of the well-known MESI (Modified, Exclusive, Shared, Invalid) protocol or a variant thereof, and the coherency messages indicate a protocol-defined coherency state transition in the cache hierarchy of the requestor and/or the recipients of a memory access request. The MESI protocol allows a cache line of data to be tagged with one of four states: “M” (modified), “E” (exclusive), “S” (shared), or “I” (invalid). The Modified state indicates that a coherency granule is valid only in the cache storing the modified coherency granule and that the value of the modified coherency granule has not been written to system memory. When a coherency granule is indicated as Exclusive, then, of all caches at that level of the memory hierarchy, only that cache holds the coherency. The data in the Exclusive state is consistent with system memory, however. If a coherency granule is marked as Shared in a cache directory, the coherency granule is resident in the associated cache and in at least one other cache at the same level of the memory hierarchy, and all of the copies of the coherency granule are consistent with system memory. Finally, the Invalid state indicates that the data and address tag associated with a coherency granule are both invalid.

0008The state to which each coherency granule (e.g., cache line or sector) is set is dependent upon both a previous state of the data within the cache line and the type of memory access request received from a requesting device (e.g., the processor). Accordingly, maintaining memory coherency in the system requires that the processors communicate messages across the system bus indicating their intention to read or write to memory locations. For example, when a processor desires to write data to a memory location, the processor must first inform all other processing elements of its intention to write data to the memory location and receive permission from all other processing elements to carry out the write operation. The permission messages received by the requesting processor indicate that all other cached copies of the contents of the memory location have been invalidated, thereby guaranteeing that the other processors will not access their stale local data.

0009In some systems, the cache hierarchy includes at least two levels. The level one (L1), or an upper-level cache is usually a private cache associated with a particular processor core in an MP system. The processor core first looks for a data in the upper-level (L1) cache. If the requested data is not found in the upper-level cache, the processor core then access lower-level caches (e.g., level two (L2) or level three (L3) caches) for the requested data. The lowest level cache (e.g., L3) is often shared among several processor cores (L2 cache being an upper-level cache relative to L3 cache).

0010Typically, when a congruence class of one of an upper-level cache becomes full, data lines are “evicted” or written to a lower-level cache or out to system memory for storage. However, in any memory hierarchy, there may be several copies of the same data residing in the memory hierarchy at the same time. The policy of evicting lines to provide for more space in the upper-level cache results in writes to lower-level caches, including updating coherency state information in the lower-level cache directory.

0011Heretofore, cache coherency protocols have generally assumed that to maintain cache coherency, coherency states from upper-level cache is copied into lower-level cache. The present invention recognizes significant performance enhancements to the data processing system can be achieved by intelligently defining the protocols for coherency state transition in the cache hierarchy.

SUMMARY OF THE INVENTION

0012In accordance with the present invention, improved methods, systems and articles of manufacture for cache management in a data processing system having a memory hierarchy including at least an upper memory cache and a lower memory cache are disclosed. One preferred method of the present invention comprises the steps of comparing a first coherency data related to cache data indicated in the lower memory cache to second coherency data related to the cache data indicated in the upper memory cache, determining a coherency state of the cache data in the lower memory cache in response to the comparison of the first coherency data and the second coherency data, and replacing a coherency value associated with the cache data within the lower memory cache with the determined coherency state.

0013All objects, features, and advantages of the present invention will become apparent in the following detailed written description.

BRIEF DESCRIPTION OF THE DRAWINGS

0014This invention is described in a preferred embodiment in the following description with reference to the drawings, in which like numbers represent the same or similar elements, as follows:

0015<figref idref="DRAWINGS">FIG. 1</figref> is illustrates a high level block diagram of an exemplary embodiment of a cache coherent symmetric multiprocessor (SMP) data processing system in accordance with the present invention.

0016<figref idref="DRAWINGS">FIG. 2 a</figref> block diagram of a detailed block diagram of an exemplary processing unit, in accordance with the preferred embodiment of the present invention.

0017<figref idref="DRAWINGS">FIG. 3</figref> is a block diagram of an exemplary embodiment of L2/L3 array and directory, in accordance with a preferred embodiment of the present invention.

0018<figref idref="DRAWINGS">FIG. 4</figref> is a time-space diagram of an exemplary operation on a local or system interconnect of the data processing system, in accordance with a preferred embodiment of the present invention.

0019<figref idref="DRAWINGS">FIG. 5</figref> is a high-level logical flow diagram of an exemplary method of performing cast-in to the L3 cache in accordance with the preferred embodiment of the present invention.

0020<figref idref="DRAWINGS">FIG. 6</figref> is a high-level logical flow diagram of an exemplary method of a coherency state transition policy implemented by the L3 cache in response to a cast-in, in accordance with a preferred embodiment of the present invention.

0021In the following detailed description of exemplary embodiments of the invention, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific exemplary embodiments in which the invention may be practiced.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

0022With reference now to the figures and, in particular, with reference to <figref idref="DRAWINGS">FIG. 1</figref>, there is illustrated a high level block diagram of an exemplary embodiment of a cache coherent symmetric multiprocessor (SMP) data processing system in accordance with the present invention. As shown, data processing system <b>100</b> includes multiple processing nodes <b>102</b><i>a</i>, <b>102</b><i>b </i>for processing data and instructions. Processing nodes <b>102</b> are coupled to a system interconnect <b>110</b> for conveying address, data and control information. System interconnect <b>110</b> may be implemented, for example, as a bused interconnect, a switched interconnect or a hybrid interconnect.

0023In the depicted embodiment, each processing node <b>102</b> is realized as a multi-chip module (MCM) containing four processing units <b>104</b><i>a</i>-<b>104</b><i>d</i>, each preferably realized as a respective integrated circuit. The processing units <b>104</b> within each processing node <b>102</b> are coupled for communication to each other and system interconnect <b>110</b> by a local interconnect <b>114</b>, which, like system interconnect <b>110</b>, may be implemented, for example, with one or more buses and/or switches.

0024The devices attached to each local interconnect <b>114</b> include not only processing units <b>104</b>, but also one or more memory controllers <b>106</b>, each providing an interface to a respective system memory <b>108</b>. Data and instructions residing in system memories <b>108</b> can generally be accessed and modified by a processor core in any processing unit <b>104</b> in any processing node <b>102</b> of data processing system <b>100</b>. In alternative embodiments of the invention, one or more memory controllers <b>106</b> (and system memories <b>108</b>) can be coupled to system interconnect <b>110</b> rather than a local interconnect <b>114</b>, or alternatively, integrated within another device such as a processing unit <b>104</b>.

0025Lookaside L3 caches <b>105</b> are preferably coupled to processing unit <b>104</b> on local interconnect <b>114</b>. Because of the lower latencies of cache memories as compared with memories <b>108</b>, L3 caches <b>105</b> are utilized by processing units <b>102</b> as “cast-out” storage facilities for recently victimized cache lines at higher level caches. Cache Controller (CC) <b>109</b> initiates transactions on local interconnect <b>114</b> and system interconnect <b>110</b> and accesses L3 array and directory in response to memory access (and other) requests received from the associated processor cores <b>200</b>. Cache Controller (CC) <b>109</b> also snoops operations on local interconnect <b>114</b>, provides appropriate responses, and performs any accesses to L3 array and directory required by the operations.

0026Those skilled in the art will appreciate that SMP data processing system <b>100</b> can include many additional unillustrated components, such as interconnect bridges, non-volatile storage, ports for connection to networks or attached devices, etc. Because such additional components are not necessary for an understanding of the present invention, they are not illustrated in <figref idref="DRAWINGS">FIG. 1</figref> or discussed further herein. It should also be understood, however, that the enhancements provided by the present invention are applicable to cache coherent data processing systems of diverse architectures and are in no way limited to the generalized data processing system architecture illustrated in <figref idref="DRAWINGS">FIG. 1</figref>.

0027Referring now to <figref idref="DRAWINGS">FIG. 2</figref>, there is depicted a more detailed block diagram of an exemplary processing unit <b>104</b> in accordance with the present invention. In the depicted embodiment, each processing unit <b>104</b> includes two processor cores <b>200</b><i>a</i>, <b>200</b><i>b </i>for independently processing instructions and data. Each processor core <b>200</b> includes at least an instruction sequencing unit (ISU) <b>222</b> for fetching and ordering instructions for execution and one or more execution units <b>224</b> for executing instructions. The instructions executed by execution units <b>224</b> include instructions that request access to a memory block or cause the generation of a request for access to a memory block.

0028The operation of each processor core <b>200</b> is supported by a multi-level volatile memory hierarchy having at its lowest level shared system memories <b>108</b>, and at its upper levels one or more levels of cache memory, which in the illustrative embodiment include a store-through level one (L1) cache <b>226</b> within each processor core <b>200</b>, a level two (L2) cache <b>230</b> shared by all processor cores <b>200</b><i>a</i>, <b>200</b><i>b </i>of the processing unit <b>104</b>, and a lookaside level three (L3) cache <b>105</b> shared by all processing units <b>104</b>. L2 cache <b>230</b> includes an L2 array and directory <b>234</b>, a master <b>109</b>, <b>232</b> and a snooper <b>236</b>. L3 cache <b>105</b> similarly includes an L3 array and directory, a master and a snooper (represented collectively as L3 cache controller <b>109</b> in <figref idref="DRAWINGS">FIG. 1</figref>). As described herein below, the L2 and L3 array and directory, a master and a snooper are similar in operation and configuration. The descriptions below refer equally to either level of memory unless expressly distinguished. Master <b>109</b>, <b>232</b> initiates transactions on local interconnect <b>114</b> and system interconnect <b>110</b> and accesses L2 array and directory <b>234</b> in response to memory access (and other) requests received from the associated processor cores <b>200</b>. Snooper <b>236</b> snoops operations on local interconnect <b>114</b>, provides appropriate responses, and performs any accesses to L2 array and directory <b>234</b> required by the operations. Although the illustrated cache hierarchy includes only three levels of cache, those skilled in the art will appreciate that alternative embodiments may include additional levels (L4, L5, etc.) of on-chip or off-chip in-line or lookaside cache, which may be fully inclusive, partially inclusive, or non-inclusive of the contents the upper levels of cache.

0029Each processing unit <b>104</b> further includes an instance of response logic <b>210</b> implements a portion of the distributed coherency signaling mechanism that maintains cache coherency within data processing system <b>100</b>. In addition, each processing unit <b>104</b> includes an instance of forwarding logic <b>212</b> for selectively forwarding communications between its local interconnect <b>114</b> and system interconnect <b>110</b>. Finally, each processing unit <b>104</b> includes an integrated I/O (input/output) controller <b>214</b> supporting the attachment of one or more I/O devices, such as I/O device <b>216</b>. An I/O controller <b>214</b> may issue read and write operations on its local interconnect <b>114</b> and system interconnect <b>110</b>, for example, in response to requests by its attached I/O device(s) <b>216</b>.

0030With reference now to <figref idref="DRAWINGS">FIG. 3</figref>, there is illustrated a block diagram of an exemplary embodiment of L2/L3 array and directory, in accordance with a preferred embodiment of the present invention. As illustrated, array and directory <b>300</b>, <b>302</b> includes a set associative cache array <b>300</b> and a cache directory <b>302</b> identifying the contents of cache array <b>300</b>. As in conventional set associative caches, memory locations in system memories <b>108</b> are mapped to particular congruence classes within cache arrays <b>300</b> utilizing predetermined index bits within the system memory (real) addresses. The standard memory block for the coherency system is set at a 128B cache line. The particular cache lines stored within cache array <b>300</b> are recorded in cache directory <b>302</b>, which contains one directory entry for each cache line in cache array <b>300</b>. As understood by those skilled in the art, each directory entry in cache directory <b>302</b> comprises at least a tag field <b>304</b>, which specifies the particular cache line stored in cache array <b>300</b> utilizing a tag portion of the corresponding real address, a state field <b>306</b>, which indicates the coherency state of the cache line, and a LRU (Least Recently Used) field <b>308</b> indicating a replacement order for the cache line with respect to other cache lines in the same congruence class.

0031Referring now to <figref idref="DRAWINGS">FIG. 4</figref>, there is depicted a time-space diagram of an exemplary operation on a local or system interconnect <b>110</b>, <b>114</b> of data processing system <b>100</b> of <figref idref="DRAWINGS">FIG. 1</figref>. The operation begins when a master <b>109</b>, <b>232</b> of an L2 cache <b>230</b> (or another master, such as cache controller <b>109</b> or an I/O controller <b>214</b>) issues a request <b>402</b> on an interconnect <b>110</b>, <b>114</b>. Request <b>402</b> preferably includes a transaction type indicating a type of desired access and a resource identifier (e.g., real address) indicating a resource to be accessed by the request. Common types of requests preferably include those set forth below in Table I. <tables id="TABLE-US-00001" num="1"><table frame="none" colsep="0" rowsep="0"><tgroup align="left" colsep="0" rowsep="0" cols="2"><colspec colname="1" colwidth="49PT" align="left" /><colspec colname="2" colwidth="168PT" align="left" /><thead><row><entry namest="1" nameend="2" align="center">TABLE I</entry></row><row><entry /></row><row><entry namest="1" nameend="2" align="center" rowsep="1" /></row><row><entry>Request</entry><entry>Description</entry></row><row><entry namest="1" nameend="2" align="center" rowsep="1" /></row></thead><tbody valign="top"><row><entry>READ</entry><entry>Requests a copy of the image of a memory block for</entry></row><row><entry /><entry>query purposes</entry></row><row><entry>RWITM</entry><entry>Requests a unique copy of the image of a memory</entry></row><row><entry>(Read-With-</entry><entry>block with the intent to update (modify) it and</entry></row><row><entry>Intent-To-</entry><entry>requires destruction of other copies, if any</entry></row><row><entry>Modify)</entry></row><row><entry>DCLAIM</entry><entry>Requests authority to promote an existing query-</entry></row><row><entry>(Data Claim)</entry><entry>only copy of memory block to a unique copy with</entry></row><row><entry /><entry>the intent to update (modify) it and requires</entry></row><row><entry /><entry>destruction of other copies, if any</entry></row><row><entry>DCBZ (Data</entry><entry>Requests authority to create a new unique copy</entry></row><row><entry>Cache Block</entry><entry>of a memory block without regard to its present</entry></row><row><entry>Zero)</entry><entry>state and subsequently modify its contents;</entry></row><row><entry /><entry>requires destruction of other copies, if any</entry></row><row><entry>CASTOUT</entry><entry>Copies the image of a memory block from a higher</entry></row><row><entry /><entry>level of memory to a lower level of memory in</entry></row><row><entry /><entry>preparation for the destruction of the higher</entry></row><row><entry /><entry>level copy. A “CASTIN” is a received CASTOUT</entry></row><row><entry /><entry>from a higher level of memory.</entry></row><row><entry>WRITE</entry><entry>Requests authority to create a new unique copy</entry></row><row><entry /><entry>of a memory block without regard to its present</entry></row><row><entry /><entry>state and immediately copy the image of the memory</entry></row><row><entry /><entry>block from a higher level memory to a lower level</entry></row><row><entry /><entry>memory in preparation for the destruction of the</entry></row><row><entry /><entry>higher level copy</entry></row><row><entry>PARTIAL</entry><entry>Requests authority to create a new unique copy of</entry></row><row><entry>WRITE</entry><entry>a partial memory block without regard to its present</entry></row><row><entry /><entry>state and immediately copy the image of the partial</entry></row><row><entry /><entry>memory block from a higher level memory to a lower</entry></row><row><entry /><entry>level memory in preparation for the destruction of</entry></row><row><entry /><entry>the higher level copy</entry></row><row><entry namest="1" nameend="2" align="center" rowsep="1" /></row></tbody></tgroup></table></tables>

0032Request <b>402</b> is received by the snooper <b>236</b> of L2 caches <b>230</b> and the snooper of cache controller <b>109</b>, as well as the snoopers <b>122</b><i>a</i>, <b>122</b><i>b </i>of memory controllers <b>106</b><i>a</i>, <b>106</b><i>b </i>(<figref idref="DRAWINGS">FIG. 1</figref>). In general, with some exceptions, the snooper <b>236</b> in the same L2 cache <b>230</b> as the master <b>109</b>, <b>232</b> of request <b>402</b> does not snoop request <b>402</b> (i.e., there is generally no self-snooping) because a request <b>402</b> is transmitted on local interconnect <b>114</b> and/or system interconnect <b>110</b> only if the request <b>402</b> cannot be serviced internally by a processing unit <b>104</b>. In response to request <b>402</b>, each snooper <b>109</b>, <b>122</b>, <b>236</b> receiving request <b>402</b> provides a respective partial response <b>406</b> representing the response of at least that snooper to request <b>402</b>. A snooper within a memory controller <b>106</b> determines the partial response <b>406</b> to provide based, for example, whether the snooper is responsible for the request address and whether it has resources available to service the request. A snooper <b>236</b> of an L2 cache <b>230</b> or cache controller <b>109</b> may determine its partial response <b>406</b> based on, for example, the availability of its cache directory <b>302</b>, the availability of a snoop logic instance within snooper to handle the request, and the cache state associated with the request address in cache directory <b>302</b>.

0033The partial responses of snoopers <b>109</b>, <b>122</b> and <b>236</b> are logically combined either in stages or all at once by one or more instances of response logic <b>210</b> to determine a system-wide combined response (CR) <b>410</b> to request <b>402</b>. Response logic <b>210</b> provides combined response <b>410</b> to master <b>109</b>, <b>232</b> and each snooper <b>109</b>, <b>122</b>, <b>236</b> via its local interconnect <b>114</b> and system interconnect <b>110</b> to indicate the system-wide response (e.g., success, failure, retry, etc.) to request <b>402</b>. If CR <b>410</b> indicates success of request <b>402</b>, CR <b>410</b> may indicate, for example, a data source for a requested memory block, a cache state in which the requested memory block is to be cached by master <b>109</b>, <b>232</b>, and whether “cleanup” operations invalidating the requested memory block in one or more L2 caches <b>230</b> are required.

0034In response to receipt of combined response <b>410</b>, one or more of master <b>109</b>, <b>232</b> and snoopers <b>109</b>, <b>122</b>, <b>236</b> typically perform one or more operations in order to service request <b>402</b>. These operations may include supplying data to master <b>109</b>, <b>232</b>, invalidating or otherwise updating the coherency state of data cached in one or more caches <b>230</b>, <b>105</b> performing castout operations, writing back data to a system memory <b>108</b>, etc. As discussed further below, if required by request <b>402</b>, a requested or target memory block may be transmitted to or from master <b>109</b>, <b>232</b> before or after the generation of combined response <b>410</b> by response logic <b>210</b>.

0035In the following description, partial response of a snooper <b>122</b>, <b>236</b> to a request and the operations performed by the snooper in response to the request and/or its combined response will be described with reference to whether that snooper is a Highest Point of Coherency (HPC), a Lowest Point of Coherency (LPC), or neither with respect to the request address specified by the request. An LPC is defined herein as a memory device or I/O device that serves as the repository for a memory block. In the absence of a HPC for the memory block, the LPC holds the true image of the memory block and has authority to grant or deny requests to generate an additional cached copy of the memory block. For a typical request in the data processing system embodiment of <figref idref="DRAWINGS">FIGS. 1 and 2</figref>, the LPC will be the L3 cache <b>105</b> or the memory controller <b>106</b> for the system memory <b>108</b> holding the referenced memory block. An HPC is defined herein as a device that caches a true image of the memory block (which may or may not be consistent with the corresponding memory block at the LPC) and has the authority to grant or deny a request to generate an additional cached copy of the memory block. Thus, for a typical request in the data processing system embodiment of <figref idref="DRAWINGS">FIGS. 1 and 2</figref>, the HPC, if any, within a given processing node <b>102</b> (also referred to as a “coherency domain” herein) will be either the L2 cache <b>230</b> of a given processing unit <b>104</b> or the L3 cache <b>105</b>.

0036Although other indicators may be utilized to designate an HPC for a memory block, a preferred embodiment of the present invention designates the HPC, if any, for a memory block utilizing selected cache coherency state(s) within the L2 cache directory <b>302</b> of an L2 cache <b>230</b> or the L3 cache directory <b>302</b> of an L3 cache <b>105</b>. In this preferred embodiment, the set of cache coherency states, in addition to providing (1) an indication of whether the cache is the HPC for a memory block, also indicate (2) whether the cached copy is unique (i.e., is the only cached copy) among caches at that memory hierarchy level, (3) whether and when the cache can provide a copy of the memory block to a master of a request, and (4) whether the cached image of the memory block is consistent with the corresponding memory block in the LPC. These four attributes can be expressed, for example, in a variant of the well-known MESI (Modified, Exclusive, Shared, Invalid) protocol summarized below in Table II. <tables id="TABLE-US-00002" num="2"><table frame="none" colsep="0" rowsep="0" pgwide="1"><tgroup align="left" colsep="0" rowsep="0" cols="4"><colspec colname="OFFSET" colwidth="21PT" align="left" /><colspec colname="1" colwidth="49PT" align="left" /><colspec colname="2" colwidth="133PT" align="left" /><colspec colname="3" colwidth="77PT" align="left" /><thead><row><entry /><entry namest="OFFSET" nameend="3" align="center">TABLE II</entry></row><row><entry /><entry /></row><row><entry /><entry namest="OFFSET" nameend="3" align="center" rowsep="1" /></row><row><entry /><entry>NAME</entry><entry>DEFINITION</entry><entry>ENTERED WHEN:</entry></row><row><entry /><entry namest="OFFSET" nameend="3" align="center" rowsep="1" /></row></thead><tbody valign="top"><row><entry /></row></tbody></tgroup><tgroup align="left" colsep="0" rowsep="0" cols="4"><colspec colname="1" colwidth="21PT" align="left" /><colspec colname="2" colwidth="49PT" align="left" /><colspec colname="3" colwidth="133PT" align="left" /><colspec colname="4" colwidth="77PT" align="left" /><tbody valign="top"><row><entry>I</entry><entry>The invalid</entry><entry>The data and tag info is invalid in the L2.</entry><entry>Power-On-Reset. Snoop</entry></row><row><entry /><entry>state.</entry><entry>This is the initial state of the L2.</entry><entry>invalidate from remote</entry></row><row><entry /><entry /><entry /><entry>(domain) device (rwitm,</entry></row><row><entry /><entry /><entry /><entry>dclaim, dcbz, dma_wr).</entry></row><row><entry>Ig</entry><entry>The invalid</entry><entry>The data is invalid but the tag info is valid</entry><entry>L2/L3 performs</entry></row><row><entry /><entry>global state.</entry><entry>in the L2. This state is a precise indication</entry><entry>modified intervention to</entry></row><row><entry /><entry /><entry>that this L2/L3 cache performed modified</entry><entry>a master outside the</entry></row><row><entry /><entry /><entry>intervention to an L2 outside this domain.</entry><entry>domain.</entry></row><row><entry /><entry /><entry>This state tracks the fact the line left this</entry></row><row><entry /><entry /><entry>domain and is responsible for indicating to</entry></row><row><entry /><entry /><entry>memory that the memory-domain bit needs</entry></row><row><entry /><entry /><entry>to be set to ‘global’.</entry></row><row><entry>In</entry><entry>The invalid</entry><entry>The data is invalid but the tag info is valid</entry><entry>L2/L3 performs</entry></row><row><entry /><entry>Node state.</entry><entry>in the L2/L3. This state is an imprecise</entry><entry>modified entervention to</entry></row><row><entry /><entry /><entry>indication that the L2/L3 cache either:</entry><entry>a master inside the</entry></row><row><entry /><entry /><entry>performed modified intervention to an</entry><entry>domain or detected a</entry></row><row><entry /><entry /><entry>L2/L3 inside this domain; or detected a</entry><entry>store-type op from a</entry></row><row><entry /><entry /><entry>store-type op by a master inside the</entry><entry>master inside the</entry></row><row><entry /><entry /><entry>domain. This state is a hint that the line is</entry><entry>domain).</entry></row><row><entry /><entry /><entry>still in this domain and the RC's next</entry></row><row><entry /><entry /><entry>request attempt for this line should be local.</entry></row><row><entry>S</entry><entry>The shared</entry><entry>The data and tag are valid. The cache line</entry><entry>Snoop read hit (SL)</entry></row><row><entry /><entry>state.</entry><entry>may also be valid in other L2/L3 caches. In</entry><entry>from within local MCM.</entry></row><row><entry /><entry /><entry>this state, the data cannot be sourced to</entry></row><row><entry /><entry /><entry>another off-chip L2/L3 via intervention(it</entry></row><row><entry /><entry /><entry>can however supply intervention data).</entry></row><row><entry>S_L</entry><entry>The shared</entry><entry>The data and tag are valid. The cache line</entry><entry>Core data-load or</entry></row><row><entry /><entry>state</entry><entry>may also be valid in other L2 caches. From</entry><entry>Instruction-fetch.</entry></row><row><entry /><entry>(source to</entry><entry>this state, the can be sourced to another</entry></row><row><entry /><entry>local).</entry><entry>L2/L3 (in this MCM only) via intervention.</entry></row><row><entry>Tn</entry><entry>The tagged</entry><entry>The data and tag are valid. The data is</entry><entry>Snoop read hit (M) from</entry></row><row><entry /><entry>node state.</entry><entry>modified, but was sourced by this cache to</entry><entry>master inside the</entry></row><row><entry /><entry /><entry>another master inside this domain (i.e. was</entry><entry>domain.</entry></row><row><entry /><entry /><entry>in the M state at sometime in the past, but</entry></row><row><entry /><entry /><entry>is not currently exclusively owned). From</entry></row><row><entry /><entry /><entry>this state, the data will not be sourced to</entry></row><row><entry /><entry /><entry>another L2/L3 via intervention until the</entry></row><row><entry /><entry /><entry>combined response is received and it is</entry></row><row><entry /><entry /><entry>determined that no other L2/L3 is sourcing</entry></row><row><entry /><entry /><entry>data (i.e. if no L2/L3's are found to be SL).</entry></row><row><entry /><entry /><entry>Castout of a Tn line requires invalidation of</entry></row><row><entry /><entry /><entry>the tag, updating memory with data.</entry></row><row><entry>Ten</entry><entry>The tagged</entry><entry>The data and tag are valid. The data has not</entry><entry>Snoop read hit (Me)</entry></row><row><entry /><entry>exclusive</entry><entry>been modified, but was sourced by this</entry><entry>from master inside this</entry></row><row><entry /><entry>node state.</entry><entry>cache to another master inside this domain</entry><entry>domain.</entry></row><row><entry /><entry /><entry>(i.e. was in the Me state at sometime in the</entry></row><row><entry /><entry /><entry>past, and a shared copy was sourced to</entry></row><row><entry /><entry /><entry>another cache). From this state, the data</entry></row><row><entry /><entry /><entry>will not be sourced to another L2 via</entry></row><row><entry /><entry /><entry>intervention until the combined response is</entry></row><row><entry /><entry /><entry>received and it is determined that no other</entry></row><row><entry /><entry /><entry>L2/L3 is sourcing data (i.e. if no L2/L3's</entry></row><row><entry /><entry /><entry>are found to be SL). Castout of a Ten line</entry></row><row><entry /><entry /><entry>only requires invalidation of the tag.</entry></row><row><entry>T</entry><entry>The tagged</entry><entry>The data and tag are valid. The data is</entry><entry>Snoop read hit (M) from</entry></row><row><entry /><entry>state.</entry><entry>modified, but was sourced by this cache to</entry><entry>master outside the</entry></row><row><entry /><entry /><entry>another master outside this domain (i.e.</entry><entry>domain.</entry></row><row><entry /><entry /><entry>was in the M state at sometime in the past,</entry></row><row><entry /><entry /><entry>but is not currently exclusively owned).</entry></row><row><entry /><entry /><entry>From this state, the data will not be sourced</entry></row><row><entry /><entry /><entry>to another L2 via intervention until the</entry></row><row><entry /><entry /><entry>combined response is received and it is</entry></row><row><entry /><entry /><entry>determined that no other L2/L3 is sourcing</entry></row><row><entry /><entry /><entry>data (i.e. if no L2/L3's are found to be SL).</entry></row><row><entry /><entry /><entry>Castout of a T line requires invalidation of</entry></row><row><entry /><entry /><entry>the tag, updating memory with data, and</entry></row><row><entry /><entry /><entry>indication to the MC that the memory-</entry></row><row><entry /><entry /><entry>domain bit should be set to ‘global’.</entry></row><row><entry>Te</entry><entry>The exclusive</entry><entry>The data and tag are valid. The data has not</entry><entry>Snoop read hit (Me)</entry></row><row><entry /><entry>tagged state.</entry><entry>been modified, but was sourced by this</entry><entry>from master outside this</entry></row><row><entry /><entry /><entry>cache to another master outside this domain</entry><entry>domain.</entry></row><row><entry /><entry /><entry>(i.e. was in the Me state at sometime in the</entry></row><row><entry /><entry /><entry>past, and a shared copy was sourced to</entry></row><row><entry /><entry /><entry>another cache). From this state, the data</entry></row><row><entry /><entry /><entry>will not be sourced to another L2 via</entry></row><row><entry /><entry /><entry>intervention until the combined response is</entry></row><row><entry /><entry /><entry>received and it is determined that no other</entry></row><row><entry /><entry /><entry>L2/L3 is sourcing data. Castout of a Te line</entry></row><row><entry /><entry /><entry>only requires invalidation of the tag and</entry></row><row><entry /><entry /><entry>indication to the MC that the memory-</entry></row><row><entry /><entry /><entry>domain bit should be set to ‘global’ (i.e.</entry></row><row><entry /><entry /><entry>data does not have to be castout to memory).</entry></row><row><entry>M</entry><entry>The modified</entry><entry>The data and tag are valid. The data has</entry><entry>Core data store.</entry></row><row><entry /><entry>state.</entry><entry>been modified and is exclusively owned.</entry></row><row><entry /><entry /><entry>The cache line cannot be valid in any other</entry></row><row><entry /><entry /><entry>L2. From this state, the data can be sourced</entry></row><row><entry /><entry /><entry>to another L2 (in the local MCM or a</entry></row><row><entry /><entry /><entry>remote MCM) via intervention.</entry></row><row><entry>Me</entry><entry>The modified</entry><entry>The data and tag are valid. The data is not</entry><entry>LPC sources data and no</entry></row><row><entry /><entry>‘exclusive’</entry><entry>considered modified but is exclusive to this</entry><entry>other caches are Shared.</entry></row><row><entry /><entry>state.</entry><entry>L2. The cache line cannot be valid in any</entry></row><row><entry /><entry /><entry>other L2. Castout of an Me line only</entry></row><row><entry /><entry /><entry>requires invalidation of the tag(i.e. data</entry></row><row><entry /><entry /><entry>does not have to be castout to memory).</entry></row><row><entry>Mu</entry><entry>The</entry><entry>The data and tag are valid. The data is</entry><entry>L2 or L3 is M and fabric</entry></row><row><entry /><entry>‘unsolicited’</entry><entry>considered to have been modified and is</entry><entry>command type is a</entry></row><row><entry /><entry>modified state.</entry><entry>exclusively owned. The cache line cannot</entry><entry>Rd(go_Mx)</entry></row><row><entry /><entry /><entry>be valid in any other L2.</entry></row><row><entry namest="1" nameend="4" align="center" rowsep="1" /></row></tbody></tgroup></table></tables>

0037In accordance with the present invention, storage of domain indicators in cache memory, such as L2 caches <b>230</b>, can also be enhanced. In particular, in the embodiment of data processing system <b>100</b> described with reference to <figref idref="DRAWINGS">FIG. 1</figref>, domain indicators are received by L2/L3 caches <b>230</b> in conjunction with the associated memory blocks and may optionally be stored with the memory blocks in cache arrays <b>300</b>. While this arrangement permits a simplified data flow for domain indicators, when a first L2 cache <b>230</b> responds to a bus RWITM operation of a second L2 cache <b>230</b> residing in a different coherency domain by supplying the requested memory block, no “global” indicator remains cached in the local coherency domain. Thus, the LPC must be accessed to determine whether or not the memory block is known to be cached, if at all, only locally. Consequently, if an HPC for a memory block receives a bus RWITM operation from a requester in a remote coherency domain, the system responds with a retry-push including a cache castout of the requested memory block and retry of the bus RWITM operation. As will be appreciated, it would be preferable to eliminate the latency and bandwidth utilization associated with retry-push responses.

0038To reduce access latency to a domain indication in cases in which no copy of a memory block remains cached in a coherency domain, an additional cache state, referred to herein as Ig (Invalid global), is provided. The Ig state is defined herein as a cache coherency state indicating (1) the associated memory block in the cache array is invalid, (2) the address tag in the cache directory is valid, and (3) a copy of the memory block identified by the address tag may possibly be cached in another coherency domain.

0039The Ig state is formed in a lower level cache in response to that cache providing a requested memory block to a requestor in another coherency domain in response to an exclusive access request (e.g., a bus RWITM or bus DClaim operation). It may be preferable to form the Ig state only in the coherency domain containing the LPC for the memory block. In such embodiments, some mechanism (e.g., a partial response by the LPC and subsequent combined response) must be implemented to indicate to the cache sourcing the requested memory block that the LPC is within its local coherency domain. In other embodiments that do not support the communication of an indication that the LPC is local, an Ig state may be formed any time that a cache sources a memory block to a remote coherency domain in response to an exclusive access request.

0040Because cache directory entries including an Ig state carry potentially useful information, it is desirable in at least some implementations to preferentially retain entries in the Ig state over entries in the I state (e.g., by modifying the Least Recently Used (LRU) algorithm utilized to evaluate LRU field <b>308</b> to select a victim cache entry for replacement). As Ig directory entries are retained in cache, it is possible for some Ig entries to become “stale” over time in that a cache whose exclusive access request caused the formation of the Ig state may deallocate or writeback its copy of the memory block without notification to the cache holding the address tag of the memory block in the Ig state. In such cases, the “stale” Ig state, which incorrectly indicates that a global operation should be issued instead of a local operation, will not cause any coherency errors, but will merely cause some operations, which could otherwise be serviced utilizing a local operation, to be issued as global operations. Occurrences of such inefficiencies will be limited in duration by the eventual replacement of the “stale” Ig cache entries.

0041Several rules govern the selection and replacement of Ig cache entries. First, if a cache selects an Ig entry as the victim for replacement, a castout of the Ig entry is performed (unlike the case when an I entry is selected). Second, if a request that causes a memory block to be loaded into a cache hits on an Ig cache entry in that same cache, the cache treats the Ig hit as a cache miss and performs a castout operation with an Ig entry as the selected victim. The cache thus avoids placing two copies of the same address tag in the cache directory. Third, the castout of the Ig state is preferably performed as a local operation, or if performed as a global operation, ignored by a remote LPC of the castout address. If an Ig entry is permitted to form in a cache that is not within the same coherency domain as the LPC for the memory block, no update to the domain indicator in the LPC is required. Fourth, the castout of the Ig state is preferably performed as a dataless address-only operation in which the domain indicator is written back to the LPC (if local to the cache performing the castout).

0042Implementation of an Ig state improves communication efficiency by maintaining a cached domain indicator for a memory block in a coherency domain even when no valid copy of the memory block remains cached in the coherency domain. As a consequence, an HPC for a memory block can service an exclusive access request (e.g., a bus RWITM or bus DClaim operation) from a remote coherency domain without retrying the request and performing a push of the requested memory block to the LPC.

0043With reference now to <figref idref="DRAWINGS">FIG. 5</figref>, there is illustrated a high-level logical flow diagram of an exemplary method of performing cast-in to the L3 cache in accordance with the preferred embodiment of the present invention. The process depicted in <figref idref="DRAWINGS">FIG. 5</figref> involves operations by the L3 cache controller <b>109</b>. The process begins at step <b>502</b> when the L3 cache controller <b>109</b> receives a write back request from one of the L2 caches <b>230</b> within PU <b>104</b> as a result of a cache line being evicted from the L2 cache. Because L3 cache <b>105</b> is shared among all processing units <b>104</b> within processing node <b>102</b>, a castout from any of those L2 caches <b>230</b> would be received as a write-back request at the L3 cache controller <b>109</b>. The write-back request received will contain a cache directory state of the cache line being cast-in to the L3 cache. L3 cache controller <b>109</b> is programmed with a replacement policy to determine whether the cache line will be saved in the L3 cache array and the coherency state for the memory block in state field <b>306</b>.

0044At step <b>504</b>, cache controller <b>109</b> checks the L3 tag field <b>304</b> to determine if a directory entry is already present for the cast-in memory block. If the cache line address match is a miss in tag field <b>304</b>, a victim is chosen within the L3 cache directory <b>302</b> and potentially is cast-out to memory, depending upon the victim's coherency state (e.g. Ig, Tx, Mx. As used herein, a class of Modified states is represented as a “Mx” variable, where Mx represents any one of M, Me, Mu. The four Tagged cache coherency states (i.e., T, Te, Ten, Tn) are represented as a “Tx” variable). The cache controller <b>109</b> stores the cache line in L3 cache array <b>300</b> and sets the state field <b>306</b> to the directory state received in the write-back request from the L2 cache <b>230</b>. The process then proceeds to step <b>506</b> where L3 cache controller <b>109</b> stores the cache line in L3 cache array <b>300</b> and creates a corresponding cache directory entry within cache directory <b>302</b> as indicated by LRU field <b>308</b> by utilizing a least-recently used (LRU) or other replacement algorithm to store the cache line within its congruence class. L3 cache controller <b>109</b> also performs a cast-out of a victimized cache line from the L3 cache <b>105</b>, if necessary. Thereafter, the process ends at step <b>508</b>.

0045Returning to step <b>504</b>, if there is a directory entry for the cast-in memory block within the L3 cache directory <b>302</b>, the process proceeds to step <b>510</b>, where the L3 cache controller <b>109</b> updates the L3 cache array and directory <b>302</b> with the cast-in cache line in accordance with a L3 cache replacement policy, as described below in accordance with the preferred embodiment of the present invention. As implemented in a preferred embodiment of the present invention, the L3 cache replacement policy specifies (1) whether the cast-in cache line is stored within the L3 cache array <b>300</b> or is discarded, and (2) the state in which the L3 cache directory state field <b>306</b> is set in response to the write back request. A detailed description of the L3 cache replacement policy is provided below in conjunction with the process illustrated in <figref idref="DRAWINGS">FIG. 6</figref>.

0046The cache coherency replacement policy of a preferred embodiment used by L3 cache <b>105</b> when performing a cast-in on a cache line currently present within the L3 cache is summarized in Table III below. <tables id="TABLE-US-00003" num="3"><table frame="none" colsep="0" rowsep="0"><tgroup align="left" colsep="0" rowsep="0" cols="2"><colspec colname="OFFSET" colwidth="70PT" align="left" /><colspec colname="1" colwidth="147PT" align="center" /><thead><row><entry /><entry namest="OFFSET" nameend="1" align="center">TABLE III</entry></row></thead><tbody valign="top"><row><entry /><entry /></row><row><entry /><entry namest="OFFSET" nameend="1" align="center" rowsep="1" /></row><row><entry /><entry>L3 CurrentState</entry></row></tbody></tgroup><tgroup align="left" colsep="0" rowsep="0" cols="8"><colspec colname="1" colwidth="70PT" align="left" /><colspec colname="2" colwidth="21PT" align="left" /><colspec colname="3" colwidth="21PT" align="left" /><colspec colname="4" colwidth="21PT" align="left" /><colspec colname="5" colwidth="21PT" align="left" /><colspec colname="6" colwidth="21PT" align="left" /><colspec colname="7" colwidth="21PT" align="left" /><colspec colname="8" colwidth="21PT" align="left" /><tbody valign="top"><row><entry>L3CI (state)</entry><entry>In</entry><entry>Ig</entry><entry>I</entry><entry>S</entry><entry>Sl</entry><entry>Tx</entry><entry>Mx</entry></row><row><entry namest="1" nameend="8" align="center" rowsep="1" /></row><row><entry>In</entry><entry>In</entry><entry>Ig</entry><entry>In</entry><entry>S</entry><entry>Sl</entry><entry>Tx</entry><entry>Mx</entry></row><row><entry>Ig</entry><entry>Ig</entry><entry>Ig</entry><entry>Ig</entry><entry>Ig</entry><entry>Ig</entry><entry>Tx</entry><entry>Mx</entry></row><row><entry>I</entry><entry>In</entry><entry>Ig</entry><entry>I</entry><entry>Sx</entry><entry>Sx</entry><entry>Tx</entry><entry>Mx</entry></row><row><entry>S</entry><entry><u style="single">S</u></entry><entry>Ig</entry><entry><u style="single">S</u></entry><entry>S</entry><entry>Sl</entry><entry>Tx</entry><entry>err</entry></row><row><entry>Sl</entry><entry><u style="single">Sl</u></entry><entry>Ig</entry><entry><u style="single">Sl</u></entry><entry>Sl</entry><entry>err</entry><entry>Tx</entry><entry>err</entry></row><row><entry>Tx→T, Te, Ten, Tn</entry><entry><u style="single">Tx</u></entry><entry><u style="single">Tx</u></entry><entry><u style="single">Tx</u></entry><entry>Tx</entry><entry>Tx</entry><entry>err</entry><entry>err</entry></row><row><entry>Mx→M, Me, Mu</entry><entry><u style="single">Mx</u></entry><entry><u style="single">Mx</u></entry><entry><u style="single">Mx</u></entry><entry>err</entry><entry>err</entry><entry>err</entry><entry>err</entry></row><row><entry namest="1" nameend="8" align="center" rowsep="1" /></row></tbody></tgroup></table></tables>

0047Table III provides the L3 cast-in state transition for a cache line cast-in to the L3 cache when the memory block being castout from the L2 is already tagged in the L3. Table III identifies the resulting coherency state to be stored in state field <b>306</b> as a function of the cache line's current state within the L3 directory and the coherency state of the cache line in the L2 cache performing the castout. The top row of Table III indicates the current coherency directory state (L3 CurrentState) as indicated in state field <b>306</b> for a cache line tagged within L3. The left column of Table III identifies the coherency state (L3CI (state)) of the cache line being cast-in to the L3 cache from L2 cache. The resulting coherency state overwrites state field <b>306</b> for the cache line upon being cast into L3 cache.

0048This cache coherency replacement policy further dictates whether the memory block stored within the L3 cache array <b>300</b> is to remain at its current value or is to be overwritten by the cast-in cache line value from the L2 cache. The overwrite policy is represented by each underlined resulting coherency state in Table III (e.g. Mx). If the resulting coherency state transition is underlined, the cast-in cache line is stored in L3 cache array <b>300</b>. If the resulting coherency state is not underlined, the cache line remains unmodified within the L3 cache array <b>300</b> at its existing value (i.e., existing value is coherent), while the cache line's coherency state in field <b>306</b> is transitioned to the resulting coherency state identified in Table III.

0049An alternative view of the replacement policy defined by Table III is represented by the following Coherency State Transition Rule, which specifies when the coherency state currently held in L3 cache directory <b>302</b> is overwritten by a cast-in coherency state: <br />(Mx|Tx)→Ig→Sl→S→In→I

0050The Coherency State Transition Rule defines a hierarchy of coherency states, where Mx|Tx is at the highest level and each arrow indicates a next-lower level of coherency. This general rule specifies that if the cast-in coherency state is higher within this hierarchy than the current state in the L3 cache directory, the cast-in state will overwrite the current entry. Correspondingly, if the current state in the L3 directory is higher than the cast-in coherency state, the current state is not overwritten and is maintained in its current state.

0051With reference back to Table III, the bottom row of Table III indicates the cast-in coherency state of the cache line is a Modified (M) state (i.e. M, Me, Mu). This class of M states is represented as a “Mx” variable, where Mx represents any one of M, Me, Mu. The Tx row within Table III represents an L3 cast-in state of any of the four Tagged cache coherency states (i.e., T, Te, Ten, Tn).

0052As seen in Table III, if the L3 current state for the cache line hitting in the L3 is In, Ig, or I, the Mx state or Tx state of the L3 cast-in cache line will be stored in the state field <b>306</b> of the L3 cache directory <b>302</b> in place of the current state for the cast-in cache line. Further, because the cast-in cache line has been modified by one of the processing units <b>104</b>, the cache line being cast out from the L2 cache array must be stored into the L3 cache array <b>300</b>. This action is represented by an underline under each of the directory cache states (i.e., Mx) shown in the last two rows of Table III. Note that the last four columns of the Mx row and the last two columns of the Tx row indicate that an error (err) has occurred, since these are invalid concurrent states for the same cache line in both the L2 and L3 under the coherency protocol. For example, if the current state of the L3 cache indicates the cache line is shared (S), it is impossible for the L2 cache to be casting out the same cache line in a modified (M) state. Accordingly, the “S” column of Table III indicates an error within the Mx row.

0053Referring now to the “S” and “Sl” rows of Table III, if the L3 cast-in state is set to Sx (i.e., S or Sl) and the current state of the cache line in the L3 cache is either the In or I states, the shared state indicated by Sx should be set in the L3 cache, since the data and tag are valid within the L2 cache casting out the data. Also, as indicated by the underlined entries in Table III, the cache line is replaced with the cast-in data within the cache array <b>300</b>. Here the data and tag are both valid being cast in from the L2 and so the state and data (as shown by the underline) are stored into the L3, since the L3 indicates the cache line is invalid. In contrast, if the L3 indicates Ig current state, the L2/L3 caches have performed modified intervention to an L2 outside the domain, and thus the data may be invalid. Consequently, the current state of the directory needs to remain Ig and the data is not stored to L3 cache. Although this may create inefficiencies in that the shared data being cast in from the L2 may potentially still be valid, the potential cache management issues outweigh the advantages of maintaining the state data. If both the cast-in and current states are both S, the current state remains S and the cache array is not updated. If the cast-in state is S and the current state is Sl or if the cast-in state is Sl and the current state is S, the cache coherency state is remains is replaced with Sl, which adds additional information to the shared state. Note that both the L2 and L3 caches cannot both contain a cache line in the Si state, so if both the cast-in and current state are set to Si, an error has occurred. If the L3 current state is Tx as shown in the Tx column, this information is always retained within the L3 cache upon a cast-in from an L2. This cache state indicates that the L3 cache is holding data and tag as valid and that the data has been modified.

0054With reference now to the “I” row of Table III, the current states within the L2 provide additional or the same information as the I state being cast in, and therefore no state is replaced in the L3 cache directory. With reference to the In, Ig and I rows of Table III, the L3 cache array <b>300</b> is never updated with a cast-in having the Ix state, as the cache line data is always invalid.

0055With reference now to the Ig row of Table III, the L3 current state of the cast-in cache line is replaced with the L3 cast-in state of Ig for each of the 1× and Sx L3 current coherency states. This follows because control of the cache line has been sent outside the domain, and therefore the invalid and/or shared state in the L3 is out-of-date. Conversely, when the L3's current state indicates it holds a modified version of the cache line, as indicated by the Tx or Mx states, the cast-in Ig state is discarded and the L3 current state remains unchanged.

0056With reference now to the In row in Table III, the only situation where the In cast-in coherency state is used to replace the current coherency state of the cache line in the L3 is when the current state in the L3 is shown as invalid (I). This is because the In state adds the additional imprecise indication that the L2/L3 cache either performed modified intervention to an L2 inside this domain or it detected a store-type operation by a master inside the domain. This state is a hint that the line is still in the domain. The remaining current states in the In row provide equal or additional information regarding the current state of the cache line in the domain, and are therefore maintained and not replaced by the cast-in state from the L2 cache.

0057With reference now to <figref idref="DRAWINGS">FIG. 6</figref>, there is illustrated a high-level logical flow diagram of an exemplary method of a coherency state transition policy implemented by the L3 cache in response to a cast-in, in accordance with a preferred embodiment of the present invention. The process for implementing the coherency state transition policy of the L3 cache begins at step <b>602</b> when a victim cache line address hits in the L3 cache directory <b>302</b> upon cast-in from the L2 cache <b>230</b>. The process proceeds to step <b>604</b> where the L3 cache controller <b>109</b> determines the cache coherency state of the victim cache line in the L2 cache specified in the write-back request received from the L2 cache <b>230</b>. At step <b>606</b>, the L3 cache controller <b>109</b> reads the cache coherency state in state field <b>306</b> upon a cache line address hit in the L3 tag field <b>304</b>. The process then proceeds to step <b>608</b> where the L3 cache controller <b>109</b> determines the coherency state transition policy for the cast-in cache line in the L3 cache directory <b>302</b>. This determination is based on the policy specified by Table III and is implemented by L3 cache controller <b>109</b> by a look-up function into a state table implementing Table III in non-volatile memory accessible by the L3 cache controller <b>109</b>, for example by read-only memory (ROM) within the L3 cache <b>105</b>. In alternative embodiments, L3 cache controller <b>109</b> algorithmically implements the Coherency State Transition Rule specified above by software functionality, for example, or through other hardware circuitry implementation.

0058Thereafter, the process proceeds to step <b>610</b> where L3 cache controller <b>109</b> determines if the current coherency state for the victim cache line will be overwritten in the L3 cache directory <b>302</b> based on the replacement policy determined at step <b>608</b>. If the current state is to be overwritten, the process proceeds to step <b>612</b>, which represents cache controller <b>109</b> overwriting the cache coherency state of the cast-in cache line with the coherency state specified by the cast-in request. The process proceeds from step <b>612</b>, or from step <b>610</b> if the current state is not to be overwritten, to decision block <b>614</b>, where cache controller <b>109</b> determines if the cast-in cache line received from the L2 cache <b>230</b> shall be stored in the L3 cache array <b>300</b>. If the replacement policy determined at step <b>608</b> specifies that the cast-in cache line should be stored in the L3, the process proceeds to step <b>616</b> where cache controller <b>109</b> stores the cast-in cache line in the L3 cache array <b>300</b>, thereby overwriting the previously stored cache line data for the cast-in cache line address. Following step <b>616</b>, or step <b>614</b> if the L3 cache array is not to store the cast-in cache line, the process ends at step <b>618</b>.

0059While the invention has been particularly shown and described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention. For example, the present invention may be implemented using any combination of computer programming software, firmware or hardware.