Method of manufacturing wiring substrate and method of manufacturing electronic component mounting structure

CROSS-REFERENCE TO RELATED APPLICATIONS

0001This application is based on and claims priority of Japanese Patent Application No. 2005-353562 filed on Dec. 7, 2005, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

00021. Field of the Invention

0003The present invention relates to a method of manufacturing a wiring substrate and a method of manufacturing an electronic component mounting structure. More specifically, the present invention relates to a method of manufacturing a wiring substrate applicable to a mounting substrate for an electronic component, and to a method of manufacturing an electronic component mounting structure for mounting an electronic component on the wiring substrate.

00042. Description of the Related Art

0005As a wiring substrate for mounting an electronic component, there has heretofore been a method of obtaining a wiring substrate by forming a desired wiring layer on a temporary substrate in a detachable manner and then detaching the wiring layer from the temporary substrate. Patent Literature 1 (Japanese Unexamined Patent Publication No. 2005-236244) discloses a method of obtaining a wiring substrate, which includes the steps of: forming a copper foil on a resin substrate while attaching only a peripheral side thereof by using an adhesive layer; forming a build-up wiring layer thereon; and thereafter separating the copper foil and the build-up wiring layer from the resin substrate by cutting out an inside portion of the resin substrate, the portion being inward from the adhesive layer.

0006Meanwhile, Patent Literature 2 (Japanese Unexamined Patent Publication No. 2004-87701) discloses a method of obtaining a wiring substrate, which includes the steps of: attaching a releasing film and a metal base onto the carrier plate by using an adhesive layer, the releasing film being smaller than a carrier plate, and the metal base having the same size as the carrier plate; forming a metal pad on the metal base; and thereafter, separating the metal base from the releasing film and the carrier plate by cutting out a peripheral portion of the releasing film of the wiring substrate.

0007Moreover, Patent Literature 3 (Japanese Unexamined Patent Publication No. 2004-235323) discloses a method of obtaining a wiring substrate, which includes the steps of: laminating a first metal layer and a second metal layer on a core substrate in a way that a position of an outer periphery of the first layer is located more inward than a position of an outer periphery of the second metal layer, and attaching both layers by use of an adhesive film; forming a build-up wiring layer on the second metal layer; and thereafter, separating the second metal layer and the build-up wiring layer from the first metal layer and the core substrate by cutting out a peripheral portion of the first metal layer of the wiring substrate.

0008Furthermore, Patent Literature 4 (Japanese Unexamined Patent Publication No. 2005-63987) discloses a method of obtaining a wiring substrate, which includes the steps of: forming a first dielectric sheet and a second dielectric sheet, located in a way that the second dielectric sheet wraps the first dielectric sheet, on a substrate provided with a groundwork dielectric sheet on an upper side; forming a wiring layer thereon; and thereafter by cutting out an outer peripheral portion of the first dielectric sheet of the wiring substrate, and thus separating the first dielectric sheet from the substrate provided with the groundwork dielectric sheet.

0009However, the techniques according to the above-described Patent Literatures 1 to 3 require a step of attaching a metal thin film or the metal base onto a variety of temporary substrates by use of the adhesive layer in a detachable state. Accordingly, this step may be complicated, and may cause a cost increase.

SUMMARY OF THE INVENTION

0010An object of the present invention is to provide a method of manufacturing a wiring substrate which can be manufactured at low costs without causing any troubles, in a method of manufacturing a wiring substrate in which after a desired wiring layer is formed on a temporary substrate in a detachable state, a wiring substrate is obtained by separating the wiring layer from the temporary substrate. And an object of the present invention is to provide a method of manufacturing an electronic component mounting structure for mounting an electronic component easily on the wiring substrate.

0011A method of manufacturing a wiring substrate according to the present invention includes the steps of: obtaining a temporary substrate from a prepreg, and concurrently attaching a metal foil onto at least one surface of the temporary substrate, by disposing the metal foil on a prepreg through a underlying layer interposed between them, in a way that the underlying layer is disposed in a wiring formation region on the prepreg, and the metal foil having a size larger than that of the underlying layer is caused to contact with an outer peripheral portion of the wiring formation region, and then by hardening the prepreg with heating and pressurization; forming a build-up wiring layer on the metal foil; and obtaining a wiring member in which the build-up wiring layer is formed on the metal foil, by cutting out a portion of structure in which the underlying layer, the metal foil and the build-up wiring layer are formed on the temporary substrate, the portion corresponding to a peripheral portion of the underlying layer, and thus by separating the metal foil from the temporary substrate.

0012In the present invention, first, a semi-hardened prepreg is prepared, and the underlying layer (a metal foil, a releasing film or a releasing agent) is disposed in the wiring formation region on the prepreg. Then, the metal foil is disposed on the prepreg while interposing the underlying layer between them such that the metal foil of which size is a one size larger than the underlying layer is caused to contact with the outer peripheral portion of the wiring formation region of the prepreg.

0013Thereafter, the temporary substrate is obtained to harden the prepreg by heating and pressurizing the prepreg, the underlying layer and the metal foil. At the same time, the metal foil is partially attached onto the temporary substrate while interposing the underlying layer between them. Here, in a case where the underlying layer is the metal foil, the two metal foils simply contact with each other in the region where the metal foils overlap each other.

0014Subsequently, the desired build-up wiring layer is formed on the metal foil. Moreover, the structure in which the underlying layer, the metal foil, and the build-up wiring layer are formed on the temporary substrate, is cut out at the portion corresponding to the peripheral portion of the underlying layer. Thus, a region where the underlying layer and the metal foil overlap each other is obtained, and the underlying layer and the metal foil can be easily separated. In a case where the release agent is used as the underlying layer, the metal foil in which the release agent is formed is separated from the temporary substrate.

0015In this way, the wiring member in which the build-up wiring layer is formed on the metal foil is obtained. According to the present invention, it is possible to easily form the structure in which the underlying layer and the peripheral portion of the metal foil are attached onto the temporary substrate by hardening the prepreg having an adhesive function without providing an adhesive layer in particular. For this reason, it is possible to simplify the step of attaching the underlying layer and the metal foil to the temporary substrate, and to reduce manufacturing costs of the wiring substrate having no core substrate.

0016In one preferred mode of the present invention, the metal foil is removed after obtaining the wiring member, and the lowermost layer of the build-up wiring layer is exposed. Moreover, one of the uppermost layer and the lowermost layer of the build-up wiring layer constitutes an internal connection pad for mounting an electronic component, and the wiring layer on the opposite side constitutes an external connection pad.

0017Meanwhile, in a preferred mode in which an electronic component is mounted on the wiring substrate of the present invention, after obtaining the wiring member by separating the metal foil and the build-up layer thereon from the underlying layer, an electronic component is mounted on an upper surface of the wiring member while leaving the metal foil on a lower surface. Thereafter, the metal foil is removed from the wiring member to expose the lowermost wiring layer, which is used as the external connection pad. Since the metal foil functions as a reinforcing member, it becomes easy to convey or handle the wiring substrate without receiving an influence of warp rather than a case of mounting the electronic component after removing the metal foil. In this way, it is possible to mount the electronic component with high reliability.

0018Alternatively, the electronic component is mounted after the underlying layer, the metal foil and the build-up wiring layer are formed on the temporary substrate, and then the underlying layer is separated from the metal foil by cutting out the structure. In a case of this mode as well, the electronic component is mounted while the temporary substrate is present. Accordingly, it is possible to mount the electronic component with high reliability without receiving an influence of warp as similar to the above-described mode.

0019As described above, according to the present invention, it is possible to manufacture a wiring substrate having no core substrate without causing any troubles.

BRIEF DESCRIPTION OF THE DRAWINGS

0020<figref idref="DRAWINGS">FIGS. 1A</figref> to <b>1</b>L are cross-sectional views showing a method of manufacturing a wiring substrate according to a first embodiment of the present invention.

0021<figref idref="DRAWINGS">FIGS. 2A</figref> to <b>2</b>F are cross-sectional views showing a method of manufacturing an electronic component mounting structure according to a second embodiment of the present invention.

0022<figref idref="DRAWINGS">FIGS. 3A</figref> to <b>3</b>D are cross-sectional views showing a method of manufacturing an electronic component mounting structure according to a variation of the second embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

0023Hereinafter, embodiments of the present invention will be described below with reference to the accompanying drawings.

First Embodiment

0024<figref idref="DRAWINGS">FIGS. 1A</figref> to <b>1</b>L are cross-sectional views sequentially showing a method of manufacturing a wiring substrate according to a first embodiment of the present invention.

0025As shown in <figref idref="DRAWINGS">FIG. 1A</figref>, first, a prepreg <b>10</b><i>a </i>which is composed by impregnating a glass cloth (a woven fabric), a nonwoven glass fabric, aramide fibers or the like with resin such as epoxy resin is prepared. The prepreg <b>10</b><i>a </i>of the B-stage (in a semi-hardened state) is used hereto.

0026Wiring formation regions A and outer peripheral portions B on the outside of the wiring formation regions A are defined on both surfaces of the prepreg <b>10</b><i>a</i>. The wiring formation regions A may be defined one by one on the respective surfaces of the prepreg <b>10</b><i>a </i>or a plurality of regions may be defined thereon.

0027Thereafter, as shown in <figref idref="DRAWINGS">FIG. 1B</figref>, underlying layers <b>12</b><i>a </i>and copper foils <b>12</b><i>b </i>(metal foils) having a thickness in a range of 12 to 18 μm are prepared. As the underlying layer <b>12</b><i>a</i>, a metal foil such as a copper foil, a releasing film or a releasing agent is used. As the releasing film, laminated film formed by laminating a thin fluorocarbon resin (PTFE) layer on a polyester or polyethylene terephthalate (PET) film, or a polyester or PET film of which surface is subjected to silicone detachable processing is used. Meanwhile, as the release agent, a silicon-type release agent or a fluorine-type release agent is used.

0028Each of the underlying layer <b>12</b><i>a </i>is formed into the same size as that of the wiring formation region A on the prepreg <b>10</b><i>a</i>. Meanwhile, each of the copper foils <b>12</b><i>b </i>is formed with a size sufficient for covering the wiring formation region A and the outer peripheral region B on the prepreg <b>10</b><i>a</i>, and a size of the copper foils <b>12</b><i>b </i>is set to be a one size larger than that of the underlying layer <b>12</b><i>a. </i>

0029Then, underlying layers <b>12</b><i>a </i>and the copper foils <b>12</b><i>b </i>are disposed on the both surfaces side of the prepreg <b>10</b><i>a </i>from the bottom sequentially. The underlying layers <b>12</b><i>a </i>are disposed so as to respectively correspond to the wiring formation regions A on the prepreg <b>10</b><i>a</i>. The copper foils <b>12</b><i>b </i>are respectively superposed on the underlying layers <b>12</b><i>a</i>, and the peripheral portions thereof are disposed so as to contact with the outer peripheral portions B on the outer periphery of the wiring formation regions A on the prepreg <b>10</b><i>a</i>. Thereafter, the prepreg <b>10</b><i>a</i>, the underlying layers <b>12</b><i>a</i>, and the copper foils <b>12</b><i>b </i>are heated and pressurized from the both surfaces side at a temperature in a range of 190° C. to 200° C. in a vacuum atmosphere. In this way, as shown in <figref idref="DRAWINGS">FIG. 1C</figref>, the prepreg <b>10</b><i>a </i>is hardened, and a temporary substrate <b>10</b> made of glass epoxy resin or the like is obtained. Concurrently, the underlying layers <b>12</b><i>a </i>and the copper foils <b>12</b><i>b </i>are attached to the both surfaces of the temporary substrate <b>10</b> with hardening of the prepreg <b>10</b><i>a</i>. A whole of the underlying layers <b>12</b><i>a </i>is attached to the temporary substrate <b>10</b>. Meanwhile, the peripheral portion of the copper foils <b>12</b><i>b </i>is partially attached to the outer peripheral portion B of the wiring formation region A on the temporary substrate <b>10</b>. In a region where the underlying layer <b>12</b><i>a </i>and the copper foil <b>12</b><i>b </i>overlap each other, both of the constituents simply contact with each other. Accordingly, it is possible to easily separate the underlying layer <b>12</b><i>a </i>from the copper foil <b>12</b><i>b </i>in the above-mentioned region as will be described later.

0030In a case where the release agent is used as the underlying layer <b>12</b><i>a</i>, the release agent as described above is formed by coating or spraying on a region of a lower surface side of the copper foil <b>12</b><i>b</i>, where the underlying layer <b>12</b><i>a </i>is disposed. Then, the copper foil <b>12</b><i>b </i>is disposed on the prepreg <b>10</b><i>a </i>while interposing the release agent between them, and is attached to the prepreg <b>10</b><i>a </i>by heating and pressurizing. Thus, it is possible to separate the copper foil <b>12</b><i>b </i>from the temporary substrate <b>10</b> easily at the portion where the release agent (the underlying layer <b>12</b><i>a</i>) is provided.

0031As described above, in this embodiment, it is possible to obtain a structure in which the underlying layers <b>12</b><i>a </i>and the copper foils <b>12</b><i>b </i>are attached onto the temporary substrate <b>10</b> by disposing the underlying layers <b>12</b><i>a </i>and the copper foils <b>12</b><i>b </i>on the prepreg <b>10</b><i>a</i>, and by heating and pressurizing these constituents without using an adhesive in particular. Hence, it is possible to curtail a material cost for an adhesive, and to simplify the step of attaching the underlying layers <b>12</b><i>a </i>and the copper foils <b>12</b><i>b </i>to the temporary substrate <b>10</b>, thereby manufacturing time can be shortened. In this way, it is possible to reduce manufacturing costs.

0032Subsequently, as shown in <figref idref="DRAWINGS">FIG. 1D</figref>, plating resist films <b>16</b> provided with openings <b>16</b><i>x </i>at desired portions are formed on the both surfaces side of the temporary substrate <b>10</b>. Moreover, first wiring layers <b>18</b> made of gold (Au), nickel (Ni), tin (Sn) or the like are formed in the openings <b>16</b><i>x </i>of the plating resist films <b>16</b> by electrolytic plating while using the copper foils <b>12</b><i>b </i>as plating power-supply layers. Thereafter, as shown in <figref idref="DRAWINGS">FIG. 1E</figref>, the plating resist films <b>16</b> are removed. The first wiring layers <b>18</b> function as internal connection pads C<b>1</b> as described later.

0033Subsequently, As shown in <figref idref="DRAWINGS">FIG. 1F</figref>, first insulating layers <b>20</b> for covering the first wiring layers <b>18</b> and the copper foils <b>12</b><i>b </i>are formed on the both surfaces side of the temporary substrate <b>10</b> respectively. As the material of the first insulating layers <b>20</b>, an epoxy resin, a polyimide resin or the like is used. In an example of a method of forming the first insulating layers <b>20</b>, the first insulating layers <b>20</b> are obtained by laminating resin films respectively on the both surfaces side of the temporary substrate <b>10</b>, and thereafter, hardening the resin films by a heat treatment at a temperature in a range from 130° C. to 150° C. while pressing (pressurizing) the resin films.

0034Subsequently, as shown in <figref idref="DRAWINGS">FIG. 1F</figref> again, the first insulating layers <b>20</b> are processed with a laser or the like so as to expose the first wiring layers <b>18</b> on the both surfaces side of the temporary substrate <b>10</b>, thereby forming first via holes <b>20</b><i>x </i>respectively.

0035Here, the first insulating layers <b>20</b> may be formed by patterning a photosensitive resin film by means of photolithography, or by patterning resin films provided with openings by means of screen printing.

0036Subsequently, as shown in <figref idref="DRAWINGS">FIG. 1G</figref>, second wiring layers <b>18</b><i>a </i>made of copper (Cu) or the like, which are connected to the first wiring layers <b>18</b> through the first via holes <b>20</b><i>x</i>, are formed on the first insulating layers <b>20</b> respectively. The second wiring layers <b>18</b><i>a </i>are formed by a semi-additive method, for example. To be more precise, first, Cu seed layers (not shown) are formed inside the first via holes <b>20</b><i>x </i>and on the first insulating layers <b>20</b> by means of electroless plating, or by a sputtering method. Thereafter, resist films (not shown) having openings corresponding to the second wiring layers <b>18</b><i>a </i>are formed thereon. Subsequently, Cu layer patterns (not shown) are formed in the openings of the resist films by means of electrolytic plating while using the Cu seed layers as plating power-supply layer. Subsequently, the resist layers are removed and then the second wiring layers <b>18</b><i>a </i>are obtained by etching the Cu seed layers while using the Cu layer patterns as masks. In addition to the aforementioned semi-additive method, it is possible to employ various other wire forming methods such as a subtractive method as the method of forming the second wiring layers <b>18</b><i>a. </i>

0037Then, as shown in <figref idref="DRAWINGS">FIG. 1H</figref>, second insulating layers <b>20</b><i>a </i>for covering the second wiring layers <b>18</b><i>a </i>are respectively formed on the both surfaces side of the temporary substrate <b>10</b> by repeating similar processes, and then second via holes <b>20</b><i>y </i>are respectively formed in portions on the second insulating layers <b>20</b><i>a </i>on the second wiring layers <b>18</b><i>a</i>. Furthermore, third wiring layers <b>18</b><i>b </i>to be connected to the second wiring layers <b>18</b><i>a </i>through the second via holes <b>20</b><i>y </i>are formed respectively on the second insulating layers <b>20</b><i>a </i>on the both surfaces side of the temporary substrate <b>10</b>.

0038Subsequently, as shown in <figref idref="DRAWINGS">FIG. 1I</figref>, solder resist films <b>22</b> provided with openings <b>22</b><i>x </i>on the third wiring layers <b>18</b><i>b </i>are respectively formed on the both surfaces side of the temporary substrate <b>10</b>. As a consequence, a portion of the third wiring layers <b>18</b><i>b </i>exposed inside the openings <b>22</b><i>x </i>of the solder resist films <b>22</b> constitute external connection pads C<b>2</b>. Here, it is possible to form contact layers such as Ni/Au plated layers on the third wiring layers <b>18</b><i>b </i>inside the openings <b>22</b><i>x </i>of the solder resist films <b>22</b> if it is necessary.

0039In this way, the desired build-up wiring layers are formed on the copper foils <b>12</b><i>b </i>above the temporary substrate <b>10</b>. Although the three-layered build-up wiring layers (the first to third wiring layers <b>18</b> to <b>18</b><i>b</i>) are formed in the above-described example, it is possible to form n-layered (n is an integer equal to or greater than one) build-up wiring layers. Meanwhile, it is also possible to form a build-up wiring layer only on one surface of the temporary substrate <b>10</b>.

0040As described previously, in this embodiment, the underlying layer <b>12</b><i>a </i>and the copper foil <b>12</b><i>b </i>simply contact with each other in the region where these constituents overlap each other. Accordingly, when forming the build-up wiring layer on the copper foil <b>12</b><i>b</i>, wrinkles may be generated in the build-up wiring layer in a case where a thermal expansion coefficient of the temporary substrate <b>10</b> is largely different from that of the build-up wiring layer, because the degrees of thermal expansion vary between the both constituents. From such a viewpoint, it is preferable that a substrate that a nonwoven glass fabric is impregnated with resin is used as the temporary substrate <b>10</b>, such as a nonwoven glass fabric epoxy resin substrate and the like. The thermal expansion coefficient of the nonwoven glass fabric epoxy resin substrate ranges from 30 to 50 ppm/° C., therefore it is possible to approximate the thermal expansion coefficient thereof to an average thermal expansion coefficient (20 to 50 ppm/° C.) of the build-up wiring layer. Note that, a similar characteristic is obtained, in the case that a nonwoven fabric formed of aramid or liquid crystal polymer besides the nonwoven glass fabric is used. The thermal expansion coefficient of the wiring layers (Cu) of the build-up wiring layer is around 18 ppm/° C., and the thermal expansion coefficient of the insulating layers (the resin) is in a range of 50 to 60 ppm/° C.

0041Thus, even when heat is applied in the manufacturing process, the temporary substrate <b>10</b> and the build-up wiring layer expand substantially in the same degree. Accordingly, generation of wrinkles in the build-up wiring layer is prevented. In this way, it is possible to improve production yields and reliability of the build-up wiring layer.

0042Subsequently, as shown in <figref idref="DRAWINGS">FIG. 1J</figref>, the outer peripheral portions B including the peripheral portions of the copper foils <b>12</b><i>b </i>are removed by cutting out portions corresponding to the periphery of the underlying layers <b>12</b><i>a </i>of the structure shown in <figref idref="DRAWINGS">FIG. 1I</figref>. Hence, as shown in <figref idref="DRAWINGS">FIG. 1K</figref>, the wiring formation regions A in which the underlying layer <b>12</b><i>a </i>and the copper foil <b>12</b><i>b </i>simply contact with each other are obtained. Thereby, the copper foils <b>12</b><i>b </i>can be easily separated from the underlying layers <b>12</b><i>a</i>. In this way, wiring members <b>30</b> composed of the copper foil <b>12</b><i>b </i>and the build-up wiring layer formed thereon are obtained from the both surfaces side of the temporary substrate <b>10</b>.

0043Thereafter, as shown in <figref idref="DRAWINGS">FIG. 1L</figref>, the copper foil <b>12</b><i>b </i>of the wiring member <b>30</b> is selectively removed from the first wiring layer <b>18</b> and the first insulating layer <b>20</b>. For example, the copper foil <b>12</b><i>b </i>can be removed by selective etching on the first wiring layer <b>18</b> (such as Au) and the first insulating layer <b>20</b> by means of wet etching with a ferric chloride aqueous solution, a cupric chloride aqueous solution or an ammonium persulfate aqueous solution, for example.

0044Hence, as shown in <figref idref="DRAWINGS">FIG. 1L</figref>, a lower surface of the first wiring layer <b>18</b> is exposed, and internal connection pads C<b>1</b> are obtained. By the manner described above, a wiring substrate <b>1</b> of the first embodiment is manufactured.

0045In a preferred example of this embodiment, a plurality of wiring formation regions A are defined on the both surfaces side of the temporary substrate <b>10</b>, and in a state that underlying layer <b>12</b><i>a </i>is disposed on the block region composed of a plurality of wiring formation regions A, peripheral sides of the copper foil <b>12</b><i>b </i>is selectively attached to an outermost peripheral portion of a block region. Then, the build-up wiring layers are formed respectively in the wiring formation regions A. Thereafter, the copper foil <b>12</b><i>b </i>is removed from the wiring members <b>30</b> obtained by cutting out the peripheral portions of the underlying layer <b>12</b><i>a </i>of the resultant structure. Then, the wiring members <b>30</b> are divided into the respective wiring substrates.

0046It is also possible to form electrodes to be connected to the first wiring layer <b>18</b> by patterning instead of removing the copper foil <b>12</b><i>b. </i>

0047Meanwhile, in preferred example of this embodiment, a semiconductor chip is electrically connected to the internal connection pads C<b>1</b> (the first wiring layer <b>18</b>) and mounted on it, and external connection terminals are provided on the external connection pads C<b>2</b> (the third wiring layer <b>18</b><i>b</i>).

0048As described above, according to the method of manufacturing a wiring substrate of this embodiment, the underlying layers <b>12</b><i>a </i>and the copper foils <b>12</b><i>b </i>larger than the underlying layers <b>12</b><i>a </i>are superposed and disposed on the both surfaces of the prepreg <b>10</b><i>a</i>, and the temporary substrate <b>10</b> is obtained by hardening the prepreg <b>10</b><i>a </i>with heating and pressurization. At this time, the underlying layers <b>12</b><i>a </i>and the copper foils <b>12</b><i>b </i>can be concurrently attached to the both surfaces of the temporary substrate <b>10</b> without using adhesive layers. Subsequently, the build-up wiring layers are formed on the copper foils <b>12</b><i>b</i>. Moreover, the underlying layers <b>12</b><i>a </i>are separated from the copper foils <b>12</b><i>b </i>by cutting out the portions of the structure corresponding to the peripheral portions of the underlying layers <b>12</b><i>a</i>. Accordingly, the wiring members <b>30</b> each composed of the copper foil <b>12</b><i>b </i>and the build-up wiring layer formed thereon are obtained from the both surfaces side of the temporary substrate <b>10</b>.

0049In this embodiment, since the prepreg <b>10</b><i>a </i>having the adhesive function is used as the material of the temporary substrate <b>10</b>, it is possible to attach the underlying layers <b>12</b><i>a </i>and the copper foils <b>12</b><i>b </i>onto the temporary substrate <b>10</b> without using adhesive layers. Thus, it is possible to simplify the step of attaching the underlying layers <b>12</b><i>a </i>and the copper foils <b>12</b><i>b</i>, and to reduce the manufacturing costs.

Second Embodiment

0050<figref idref="DRAWINGS">FIGS. 2A</figref> to <b>2</b>F are cross-sectional views showing a method of manufacturing an electronic component mounting structure according to a second embodiment of the present invention. In the second embodiment, a preferred method of mounting an electronic component on a wiring substrate will be described on the basis of the technical idea of the method of manufacturing a wiring substrate of the present invention.

0051As shown in <figref idref="DRAWINGS">FIG. 2A</figref>, first, a structure in which underlying layers <b>12</b><i>a </i>and copper foils <b>12</b><i>b </i>larger than the underlying layers <b>12</b><i>a </i>are attached to both surfaces side of a temporary substrate <b>10</b> is obtained by the method similar to that of the first embodiment. Moreover, after solder resist films <b>22</b><i>a </i>which are provided with openings <b>22</b><i>y </i>on the copper foils <b>12</b><i>b </i>are formed on the copper foil <b>12</b><i>b </i>on the both surfaces side of the temporary substrate <b>10</b>, first wiring layers <b>28</b> are formed on the openings <b>22</b><i>y </i>by electrolytic plating. In the second embodiment, the internal connection pads C<b>1</b> and the external connection pads C<b>2</b> of the first embodiment are disposed with reversing up and down, and the first wiring layers <b>28</b> function as the external connection pads C<b>2</b>.

0052Next, as shown in <figref idref="DRAWINGS">FIG. 2B</figref>, first insulating layers <b>20</b> for covering the first wiring layers <b>28</b> are formed on the both surfaces side of the temporary substrate <b>10</b>. Then, second wiring layers <b>28</b><i>a </i>to be connected to the first wiring layers <b>28</b> through first via holes <b>20</b><i>x </i>provided on the first insulating layers <b>20</b> are respectively formed on the first insulating layers <b>20</b> by the method similar to that of the first embodiment.

0053Subsequently, as shown in <figref idref="DRAWINGS">FIG. 2C</figref>, after second insulating layers <b>20</b><i>a </i>for covering the second wiring layers <b>28</b><i>a </i>are formed on the both surfaces side of the temporary substrate <b>10</b>, second via holes <b>20</b><i>y </i>are formed respectively on portions of the second insulating layers <b>20</b><i>a </i>on the second wiring layers <b>28</b><i>a</i>. Moreover, third wiring layers <b>28</b><i>b </i>to be connected to the second wiring layers <b>28</b><i>a </i>through the second via holes <b>20</b><i>y </i>are respectively formed on the second insulating layers <b>20</b><i>a </i>on the both surfaces side of the temporary substrate <b>10</b>.

0054Next, as shown in <figref idref="DRAWINGS">FIG. 2D</figref>, solder resist films <b>22</b><i>b </i>provided with openings <b>22</b><i>z </i>are formed on the third wiring layers <b>28</b><i>b</i>. Then, in the second embodiment, exposed portions of the third wiring layers <b>28</b><i>b </i>constitute internal connection pads C<b>1</b>.

0055Next, as shown in <figref idref="DRAWINGS">FIG. 2D</figref> again, a portion of the structure of <figref idref="DRAWINGS">FIG. 2D</figref>, the portion corresponding to the peripheral portions of the underlying layer <b>12</b><i>a </i>are cut out as similar to the first embodiment. In this way, as shown in <figref idref="DRAWINGS">FIG. 2E</figref>, wiring members <b>30</b> having the structure in which build-up wiring layers are formed on the copper foils <b>12</b> are obtained. Furthermore, a semiconductor chip <b>40</b> (an electronic component) having bumps <b>40</b><i>a </i>is prepared and the bumps <b>40</b><i>a </i>of the semiconductor chip <b>40</b> are connected to the internal connection pads C<b>1</b> on an upper side of the wiring member <b>30</b> by flip-chip bonding. Moreover, underfill resin <b>39</b> is filled into an interstice on a lower side of the semiconductor chip <b>40</b>.

0056Here, the semiconductor chip <b>40</b> is used as an example of the electronic component. However, it is also possible, to mount various electronic components such as a capacitor component. Moreover, in addition to flip-chip bonding, various mounting methods such as a wire bonding method may be employed as the method of mounting the electronic component.

0057In this embodiment, the copper foil <b>12</b><i>b </i>which functions as a reinforcing member remains in the wiring member <b>30</b>, when the semiconductor chip <b>40</b> is mounted. Accordingly, it is easier to convey or handle the wiring member <b>30</b> while avoiding occurrence of warp. In this way, it is possible to mount the semiconductor chip <b>40</b> with high reliability.

0058Thereafter, as shown in <figref idref="DRAWINGS">FIG. 2F</figref>, the external connection pads C<b>2</b> (the first wiring layers <b>28</b>) are exposed on the lower side by removing the copper foil <b>12</b><i>b </i>from the wiring member <b>30</b>. Here, in a case where the conveyance or handling does not become problem, it is also possible to mount the semiconductor chip <b>40</b> after removing the copper foil <b>12</b><i>b. </i>

0059By the manner described above, an electronic component mounting structure <b>2</b> (a semiconductor device) of the second embodiment is obtained.

0060<figref idref="DRAWINGS">FIGS. 3A</figref> to <b>3</b>D show a method of manufacturing an electronic component mounting structure according to a variation of the second embodiment. As shown in <figref idref="DRAWINGS">FIG. 3A</figref>, before cutting out the structure as described in <figref idref="DRAWINGS">FIG. 2D</figref>, the bumps <b>40</b><i>a </i>of the semiconductor chips <b>40</b> may be connected to the internal connection pads C<b>1</b> (the third wiring layers <b>28</b><i>b</i>) on the both surfaces by flip-chip bonding.

0061Thereafter, as shown in <figref idref="DRAWINGS">FIG. 3B</figref>, the portions corresponding to the peripheral portions of the underlying layers <b>12</b><i>a </i>of the structure of <figref idref="DRAWINGS">FIG. 3A</figref> are cut out. In this way, as shown in <figref idref="DRAWINGS">FIG. 3C</figref>, the copper foils <b>12</b><i>b </i>are separated from the underlying layers <b>12</b><i>a</i>, and the structures in each of which the semiconductor chip <b>40</b> is mounted on the wiring member <b>30</b> composed of the copper foil <b>12</b><i>b </i>and the build-up wiring layer formed thereon are obtained from the both surfaces side of the temporary substrate <b>10</b>. Furthermore, as shown in <figref idref="DRAWINGS">FIG. 3D</figref>, the external pads C<b>2</b> (the first wiring layer <b>28</b>) are exposed by removing the copper foil <b>12</b><i>b </i>from the wiring member <b>30</b>. In this way, the electronic mounting structure <b>2</b> having the identical structure with <figref idref="DRAWINGS">FIG. 2F</figref> is obtained.

0062In this variation also, since the semiconductor chip <b>40</b> is mounted on the wiring member <b>30</b> provided on the temporary substrate <b>10</b>, it is possible to mount the semiconductor chip <b>40</b> with high reliability without receiving an influence of warp and the like.

0063<figref idref="DRAWINGS">FIG. 2F</figref> and <figref idref="DRAWINGS">FIG. 3D</figref> show examples of adopting a land grid array (LGA) type as an external connection type, and the external connection pads C<b>2</b> are used as lands. In a case where a ball grid array (BGA) type is adapted, solder balls or the like are placed on the external connection pads C<b>2</b> and external connection terminals are provided thereon. Meanwhile, in a case where a pin grid array (PGA) type is adapted, lead pins are provided on the external connection pads C<b>2</b>.