Graphics pipeline precise interrupt method and apparatus

CROSS REFERENCE TO RELATED APPLICATIONS

0001This application is related to the following copending U.S. utility patent applications: (1) U.S. Patent Application entitled “INTERRUPTIBLE GPU AND METHOD FOR CONTEXT SAVING AND RESTORING,” filed on Nov. 10, 2005, and having Express Mail Label No. EV696132925US, which is entirely incorporated herein by reference; and (2) U.S. Patent Application entitled “INTERRUPTIBLE GPU AND METHOD FOR PROCESSING MULTIPLE CONTEXTS AND RUNLISTS,” filed on Nov. 10, 2005, and having Express Mail Label No. EV696132934US, which is also entirely incorporated herein by reference.

TECHNICAL FIELD

0002The present disclosure relates to graphics processing and, more particularly, to a system and method for saving and restoring contexts in an interruptible graphics processing unit.

BACKGROUND

0003Today's computer systems typically include multiple processors. For example, a graphics processing unit (GPU) is an example of a coprocessor in addition to a primary processor, such as a central processing unit (CPU), that performs specialized processing tasks for which it is designed. In performing these tasks, the GPU may free the CPU to perform other tasks. In some cases, coprocessors, such as a GPU, may actually reside on the computer system's motherboard along with the CPU, which may be a microprocessor. However, in other applications, as one of ordinary skill in the art would know, a GPU and/or other coprocessing devices may reside on a separate but electrically coupled card, such as a graphics card in the case of the GPU.

0004A coprocessor such as a GPU may often access supplemental memory, such as video memory, for performing its processing tasks. Coprocessors may be generally configured and optimized for performing specialized tasks. In the case of the GPU, such devices may be optimized for execution of three dimensional graphics calculations to support applications with intensive graphics. While conventional computer systems and coprocessors may adequately perform when running a single graphically intensive application, such computer systems and coprocessors may nevertheless encounter problems when attempting to execute multiple graphically intensive applications at once.

0005It is not uncommon for a typical coprocessor to schedule its processing workload in an inefficient manner. In some operating systems, a GPU may be multitasked using an approach that submits operations to the GPU in a serialized form such that the GPU executes the operations in the order in which they were received. One problem with this approach is that it does not scale well when many applications with differing priorities access the same resources. In this nonlimiting example, a first application that may be currently controlling the resources of a GPU coprocessor needs to relinquish control to other applications for the other applications to accomplish their coprocessing objectives. If the first application does not relinquish control to the other waiting application, the GPU may be effectively tied up such that the waiting application is bottlenecked while the GPU finishes processing the calculations related to the first application. As indicated above, this may not be a significant bottleneck in instances where a single graphically intensive application is active; however, the problem of tying up a GPU or other coprocessor's resources may become more accentuated when multiple applications attempt to use the GPU or coprocessor at the same time.

0006The concept of apportioning processing between operations has been addressed with the concept of interruptible CPUs that context switch from one task to another. More specifically, the concept of context save/restore has been utilized by modern CPUs that operate to save the content of relevant registers and program counter data to be able to resume an interrupted processing task. While the problem of apportioning processing between the operations has been addressed in CPUs, where the sophisticated scheduling of multiple operations is utilized, scheduling for coprocessors has not been sufficiently addressed.

0007At least one reason for this failure is related to the fact that coprocessors, such as GPUs, are generally viewed as a resource to divert calculation-heavy and time consuming operations away from the CPU so that the CPU may be able to process other functions. It is well known that graphics operations can include calculation-heavy operations and therefore utilize significant processing power. As the sophistication of graphics applications has increased, GPUs have become more sophisticated to handle the robust calculation and rendering activities.

0008Yet, the complex architecture of superscalar and EPIC-type CPUs with parallel functional units and out-of-order execution has created problems for precise interruption in CPUs where architecture registers are to be renamed, and where several dozens of instructions are executed simultaneously in different stages of a processing pipeline. To provide for the possibility of precise interrupt, superscalar CPUs have been equipped with a reorder buffer and an extra stage of “instruction commit (retirement)” in the processing pipeline.

0009Current GPU versions use different type of commands, which can be referred as macroinstructions. Execution of each GPU command may take from hundreds to several thousand cycles. GPU pipelines used in today's graphics processing applications have become extremely deep in comparison to CPUs. Accordingly, most GPUs are configured to handle a large amount of data at any given instance, which complicates the task of attempting to apportion the processing of a GPU, as the GPU does not have a sufficient mechanism for handling this large amount of data in a save or restore operation. Furthermore, as GPUs may incorporate external commands, such as the nonlimiting example of a “draw primitive,” that may have a long sequence of data associated with the command, problems have existed as to how to accomplish an interrupt event in such instances.

0010Thus, there is a heretofore-unaddressed need to overcome these deficiencies and shortcomings described above.

SUMMARY

0011A graphics processing unit (“GPU”) is configured to be interruptible so that it may execute multiple graphics programs at the same relative time. The GPU is configured in hardware to interruptible operation and operates to provide multiple programs access to processing so as to be able to switch between multiple tasks.

0012The GPU is configured to interrupt processing of a first context and to initiate processing of a second context upon command. A command processor communicates an interrupt signal on a communication path from to a plurality of pipeline processing blocks in a graphics pipeline. A token, which corresponds to an end of an interrupted context, is forwarded from the command processor to a first pipeline processing block and subsequently to other pipeline blocks in the graphics pipeline. Each pipeline processing block discards contents of associated FIFO memory units upon receipt of the interrupt signal until the token is reached. The token may be forwarded to one or more additional pipeline processing blocks and memory units so that the token is communicated throughout the graphics pipeline to flush data associated with the first context. Data associated with the second context may follow behind the token through graphics pipeline.

0013The pipeline may include a number of pipeline processing blocks in the graphics pipeline not coupled to the command processor by the communication path. These pipeline processing blocks continue processing data associated with the first context until receiving the token through the graphics pipeline. Upon receiving the token, these pipeline processing blocks may also discard data in memory associated with the first context and begin processing data associated with the second context.

0014Other systems, methods, features, and advantages of this disclosure will be or become apparent to one with skill in the art upon examination of the following drawings and detailed description. It is intended that all such additional systems, methods, features, and advantages be included within this description, be within the scope of this disclosure, and be protected by the accompanying claims.

DESCRIPTION OF THE DRAWINGS

0015Many aspects of the disclosure can be better understood with reference to the following drawings. The components in the drawings are not necessarily to scale, emphasis instead being placed upon clearly illustrating the principles of the present disclosure.

0016<figref idref="DRAWINGS">FIG. 1</figref> is a diagram illustrating an exemplary nonlimiting computing device in which a context switch in a GPU may be implemented.

0017<figref idref="DRAWINGS">FIG. 2</figref> is a diagram depicting the major states of a context switch process that may be implemented by the GPU of <figref idref="DRAWINGS">FIG. 1</figref>.

0018<figref idref="DRAWINGS">FIG. 3</figref> is a diagram of the context save data structure that may be implemented in the context switch process of <figref idref="DRAWINGS">FIG. 2</figref>

0019<figref idref="DRAWINGS">FIG. 4</figref> is a diagram of an initial structure of the ring buffer that may be implemented in <figref idref="DRAWINGS">FIG. 2</figref> prior to a first save/restore.

0020<figref idref="DRAWINGS">FIG. 5</figref> is a diagram of the ring buffer structure of <figref idref="DRAWINGS">FIG. 4</figref> after a save/restore context operation as also shown in <figref idref="DRAWINGS">FIG. 2</figref>.

0021<figref idref="DRAWINGS">FIG. 6</figref> is a diagram of a ring buffer structure of <figref idref="DRAWINGS">FIG. 4</figref> or <figref idref="DRAWINGS">FIG. 5</figref> being executed by the GPU, as shown in <figref idref="DRAWINGS">FIG. 1</figref>.

0022<figref idref="DRAWINGS">FIG. 7</figref> is a diagram of a portion of the architecture of the GPU of <figref idref="DRAWINGS">FIG. 1</figref> that may be included in saving and restoring states, as described in regard to <figref idref="DRAWINGS">FIG. 6</figref>.

0023<figref idref="DRAWINGS">FIG. 8</figref> is a flowchart diagram depicting the flow of saving states and writing the state commands to the command stream processor (“CSP”) of <figref idref="DRAWINGS">FIG. 7</figref>.

0024<figref idref="DRAWINGS">FIG. 9</figref> is a nonlimiting exemplary diagram of the 3D architecture blocks from <figref idref="DRAWINGS">FIG. 7</figref> for the GPU of <figref idref="DRAWINGS">FIG. 1</figref>.

0025<figref idref="DRAWINGS">FIG. 10</figref> is a diagram depicting a flowchart for a save and restore process as may be implemented in the 3D graphics pipeline of <figref idref="DRAWINGS">FIG. 9</figref>.

0026<figref idref="DRAWINGS">FIG. 11</figref> is a diagram of the run lists that the CSP of <figref idref="DRAWINGS">FIG. 7</figref> may execute containing a plurality of contexts, each context having its own ring buffer.

0027<figref idref="DRAWINGS">FIG. 12</figref> is a flowchart diagram of the CSP processing of a current run list and ring buffer, as shown in <figref idref="DRAWINGS">FIG. 11</figref>.

0028<figref idref="DRAWINGS">FIG. 13</figref> is a flowchart diagram depicting the operation of the CSP of <figref idref="DRAWINGS">FIG. 7</figref> as it executes a ring buffer structure and searches for a ring buffer end command.

0029<figref idref="DRAWINGS">FIG. 14</figref> is an expanded view diagram of the data structure of the contexts and ring buffer of <figref idref="DRAWINGS">FIG. 11</figref>.

0030<figref idref="DRAWINGS">FIG. 15</figref> is a diagram of the precise location process of a restored process that is implemented in a portion of the steps of <figref idref="DRAWINGS">FIG. 10</figref> by the CSP of <figref idref="DRAWINGS">FIG. 9</figref>.

0031<figref idref="DRAWINGS">FIG. 16</figref> is a flowchart diagram of a process for interrupting a first context in the pipeline of <figref idref="DRAWINGS">FIG. 9</figref> and for initiating processing of a next context.

0032<figref idref="DRAWINGS">FIG. 17</figref> is a flowchart diagram of the triangle setup unit of <figref idref="DRAWINGS">FIG. 9</figref> as it operates upon receipt of a cleanup token.

0033<figref idref="DRAWINGS">FIG. 18</figref> is a diagram of the process executed by the dump/reset/query state machine in each architectural unit of the 3D pipeline of <figref idref="DRAWINGS">FIG. 9</figref>.

0034<figref idref="DRAWINGS">FIG. 19</figref> is a diagram depicting a process implemented by the attribute setup unit of <figref idref="DRAWINGS">FIG. 9</figref> in the event of a hardwire interrupt signal being received.

0035<figref idref="DRAWINGS">FIG. 20</figref> is a diagram of a process implemented by the span generator of <figref idref="DRAWINGS">FIG. 9</figref> in regard to the handling of the cleanup token communicated down the pipeline of <figref idref="DRAWINGS">FIG. 9</figref>.

0036<figref idref="DRAWINGS">FIG. 21</figref> is a diagram of a process flow implemented by the tile generator of <figref idref="DRAWINGS">FIG. 9</figref> upon receipt of an interrupt command from the CSP of <figref idref="DRAWINGS">FIG. 9</figref>.

0037<figref idref="DRAWINGS">FIG. 22</figref> is a flowchart diagram of the Z unit level <b>1</b> module of <figref idref="DRAWINGS">FIG. 9</figref> as it may respond to receiving a tile generator interrupt token from the tile generator of <figref idref="DRAWINGS">FIG. 9</figref>.

0038<figref idref="DRAWINGS">FIG. 23</figref> is a diagram of the 3D pipeline of <figref idref="DRAWINGS">FIG. 9</figref> depicting the cutoff for saving a portion of an interrupted context and the continued processing of another portion of the interrupted context.

DETAILED DESCRIPTION

0039This disclosure provides for advanced scheduling so as to virtualize a GPU, thereby enabling different processes seeking GPU processing to be assigned a timeslot to be executed and provided some level of service that an operating system can control. While several applications may share the GPU, the operating system may be configured to schedule each application according to various criteria, such as when, as a nonlimiting example, a time quantum of one process expires, the GPU may schedule another process or even reschedule the same process to run in a next time slot.

0040A process may comprise a number of contexts, or operations, related to portions of the process being executed as a whole. As described herein, a context may represent all the state of the GPU at the time of a last execution (or initial execution) of the process on the GPU. The state may include the state registers, cache and memory contents, all the internal FIFOs, internal registers, etc. at the time of the last switch from one context to a different context, perhaps, as a nonlimiting example for a different process being executed by the GPU.

0041While it may not be practical to save an entire state of a GPU when a context is switched, the entire state may also not be needed, since a switch may be permitted to transpire between 1 to 3 milliseconds. During this time, the GPU can be configured to wrap up some level of processing so as to minimize an amount of a state that is saved.

0042GPUs may be configured with deep pipelines such that a significant number of triangles and pixels are contained in various stages of completion at any given cycle. Plus, a typical GPU may read, modify, and/or write to memory throughout the various stages of the processing pipeline. As a nonlimiting example, a GPU may be configured in the Z stages to read, compare, and conditionally update Z. Additionally, a write back unit of the GPU may be configured for destination blending of graphics elements. Thus, for these reasons, memory may be part of the state that is tracked, and if the context is going to be stopped and restarted, the GPU should not read/modify/write the same memory for the same pixel a second time. In this nonlimiting example, blending twice would yield different results. Thus, the GPU may be configured so that it does not track, as part of the saved state, all the history of what was written to memory up to the point of the context switch so as to avoid this situation described above.

0043<figref idref="DRAWINGS">FIG. 1</figref> is a diagram illustrating an exemplary nonlimiting computing device in which a context switch in a GPU may be implemented. <figref idref="DRAWINGS">FIG. 1</figref> and the following discussion are intended to provide a brief general description of a suitable computing environment in connection with the disclosure herein. It should be understood, however, that handheld, portable, and other computing devices and computer objects of all kinds may be utilized in association with this disclosure as well. Consequently, while a general purpose computer is described herein, it is but one nonlimiting example, and this disclosure may be implemented in a plurality of additional applications, as one of ordinary skill in the art would know. As an additional nonlimiting example, anywhere that data may be stored or from which data may be retrieved or transmitted to another computer is a desirable, or suitable, environment for operation of the techniques, as disclosed herein.

0044This disclosure may be implemented by an operating system as a nonlimiting example, for use by a developer of services of a device or object, and/or included within application software that operates in connection with the techniques described herein. Software may be described or represented in the general context of computer executable instructions, such as program modules, being executed by one or more computers, such as client workstations, servers, or other devices. Program modules may include routines, programs, objects, components, data structures, and the like that perform a particular task or implement particular abstract data types, as one of ordinary skill in the art would know. The functionality of program modules may be combined or distributed as desired in various configurations.

0045Other well-known computing systems, environments, and/or configurations that may be suitable for use with this disclosure include, but are not limited to, personal computers (PCs), automated teller machines (ATMs), server computers, handheld or laptop devices, multiprocessor systems, microprocessor based systems, programmable consumer electronics, network PCs, appliances, lights, environmental control elements, minicomputers, mainframe computers, and the like. This disclosure may be applied and distributed in computing environments where tasks are performed by remote processing devices that are coupled via communication networks/buses or another data transmission medium. In a distributed computing environment, program modules may be located in both local and remote computer storage media, including memory storage devices, and client nodes may in turn behave as server nodes.

0046The computing system <b>10</b> of <figref idref="DRAWINGS">FIG. 1</figref> includes a computer <b>12</b>. The components of the computer <b>12</b> may include, as nonlimiting examples, a processing unit <b>16</b>, a system memory <b>18</b>, and a system bus <b>21</b> that couples various system components, including the system memory <b>18</b>, to the processing unit <b>16</b>. The system bus <b>21</b> may be any of several types of bus structures, as one of ordinary skill in the art would know, including a memory bus or memory controller, a peripheral bus, and a local bus using any of a variety of bus architectures. As a nonlimiting example, such architectures may include a peripheral component interconnect (PCI) bus, accelerated graphics port (AGP), and/or PCI Express bus.

0047Computer <b>12</b> may include a variety of computer readable media. Computer readable media can be any available media that can be accessed by computer <b>12</b> and includes both volatile and nonvolatile memory, removable and nonremovable memory. As a nonlimiting example, computer readable media may comprise computer storage media and communication media. Computer storage media may include both volatile and nonvolatile, removable and nonremovable media implemented in any method or technology for storage such as computer readable instructions, data structures, program modules, or other data, as one of ordinary skill in the art would know. Computer storage media includes, as nonlimiting examples, RAM, ROM, EEPROM, flash memory, or other memory technology, CDROM, digital versatile disks (DVD) or other optical disk storage disks, magnetic cassettes, magnetic tape, magnetic disk storage, or other magnetic storage devices, or any other medium that can be used to store desired information and which can be accessed by computer <b>12</b>.

0048The system memory <b>18</b> may include computer storage media in the form of volatile and/or nonvolatile memory, such as read only memory (ROM) <b>24</b> and random access memory (RAM) <b>26</b>. A basic input/output system <b>27</b> (BIOS), containing the basic routines that may help to transfer information between elements within computer <b>12</b>, such as during startup, may be stored in ROM <b>24</b>. RAM <b>26</b> may contain data and/or program modules that are accessible to and/or presently being operated on by processing unit <b>16</b>. As a nonlimiting example, operating system <b>29</b>, application programs <b>31</b>, other program modules <b>33</b>, and program data <b>35</b> may be contained in RAM <b>26</b>.

0049Computer <b>12</b> may also include other removable/nonremovable volatile/nonvolatile computer storage media. As a nonlimiting example, a hard drive <b>41</b> may read from or write to nonremovable, nonvolatile magnetic media. A magnetic disk drive <b>51</b> may read from or write to a removable, nonvolatile magnetic disk <b>52</b>. An optical disk drive <b>55</b> may read from or write to a removable, nonvolatile optical disk <b>56</b>, such as a CDROM or other optical media. Other removable/nonremovable volatile/nonvolatile computer storage media that can be used in the exemplary computing system <b>10</b> include, but are not limited to, magnetic tape cassettes, flash memory cards, DVDs, digital video tape, solid state RAM, solid state ROM, and the like.

0050Hard disk drive <b>41</b> may typically be connected to bus system <b>21</b> through a nonvolatile memory interface such as interface <b>40</b>. Likewise, magnetic disk drive <b>51</b> and optical disk drive <b>55</b> may be connected to bus system <b>21</b> by removable memory interface, such as interface <b>50</b>. The drives and their associated computer storage media described above and shown in <figref idref="DRAWINGS">FIG. 1</figref> may provide storage of computer readable instructions, data structures, program modules, and other data for computer <b>12</b>. As a nonlimiting example, hard disk drive <b>41</b> is illustrated as storing operating system <b>44</b>, application programs <b>45</b>, other program modules <b>46</b>, and program data <b>47</b>.

0051These components may either be the same as or different from operating system <b>29</b>, application programs <b>31</b>, other program modules <b>33</b>, and/or program data <b>35</b>. At least in this nonlimiting example described herein as shown in <figref idref="DRAWINGS">FIG. 1</figref>, these components of software are given separate reference numerals to at least illustrate that they are different copies.

0052A user may enter commands and information into computer <b>12</b> through input devices such as keyboard <b>62</b> and pointing device <b>61</b>. These devices are but nonlimiting examples, as one of ordinary skill in the art would know. Keyboard <b>62</b> and pointing device <b>61</b>, however, may be coupled to processing unit <b>16</b> through a user input interface <b>60</b> that is coupled to system bus <b>21</b>. However, one of ordinary skill in the art would know that other interface and bus structures such as a parallel port, game port, or a universal serial bus (USB) may also be utilized for coupling these devices to the computer <b>12</b>.

0053A graphics interface <b>82</b> may also be coupled to the system bus <b>21</b>. As a nonlimiting example, the graphics interface <b>82</b> may be configured as a chip set that communicates with the processing unit <b>16</b>, and assumes responsibility for accelerated graphics port (AGP) or PCI-Express communications. One or more graphics processing units (GPUs) <b>84</b> may communicate with the graphics interface <b>82</b>. As a nonlimiting example, GPU <b>84</b> may include on-chip memory storage, such as register storage and cache memory. GPU <b>84</b> may also communicate with a video memory <b>86</b>, wherein application variables, as disclosed herein may have impact. GPU <b>84</b>, however, is but one nonlimiting example of a coprocessor, and thus a variety of coprocessing devices may be included with computer <b>12</b>.

0054A monitor <b>91</b> or other type of display device may be also coupled to system bus <b>21</b> via video interface <b>90</b>, which may also communicate with video memory <b>86</b>. In addition to monitor <b>91</b>, computer system <b>10</b> may also include other peripheral output devices, such as printer <b>96</b> and speakers <b>97</b>, which may be coupled via output peripheral interface <b>95</b>.

0055One of ordinary skill in the art would know that computer <b>12</b> may operate in a networked or distributed environment using logical connections to one or more remote computers, such as remote computer <b>80</b>. Remote computer <b>80</b> may be a personal computer, a server, a router, a network PC, a pier device, or other common network node. Remote computer <b>80</b> may also include many or all of the elements described above in regard to computer <b>12</b>, even though only memory storage device <b>81</b> and remote application programs <b>85</b> are depicted in <figref idref="DRAWINGS">FIG. 1</figref>. The logical connections depicted in <figref idref="DRAWINGS">FIG. 1</figref> include a local area network (LAN) <b>71</b> and a wide area network (WAN) <b>73</b>, but may include other network/buses, as one of ordinary skill in the art would know.

0056In this nonlimiting example of <figref idref="DRAWINGS">FIG. 1</figref>, remote computer <b>80</b> may be coupled to computer <b>12</b> via LAN connection <b>71</b> and network interface <b>70</b>. Likewise, a modem <b>72</b> may be used to couple computer <b>12</b> (via user input interface <b>60</b>) to remote computer <b>80</b> across WAN connection <b>73</b>.

0057As stated above, the GPU <b>84</b> may be configured to switch processes, or contexts, during the processing of another context, or operation. In this instance, the GPU <b>84</b> is configured to save an interrupted context and to initiate processing of another context, which itself may have been previously interrupted and saved.

0058In regard to saving state context states and restoring previously saved context states, <figref idref="DRAWINGS">FIG. 2</figref> is an illustration of the major states of a context switch process that may be implemented by GPU <b>84</b>. At stage <b>101</b>, GPU <b>84</b> may be configured to execute a current GPU state context in regard to a given operation. However, as shown in a first step, the processing unit <b>16</b> may communicate an interrupt command or event so that GPU <b>84</b> operates to save the GPU state context, as shown in stage <b>103</b>. (The method for effectuating the interrupt command or event is described in detail below.) Thereafter, the GPU state context is saved as in step <b>2</b>, as the GPU <b>84</b> switches GPU state context, as shown in stage <b>105</b>. GPU <b>84</b> may then implement the third step to load a new GPU state context, as depicted in stage <b>107</b>. Thereafter, GPU <b>84</b> implements step <b>4</b> to return to stage <b>101</b> to execute this newly loaded GPU state context.

0059When the GPU <b>84</b> completes execution of this newly loaded GPU state context, a fifth step is implemented at the end of the newly loaded context so that the GPU <b>84</b> returns to stage <b>105</b> to switch GPU state context back to the previously executed context, as shown in step <b>6</b>. In so doing, the GPU <b>84</b> moves to stage <b>109</b> to restore the GPU state context previously saved in step <b>2</b>, as described above. Thereafter, in step <b>7</b>, the GPU <b>84</b> returns to stage <b>101</b> to execute this newly restored GPU state context at the point where it left off prior to receiving the interrupt command in step <b>1</b>.

0060GPU <b>84</b> is configured according to <figref idref="DRAWINGS">FIG. 2</figref> to support sequential execution of multiple GPU programs (commands) belonging to the same context that have also the name of the “ring buffer,” which comprises processor functions and command DMA buffer pointers in memory. As described above, the GPU <b>84</b> switches from one context to another upon receipt of an interrupt command and also at the end of the ring buffer, as corresponding to steps <b>1</b> and <b>5</b>, respectively. In the case of the interrupt command, the GPU <b>84</b> saves the state context so that it is able to continue execution of that context subsequent in time at the precise point saved.

0061<figref idref="DRAWINGS">FIG. 3</figref> is a diagram of a context saved data structure <b>111</b> that may be implemented in <figref idref="DRAWINGS">FIG. 2</figref>. These states of the architecture units saved in the context saved data structure <b>111</b> may define the status of the units at the moment of the interrupt. The context saved data structure <b>111</b> may include several fields, such as a DMA word offset pointer <b>114</b>, a primitive ID <b>118</b>, an instance ID <b>120</b>, and a tile ID <b>122</b> of an interrupted DRAW command. Context saved data structure <b>111</b> may also include various commands of a stream processor, execution unit, tile shader unit, and other processor unit states <b>116</b>. These states of the architecture units saved in the context saved data structure <b>1</b><b>11</b> may define the status of the units at the moment of the interrupt. If the GPU <b>84</b> maintains such information in ready-to-save form, and later restores all states before restarting context execution, the GPU <b>84</b> may be considered to be fully interruptible.

0062The following constitutes a nonlimiting exemplary list of elements in the state context save data structure <b>111</b>: <tables id="TABLE-US-00001" num="1"><table frame="none" colsep="0" rowsep="0"><tgroup align="left" colsep="0" rowsep="0" cols="1"><colspec colname="1" colwidth="217PT" align="left" /><thead><row><entry /></row><row><entry namest="1" nameend="1" align="center" rowsep="1" /></row></thead><tbody valign="top"><row><entry>typedef struct context_save_area</entry></row><row><entry>{</entry></row><row><entry>DMA_DW_Offset ;</entry></row></tbody></tgroup><tgroup align="left" colsep="0" rowsep="0" cols="2"><colspec colname="1" colwidth="91PT" align="left" /><colspec colname="2" colwidth="126PT" align="left" /><tbody valign="top"><row><entry>CSP_Registers CSP [551];</entry><entry>Command Stream Processor Registers</entry></row><row><entry>C2D_Registers C2D [13];</entry><entry>Block1 registers</entry></row><row><entry>MXU_Registers MXU[19];</entry><entry>Block2 registers</entry></row><row><entry>TSU_Registers TSU [163];</entry><entry>Block 3 registers</entry></row></tbody></tgroup><tgroup align="left" colsep="0" rowsep="0" cols="2"><colspec colname="OFFSET" colwidth="14PT" align="left" /><colspec colname="1" colwidth="203PT" align="left" /><tbody valign="top"><row><entry /><entry>SG_TG_Registers SG_TG [3];</entry></row></tbody></tgroup><tgroup align="left" colsep="0" rowsep="0" cols="1"><colspec colname="1" colwidth="217PT" align="left" /><tbody valign="top"><row><entry>ZL1_Registers ZL1 [17];</entry></row><row><entry>ZL2_Registers ZL2 [21];</entry></row><row><entry>Primitive_ID Primitive_ID;</entry></row><row><entry>Instance_ID Instance_ID;</entry></row><row><entry>Tile_ID Tile_ID;</entry></row><row><entry>} context_save_area</entry></row><row><entry namest="1" nameend="1" align="center" rowsep="1" /></row></tbody></tgroup></table></tables>

0063<figref idref="DRAWINGS">FIG. 4</figref> is an illustration of the initial structure of the ring buffer <b>125</b> prior to a first save/restore that related to the context switch procedure in <figref idref="DRAWINGS">FIG. 2</figref>. A ring buffer, such as ring buffer <b>125</b>, may comprise a string of commands and memory pointers associated with the execution of a context. This ring buffer <b>125</b> may contain a head pointer slot <b>127</b> and a tail pointer slot <b>129</b>. Head pointer slot <b>127</b> contains data regarding the logical location of processing the commands and pointers of the ring buffer <b>125</b>, and the tail pointer slot <b>129</b> stores data compiling to the logical end of the ring buffer <b>125</b>. The tail pointer slot <b>129</b> is updated during the context execution (stage <b>101</b> of <figref idref="DRAWINGS">FIG. 2</figref>) when more commands are added to the context.

0064The ring buffer <b>125</b> also contains, in this nonlimiting example, DMA memory command <b>131</b> and associated DMA pointer <b>133</b> that points to DMA buffer <b>147</b>, which may contain commands and data related to the context for this ring buffer <b>125</b>. Additionally, ring buffer <b>125</b> may contain DMA commands, such as DMA command <b>135</b>, and associated DMA pointers, such as pointer <b>137</b>, that point to a DMA buffer with commands and data, such as DMA buffer <b>148</b>. Ring buffer <b>125</b> of <figref idref="DRAWINGS">FIG. 4</figref> also contains place holders <b>141</b> and <b>142</b> which, in this nonlimiting example, is skip <b>1</b> DWORD <b>141</b> and null position <b>142</b> to hold the place for a context save command and address pointer, respectively, after a save/restore operation, as described below.

0065In application, when GPU <b>84</b> begins to execute the ring buffer <b>125</b>, GPU <b>84</b> receives both head pointer <b>127</b> and tail pointer <b>129</b> and checks for a saved context. Placeholder <b>141</b>, which, in this nonlimiting example, is configured as a skip <b>1</b> DWORD, which causes the GPU <b>84</b> to skip, or ignore, null <b>142</b> to the next command, which is DMA command <b>131</b>. In this instance, the ring buffer <b>125</b> is not interrupted at this point, and GPU <b>84</b> otherwise continues to execute the commands and instructions of ring buffer <b>125</b> of <figref idref="DRAWINGS">FIG. 4</figref> and also the contents of DMA buffers <b>147</b> and <b>148</b> (such as draw commands, primitives, instances, and tiles).

0066<figref idref="DRAWINGS">FIG. 5</figref> is a diagram of a ring buffer <b>150</b> after a save/restore context operation has been implemented, as shown in <figref idref="DRAWINGS">FIG. 2</figref>. In this nonlimiting example, the placeholders <b>141</b> and <b>142</b> of the ring buffer <b>125</b> in <figref idref="DRAWINGS">FIG. 4</figref> are replaced by a restore command <b>152</b> and context save address <b>154</b>, which point to a state context save buffer <b>111</b> (as shown in <figref idref="DRAWINGS">FIG. 3</figref>).

0067As the GPU <b>84</b> processes the ring buffer <b>150</b> of <figref idref="DRAWINGS">FIG. 5</figref>, upon recognizing restore command <b>152</b>, GPU <b>84</b> acknowledges the context save address <b>154</b> of a previous run state context that should be retrieved from state context save buffer <b>111</b>. Data retrieved from state context save buffer <b>111</b>, as discussed above, may also provide a DMA offset <b>146</b> for DMA buffer <b>147</b> so that processing can resume at the precise point interrupted.

0068<figref idref="DRAWINGS">FIG. 6</figref> is a diagram <b>160</b> of a ring buffer structure <b>162</b> being executed by architectural components of the GPU <b>84</b>, as shown in <figref idref="DRAWINGS">FIG. 1</figref> and also described in more detail below. Ring buffer <b>162</b>, which may be similar to ring buffers <b>125</b> (<figref idref="DRAWINGS">FIG. 4</figref>) or <b>150</b> (<figref idref="DRAWINGS">FIG. 5</figref>), includes a ring buffer head pointer <b>166</b> and ring buffer tail pointer <b>168</b>. A skip or restore pointer <b>170</b> may follow ring buffer tail pointer <b>168</b> (as similarly shown in <figref idref="DRAWINGS">FIGS. 4 and 5</figref> as references <b>141</b> and <b>152</b>, respectively), as well as a remaining portion of the context <b>172</b> in the ring buffer <b>162</b>. The remaining portion of context <b>172</b> may include one or more DMA commands and pointers, as described above.

0069The GPU <b>84</b> may include a command stream processor <b>190</b>, as shown in <figref idref="DRAWINGS">FIG. 7</figref> and described below. The command stream processor (“CSP”) <b>190</b> may be configured to include a pair of parsers, including a front-end parser <b>164</b> and a back-end parser <b>178</b>, which communicate with a <b>3</b>D pipeline <b>176</b>.

0070CSP front-end parser <b>164</b> may begin to parse the ring buffer <b>162</b> such that it receives head and tail pointers <b>166</b>, <b>168</b>. Thereafter, CSP front-end parser <b>164</b> may check for a saved context according to whether command pointer <b>170</b> is a skip or restore command. If the command <b>170</b> is a skip command, this indicates that ring buffer <b>162</b> was not previously interrupted. Thus, CSP <b>190</b> executes the remaining portion of the context <b>172</b>, which may include one or more DMA commands and pointers. If, however, the CSP front-end parser <b>164</b> recognizes command <b>170</b> as a restore command, such as restore command <b>152</b> in <figref idref="DRAWINGS">FIG. 5</figref>, the restore command is executed so that the previous run state context save data structure <b>175</b> is retrieved, as shown in <figref idref="DRAWINGS">FIG. 6</figref>, and restored at CSP front-end parser <b>164</b>. Thereafter, this restored context is executed by <b>3</b>D pipeline <b>176</b> and forwarded to CSP back-end parser <b>178</b>, which operates on it as the current run state save context data structure <b>181</b>.

0071<figref idref="DRAWINGS">FIG. 7</figref> is a diagram of a portion of the architecture of GPU <b>84</b> that may be included in saving and restoring states, as described in regard to <figref idref="DRAWINGS">FIG. 6</figref>. GPU <b>84</b> may include the command stream processor (“CSP”) <b>190</b> that has a front-end parser <b>164</b> and back-end parser <b>178</b>, all as described above. These devices coordinate instructions for processing by the 3D pipeline <b>176</b>. A DMA block <b>192</b> may access memory <b>186</b> for retrieving states and commands that are communicated to front-end parser <b>164</b>. A memory <b>194</b>, which in this nonlimiting example is a state FIFO 128×512, may also be included with CSP <b>190</b> for receiving states and commands from back-end parser <b>178</b>.

0072The 3D pipeline <b>176</b> of <figref idref="DRAWINGS">FIG. 6</figref> may be further represented by the 3D pipeline architectural blocks <b>176</b><i>a</i>-<b>176</b><i>d</i>, as shown in <figref idref="DRAWINGS">FIG. 7</figref>. These 3D pipeline architectural blocks <b>176</b> may, in one nonlimiting example, be represented by a tile shade unit, shade generator unit, tile generator, etc., as one of ordinary skill in the art would know. (See <figref idref="DRAWINGS">FIG. 10</figref>).

0073To prepare all states for saving when an interrupt command is received, each 3D pipeline architectural block <b>176</b> may be configured to forward a copy of its state command to the CSP <b>190</b>. Upon receipt of each architecture block's <b>176</b> state command, the CSP <b>190</b> may write this information in a state FIFO 128×512 (reference <b>194</b>) and later into memory <b>86</b> until subsequently restored, as described above. In at least one nonlimiting example, the 3D pipeline architectural blocks <b>176</b><i>b </i>and <b>176</b><i>d </i>are configured to include data paths <b>207</b>, <b>209</b> to back-end parser <b>178</b> of the CSP <b>190</b>. Although discussed in more detail below, not every 3D pipeline architectural block <b>176</b> includes a data path to back-end parser <b>178</b>, as the paths <b>207</b>, <b>209</b> may share data from multiple blocks <b>176</b>. However, these paths <b>207</b>, <b>209</b> enable GPU <b>84</b> to save data mid-processing so that one context may be interrupted and another begun.

0074Data paths <b>207</b> and <b>208</b> between architectural blocks <b>176</b><i>b </i>and <b>176</b><i>d</i>, respectively, are the two data paths shown in this nonlimiting example. Stated another way, at least one nonlimiting example provides that each architectural block in the 3-D pipeline <b>176</b> does not have a dedicated data path back to back-end parser <b>78</b>. Thus, the data path to copy the state entry of each architectural block <b>176</b> to the state FIFO <b>194</b> can be dedicated or shared for several 3D pipeline architecture blocks <b>176</b>. Because state changes may occur relatively infrequently, it may be more economical or desirable to share the data path <b>207</b>, <b>209</b> with multiple blocks <b>176</b> so as to reduce the overall number of data paths between the 3-D pipeline <b>176</b> and CSP back-end parser <b>178</b>. Stated another way, by having fewer data paths, chip real estate may be preserved for other modules and/or configurations.

0075<figref idref="DRAWINGS">FIG. 8</figref> is a diagram <b>205</b> depicting the 3D pipeline <b>176</b> of <figref idref="DRAWINGS">FIG. 7</figref> and an operation for interrupting a context so as to retain a precise tile head pointer <b>206</b>, DMA offset <b>293</b> (<figref idref="DRAWINGS">FIG. 15</figref>), instance ID <b>309</b> (<figref idref="DRAWINGS">FIG. 15</figref>), and primitive ID <b>311</b> (<figref idref="DRAWINGS">FIG. 15</figref>). A front part <b>195</b> of the 3D pipeline <b>176</b>, which may include the triangle setup unit <b>214</b> and attribute setup unit <b>218</b>, may be configured according to process <b>197</b> to discard data associated with an interrupted context. Thus, the draw commands, vertices, state commands, assembled primitives, etc. are discarded prior to having reached the tile generator <b>226</b>, which is further described in step <b>334</b> of <figref idref="DRAWINGS">FIG. 17</figref>.

0076The tile generator <b>226</b> may be configured to save the tile ID at the point of interrupt as well as the current head pointer <b>206</b>, DMA offset <b>293</b>, instance ID <b>309</b>, and the primitive ID <b>311</b>. This process is depicted in <figref idref="DRAWINGS">FIG. 8</figref> at step <b>198</b> and is also described below in greater detail.

0077In step <b>199</b> of <figref idref="DRAWINGS">FIG. 8</figref>, the back end part <b>196</b> of the 3D pipeline <b>176</b> continues to process data related to the old context so that a certain amount of the old context is drained through the pipeline <b>176</b> via normal processing. Thus, at least a portion of the old context is completed at the receipt of an interrupt operation.

0078<figref idref="DRAWINGS">FIG. 9</figref> is a flowchart diagram <b>200</b> depicting the flow of saving states and writing the state commands to the CSP <b>190</b> of <figref idref="DRAWINGS">FIGS. 7 and 8</figref>. During normal processing operations, the 3D pipeline architectural blocks <b>176</b> operate at stage <b>201</b>, which directs the architectural blocks <b>176</b> to write to state the register according to the register ID. So in noninterrupt mode, each 3D pipeline architectural block <b>176</b> moves from stage <b>201</b> to <b>203</b> to check for the next entry. Upon receiving the block state entry, a 3D pipeline architectural block <b>176</b> may again perform stage <b>201</b> if an interrupt is not received at the architectural block.

0079However, if the CSP <b>190</b> does receive a command switching to the interruptible mode of a currently processed context, the 3D pipeline architectural blocks <b>176</b> move to stage <b>204</b> so as to save the current state context executed by the GPU <b>84</b> (see step <b>103</b> of <figref idref="DRAWINGS">FIG. 2</figref>). Thereafter, the architectural block <b>176</b> returns to stage <b>203</b> to check for the next entry and continues to operate as described above.

0080In this event, the 3D pipeline architectural blocks <b>176</b> operate to establish a context saved data structure <b>111</b> (<figref idref="DRAWINGS">FIG. 3</figref>) by forwarding state data to the CSP <b>190</b> via data paths <b>207</b> and <b>209</b>. Blocks <b>176</b><i>a </i>and <b>176</b>c may forward such data to blocks <b>176</b><i>b </i>and <b>176</b><i>d</i>, respectively, which each forward the data received to the back-end parser <b>178</b> via data paths <b>207</b> and <b>209</b>.

0081<figref idref="DRAWINGS">FIG. 10</figref> is a nonlimiting exemplary diagram of the 3D architecture blocks <b>176</b> from <figref idref="DRAWINGS">FIG. 7</figref> and a more detailed view of the pipeline of <figref idref="DRAWINGS">FIG. 8</figref>. This is but one nonlimiting example of a graphics pipeline, as one of ordinary skill in the art would know, and these blocks could be rearranged or reconfigured to accomplish a similar result without departing from the spirit of this disclosure. As described above, CSP <b>190</b> may communicate with the 3-D pipeline architecture blocks <b>176</b>, which may include a triangle setup unit (“TSU”) <b>214</b> that receives instructions from a CSP FIFO memory <b>211</b>. The TSU <b>214</b> may communicate processed data to the attribute setup unit (“ASU”) <b>218</b> by way of TSU FIFO memory <b>215</b>. The ASU <b>218</b> may forward processed data to ASU/ZL<b>1</b> FIFO <b>219</b>, span generator unit (“SG”) <b>222</b> by way of ASU FIFO memory <b>220</b>, and AFIFO memory (Attribute FIFO) <b>223</b>.

0082SG <b>222</b> communicates processed data to tile generator unit (“TG”) <b>226</b>. A Z unit level <b>1</b> block (“ZL1”) <b>230</b> receives data from ASU/ZL<b>1</b> FIFO <b>219</b>, AFIFO <b>223</b>, and also TG FIFO <b>227</b>, which is also coupled to an output of TG <b>226</b>. ZL<b>1</b><b>230</b> processes data from these sources and communicates an output to a Z unit level <b>2</b> block (“ZL2”) <b>234</b> via ZFIFO <b>231</b> and ZL<b>1</b> FIFO memory <b>232</b>.

0083The 3D architecture pipeline (hereinafter “3D pipeline”) <b>176</b> of <figref idref="DRAWINGS">FIG. 10</figref> is but one portion of a graphics pipeline, as one of ordinary skill in the art would know. Additionally, a write back unit, a pixel packer, and other logical blocks may be included in a rest of the pipeline <b>176</b>, as one of ordinary skill in the art would know, but are excluded here for simplicity.

0084The context save and restore state process described above may be implemented in the 3D pipeline <b>176</b> of <figref idref="DRAWINGS">FIG. 10</figref>. <figref idref="DRAWINGS">FIG. 11</figref> is a diagram <b>240</b> depicting a flowchart for a save and restore process as may be implemented in the 3D pipeline <b>176</b> of <figref idref="DRAWINGS">FIG. 10</figref>.

0085For a context save process, when the GPU <b>84</b> is processing a context, an interrupt command may be received from the CPU (processing unit <b>16</b> of <figref idref="DRAWINGS">FIG. 1</figref>), as shown in step <b>242</b>. As shown in step <b>244</b>, 3D pipeline <b>176</b> may be configured to wait until the tile generator <b>226</b> or a write back unit (not shown in <figref idref="DRAWINGS">FIG. 10</figref>) clears of instructions being executed. The CSP <b>190</b> may recognize the tile generator <b>226</b> clearing due to the fact that the CSP <b>190</b> may send a token through the pipeline every time when the head pointer is changed. The tile generator <b>226</b> may communicate the token back to the CSP <b>190</b> when the tile generator <b>226</b> receives and processes it.

0086The CSP <b>190</b> may further communicate a DMA DWORD OFFSET down the pipeline <b>176</b> when the CSP <b>190</b> is initiating a draw command or starting states. The tile generator <b>226</b> may communicate this DMA DWORD OFFSET to the CSP <b>190</b> as well. The tile generator <b>226</b> may then communicate back each state when the states are communicated down to the tile generator as described above in regard to <figref idref="DRAWINGS">FIG. 7</figref> and the data paths <b>207</b> and <b>209</b>.

0087Block <b>247</b> of <figref idref="DRAWINGS">FIG. 11</figref> describes the states that may be saved as well as the pointers that may be stored upon receipt of the interrupt from the CPU <b>16</b> in step <b>242</b>. When the interrupt is received by the tile generator <b>226</b>, the tile generator <b>226</b> may communicate all 0s for IDs to the CSP <b>190</b> if the tile generator <b>226</b> is processing states during the interrupt. Otherwise, as shown in step <b>247</b>, the tile generator <b>226</b>, in this nonlimiting example, may store the pointers and states including the tile head pointer (DMA Offset), the instance ID, the primitive ID, the tile ID, and all register states so that the context being saved can be quickly restored. This data may comprise and be stored as the context saved data structure <b>111</b> of <figref idref="DRAWINGS">FIG. 3</figref>.

0088Thereafter, the GPU <b>84</b> may be configured to switch to another run list, as shown in step <b>249</b>. The run lists that may be switched to may include one or more other contexts for execution by the 3D pipeline <b>176</b>, as shown in <figref idref="DRAWINGS">FIG. 12</figref> below.

0089For the process flow of restoring a state for execution of the pipeline <b>176</b>, the GPU <b>84</b> may be configured to switch back to a previously, but partially executed run list, as in step <b>251</b>, that is, when the currently executed run list is finished or when an instruction is received to do so. Thereafter, the GPU <b>84</b> can be configured to restore all previously saved states in step <b>253</b>, which may have been saved in step <b>247</b> during a save state process. The CSP <b>190</b> may be configured in step <b>256</b> to skip draw commands until the saved draw command is reached according to the previously saved DMA offset, as in step <b>256</b>, and also as discussed in more detail below. Thereafter, in step <b>258</b>, the tile generator <b>226</b> may skip draw commands until all of the instance ID, primitive ID, and tile IDs which were saved in step <b>247</b> are received. Thereafter, in step <b>260</b>, the pipeline may execute any unfinished geometries. This process is described in additional detail below.

0090For the beginning of a context restore process, the CSP <b>190</b> needs to process the states to the entire engine, including the current head pointer, DMA offset, instance ID, primitive ID, and tile ID, which may have been previously saved in step <b>247</b>. Thus, the CSP <b>190</b> will retrieve the ring buffer head pointer from the ring buffer that was saved through the save process, as described above, and process the DMA command that is pointed to by the head pointer, and then skip all commands until the DMA address is equal to the DMA offset. This enables the CSP <b>190</b> to restart execution of the command exactly where it was interrupted, which may have been in the middle of a triangle that was being executed, as a nonlimiting example.

0091The CSP <b>190</b> may skip instances in the restored state process described above until the instance ID is matched, and may also skip primitives until the primitive ID is matched. The instance ID and primitive ID may be stored in state FIFO register <b>194</b> so that the CSP <b>190</b> may make the comparisons of the instances restored to the instance ID. Additional processing blocks that may be part of the GPU <b>84</b> computational core (not shown) may be configured to skip triangles until the primitive ID for a particular triangle is matched. For example, triangle IDs may be stored in a separate execution block register, also not shown herein. The tile generator <b>226</b> in the restore state process may be configured to skip tiles until the tiles match the tile ID saved at stage <b>247</b> during a save state process. Once the IDs are matched as described above, the CSP <b>190</b> may switch the 3D pipeline from a skip state to a normal state for execution.

0092The CSP <b>190</b> may create one or more tokens that are communicated to the 3D pipeline components <b>176</b> bearing the address of the registers for operation with an offset representing the point of processing during the previous interrupt, as well as identification of the registers to be restored. To provide flexible changes in the state context save structure, CSP <b>190</b> may operate in a configuration that includes densely packing all block state data in memory <b>86</b>. As a result, the CSP <b>190</b> may implement a flexible pack register offset. The register offset communicates to each 3D pipeline block <b>176</b> the point to resume or restore operation upon an interrupted context. By adding the offset to the register address of the interrupted context, the precise point of the interrupted context may be quickly determined. Accordingly, for each 3D pipeline architectural block <b>176</b> in <figref idref="DRAWINGS">FIG. 10</figref>, a block ID may be associated thereto and a corresponding offset for resuming calculations. In this way, GPU <b>84</b> is able to implement an interrupt with state context save and restore which may be done completely transparent to the application so that the 3D pipeline <b>176</b> may be utilized for one or more applications in a time sharing function and operation.

0093For the context save process <b>240</b> described in <figref idref="DRAWINGS">FIG. 11</figref>, it may be desirable to provide for flexible changes in the state context save structure. Thus, one nonlimiting exemplary process includes densely packing all block state data in the memory <b>86</b>. During a GPU subversion design process, each block in pipeline <b>176</b> may change register specification frequently. As a nonlimiting example, if there are in excess of <b>20</b> processing blocks (i.e., <b>176</b><i>a</i>, <b>176</b><i>b</i>, . . . <b>176</b><i>n</i>, where n>20), it make take a substantial amount of time to change the register data packing hardware.

0094Therefore, implementing a flexible packed register offset can address this issue. The table below provides for a set of registers that configures the state data save in a context save structure. For each block of state data, individual offset values are provided, which may be a combination of an offset register content and a register ID. The CSP <b>190</b> may be configured to issue a set register command targeted to a specific block in the pipeline <b>176</b>. In at least one nonlimiting example, the offsets are 128-bit aligned. A nonlimiting exemplary table of register set may be configured as follows: <tables id="TABLE-US-00002" num="2"><table frame="none" colsep="0" rowsep="0"><tgroup align="left" colsep="0" rowsep="0" cols="4"><colspec colname="OFFSET" colwidth="21PT" align="left" /><colspec colname="1" colwidth="84PT" align="left" /><colspec colname="2" colwidth="56PT" align="left" /><colspec colname="3" colwidth="56PT" align="left" /><thead><row><entry /><entry /></row><row><entry /><entry namest="OFFSET" nameend="3" align="center" rowsep="1" /></row></thead><tbody valign="top"><row><entry /><entry>Offset Register 0</entry><entry>Blockid1</entry><entry>Blockid0</entry></row><row><entry /><entry>Offset Register 1</entry><entry>Blockid3</entry><entry>Blockid2</entry></row><row><entry /><entry>Offset Register 2</entry><entry>Blockid5</entry><entry>Blockid4</entry></row><row><entry /><entry>Offset Register 3</entry><entry>Blockid7</entry><entry>Blockid6</entry></row><row><entry /><entry>Offset Register 4</entry><entry>Blockid9</entry><entry>Blcokid8</entry></row><row><entry /><entry>Offset Register 5</entry><entry>Blockid11</entry><entry>Blockid10</entry></row><row><entry /><entry>Offset Register 6</entry><entry>Blockid13</entry><entry>Blockid12</entry></row><row><entry /><entry>Offset Register 7</entry><entry>Blockid15</entry><entry>Blockid14</entry></row><row><entry /><entry>Offset Register 8</entry><entry>Blockid17</entry><entry>Blockid16</entry></row><row><entry /><entry>Offset Register 9</entry><entry>Blockid19</entry><entry>Blockid18</entry></row><row><entry /><entry>Offset Register 10</entry><entry>Blockid21</entry><entry>Blockid20</entry></row><row><entry /><entry namest="OFFSET" nameend="3" align="center" rowsep="1" /></row></tbody></tgroup></table></tables>

0095A table of length registers, such as depicted below, may be configured to describe the length of state data for each block and define the upper limit of data in opcode double word for each block. The length registers may be used by the CSP <b>190</b> for an internal test. Unlike the offset register described above, the length register may be formatted for the length of 32 bits. The following table is a nonlimiting exemplary length register table: <tables id="TABLE-US-00003" num="3"><table frame="none" colsep="0" rowsep="0"><tgroup align="left" colsep="0" rowsep="0" cols="5"><colspec colname="1" colwidth="63PT" align="left" /><colspec colname="2" colwidth="35PT" align="left" /><colspec colname="3" colwidth="42PT" align="left" /><colspec colname="4" colwidth="35PT" align="left" /><colspec colname="5" colwidth="42PT" align="left" /><thead><row><entry /></row><row><entry namest="1" nameend="5" align="center" rowsep="1" /></row></thead><tbody valign="top"><row><entry>Length Register 0</entry><entry>Blockid3</entry><entry>Blockid2</entry><entry>Blockid1</entry><entry>Blockid0</entry></row><row><entry>Length Register 1</entry><entry>Blockid7</entry><entry>Blockid6</entry><entry>Blockid5</entry><entry>Blockid4</entry></row><row><entry>Length Register 2</entry><entry>Blockid11</entry><entry>Blockid10</entry><entry>Blickid9</entry><entry>Blockid8</entry></row><row><entry>Length Register 3</entry><entry>Blockid15</entry><entry>Blockid14</entry><entry>Blockid13</entry><entry>Blockid12</entry></row><row><entry>Length Register 4</entry><entry>Blockid19</entry><entry>Blockid18</entry><entry>Blockid17</entry><entry>Blcokid16</entry></row><row><entry>Length Register 5</entry><entry /><entry /><entry>null</entry><entry>Blockid20</entry></row><row><entry namest="1" nameend="5" align="center" rowsep="1" /></row></tbody></tgroup></table></tables>

0096With this information, the CSP <b>190</b> can determine the length and offset of each block registers' memory location of address (block_id) for register(n), which is the base address summed with the offset register (block_id(n))&lt;&lt;4 (12 bits aligned). In this manner, the state context save structure is flexible. This feature provides flexibility in GPU derivative versions design.

0097<figref idref="DRAWINGS">FIG. 12</figref> is a diagram of multiple run lists that the CSP <b>190</b> of <figref idref="DRAWINGS">FIG. 7</figref> may execute containing a plurality of contexts, each context having its own ring buffer such as ring buffer <b>125</b>, <b>150</b>, or <b>162</b>. As shown in <figref idref="DRAWINGS">FIG. 12</figref>, CSP <b>190</b> may alternate execution of two run lists, including run list odd and run list even, as nonlimiting examples. Each run list contains, in this nonlimiting example, four separate contexts including context <b>0</b>, context <b>1</b>, context <b>2</b>, and context <b>3</b>. The context <b>0</b>—context <b>3</b> in each run list points to a separate ring buffer that may be executed by CSP <b>190</b>, as described above.

0098In the nonlimiting example of <figref idref="DRAWINGS">FIG. 12</figref>, ring buffer <b>1</b> may be referenced in context <b>1</b> of run list even. In this nonlimiting example, ring buffer <b>1</b> contains various GPU commands and/or DMA commands with DMA buffer pointers, such as described above in regard to ring buffers <b>125</b>, <b>150</b>, and <b>162</b>. In conjunction with <figref idref="DRAWINGS">FIG. 12</figref>, <figref idref="DRAWINGS">FIG. 13</figref> is a flowchart diagram <b>275</b> of the CSP <b>190</b> processing of a current run list and ring buffer, as shown in <figref idref="DRAWINGS">FIG. 12</figref>.

0099GPU <b>84</b> may receive the run list command and thereafter fill the context base address slot <b>0</b>-<b>3</b>, as shown in <figref idref="DRAWINGS">FIG. 12</figref>, and as also referenced as step <b>279</b> of <figref idref="DRAWINGS">FIG. 13</figref> so as to establish a run list for execution. As also shown in <figref idref="DRAWINGS">FIG. 12</figref>, CSP <b>190</b> thereafter starts at context <b>0</b> of the run list to be executed, whether run list even or run list odd.

0100In <figref idref="DRAWINGS">FIG. 13</figref>, the CSP <b>190</b> may fetch the head and tail pointers and check a next token for a skip or restore command, as shown in step <b>282</b> and also described above. If the CSP <b>190</b> determines that the next token is a restore command, as referenced by decision block <b>285</b> and as described above (restore command <b>152</b> in <figref idref="DRAWINGS">FIG. 5</figref>), the CSP <b>190</b> executes the restore command and fetches all of the GPU state info, as also described above and as shown in block <b>288</b>. If decision block <b>285</b> does not result in detection of a restore command in the next token, the CSP <b>190</b> may fetch the ring buffer <b>1</b> of <figref idref="DRAWINGS">FIG. 12</figref> and execute a DMA command (such as DMA command <b>131</b> of <figref idref="DRAWINGS">FIG. 4</figref>) and its associated DMA buffer (such as DMA buffer <b>147</b> of <figref idref="DRAWINGS">FIG. 4</figref>).

0101In <figref idref="DRAWINGS">FIG. 12</figref>, CSP <b>190</b> and 3D pipeline <b>176</b> may access DMA pointer <b>290</b>, which causes the DMA buffer <b>292</b> to be accessed. In this nonlimiting example, DMA buffer <b>292</b> contains draw command <b>0</b> and draw command <b>1</b>, which is fetched when the head pointer reaches DMA pointer <b>290</b>. As the head pointer moves logically from left to right down ring buffer <b>1</b>, it will reach either a skip or restore command prior to DMA pointer <b>290</b> as described above. Yet, in this nonlimiting example of <figref idref="DRAWINGS">FIG. 12</figref>, the absence of a restore command causes the CSP <b>190</b> to start the DMA buffer fetch, which results in accessing a DMA buffer <b>292</b> and the processing of graphics related data contained in and/or referenced by the buffer.

0102Returning to <figref idref="DRAWINGS">FIG. 13</figref>, CSP <b>190</b> and 3D pipeline <b>176</b> begins to process the current ring buffer location in step <b>289</b> after the appropriate ring buffer has been fetched. In the nonlimiting example of <figref idref="DRAWINGS">FIG. 12</figref>, the CSP <b>190</b> may begin processing context <b>0</b> containing run buffer <b>0</b> for the run list even group. If the context is empty, as determined in step <b>294</b>, a switch is made to the next context in the run list in step <b>297</b>. In this nonlimiting example, the CSP <b>190</b> would switch from context <b>0</b> to context <b>1</b> such that the ring buffer <b>1</b> would be loaded and executed. In switching to ring buffer <b>1</b>, the determination would be made whether there is an interrupt from the processing unit (“CPU”) <b>16</b>, as determined in step <b>299</b> of <figref idref="DRAWINGS">FIG. 13</figref>. If not, then the CSP <b>90</b> would return to step <b>282</b> for execution of the ring buffer <b>1</b> of <figref idref="DRAWINGS">FIG. 12</figref>. However, if an interrupt were detected in step <b>299</b>, the next step would result in processing of the interrupt as shown in step <b>301</b>, which subsequently would cause the process to return to step <b>282</b>. The context save process of <figref idref="DRAWINGS">FIG. 11</figref> would follow, as well.

0103If, in step <b>294</b>, the context is determined not to be empty, the front-end parser <b>164</b> of CSP <b>190</b> may thereafter send the current ring buffer pointer and DMA offset and ID, as well as register states, to the triangle setup unit <b>214</b> of <figref idref="DRAWINGS">FIG. 10</figref>. The front-end parser <b>164</b> may also communicate the instance ID, primitive ID, and vertex ID as well as indices to the appropriate locations for execution. Additionally, the front-end parser <b>164</b> may execute any initial CSP commands as needed.

0104In continuing to execute the ring buffer <b>1</b> of <figref idref="DRAWINGS">FIG. 12</figref>, the process may flow to step <b>306</b> wherein additional logical blocks of the 3D pipeline <b>176</b> are communicated to back-end parser <b>178</b>, thus signifying the approaching end of the execution of the ring buffer. Finally, in step <b>308</b>, the CSP <b>190</b> executes the back-end portion of any command that stores all states resulting from the processed operation.

0105The process of <figref idref="DRAWINGS">FIG. 13</figref> of fetching the head and tail pointer of a ring buffer and processing continues until the end of the ring buffer is found, or until interrupted. <figref idref="DRAWINGS">FIG. 14</figref> is a flowchart diagram depicting the operation of the CSP <b>190</b> of <figref idref="DRAWINGS">FIG. 7</figref> as it executes a ring buffer structure and searches for a ring buffer end command. In step <b>310</b> of <figref idref="DRAWINGS">FIG. 14</figref>, the CSP <b>190</b> may be idle awaiting for receipt of a ring buffer for execution. In step <b>312</b>, which may correspond to step <b>282</b> of <figref idref="DRAWINGS">FIG. 13</figref>, the CSP <b>190</b> fetches the head and tail pointer of a ring buffer (such as ring buffer of context <b>1</b> of run list <b>264</b> even in <figref idref="DRAWINGS">FIG. 12</figref>) and awaits in step <b>314</b> for the head and tail pointer to be referenced and ultimately filled in step <b>314</b>. In decision step <b>285</b> of <figref idref="DRAWINGS">FIG. 13</figref>, if a restore context command is encountered, the operation, as referenced in <figref idref="DRAWINGS">FIG. 14</figref>, moves to step <b>316</b> for loading the restored state, which also corresponds to block <b>288</b> of <figref idref="DRAWINGS">FIG. 13</figref>. Once the load state is done, the operation moves to step <b>318</b> such that the ring buffer is fetched and operation may continue, as corresponding to step <b>289</b> of <figref idref="DRAWINGS">FIG. 13</figref>.

0106If a restore command is not activated or recognized at step <b>314</b>, a determination is made whether the head pointer is equal to tail pointer, meaning whether the context is empty, thereby corresponding to step <b>294</b> of <figref idref="DRAWINGS">FIG. 13</figref>. If the head pointer does not equal the tail pointer, then the ring buffer contains operations for processing, thereby causing the process to move from step <b>314</b> to step <b>318</b>, as described above. At step <b>318</b>, the current pointer is moved from its initial position toward the tail pointer and with each calculation a determination is made whether the current pointer, which may be the head pointer, equals the tail pointer. As processing continues, the head pointer, or current pointer, moves toward the tail pointer to where it ultimately equals the tail pointer. Step <b>318</b> may repeat in a loop several times until the current pointer (CUR_PTR) becomes equal to the tail pointer (TAIL_PTR).

0107When the current pointer, or head pointer, reaches the tail pointer, step <b>322</b> is reached, which causes the CSP <b>190</b> to wait for a tail pointer update. As shown in <figref idref="DRAWINGS">FIG. 12</figref>, the tail pointer may be moved if additional commands or pointers are added to the ring buffer during processing. However, if the tail pointer is not moved, the process moves to step <b>324</b> which connotes the end of the ring buffer, as shown in <figref idref="DRAWINGS">FIG. 12</figref>. The CSP <b>190</b> returns to an idle state <b>310</b> and prepares to repeat the process described above.

0108<figref idref="DRAWINGS">FIG. 15</figref> is an additional diagram of the data structures as described above in reference to <figref idref="DRAWINGS">FIGS. 12-14</figref> that may be utilized for the GPU <b>84</b> of <figref idref="DRAWINGS">FIG. 1</figref> to precisely restore a previously interrupted context, as described herein. In this nonlimiting example, run list <b>264</b> (also shown in <figref idref="DRAWINGS">FIG. 12</figref>) may have been executed as described above such that a context switch is made from context <b>0</b> to context <b>1</b>.

0109Ring buffer <b>1</b> data structure <b>265</b> in memory may be accessed for restoration of this particular context <b>1</b>, that is, in this nonlimiting example. As similarly described above, the ring buffer <b>1</b> data structure <b>265</b> may contain a tile head pointer slot <b>268</b> that may be updated by the GPU <b>84</b> during processing of this context. Likewise, ring buffer <b>1</b> data structure <b>265</b> may contain a ring buffer tail slot <b>268</b> that may also be updated, as described in regard to <figref idref="DRAWINGS">FIG. 12</figref>. If commands or pointers are added to the ring buffer <b>1</b> data structure in <figref idref="DRAWINGS">FIG. 15</figref>, then the ring buffer tail slot may be adjusted accordingly.

0110The ring buffer data fetch sequence may entail that a CSP function leads to the execution of DMA command pointer <b>290</b>, as also referenced in <figref idref="DRAWINGS">FIG. 12</figref>. The CSP <b>190</b> fetches the tile head pointer, as shown in <figref idref="DRAWINGS">FIG. 15</figref> in association to the ring buffer <b>1</b> data structure, which was in the ring buffer <b>1</b> data structure when this context <b>1</b> in run list <b>264</b> was previously interrupted. The CSP <b>190</b> may load all of the data corresponding to DMA command pointer <b>290</b> to the CSP head pointer, which points to the CSP function <b>291</b>, into the pipeline <b>176</b>.

0111The DMA command pointer <b>290</b> references the DMA buffer structure <b>292</b> in memory that may, at least on one nonlimiting example, contain draw command <b>0</b> through draw command <b>5</b>. In restoring this context, the CSP <b>190</b> also processes a DMA offset <b>293</b>, as similarly described above (<figref idref="DRAWINGS">FIG. 5</figref>), which enables matching of the processing of the context to the precise point where previously interrupted. The DMA offset <b>293</b> is the logical distance between the DMA buffer head pointer and the current command pointer for the DMA buffer structure <b>292</b>.

0112In this nonlimiting example of <figref idref="DRAWINGS">FIG. 15</figref>, the CSP <b>190</b> is configured to recognize that the DMA offset <b>293</b> establishes draw command <b>4</b> as the point to resume processing. Draw command <b>4</b> may be comprised of multiple instances <b>295</b> of the draw command <b>4</b>. More specifically, draw command <b>4</b> may include instances <b>0</b>-<b>5</b> that are executed sequentially. After instance <b>5</b> is processed, in this nonlimiting example, processing may then turn to draw command <b>5</b> in the DMA buffer structure <b>292</b>, which, as with any draw command, may itself have multiple instances.

0113In reestablishing this context from run list <b>264</b>, the CSP <b>190</b> discards all instances previously executed until matching the instance ID corresponding to the value stored at the previous interrupt. In this nonlimiting example, the instance ID <b>304</b> points to instance <b>4</b> of the multiple instances <b>295</b>. Thus, the CSP <b>190</b> discards all instances <b>0</b>-<b>3</b> until reaching instance <b>4</b>, for it is this logical position where the instance ID <b>304</b> matches.

0114Each instance of the multiple instances <b>295</b> contains one or more primitives, which may be sequenced, as shown in primitive structure <b>296</b>. In this nonlimiting example, primitives <b>0</b>-M may form an instance, which M is an integer. The interrupted draw command <b>4</b> in the DMA buffer structure <b>292</b> is processed by the CSP <b>190</b> until the primitive ID <b>311</b> matches the value corresponding to the point of prior interrupt, which was saved, as described above. In this nonlimiting example, the primitive ID <b>311</b> points to primitive <b>1</b>, which means that the CSP <b>190</b> would skip primitive <b>0</b>, as primitive <b>0</b> was processed prior to the previous interrupt.

0115Each primitive <b>0</b>-M references one or more tiles, which may be processed for drawing triangle <b>298</b>. In this nonlimiting example, primitive <b>2</b> may contain tiles <b>0</b>-<b>8</b> to construct triangle <b>298</b>. Also in this nonlimiting example, the tile generator TG <b>226</b> will skip tiles <b>0</b>-<b>3</b> until reaching the tile ID <b>317</b> that references tile <b>4</b>, thereby corresponding to the tile ID value stored in memory for the point where previously interrupted.

0116In this manner, the data structure depicted in <figref idref="DRAWINGS">FIG. 15</figref> illustrates at least one method for restoring a graphics operation at the precise point where the operation may have been previously interrupted. By the CSP <b>190</b> skipping the draw commands, instances, primitives, and TG <b>226</b> skipping tiles until reaching the IDs corresponding to the values saved when the context was previously interrupted, processing can resume quickly at the correct point, thereby avoiding duplicative processing of previously processed data.

0117<figref idref="DRAWINGS">FIG. 16</figref> is a flowchart diagram <b>252</b> of the process that the CSP <b>190</b> implements, in this nonlimiting example, when restoring a context. The diagram <b>252</b> of <figref idref="DRAWINGS">FIG. 16</figref> includes steps <b>253</b>, <b>256</b>, and <b>258</b> of <figref idref="DRAWINGS">FIG. 11</figref>, but is also focused on the operation of precise context restoration.

0118In <figref idref="DRAWINGS">FIG. 16</figref>, in step <b>300</b> the CSP <b>190</b> fetches the restored context from the ring buffer, which may be ring buffer <b>265</b> of <figref idref="DRAWINGS">FIGS. 12 and 15</figref>. In so doing, the ring buffer <b>265</b> tile head pointer <b>206</b> is accessed so as to ascertain the precise context restart address or logical location in ring buffer <b>265</b>. In the nonlimiting example of <figref idref="DRAWINGS">FIG. 15</figref>, the tile head pointer points to DMA command pointer <b>290</b>.

0119Continuing to step <b>304</b>, the CSP <b>190</b> processes the DMA command, as similarly described above, and operates to match the DMA offset <b>293</b> (also in <figref idref="DRAWINGS">FIG. 15</figref>) to the correct draw command in the DMA buffer structure <b>292</b> (<figref idref="DRAWINGS">FIG. 15</figref>). Upon identifying the precise draw command, which in the nonlimiting example of <figref idref="DRAWINGS">FIG. 15</figref> is draw command <b>4</b>, the CSP <b>190</b> moves to step <b>307</b> and matches the instance ID <b>309</b> and the primitive ID <b>311</b>, as discussed above. In making these matches, the CSP <b>190</b> identifies the precise triangle where processing was previously interrupted.

0120At that point, the CSP <b>190</b> may identify the precise tile ID <b>317</b> where prior processing was interrupted so that the tile generator <b>226</b> (<figref idref="DRAWINGS">FIG. 10</figref>) may finish processing the triangle, as shown in step <b>315</b>. After this precise DMA command, draw command, instance ID, primitive ID, and tile ID are identified, the context can be fully restored in the 3D pipeline <b>176</b> as if it had not previously been interrupted, that is, in at least one nonlimiting example.

0121In instances where a triangle may have been partially processed when previously interrupted due to a context change, a triangle ID may be forwarded to the TSU <b>214</b>. Individual triangles within a draw primitive (having a single primitive ID) may have unique triangle IDs, some of which may have been processed in whole or in part at the time the context was previously interrupted. In this instance, a tessellated triangle ID <b>313</b>, which may be generated by an execution unit, may be forwarded to the TSU <b>214</b> for resuming processing operations on this partially processed primitive, as shown in step <b>319</b> of <figref idref="DRAWINGS">FIG. 16</figref>. The result is that a precise triangle is forwarded to the tile generator <b>226</b> that may be matched to a corresponding tile ID, as discussed above. So regardless of whether a primitive has been previously tessellated or not, the resumption of processing of a previously interrupted context can be seamless and precise.

0122Thus far, the focus of this disclosure has been on the structure and the switching of contexts upon receipt of an interrupt command from the processing unit <b>16</b> of <figref idref="DRAWINGS">FIG. 1</figref>, including the data structure that provides for precise restoration. However, when a context is interrupted for future restoration, the GPU <b>84</b>, and more particularly, the 3D pipeline <b>176</b> of <figref idref="DRAWINGS">FIG. 10</figref>, should be configured so as to terminate the interrupted process at a logical point so that a next process, whether restored or not, may be executed by the 3D pipeline <b>176</b> in accordance with the process described above.

0123At least one nonlimiting example prescribes that a context may be saved and a new context restarted in approximately one to two million cycles, which should generally be sufficient to provide enough wrap-up time for some processing so as to minimize the state that may be tracked and to minimize the complexity when a save state is restarted subsequently in time. Consequently, as described above, one logical location to break the 3D pipeline <b>176</b> of <figref idref="DRAWINGS">FIG. 10</figref> is at tile generator <b>226</b>. However, as an alternate nonlimiting example, another location of breakpoint could be ZL<b>1</b> unit <b>230</b> instead of tile generator <b>226</b>. In this nonlimiting example, the same rules and IDs could apply, and the saved Tile ID would go to the ZL<b>1</b> unit <b>230</b> to be compared.

0124However, according to the nonlimiting example where the break is at the tile generator <b>226</b>, any tiles that are already admitted by the tile generator <b>226</b> to the remaining portions of the pipeline, including ZL<b>1</b> unit <b>230</b> and the subsequent units, up until the time of a context switch is signaled by the processing unit <b>16</b>, will be allowed to drain through the 3D pipeline <b>176</b>. However, any triangles or tiles that have not reached the tile generator <b>226</b> when an interrupt is received by the GPU <b>84</b> may be, in this nonlimiting example, discarded and regenerated when the context is subsequently restored. Stated another way, for the portion of the 3D pipeline <b>176</b> above the tile generator <b>226</b>, all processing results are discarded and are subsequently regenerated when the context is restored (see <figref idref="DRAWINGS">FIG. 8</figref>).

0125At least one reason for interrupting at the tile level (at tile generator <b>226</b>) is that, except in the case of extremely long pixel shader programs, the 3D pipeline <b>176</b> may be configured to process all tiles in the pipeline below the tile generator <b>226</b> within the target one to two million cycles. As a nonlimiting example, if an interrupt is configured at the triangle setup unit <b>214</b> of <figref idref="DRAWINGS">FIG. 10</figref>, it is possible that the pipeline may not be able to drain in the 1 to 3 milliseconds desired in this nonlimiting example. Interrupting on a scale smaller than tiles may not have much impact on how fast the pipeline can be drained. By configuring interrupts at the tile generator level of the pipeline, a certain amount of processing may continue, a certain amount of processing may be aborted, and the point of interrupt may be saved for subsequent restart. This nonlimiting example results in that some data will be reparsed and repeated in order to restore the 3D pipeline <b>176</b> to the point in which it was stopped at the interrupt.

0126According to at least one nonlimiting example, in order for the CSP <b>190</b> to know where in the command parsing that it will need to restart a context, the CSP <b>190</b> may be configured to communicate a token (internal fence) through the 3D pipeline <b>176</b> to the tile generator <b>226</b> and then back to the CSP <b>190</b> whenever the DMA buffer (context) is switched. According to this nonlimiting example, the CSP <b>190</b> may then know when it is safe to discard a DMA buffer. Also, this nonlimiting example provides that the position in the DMA buffer corresponding to the processing position in the tile generator <b>226</b> is recorded in this way with each new draw command, such as shown in <figref idref="DRAWINGS">FIG. 12</figref> in DMA buffer <b>292</b>. Thus, when a context, such as context <b>1</b> in run list even in <figref idref="DRAWINGS">FIG. 12</figref>, is subsequently restored, parsing can start from the draw command that was interrupted, such as a draw command <b>0</b> in buffer <b>292</b>.

0127<figref idref="DRAWINGS">FIG. 17</figref> is a diagram of the process <b>325</b> that CSP <b>190</b> of <figref idref="DRAWINGS">FIG. 10</figref> may implement to interrupt a context and restart another context in the 3D pipeline <b>176</b> of <figref idref="DRAWINGS">FIG. 10</figref>. In step <b>326</b>, which also corresponds to step <b>101</b> of <figref idref="DRAWINGS">FIG. 2</figref>, a current context may be processed, as described above, until empty, such as in step <b>294</b> of <figref idref="DRAWINGS">FIG. 13</figref>. As the context is processed in step <b>326</b>, a determination may be made as to whether an interrupt event has transpired, as in step <b>327</b>. If not, the context may be further processed in step <b>326</b> until empty.

0128If, however, an interrupt event is recognized in step <b>327</b>, the CSP <b>190</b> may move to step <b>329</b> and generate an interrupt signal that may be electrically communicated to one or more of the processing blocks of the 3D pipeline <b>176</b>. As stated above, a certain portion of the pipeline may be immediately discarded, as the continued processing of the upper portions of the pipeline may result in unsatisfactory context switch times due to the delay in clearing the top portion blocks. Yet, step <b>329</b> provides that a predetermined number of blocks of 3D pipeline <b>176</b> receive the interrupt signal as a result of a dedicated communication path with the CSP <b>190</b>.

0129In addition to generating the interrupt signal in step <b>329</b>, the CSP <b>190</b> may also generate an interrupt token to memory FIFOs in the 3D pipeline <b>176</b>. This interrupt token operates as a fence between the interrupted context and a next or restored context, such as in run list <b>264</b> of <figref idref="DRAWINGS">FIG. 15</figref>. The interrupt token/fence communicates to each architectural block in the 3D pipeline <b>176</b> that the changeover to a next or restored context is complete.

0130As discussed above, the current DMA offset <b>293</b>, instance ID <b>309</b>, primitive ID <b>311</b>, and tile ID <b>317</b> may be sent to the CSP context save buffer <b>111</b> (<figref idref="DRAWINGS">FIG. 3</figref>), which may be state FIFO <b>194</b> of <figref idref="DRAWINGS">FIG. 7</figref>. More specifically, the 3D architectural blocks <b>176</b> use paths <b>207</b>, <b>209</b>, etc. to forward this information to the CSP <b>190</b>, as similarly described above.

0131Thereafter, in step <b>334</b>, each 3D pipeline architectural block <b>176</b>, such as one or more blocks shown in <figref idref="DRAWINGS">FIG. 10</figref>, discard old context entries in the pipeline <b>176</b> until the interrupt token generated in step <b>331</b> is reached and identified. The old context is the interrupted context. Stated another way, upon receipt of the interrupt signal on the dedicated communication path in step <b>329</b>, the architectural blocks <b>334</b> discard associated FIFOs until receiving the interrupt token, which signifies that all commands thereafter belong to the next or restored state, which are processed in step <b>336</b>.

0132This process depicted in <figref idref="DRAWINGS">FIG. 17</figref> is described in greater detail below in regard to <figref idref="DRAWINGS">FIGS. 10 and 18</figref>-<b>23</b> in regard to the individual components of the 3D pipeline <b>176</b>. Beginning with <figref idref="DRAWINGS">FIG. 10</figref>, when the GPU <b>84</b> receives the command from the processing unit <b>16</b> to interrupt a process being processed, the CSP <b>190</b> communicates the hardwired signal to the execution unit pool front module <b>212</b>, which is shown in <figref idref="DRAWINGS">FIG. 10</figref> as EUP_FRONT <b>212</b>, via hardwire interrupt line <b>331</b>. This same hardwire interrupt line <b>331</b> is also electrically coupled to tile generator <b>226</b>, as shown in <figref idref="DRAWINGS">FIG. 10</figref>. Additionally, hardwire interrupt <b>331</b> may also be coupled to triangle setup unit <b>214</b> and attribute setup unit <b>218</b> all in accordance with step <b>329</b> of <figref idref="DRAWINGS">FIG. 17</figref>.

0133The tile generator <b>226</b> may maintain a counter for the tile number and pipeline registers for triangle number and primitive number of the last tile emitted. This information is sent back to the CSP <b>190</b> via data path <b>207</b> to be saved as part of the interrupted context state. This information references the position in the command stream where the GPU <b>84</b> should start processing again when the saved context is later restored.

0134The hardwire interrupt signal communicated on line <b>331</b> is also communicated to each of triangle setup units <b>214</b> and attribute setup unit <b>218</b>. Upon receipt of the hardwire interrupt signal on line <b>331</b>, each of the triangle setup unit <b>214</b>, attribute setup unit <b>218</b>, and tile generator <b>226</b> immediately discard all data being processed and cease further operations on that particular context, as also described in step <b>334</b> of <figref idref="DRAWINGS">FIG. 17</figref>. The CSP <b>190</b>, in addition to issuing the wire signal interrupt on line <b>331</b>, passes an interrupt end token, which may be represented as “INT_End token” in this nonlimiting example, down the 3-D pipeline <b>176</b> so as to flush all dirty lines in the processing stream, as described in step <b>331</b> of <figref idref="DRAWINGS">FIG. 17</figref>. This interrupt end token is communicated from the CSP <b>190</b> to the triangle setup unit <b>214</b>, to the attribute setup unit <b>218</b>, and through the rest of the pipeline <b>176</b>.

0135<figref idref="DRAWINGS">FIG. 18</figref> is a flowchart diagram <b>340</b> of the triangle setup unit input decoder <b>214</b> as it operates upon receipt of an interrupt end token, as described above. CSP <b>190</b> issues the interrupt end token to the execution unit pool front <b>212</b> via path <b>331</b>. However, at the same time, CSP <b>190</b> communicates the interrupt end token through CSP FIFO memory <b>211</b> that is ultimately communicated to triangle setup unit <b>214</b>. Thus, in <figref idref="DRAWINGS">FIG. 18</figref>, the triangle setup unit <b>214</b> engages in step <b>342</b> initially upon receiving the wire interrupt signal on line <b>331</b> so as to check the CSP FIFO memory <b>211</b> for its entry type.

0136Upon receiving the interrupt signal on line <b>331</b>, which may be shown in <figref idref="DRAWINGS">FIG. 18</figref> as the CSP_TSU_INT signal, the triangle setup unit <b>214</b> moves to step <b>346</b>, which prescribes that the triangle setup unit <b>214</b> reads, checks, and discards the EUP FIFO memory <b>347</b>. The EUP FIFO memory <b>347</b> is a FIFO storing data passed from the EUP_Front module <b>212</b> to the triangle setup unit <b>214</b>. The triangle setup unit <b>212</b> invokes a discard loop, as shown in <figref idref="DRAWINGS">FIG. 18</figref>, to discard the contents of the EUP FIFO memory <b>347</b> until reaching the interrupt end token, which represents the discarding of all data for the context being saved.

0137Upon reaching the interrupt end token at EUP FIFO memory <b>347</b>, the triangle setup unit <b>214</b> returns to the CSP FIFO memory <b>211</b> to read, check, and discard its contents in similar fashion as performed on EUP FIFO memory <b>347</b>, as shown in step <b>348</b> of <figref idref="DRAWINGS">FIG. 18</figref>. Triangle setup unit <b>214</b> engages in a discard loop to discard all contents in the CSP FIFO memory <b>211</b> until reaching the interrupt end token representing the end of the context being saved. Consequently, one of ordinary skill in the art would realize that data associated with the context being interrupted is discarded at this stage of the 3D pipeline <b>176</b>. The triangle setup unit ultimately moves from step <b>348</b> to step <b>350</b> in <figref idref="DRAWINGS">FIG. 18</figref>, which prescribes the dumping and/or resetting of the query state machine in preparation of the next context to be executed. After checking the next FIFO entry type in CSP FIFO memory <b>211</b>, the triangle setup unit <b>214</b> may return to normal operations in step <b>343</b> to process a new (next) context.

0138In regard to dump-reset-query state machine stage <b>350</b>, <figref idref="DRAWINGS">FIG. 19</figref> is a simplified diagram of the process executed by the dump/reset/query state machine (“DRQ state machine”) in each unit of the 3D pipeline <b>176</b> of <figref idref="DRAWINGS">FIG. 10</figref>. While the DRQ state machine may initially be in normal operating mode <b>352</b>, upon execution of a command, the DRQ state machine moves to step <b>354</b>. Movement to step <b>354</b> pertains to a CSP command decode operation, which informs the DRQ state machine (i.e., TSU <b>214</b>, etc.) what to do next. In the case when an interrupt end token is received by a unit, such as triangle setup unit <b>214</b>, step <b>356</b> follows so as to forward the interrupt end token down the 3D pipeline <b>176</b>. Thereafter, the unit such as triangle setup unit <b>214</b>, returns to normal operations in step <b>352</b>, regarding the new context.

0139After the interrupt end token is processed, as described above in regard to <figref idref="DRAWINGS">FIG. 18</figref> and triangle setup unit <b>214</b>, focus shifts to the attribute setup unit <b>218</b> of <figref idref="DRAWINGS">FIG. 10</figref>. As described above, the attribute setup unit <b>218</b> also receives the wire interrupt signal on line <b>331</b>, thereby notifying the attribute setup unit <b>218</b> to immediately discard all contents related to the current context.

0140<figref idref="DRAWINGS">FIG. 20</figref> is a diagram <b>360</b> depicting a process implemented by the attribute setup unit <b>218</b> in the event of a hardwire interrupt signal being received on line <b>331</b>. In this instance, the attribute setup unit <b>218</b>, upon receiving the wire interrupt signal, operates in step <b>364</b> to read, check, and discard the TSU_FIFO memory <b>215</b> of <figref idref="DRAWINGS">FIG. 10</figref>. More specifically, the attribute setup unit <b>218</b> engages in a discard loop to discard the contents of the TSU FIFO memory <b>215</b> until reaching the interrupt end token communicated by the triangle setup unit <b>214</b>, as described above. When the DRQ state machine component of attribute setup unit <b>218</b> receives the interrupt end token, step <b>366</b> is implemented, wherein the interrupt end token is communicated to each of the ASU FIFO memory <b>220</b>, ASU/ZL<b>1</b> FIFO memory <b>219</b>, and also AFIFO memory <b>223</b>. Thereafter, the attribute setup unit <b>218</b> returns to step <b>362</b> to check the entry type of the next instruction in the TSU FIFO memory <b>215</b>, which may relate to a new context to be executed, thereby leading to normal operations in step <b>368</b>.

0141As described above, attribute setup unit <b>218</b> forwards the interrupt end token to ASU FIFO memory <b>220</b>, which is ultimately communicated to span generator unit <b>222</b>. <figref idref="DRAWINGS">FIG. 21</figref> is a diagram of the process implemented by span generator unit <b>222</b> in regard to the handling of the interrupt end token communicated down the 3D pipeline <b>176</b> of <figref idref="DRAWINGS">FIG. 10</figref>. While the span generator unit <b>222</b> may operate in step <b>372</b> to execute normal operations, upon checking the entry type in step <b>374</b> and recognizing the interrupt end token as communicated from the ASU FIFO memory <b>220</b>, the span generator unit <b>222</b> moves to step <b>376</b>. In step <b>376</b>, the interrupt end token is forwarded on to the tile generator unit <b>226</b>, thereafter causing the span generator unit <b>222</b> to return to step <b>374</b> to check the next entry type. In the case of a next context command following the interrupt end token, the span generator unit <b>222</b> may return to normal operations, as in step <b>372</b>.

0142As described above, the tile generator <b>226</b> is configured to receive a hardwire interrupt signal on line <b>331</b> communicated by CSP <b>190</b> after being issued by the processing unit <b>16</b> of <figref idref="DRAWINGS">FIG. 1</figref>. <figref idref="DRAWINGS">FIG. 22</figref> is a diagram of the process flow <b>380</b> implemented by the tile generator <b>226</b> upon receipt of an interrupt command from the CSP <b>190</b> of <figref idref="DRAWINGS">FIG. 10</figref>. When the hardwire interrupt signal is communicated to the tile generator <b>226</b> on line <b>331</b>, the tile generator <b>226</b> operates in step <b>382</b> to check the header type and the command associated with the interrupt received from CSP <b>190</b>.

0143Upon determining that an interrupt signal has been received on line <b>331</b>, the tile generator <b>226</b> moves to step <b>384</b> to immediately forward a tile generator interrupt token to the Z unit level <b>1</b> module <b>230</b> (“ZL<b>1</b> module”) in <figref idref="DRAWINGS">FIG. 10</figref>. One of ordinary skill in the art would understand, additionally, that the tile generator interrupt token that is communicated to the ZL<b>1</b> module <b>230</b> is communicated in advance of receipt of the interrupt end token being communicated down the pipeline <b>176</b>, as described above. This tile generator interrupt token is communicated so as to flush all FIFOs and caches subsequently coupled to the tile generator <b>226</b> but to otherwise allow all data in advance of the tile generator interrupt token to be processed in association with the context being saved.

0144In step <b>386</b>, the tile generator <b>226</b> engages in a discard loop to discard the input entry and check for the interrupt end token being communicated down the pipeline, as described above. Ultimately, upon execution of step <b>386</b>, the interrupt end token will reach the tile generator <b>226</b> through the 3D pipeline <b>176</b> of <figref idref="DRAWINGS">FIG. 10</figref>. At that point, the tile generator <b>226</b> moves to step <b>388</b>, as similarly described above. Thereafter, the tile generator <b>226</b> may check the header type of the next instruction communicated to determine its type and may return to normal operations as in step <b>389</b>, which may be associated with a next context that has been restored.

0145The next module in the 3D pipeline <b>176</b> of <figref idref="DRAWINGS">FIG. 10</figref> is the ZL<b>1</b> module <b>230</b>. <figref idref="DRAWINGS">FIG. 23</figref> is a flowchart diagram <b>390</b> of the ZL<b>1</b> module <b>230</b> of <figref idref="DRAWINGS">FIG. 10</figref>, as it may operate in regard to receiving a tile generator interrupt token from tile generator unit <b>226</b>.

0146In a first step <b>392</b> (read &amp; decode), the ZL<b>1</b> module <b>230</b> reads the entry from TG FIFO memory <b>227</b> and processes instructions, as received. However, in the instance when an instruction is a tile generator interrupt token, as communicated by tile generator unit <b>226</b>, the ZL<b>1</b> module <b>230</b> moves to step <b>394</b>.

0147In step <b>394</b>, the ZL<b>1</b> module <b>230</b> switches to the ASU/ZL<b>1</b> FIFO memory <b>219</b> and thereafter initiates a discard loop, as shown in step <b>396</b>. In step <b>396</b>, the ZL<b>1</b> module <b>230</b> checks and discards all entries in the ASU/ZL<b>1</b> FIFO memory <b>219</b> until reaching the interrupt end token being communicated down the 3D pipeline <b>176</b>. Upon receiving the interrupt end token, the ZL<b>1</b> module <b>230</b> moves to the AFIFO memory <b>223</b> in step <b>398</b> and subsequently initiates discard loop <b>401</b>.

0148In discard loop <b>401</b>, the ZL<b>1</b> module <b>230</b> checks and discards all entries in AFIFO memory <b>223</b> until reaching the interrupt end token contained in AFIFO memory <b>223</b>. After cleaning these two FIFO memories <b>219</b> and <b>223</b>, the ZL<b>1</b> module <b>230</b> switches to the TG FIFO memory <b>227</b> in step <b>403</b> and initiates yet another discard loop, as shown in step <b>405</b>. In step <b>405</b>, the ZL<b>1</b> module <b>230</b> checks and discards all entries in the TG FIFO memory <b>227</b> until reaching the interrupt end token in similar fashion, as described above. Thereafter, the DRQ state machine step <b>407</b> is implemented (as similarly described above) so that the ZL<b>1</b> module <b>230</b> returns to step <b>392</b> for the next instruction after the interrupt end token. Subsequently, the ZL<b>1</b> module <b>233</b> begins processing a next context in normal operation step <b>409</b>.

0149After the interrupt end token is received by ZL<b>1</b> module <b>230</b> as described above, it is forwarded to ZL<b>1</b> FIFO memory <b>232</b> and then ultimately to Z unit level <b>2</b> module (hereinafter “ZL2 module”) <b>234</b>. Unlike as described above, ZL<b>2</b> module <b>234</b> does not discard all FIFOs, but instead continues processing operations in regard to the context being saved due to the fact that continued processing can be completed within the target 1 to 2 million cycle window, that is, in at least this nonlimiting example. Nevertheless, the interrupt end token is ultimately received from the ZL<b>1</b> FIFO memory <b>232</b> representing the end of the saved context and the beginning of the new and/or restored context.

0150The interrupt end token is further communicated throughout the remaining portions of the 3D pipeline <b>176</b>, as one of ordinary skill in the art would know. As described above, the interrupt end token may be communicated to additional architectural components <b>176</b> to flush all dirty lines associated with the data preceding the interrupt end token.

0151Consequently, as disclosed herein, the graphics pipeline of the graphics processor may change states, or processing operations, as directed to increase the efficiency of graphics processing operations as a whole. In instances where a certain operation needs to wait on other information and data before concluding its own processing operation, the graphics pipeline may be interrupted and quickly oriented to execute another context or operation so that the pipeline is not idle. Thus, the graphics pipeline, as disclosed herein, may realize more efficient operation, as a nonlimiting example, by resolving situations that may previously resulted in a bottleneck in the graphics pipeline. Instead, this disclosure enables fast transitions between different contexts to avoid bottleneck situations.

0152The foregoing description has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Obvious modifications or variations are possible in light of the above teachings. The embodiments discussed, however, were chosen, and described to illustrate the principles disclosed herein and the practical application to thereby enable one of ordinary skill in the art to utilize the disclosure in various embodiments and with various modifications as are suited to the particular use contemplated. All such modifications and variation are within the scope of the disclosure as determined by the appended claims when interpreted in accordance with the breadth to which they are fairly and legally entitled.