Test system and method for parallel modulation error measurement of transceivers

BACKGROUND OF THE INVENTION

0001Each wireless communication device, such as a cellular telephone, two-way radio, personal digital assistant (PDA), pager, personal computer (PC), laptop computer, home entertainment equipment, etc., either includes a built-in radio transceiver (i.e., receiver and transmitter) or is coupled to an associated radio transceiver (e.g., a station for in-home and/or in-building wireless communication networks, RF modem, etc.). Radio transceivers are currently being integrated, in System-on-Chip (SoC) or System-in-Package (SiP), to reduce cost, size, and power, and to increase functionality. One consequence of this integration is reduced test access to the radio system's functional blocks (e.g., individual transmitter and receiver blocks). Traditionally, radio transceiver testing has relied on separate testing of each transmitter and parallel testing of multiple receivers. Thus, receiver testing has generally enjoyed the benefits of reduced test time and reduced test cost. However, with the integration of transmitters and receivers onto a single chip, the ability to test multiple receivers in parallel does not result in a decrease in test time or test cost of integrated transceivers.

0002For example, modulation accuracy of a transmitter is typically measured by a precision receiver, while demodulation accuracy of a receiver typically uses a test signal generator (source). Both the precision receiver and the precision source are expensive test instruments. Although a single precision source can simultaneously stimulate multiple transceivers, a precision receiver is only capable of measuring the output of one transceiver at a time. Therefore, attempting to test multiple transceivers in parallel would not result in a corresponding decrease in test time or test cost, because one precision receiver test instrument is still required per transceiver device under test (DUT).

0003Therefore, what is needed is a test system that allows transceiver modulation error to be tested on multiple transceiver devices in parallel without increasing the number of test instruments in proportion to the number of transceivers being tested.

SUMMARY OF THE INVENTION

0004Embodiments of the present invention provide a test system for parallel modulation error measurement of transceivers using a loop-back test configuration. Each transceiver includes a transmitter and a receiver. A signal generator generates a first modulated signal for input to the receivers of the transceivers. A tester is operable to measure a first demodulation error produced by the receiver in response to the first modulated signal and to measure a modulation error of the transmitter based on the first demodulation error and a second demodulation error. The second demodulation error is produced by the receiver in response to a second modulated signal generated by the transmitter and coupled from the transmitter to the receiver.

0005In one embodiment, the transceiver includes an internal connection connecting the transmitter to the receiver. In another embodiment, the transmitter is connected to the receiver via an interface to the tester.

0006In a further embodiment, the first modulated signal includes a plurality of symbols, each defined by a respective in-phase (I) and quadrature-phase (Q) value. The receiver is operable to demodulate the first modulated signal to produce a first output demodulated signal approximating the symbols in the first modulated signal. The first demodulation error for one of the symbols is measured as a difference between the I and Q values in the first output demodulated signal for that symbol and the I and Q values in the first modulated signal for that symbol.

0007In still a further embodiment, the receiver is operable to demodulate the second modulated signal to produce a second output demodulated signal. The modulation error for a symbol is measured as a difference between the first demodulation error for the symbol and a difference of the I and Q values in the first modulated signal that define the symbol and the I and Q values in the second output demodulated signal for the symbol.

0008By utilizing a loop-back test configuration, the test system requires only a single precision source to measure both the demodulation and modulation errors of a radio transceiver, thus eliminating the need for precision receivers to measure transmitter modulation error. As a result, the test system is capable of testing transceiver modulation error on multiple devices in parallel without increasing the number of test instruments necessary for testing.

BRIEF DESCRIPTION OF THE DRAWINGS

0009The disclosed invention will be described with reference to the accompanying drawings, which show important sample embodiments of the invention and which are incorporated in the specification hereof by reference, wherein:

0010<figref idref="DRAWINGS">FIGS. 1A and 2B</figref> are block diagrams illustrating an exemplary test system for testing multiple transceivers in parallel, in accordance with embodiments of the present invention;

0011<figref idref="DRAWINGS">FIGS. 2A and 2B</figref> are more detailed block diagrams of the exemplary test system for testing multiple transceivers in parallel, in accordance with embodiments of the present invention;

0012<figref idref="DRAWINGS">FIG. 3</figref> is a block diagram illustrating an exemplary tester for testing multiple transceivers in parallel, in accordance with embodiments of the present invention;

0013<figref idref="DRAWINGS">FIG. 4</figref> is a block diagram illustrating another exemplary test system for testing multiple transceivers in parallel, in accordance with embodiments of the present invention;

0014<figref idref="DRAWINGS">FIG. 5</figref> is a block diagram illustrating another exemplary test system for testing multiple FDD transceivers in parallel, in accordance with embodiments of the present invention;

0015<figref idref="DRAWINGS">FIG. 6</figref> is a block diagram illustrating another exemplary test system for testing multiple FDD transceivers in parallel, in accordance with embodiments of the present invention;

0016<figref idref="DRAWINGS">FIG. 7</figref> is a block diagram illustrating another exemplary test system for testing multiple FDD/TDD transceivers in parallel, in accordance with embodiments of the present invention; and

0017<figref idref="DRAWINGS">FIG. 8</figref> is a flow chart illustrating an exemplary method for testing a transceiver, in accordance with embodiments of the present invention.

DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS

0018Common transceiver tests include error-vector magnitude (EVM) for transmitter modulation and receiver demodulation accuracy, signal to noise and distortion (SINAD) for the receiver adding unwanted signals, and spectral mask for the transmitter adding unwanted signals. In general, EVM is a measure of signal quality, and provides a mechanism for uncovering at least some of the underlying causes of signal impairments and distortion.

0019Transceivers modulate signals onto a sinusoidal carrier by varying both its amplitude and phase using a process known as vector modulation. This modulation process typically includes multiple combinations of amplitude and phase, where each combination is referred to as a symbol. When displayed in polar coordinates of amplitude and phase or in rectangular coordinates of in-phase (I or cosine) component and quadrature (Q or sine) component these symbols form a regular arrangement referred to as a constellation. Each symbol has an ideal position in the constellation. Actual symbols deviate from their ideal locations by an error vector. The greater the error vector, the greater the probability of mistaking a symbol for another symbol.

0020Error vector analysis deals with patterns of the magnitude and angle of the error vectors of all the symbols in a modulation format's constellation. EVM lumps all the error vectors into a single number that is the magnitude of their vector sum.

0021<figref idref="DRAWINGS">FIG. 1A</figref> is a block diagram illustrating an exemplary EVM test system <b>10</b> for testing the receivers <b>100</b> of multiple transceiver devices under test (DUT) <b>40</b> in parallel, in accordance with embodiments of the present invention. The test system <b>10</b> includes a precision signal generator <b>20</b>, a signal splitter <b>30</b> and one or more testers <b>50</b>. The precision signal generator <b>20</b> generates a modulated test signal <b>60</b> from a test symbol sequence. The precision signal generator <b>20</b> applies the modulated test signal <b>60</b> to the transceivers <b>40</b> in parallel via the splitter <b>30</b>.

0022Each of the receivers <b>115</b> demodulates the modulated test signal to recapture inbound data in accordance with the particular wireless communication standard being implemented by the radio transceiver <b>40</b>, and provides an output demodulated signal <b>70</b>, including the recaptured inbound data (i.e., a receiver version of the test symbol sequence), to the tester <b>50</b>. The tester <b>50</b> measures the demodulation error of each receiver <b>100</b> by comparing the receiver test symbol sequence in the output demodulated signal <b>70</b> to the original test symbol sequence represented by the modulated test signal <b>60</b> generated by the precision signal generator <b>20</b>.

0023In one embodiment, the tester <b>50</b> is an external device connected to the output of one or more transceivers <b>40</b>, and the tester <b>50</b> can be implemented using various automatic test equipment (ATE), as is known in the art. In another embodiment, at least a portion of the functionality of the tester <b>50</b> is included within the transceivers <b>40</b> to reduce the test equipment needed to test multiple transceivers in parallel.

0024<figref idref="DRAWINGS">FIG. 1B</figref> is a block diagram illustrating an exemplary EVM test system for testing the transmitters <b>105</b> of multiple transceiver devices under test (DUT) <b>40</b> in parallel, in accordance with embodiments of the present invention. The test system <b>10</b> includes a digital pattern generator <b>230</b>, a signal splitter <b>35</b> and one or more testers <b>50</b>. The digital pattern generator <b>230</b> generates a test symbol sequence <b>200</b> that stimulates one or more of the transceivers <b>40</b> in parallel via a splitter (not shown). In other embodiments, the test symbol sequence <b>200</b> is generated internally by the individual transceivers <b>40</b>.

0025In testing operation, each transceiver <b>40</b> receives the test symbol sequence <b>200</b> from the digital pattern generator <b>230</b> via the splitter <b>35</b>. The digital pattern generator <b>230</b> feeds the test symbol sequence <b>200</b> to the transmitters <b>105</b> of each of the transceivers <b>40</b>. The transmitters <b>105</b> each process the test symbol sequence <b>200</b> in accordance with a respective particular wireless communication standard to produce a respective outbound modulated transmitter signal. The outbound modulated transmitter signal of each transmitter is input to the respective receiver <b>100</b> of each transceiver <b>40</b> via a respective loop-back connection <b>240</b>.

0026In one embodiment, the loop-back connection <b>240</b> is provided within the transceiver <b>40</b>. In another embodiment, the loop-back connection <b>240</b> is provided externally by a DUT interface, e.g., the loadboard or probecard in package or wafer test, respectively, to the tester <b>50</b>.

0027Each receiver <b>100</b> demodulates the respective outbound modulated transmitter signal in accordance with the particular wireless communication standard being implemented by the radio transceiver <b>40</b>, and provides an additional respective output demodulated signal <b>220</b> that represents a recovered test symbol sequence to the tester <b>50</b>. For each transceiver <b>40</b>, the tester <b>50</b> measures the combined modulation error of the transmitter <b>105</b> and receiver <b>100</b> by comparing the recovered test symbol sequence in the additional output demodulated signal <b>220</b> to the original test symbol sequence <b>200</b> input to the transmitter <b>105</b> to determine the measured error. The known demodulation error of the receiver is subtracted from the measured error to obtain the transmitter modulation error.

0028<figref idref="DRAWINGS">FIG. 2A</figref> is a more detailed block diagram illustrating an exemplary EVM test system <b>10</b> for testing the receiver <b>100</b> of one of the multiple transceiver devices under test (DUT) <b>40</b>, in accordance with embodiments of the present invention. As described above in connection with <figref idref="DRAWINGS">FIG. 1A</figref>, the test system <b>10</b> includes the precision signal generator <b>20</b>, the splitter <b>30</b> and one or more testers <b>50</b>. The precision signal generator <b>20</b> generates a modulated test signal <b>60</b> from a test symbol sequence. The precision signal generator <b>20</b> applies the modulated test signal <b>60</b> to the transceivers <b>40</b> (only one of which is shown for simplicity) in parallel via the splitter <b>30</b>.

0029The transceiver DUT <b>40</b> includes a receiver <b>100</b>, a frequency synthesizer <b>125</b> and a digital baseband processor <b>115</b>. The digital baseband processor <b>115</b> performs various digital receiver functions, including, but not limited to, demodulation, constellation demapping, decoding, and/or descrambling.

0030Receiver <b>100</b> includes a low noise amplifier <b>110</b>, a bandpass filter <b>120</b>, mixers <b>130</b> and <b>135</b>, anti-aliasing filters <b>140</b> and <b>145</b> and analog-to-digital converters <b>150</b> and <b>155</b>. In testing operation, the receiver <b>100</b> receives the precision modulated inbound RF signal <b>60</b> from the precision signal generator <b>20</b> via the splitter <b>30</b>, and provides the precision modulated inbound RF signal <b>60</b> to the low noise amplifier (LNA) <b>110</b>. The LNA <b>110</b> amplifies the precision modulated inbound RF signal <b>60</b> to produce an amplified inbound RF signal. The LNA <b>110</b> provides the amplified inbound RF signal to the bandpass filter <b>120</b>. The bandpass filter <b>120</b> isolates the frequency band of interest in the amplified inbound RF signal to produce a bandpass filtered inbound RF signal. The bandpass filtered inbound RF signal is provided to mixers <b>130</b> and <b>135</b>. Mixers <b>130</b> and <b>135</b> down-convert the bandpass filtered inbound RF signal into inbound baseband in-phase (I) and quadrature-phase (Q) signals, respectively, using cosine and sine local oscillator signals provided by the frequency synthesizer <b>125</b>.

0031The mixers <b>130</b> and <b>135</b> provide the I and Q inbound baseband signals to respective anti-aliasing filters <b>140</b> and <b>145</b> to filter and/or attenuate aliasing signals out of the I and Q inbound baseband signals to produce filtered inbound I and Q signals. The analog-to-digital converters <b>150</b> and <b>155</b> convert the filtered inbound I and Q signals, respectively, from the analog domain to the digital domain to produce a digital baseband signal. The receiver <b>100</b> architecture shown in <figref idref="DRAWINGS">FIG. 1</figref> is merely illustrative of common receiver <b>100</b> architectures, and the present invention is not limited to any particular receiver <b>100</b> architecture.

0032The digital baseband processor <b>115</b> decodes, descrambles, demaps, and/or demodulates the digital baseband signal to recapture inbound data in accordance with the particular wireless communication standard being implemented by the radio transceiver <b>40</b>, and provides an output demodulated signal <b>70</b>, including the recaptured inbound data (i.e., receiver version of the test symbol sequence), to the tester <b>50</b>. The tester <b>50</b> measures the demodulation error of the receiver <b>100</b> by comparing the receiver test symbol sequence in the output demodulated signal <b>70</b> to the original test symbol sequence represented by the modulated test signal <b>60</b> generated by the precision signal generator <b>20</b>.

0033For example, in one embodiment, the tester <b>50</b> measures the demodulation error for each symbol as a difference between the I and Q values in the output demodulated signal <b>70</b> and the I and Q values that define the symbol in the modulated test signal <b>60</b>. Since the symbols have precisely defined I and Q coordinates in the signal used to modulate the modulated test signal <b>60</b> produced by the precision signal generator <b>20</b>, the demodulation error at each symbol can be fairly represented by the difference between the I and Q values in the output demodulated signal <b>70</b> output by the receiver <b>100</b> and the I and Q values that define the symbol in the modulated test signal <b>60</b>. The demodulation errors for the symbols in the test symbol sequence are used to compute the error vector magnitude (EVM).

0034<figref idref="DRAWINGS">FIG. 2B</figref> is a more detailed block diagram illustrating an exemplary EVM test system <b>10</b> for testing the transmitter <b>105</b> of one of the multiple transceiver devices under test (DUT) <b>40</b>, in accordance with embodiments of the present invention. As described above in connection with <figref idref="DRAWINGS">FIG. 1B</figref>, the test system <b>10</b> includes the digital pattern generator <b>230</b>, the splitter <b>35</b> and one or more testers <b>50</b>. The digital pattern generator <b>230</b> generates a test symbol sequence <b>200</b> that is applied to the transmitters <b>105</b> of one or more of the transceivers <b>40</b> (only one of which is shown for simplicity) in parallel via the splitter <b>35</b>. In other embodiments, the test symbol sequence <b>200</b> is generated internally by the digital baseband processors <b>115</b> of the individual transceivers <b>40</b>.

0035The transceiver DUT <b>40</b> includes the receiver <b>100</b>, the frequency synthesizer <b>125</b>, the digital baseband processor <b>115</b> and a transmitter <b>105</b>. The digital baseband processor <b>115</b> performs the digital receiver functions described above in connection with <figref idref="DRAWINGS">FIG. 1</figref> and also performs various digital transmitter functions, including, but not limited to, scrambling, encoding, constellation mapping and modulation.

0036Transmitter <b>105</b> includes digital-to-analog converters <b>160</b> and <b>165</b>, reconstruction filters <b>170</b> and <b>175</b>, mixers <b>180</b> and <b>185</b>, a summing node <b>190</b>, a bandpass filter <b>195</b> and a power amplifier <b>198</b>. In testing operation, the transceiver <b>40</b> receives the test symbol sequence <b>200</b> from the digital pattern generator <b>230</b>. The digital pattern generator <b>230</b> feeds the test symbol sequence <b>200</b> to the digital baseband processor <b>115</b>. The digital baseband processor <b>115</b> processes the outbound data <b>200</b> in accordance with a particular wireless communication standard to produce digital transmission formatted I and Q data. The digital transmission formatted I and Q data is typically a digital baseband signal.

0037The digital-to-analog converters <b>160</b> and <b>165</b> convert the digital transmission formatted I and Q data, respectively, from the digital domain to the analog domain to produce baseband I and Q analog signals. The reconstruct filters <b>170</b> and <b>175</b> reconstruct (e.g., smooth) the baseband I and Q analog signals prior to providing them to the up-conversion mixers <b>180</b> and <b>185</b>. The up-conversion mixers <b>180</b> and <b>185</b> directly convert the baseband I and Q analog signals, respectively, into I and Q RF signals using cosine and sine local oscillator signals provided by the frequency synthesizer <b>125</b>.

0038The outputs of mixers <b>180</b> and <b>185</b> are fed to a summation node <b>190</b> that produces an outbound modulated RF signal. The outbound modulated RF signal is input to the bandpass filter <b>195</b> to isolate the frequency range interest in the outbound RF modulated signal to produce a filtered outbound RF signal. The power amplifier <b>195</b> amplifies the filtered outbound RF signal to produce an outbound modulated transmitter signal <b>210</b>. The outbound modulated transmitter signal <b>210</b> is input to the receiver <b>100</b> of the transceiver <b>40</b> via a loop-back connection <b>240</b>. In exemplary embodiments, the loop-back connection includes a variable attenuator.

0039In one embodiment, the loop-back connection <b>240</b> is provided internally within the transceiver <b>40</b> from the power amplifier <b>198</b> to the LNA <b>110</b>. In another embodiment, the loop-back connection <b>240</b> is provided externally by a DUT interface, e.g., the loadboard or probecard in package or wafer test, respectively, to the tester <b>50</b>.

0040The transmitter <b>105</b> architecture shown in <figref idref="DRAWINGS">FIG. 2</figref> is merely illustrative of common transmitter <b>105</b> architectures, and the present invention is not limited to any particular transmitter <b>105</b> architecture. In addition, one or more of the power amplifier <b>198</b>, LNA <b>110</b> and RF bandpass filters <b>195</b> and <b>120</b> can be located external to the transceiver chip. As a result, the loop-back connection <b>240</b> is not limited to a connection between any two particular components in the transmitter <b>105</b> and the receiver <b>100</b>. For example, the loop-back connection <b>240</b> can be made between the RF bandpass filters <b>195</b> and <b>120</b> or from the summation node <b>190</b> to the mixers <b>130</b> and <b>135</b>.

0041The receiver <b>100</b> produces a digital baseband signal from the outbound modulated transmitter signal <b>210</b> and provides the digital baseband signal to the digital baseband processor <b>115</b> for decoding, descrambling, demapping, and/or demodulating the digital baseband signal to produce an output demodulated signal <b>220</b> that represents a recovered test symbol sequence. The output demodulated signal <b>220</b> is input to the tester <b>50</b>, which measures the combined modulation error of the transmitter <b>105</b> and the receiver <b>100</b> by comparing the recovered test symbol sequence in the output demodulated signal <b>220</b> to the original test symbol sequence <b>200</b> input to the transmitter <b>105</b>. The known demodulation error of the receiver is subtracted from the combined modulation error to obtain the transmitter modulation error.

0042For example, in one embodiment, the tester <b>50</b> measures the combined modulation error of the transmitter <b>105</b> and the receiver <b>100</b> by subtracting the symbol's defining I and Q coordinates from the actual (recovered) values output by the receiver <b>100</b>. The combined modulation error includes the combined errors of both the modulator and the demodulator. Since the demodulation error of the receiver <b>100</b> has been measured, and is therefore known, the demodulation error is subtracted symbol by symbol from the combined modulation error to extract the transmitter modulation error. Thus, the transmitter modulation error is measured for each symbol as a difference between the known symbol demodulation error for that symbol and the combined measured error for that symbol, in which the combined measured error is a difference between the recovered I and Q values represented by the output demodulated signal <b>220</b> and the symbol I and Q values in the test symbol sequence <b>200</b>. The demodulation errors for the symbols in the test symbol sequence are used to compute the error vector magnitude (EVM).

0043<figref idref="DRAWINGS">FIG. 3</figref> is a block diagram illustrating an exemplary embodiment of a tester <b>50</b> for testing multiple transceivers in parallel, in accordance with embodiments of the present invention. As mentioned above in connection with <figref idref="DRAWINGS">FIGS. 1 and 2</figref>, all or part of the tester <b>50</b> can be an external device connected to the output of the digital baseband processor <b>115</b> of one or more transceivers <b>40</b>. Alternatively, all or a part of the tester <b>50</b> can constitute part of the digital baseband processor <b>115</b> to reduce the test equipment needed to test multiple transceivers in parallel. The tester <b>50</b> includes a I/O unit <b>310</b>, a processor <b>320</b> and memory <b>330</b>. The I/O unit <b>310</b> is coupled to receive the output demodulated signal labeled <b>70</b> from the receiver <b>100</b> (shown in <figref idref="DRAWINGS">FIGS. 1A and 2A</figref>) during receiver testing and the output demodulated signal labeled <b>220</b> from the receiver <b>100</b> (shown in <figref idref="DRAWINGS">FIGS. 1B and 2B</figref>) during transmitter testing.

0044The I/O unit <b>310</b> passes the output demodulated signal <b>70</b> to the processor <b>320</b> to measure the demodulation error of the receiver of the transceiver and passes the output demodulated signal <b>220</b> to the processor <b>320</b> to measure the modulation error of the transmitter of the transceiver. The processor <b>320</b> measures the demodulation error of the receiver by comparing the receiver test symbol sequence in the output demodulated signal <b>70</b> to an original test symbol sequence <b>350</b> stored in the memory <b>330</b>. The original test symbol sequence <b>350</b> corresponds to the test symbol sequence used in the precision signal generator's <b>20</b> modulated test signal <b>60</b>, shown in <figref idref="DRAWINGS">FIG. 1</figref>. The processor <b>320</b> stores the measured receiver demodulation error <b>360</b> in the memory <b>330</b> for subsequent use in measuring the modulation error <b>370</b> of the transmitter based on the additional output demodulated signal <b>220</b>. For example, in one embodiment, the transmitter modulation error <b>370</b> is computed by subtracting the receiver demodulation error from the difference between the I and Q values of the original test symbol sequence <b>350</b> and the recovered test symbol sequence represented by the output demodulated signal <b>220</b>. The demodulation error <b>360</b> and the modulation error <b>370</b> can be output to another device (e.g., a display) via I/O unit <b>310</b>.

0045When implemented as part of the digital baseband processor <b>115</b> on the transceiver <b>40</b> (shown in <figref idref="DRAWINGS">FIGS. 2A and 2B</figref>), the processor <b>320</b> and digital baseband processor <b>115</b> can be implemented using a shared processing device or respective individual processing devices. The memory <b>330</b> stores software <b>385</b> (e.g., operating instructions) corresponding to at least part of the functions discussed herein.

0046The loop-back test configuration illustrated in <figref idref="DRAWINGS">FIGS. 1B and 2B</figref> is most easily applicable to a transceiver capable of transmitting and receiving simultaneously on the same frequency. However, the loop-back test configuration of the present invention is also applicable to other transceivers employing time division duplexing (TDD) and/or frequency division duplexing (FDD). To accommodate TDD and/or FDD transceivers, various test resources are provided externally, some of which could be provided on the DUT interface (e.g., probecard or loadboard).

0047<figref idref="DRAWINGS">FIG. 4</figref> is a block diagram illustrating another exemplary test system for testing multiple transceivers in parallel, in accordance with embodiments of the present invention. Transceivers operating in time-division duplex (TDD) mode do not need to be designed to avoid the detrimental effects of signal coupling between the transmitter and the receiver. Thus, TDD transceivers are usually not capable of simultaneously transmitting and receiving. However, if the circuits in a TDD transceiver are designed to avoid or tolerate coupling between the transmitter and the receiver, such transceivers can be capable of simultaneous transmission and reception in a test mode, even though they do not operate with simultaneous transmission and reception in the TDD protocol. In a typical TDD radio transceiver architecture, cost is usually reduced by sharing components between the transmitter <b>105</b> and the receiver <b>100</b>. For example, the frequency synthesizer <b>125</b> and digital baseband processor <b>115</b> are two common shared components. In order to implement the loop-back test configuration of the present invention in a TDD transceiver that is designed to avoid or tolerate coupling between the transmitter and the receiver, the shared components are duplicated externally in either the transmit or receive paths to override the TDD mode and permit loop-back testing.

0048In such a TDD transceiver, as shown in <figref idref="DRAWINGS">FIG. 4</figref>, the shared LO <b>125</b> is used simultaneously by the transmitter <b>105</b> and the receiver <b>100</b> during test. However, an external digital baseband processor <b>410</b> is provided to enable simultaneous transmission and reception processing during transmitter modulation testing. Switches <b>400</b> and <b>405</b> enable switching between the internal digital baseband processor <b>115</b> and the external digital baseband processor <b>410</b>. For example, in receiver demodulation testing mode, switches <b>400</b> and <b>405</b> switch the I and Q digital signals to the internal digital baseband processor <b>115</b>, while in transmitter modulation testing mode, switches <b>400</b> and <b>405</b> switch the I and Q digital signals to the external digital baseband processor <b>410</b>.

0049<figref idref="DRAWINGS">FIG. 5</figref> is a block diagram illustrating another exemplary test system for testing multiple frequency-division duplexing (FDD) transceivers (only one of which is shown for simplicity) in parallel, in accordance with embodiments of the present invention. Mobile radio transceivers that communicate with a base station typically transmit and receive on different frequencies using FDD. As a result, during transceiver testing, the transmit frequency must be translated to the receive frequency for proper operation. As shown in <figref idref="DRAWINGS">FIG. 5</figref>, the frequency translation is provided by an external difference frequency oscillator <b>500</b>, an external mixer <b>510</b> and an external anti-alias bandpass filter <b>520</b>. The configuration of <figref idref="DRAWINGS">FIG. 5</figref> maintains high parallelism by sharing the external difference frequency oscillator <b>500</b> among all transceiver DUTs <b>40</b>. However, the configuration of <figref idref="DRAWINGS">FIG. 5</figref> does require an external mixer <b>510</b> and anti-alias filter <b>520</b> for each transceiver DUT <b>40</b> tested simultaneously.

0050<figref idref="DRAWINGS">FIG. 6</figref> is a block diagram illustrating another exemplary test system for testing multiple FDD transceivers (only one of which is shown for simplicity) in parallel, in accordance with embodiments of the present invention. In transceiver architectures in which the receiver and transmitter have separate local oscillators (LOs), as shown in <figref idref="DRAWINGS">FIG. 6</figref>, the LOs are designed so that their tuning ranges are capable of overlapping during testing. Designing the transmit and receive frequency synthesizers <b>125</b><i>a </i>and <b>125</b><i>b, </i>respectively, to overlap or causing the transmit and receive frequency synthesizer <b>125</b><i>a </i>and <b>125</b><i>b </i>to overlap during testing maintains the highest parallel use of external test resources at the cost of expanding the bandwidth of the receiver chain for test purposes. However, the RF bandpass filters <b>195</b> and <b>120</b> cannot be designed so that their pass bands overlap. Therefore, during test, one of the RF bandpass filters <b>195</b> or <b>120</b> is bypassed. In <figref idref="DRAWINGS">FIG. 6</figref>, the transceiver DUT <b>40</b> is designed to include a switch <b>610</b> in the receiver <b>100</b> that enables bypass of the RF bandpass filter <b>120</b> during testing.

0051<figref idref="DRAWINGS">FIG. 7</figref> is a block diagram illustrating another exemplary test system for testing multiple FDD/TDD transceivers (only one of which is shown for simplicity) in parallel, in accordance with embodiments of the present invention. In architectures where the LO frequency synthesizer <b>125</b> is shared, as in FDD with TDD transceivers, the transceiver DUT <b>40</b> can be designed to include connection between either the receive or transmit path and the output of an external LO frequency synthesizer <b>700</b>. In <figref idref="DRAWINGS">FIG. 7</figref>, the transceiver DUT <b>40</b> is designed to include switches <b>710</b> and <b>720</b> that enable switching between the internal frequency synthesizer <b>125</b> and the external frequency synthesizer <b>700</b>. For example, in receiver demodulation testing mode, switches <b>710</b> and <b>720</b> switch to the internal frequency synthesizer <b>125</b>, while in transmitter modulation testing mode, switches <b>710</b> and <b>720</b> can switch to the external frequency synthesizer <b>700</b>.

0052In addition, the transceiver DUT <b>40</b> shown in <figref idref="DRAWINGS">FIG. 7</figref> is designed to include an external digital baseband processor <b>410</b> to enable simultaneous transmission and reception processing during transmitter modulation testing, as described above in connection with <figref idref="DRAWINGS">FIG. 4</figref>. Although the external synthesizer <b>700</b> can be shared among the transceiver DUTs <b>40</b>, one external baseband processor <b>410</b> is required per transceiver DUT <b>40</b>. Furthermore, as in <figref idref="DRAWINGS">FIG. 6</figref>, the transceiver DUT <b>40</b> is designed to include switch <b>610</b> that enables bypass of the RF bandpass filter <b>120</b> during testing.

0053<figref idref="DRAWINGS">FIG. 8</figref> is a flow chart illustrating an exemplary method <b>800</b> for testing a transceiver, in accordance with embodiments of the present invention. To measure the demodulation error of a receiver of an integrated transceiver, a modulated test signal is received at the receiver from a precise signal generator at step <b>810</b>. The receiver demodulates the modulated test signal and outputs a demodulated signal to a tester for measuring the demodulation error of the receiver at step <b>820</b>. For example, in one embodiment, the tester measures the demodulation error for each symbol as a difference between the symbol I and Q values in the output demodulated signal and the symbol I and Q values in the modulated test signal.

0054At step <b>830</b>, the transmitter of the integrated transceiver produces an outbound modulated transmitter signal from an original test symbol signal, and inputs the outbound modulation signal to the receiver via a loop-back connection at step <b>840</b>. The receiver demodulates the outbound modulated transmitter signal to produce an output demodulated signal, from which the modulation error of the transmitter is measured based on the known demodulation error of the receiver at step <b>850</b>. For example, in one embodiment, the transmitter modulation error is computed by subtracting the demodulation error of the receiver from the difference between the original test symbol signal and the output demodulated signal produced in response to the outbound modulated transmitter signal. Using the loop-back test configuration, multiple transceivers can be tested in parallel using the same precision signal generator without requiring separate precision receivers for each transceiver.

0055As will be recognized by those skilled in the art, the innovative concepts described in the present application can be modified and varied over a wide rage of applications. Accordingly, the scope of patents subject matter should not be limited to any of the specific exemplary teachings discussed, but is instead defined by the following claims.