Pinned photodiode fabricated with shallow trench isolation
Claim Score by NHIP
Abstract
A method and system is disclosed for reducing or eliminating leakage between a pinned photodiode and shallow trench isolation structure fabricated therewith while optimizing the sensitivity of the photodiode. Provided is a system with an N+ region implanted in a P-type substrate; a P-type well separating the N+ region from the shallow trench isolation (STI) structure; and at least a P+ region over the N+ region, and overlapping at least part of the P-type well and a substrate portion between the N+ region and P-type well. The space between the N+ region and a damaged region adjacent the STI is greater than the distance that the depletion region between the N+ region and the P-type well, expands. The junctions of the various features are optimized to maximize a photosensitive response for the wavelength of the absorbed light as well as reducing or eliminating electrical leakage.

Term
Term ended
Projected expiry passed 19 September 2025, 1 year ago.
- Priority and filed
- Published
- Projected expiry
- Today
28 claims: 6 independent, 22 dependent
- 1A semiconductor structure to reduce or eliminate electrical leakage between a pinned photodiode and a shallow trench isolation structure, the semiconductor structure comprising:a first region of a first impurity type formed beneath a surface of a semiconductor substrate of a second impurity type and disposed between shallow trench isolation (STI) structures;a semiconductor well of a second impurity type laterally separating the first region from each of the STI structures and including a damaged portion adjacent each STI structure and facing the first region;a substrate portion of the semiconductor substrate interposed between the first region and each of the semiconductor wells;a second region of the second impurity type covering the first region and each substrate portion and overlapping at least part of each of the semiconductor wells, the second region formed within the semiconductor substrate and extending downwardly from the surface;an expandable depletion region formed along a boundary between the first region and each substrate portion, a lateral spacing between the first region and each of the adjacent damaged portions sufficient to prevent the depletion region from expanding into the damaged portions at a maximum expansion of the depletion region, and the first region having a lower boundary more than about 0.8 microns below the surface.
- 1A semiconductor structure to reduce or eliminate electrical leakage between a pinned photodiode and a shallow trench isolation structure, the semiconductor structure comprising:a first region of a first impurity type formed beneath a surface of a semiconductor substrate of a second impurity type and disposed between shallow trench isolation (STI) structures;a semiconductor well of a second impurity type laterally separating the first region from each of the STI structures and including a damaged portion adjacent each STI structure and facing the first region;a substrate portion of the semiconductor substrate interposed between the first region and each of the semiconductor wells;a second region of the second impurity type covering the first region and each substrate portion and overlapping at least part of each of the semiconductor wells, the second region formed within the semiconductor substrate and extending downwardly from the surface;an expandable depletion region formed along a boundary between the first region and each substrate portion, a lateral spacing between the first region and each of the adjacent damaged portions sufficient to prevent the depletion region from expanding into the damaged portions at a maximum expansion of the depletion region, and the first region having a lower boundary more than about 0.8 microns below the surface.
- 8A semiconductor structure to reduce or eliminate electrical leakage between a pinned photodiode and a shallow trench isolation structure, the semiconductor structure comprising:a first region of a first impurity type formed beneath a surface of a semiconductor substrate of a second impurity type and disposed between shallow trench isolation (STI) structures;a semiconductor well of a second impurity type laterally separating the first region from each of the STI structures and including a damaged portion adjacent each STI structure and facing the first region;a substrate portion of the semiconductor substrate interposed between the first region and each of the semiconductor wells;a second region of the second impurity type covering the first region and each substrate portion and overlapping at least part of each of the semiconductor wells, the second region formed within the semiconductor substrate and extending downwardly from the surface;an expandable depletion region formed along a boundary between the first region and the substrate portion, a lateral spacing between the first region and each of the adjacent damaged portions sufficient to prevent the depletion region from expanding into the damaged portions at a maximum expansion of the depletion region, and the first region having a lower boundary at substantially the same depth as a lower boundary of the semiconductor wells and disposed about 0.2 to 0.8 microns below the surface.
- 8A semiconductor structure to reduce or eliminate electrical leakage between a pinned photodiode and a shallow trench isolation structure, the semiconductor structure comprising:a first region of a first impurity type formed beneath a surface of a semiconductor substrate of a second impurity type and disposed between shallow trench isolation (STI) structures;a semiconductor well of a second impurity type laterally separating the first region from each of the STI structures and including a damaged portion adjacent each STI structure and facing the first region;a substrate portion of the semiconductor substrate interposed between the first region and each of the semiconductor wells;a second region of the second impurity type covering the first region and each substrate portion and overlapping at least part of each of the semiconductor wells, the second region formed within the semiconductor substrate and extending downwardly from the surface;an expandable depletion region formed along a boundary between the first region and the substrate portion, a lateral spacing between the first region and each of the adjacent damaged portions sufficient to prevent the depletion region from expanding into the damaged portions at a maximum expansion of the depletion region, and the first region having a lower boundary at substantially the same depth as a lower boundary of the semiconductor wells and disposed about 0.2 to 0.8 microns below the surface.
- 15A semiconductor structure to reduce or eliminate electrical leakage between a pinned photodiode and a shallow trench isolation structure, the semiconductor structure comprising:a first region of a first impurity type formed beneath a surface of a semiconductor substrate of a second impurity type and disposed between shallow trench isolation (STI) structures,;a semiconductor well of a second impurity type laterally separating the first region from each of the STI structures and including a damaged portion adjacent each STI structure and facing the first region;a substrate portion of the semiconductor substrate interposed between the first region and each of the semiconductor wells;a second region of the second impurity type covering the first region and each substrate portion and overlapping at least part of each of the semiconductor wells, the second region formed within the semiconductor substrate and extending downwardly from the surface to a depth no more than about 0.2 microns;an expandable depletion region formed along a boundary between the first region and the substrate portion, and a lateral spacing between the first region and each of the adjacent damaged portions sufficient to prevent the depletion region from expanding into the damaged portions at a maximum expansion of the depletion region, wherein the first impurity type is N-type and the second impurity type is P-type.
- 15A semiconductor structure to reduce or eliminate electrical leakage between a pinned photodiode and a shallow trench isolation structure, the semiconductor structure comprising:a first region of a first impurity type formed beneath a surface of a semiconductor substrate of a second impurity type and disposed between shallow trench isolation (STI) structures,;a semiconductor well of a second impurity type laterally separating the first region from each of the STI structures and including a damaged portion adjacent each STI structure and facing the first region;a substrate portion of the semiconductor substrate interposed between the first region and each of the semiconductor wells;a second region of the second impurity type covering the first region and each substrate portion and overlapping at least part of each of the semiconductor wells, the second region formed within the semiconductor substrate and extending downwardly from the surface to a depth no more than about 0.2 microns;an expandable depletion region formed along a boundary between the first region and the substrate portion, and a lateral spacing between the first region and each of the adjacent damaged portions sufficient to prevent the depletion region from expanding into the damaged portions at a maximum expansion of the depletion region, wherein the first impurity type is N-type and the second impurity type is P-type.
- 21A method to reduce or eliminate electrical leakage between a pinned photodiode and shallow trench isolation fabricated therewith, the method comprising:implanting N+ impurities to form an N+ region beneath a surface of a P-type semiconductor substrate;forming at least one shallow trench isolation (STI) structure in the semiconductor substrate;forming at least one P-type well laterally separating the first region from each STI structure wherein a substrate portion of the semiconductor substrate remains interposed between the N+ region and each P-type well and the P-type well includes a damaged portion adjacent the STI and facing the N+ region;forming a P+ region covering the N+ region and each substrate portion and overlapping at least part of each P-type well, the P+ region formed within the semiconductor substrate and extending downwardly from the surface;creating an expandable depletion region along a boundary between the N+ region and the substrate portion, laterally spacing the N+ region from each adjacent damaged portion by a distance sufficient to prevent the depletion region from expanding into the associated damaged portion when the depletion region expands to a maximum expansion width, and the first region having a lower boundary more than about 0.8 microns below the surface.
- 21A method to reduce or eliminate electrical leakage between a pinned photodiode and shallow trench isolation fabricated therewith, the method comprising:implanting N+ impurities to form an N+ region beneath a surface of a P-type semiconductor substrate;forming at least one shallow trench isolation (STI) structure in the semiconductor substrate;forming at least one P-type well laterally separating the first region from each STI structure wherein a substrate portion of the semiconductor substrate remains interposed between the N+ region and each P-type well and the P-type well includes a damaged portion adjacent the STI and facing the N+ region;forming a P+ region covering the N+ region and each substrate portion and overlapping at least part of each P-type well, the P+ region formed within the semiconductor substrate and extending downwardly from the surface;creating an expandable depletion region along a boundary between the N+ region and the substrate portion, laterally spacing the N+ region from each adjacent damaged portion by a distance sufficient to prevent the depletion region from expanding into the associated damaged portion when the depletion region expands to a maximum expansion width, and the first region having a lower boundary more than about 0.8 microns below the surface.
- 25Broadest claimClaim Score 42, average(NHIP)A method to reduce or eliminate electrical leakage between a pinned photodiode and shallow trench isolation fabricated therewith, the method comprising:implanting N+ impurities to form an N+ region beneath a surface of a P-type semiconductor substrate;forming at least one shallow trench isolation (STI) structure in the semiconductor substrate;forming at least one P-type well laterally separating the first region from each STI structure wherein a substrate portion of the semiconductor substrate remains interposed between the N+ region and each P-type well and the P-type well includes a damaged portion adjacent the STI and facing the N+ region;forming a P+ region covering the N+ region and each substrate portion and overlapping at least part of each P-type well, the P+ region formed within the semiconductor substrate and extending downwardly from the surface;creating an expandable depletion region along a boundary between the N+ region and the substrate portion, laterally spacing the N+ region from each adjacent damaged portion by a distance sufficient to prevent the depletion region from expanding into the associated damaged portion when the depletion region expands to a maximum expansion, and forming the P+ region to have a lower boundary extending no more than 0.2 microns below the surface.
- 25Broadest claimClaim Score 42, average(NHIP)A method to reduce or eliminate electrical leakage between a pinned photodiode and shallow trench isolation fabricated therewith, the method comprising:implanting N+ impurities to form an N+ region beneath a surface of a P-type semiconductor substrate;forming at least one shallow trench isolation (STI) structure in the semiconductor substrate;forming at least one P-type well laterally separating the first region from each STI structure wherein a substrate portion of the semiconductor substrate remains interposed between the N+ region and each P-type well and the P-type well includes a damaged portion adjacent the STI and facing the N+ region;forming a P+ region covering the N+ region and each substrate portion and overlapping at least part of each P-type well, the P+ region formed within the semiconductor substrate and extending downwardly from the surface;creating an expandable depletion region along a boundary between the N+ region and the substrate portion, laterally spacing the N+ region from each adjacent damaged portion by a distance sufficient to prevent the depletion region from expanding into the associated damaged portion when the depletion region expands to a maximum expansion, and forming the P+ region to have a lower boundary extending no more than 0.2 microns below the surface.
- 27A method to reduce or eliminate electrical leakage between a pinned photodiode and shallow trench isolation fabricated therewith, the method comprising:implanting N+ impurities to form an N+ region beneath a surface of a P-type semiconductor substrate;forming at least one shallow trench isolation (STI) structure in the semiconductor substrate;forming at least one P-type well laterally separating the first region from each STI structure wherein a substrate portion of the semiconductor substrate remains interposed between the N+ region and each P-type well and the P-type well includes a damaged portion adjacent the STI and facing the N+ region;forming a P+ region covering the N+ region and each substrate portion and overlapping at least part of each P-type well, the P+ region formed within the semiconductor substrate and extending downwardly from the surface;creating an expandable depletion region along a boundary between the N+ region and the substrate portion, laterally spacing the N+ region from each adjacent damaged portion by a distance sufficient to prevent the depletion region from expanding into the associated damaged portion when the depletion region expands to a maximum expansion, and forming each of the first region and each at least one P-type well to have the substantially same lower boundary being about 0.2 to 0.8 microns below the surface.
- 27A method to reduce or eliminate electrical leakage between a pinned photodiode and shallow trench isolation fabricated therewith, the method comprising:implanting N+ impurities to form an N+ region beneath a surface of a P-type semiconductor substrate;forming at least one shallow trench isolation (STI) structure in the semiconductor substrate;forming at least one P-type well laterally separating the first region from each STI structure wherein a substrate portion of the semiconductor substrate remains interposed between the N+ region and each P-type well and the P-type well includes a damaged portion adjacent the STI and facing the N+ region;forming a P+ region covering the N+ region and each substrate portion and overlapping at least part of each P-type well, the P+ region formed within the semiconductor substrate and extending downwardly from the surface;creating an expandable depletion region along a boundary between the N+ region and the substrate portion, laterally spacing the N+ region from each adjacent damaged portion by a distance sufficient to prevent the depletion region from expanding into the associated damaged portion when the depletion region expands to a maximum expansion, and forming each of the first region and each at least one P-type well to have the substantially same lower boundary being about 0.2 to 0.8 microns below the surface.
Independent claims12
30 paragraphs in 4 sections, as filed
BACKGROUND
The present invention relates generally to integrated circuit designs, and more particularly to a system reducing or eliminating leakage between a pinned photodiode and shallow trench isolation fabricated therewith.
Semiconductor integrated circuit (IC) chips can be produced to function as image photosensors for image applications such as camera devices. A semiconductor photosensor produces signals that are proportional to light images by reading a predetermined number of individual pixels of an image. At least one device, such as a photodiode, is required for each pixel. By further incorporating a plurality of electronic reading and decoding circuitries, an array of image photosensors may digitally record an image with a predetermined pixel resolution.
Charge coupled devices (CCD) have been produced for this purpose with pinned photodiodes. In a pinned photodiode, a N+ region acts as a pixel sensor and is isolated from the surface of the IC by a P+ region. However, CCDs are typically difficult to integrate with logic circuits that might include metal-oxide-semiconductor field-effect-transistors (MOSFETs). Since MOSFETs are typically constructed with shallow trench isolation (STI), which is proved to be quite difficult to be integrated with pinned photodiodes, their mutual existence has been a challenging question for IC designers. In theory, STI is a device isolation structure of channels that are typically filled with oxide. The semiconductor crystal sidewalls of STI are damaged by the dry etch that is used to produce them. The sidewalls are further damaged by stresses that arise from the extreme temperature cycles that occur in semiconductor processing. The difficulty is that such damage causes electrical leakage if an electrical junction expands to such a damaged region.
Any electrical leakage appears as a signal in darkness. Such dark current reduces sensitivity and the quality of image depiction. Dark current can be generated by several typical structures in semiconductor devices. Electrical junctions that meet the oxide-covered surface are imperfect and can generate dark current. Shallow trench isolation between devices is produced by dry etching that damages the semiconductor crystal. If that damaged material is included in a junction depletion region, dark current can be generated.
Dark current is a bane of camera image quality. Therefore, desirable in the art of pinned photodiode designs are additional systems to integrate shallow trench isolation structures therewith, thereby improving image quality and overall IC performance. Prior attempts to reduce leakage and dark current typically do so at the expense of photodiode sensitivity. As such, it would be particularly desirable to provide a pinned photodiode that is resistant to leakage and dark current effects without compromising sensitivity.
SUMMARY
In view of the foregoing, the following provides a system to reduce or eliminate leakage between a pinned photodiode and shallow trench isolation fabricated therewith.
In one embodiment, a system comprises at least a N+ region implanted on a P-type substrate; at least a P-type well surrounding the N+ region for separating the N+ region from a shallow trench isolation; and at least a P+ region overlapping the N+ region, and further overlapping at least part of the P-type well to form a pinned photodiode, wherein a space between the N+ region and the shallow trench isolation provides a distance for the expansion of a depletion region between the N+ region and a first area comprising the P+ region, the P-type substrate and the P-type well, the space for reducing or eliminating electrical leakage and the depletion region for facilitating a photosensitive response during the operation of the pinned photodiode.
The sensitivities of the various pinned photodiodes may be optimized for the detection of different wavelengths of light. For example, for the detection of red light, the junction between the N+ region and the substrate may be about 0.8 microns or greater. For the optimal detection of blue light, the junction between the P+ region and the N+ region may be less than about 0.2 microns. For the detection of green light, the lower junction of the N+ region and the P-type wells may have the same depth of about 0.2 to 0.8 microns.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
<figref idref="DRAWINGS">FIG. 1</figref> illustrates a cross section of a conventional design with a pinned photodiode fabricated alongside a shallow trench isolation, according to the Prior Art.
<figref idref="DRAWINGS">FIG. 2</figref> illustrates a cross section of a pinned photodiode fabricated alongside a shallow trench isolation in accordance with one embodiment of the present invention.
<figref idref="DRAWINGS">FIG. 3</figref> illustrates a cross section of a pinned photodiode fabricated alongside a shallow trench isolation in accordance with a further embodiment of the present invention.
DESCRIPTION
The following will provide a detailed description of a system to reduce or eliminate leakage between a pinned photodiode and shallow trench isolation fabricated therewith.
<figref idref="DRAWINGS">FIG. 1</figref> illustrates a cross section <b>100</b> of a conventional design with a pinned photodiode having a N+ photosensitive region, adjacent to a P-type well and surrounded just inside a STI. Segmenting a semiconductor P-type substrate <b>102</b> is a ring, typically rectangular, of a dielectric STI <b>104</b>. Adjacent to the inner wall and the bottom of the STI <b>104</b> is a ring of diffused P-type well <b>106</b>. A N+ region <b>108</b> is implanted to a substrate surface <b>110</b> of the P-type substrate <b>102</b>.
The N+ region <b>108</b> spans the area inside the ring of P-type well <b>106</b> such that the N+ region <b>108</b> is isolated from the STI <b>104</b> by a distance <b>112</b>, which is the same as the width of the P-type well <b>106</b>. The P-type well <b>106</b>, or other diffusion, has a heavier doping than has the P-type substrate <b>102</b>. A shallow P+ region <b>114</b> spans the entire substrate surface <b>110</b> of the P-type substrate <b>102</b> interior to the P-type well <b>106</b>, and further overlaps part of the P-type well <b>106</b>. This overlapping is effectively the P-type pinning implant of the photodiode. It subdues the N+ region <b>108</b> beneath the substrate surface <b>110</b>. Since this P+ region <b>114</b> is more heavily doped than is the N+ region <b>108</b>, the P+ doping overpowers the N+ doping, thereby isolating the N+ region <b>108</b> from the substrate surface <b>110</b>. The purpose of isolating the N+ region from the substrate surface <b>110</b> is to further reduce leakage. Here, the junction of the N+ region <b>108</b> does not reach the substrate surface <b>110</b> where it could cause electrical leakage.
The boundary surfaces between the N+ type interior to the N+ region <b>108</b> and the various P-type regions outside that region constitute an electrical junction. For example, the N+ region <b>108</b> is enclosed by the P+ region <b>114</b> at the top, the P-type well <b>106</b> at the sides, and the P-type substrate <b>102</b> at the bottom. When this electrical junction is reverse-biased, with a positive bias on the N-type interior and a relatively negative bias on the P-type exterior, the depletion region of the electrical junction expands outward to an outer surface <b>116</b> and inward to an inner surface <b>118</b>.
It is the volume of the depletion region between the outer surface <b>116</b> and the inner surface <b>118</b> that is the photosensitive element. Within this volume, absorbed light generates paired electrons and holes that are driven in opposite directions and collected as photocurrent. Photocurrent is also collected from within a carrier diffusion length of the depletion region. This larger sensitive volume has slightly slower response.
The pinned photodiode thus has two photosensitive depletion regions that are parallel to the substrate surface <b>110</b>, one at the top and one at the bottom of the N+ region <b>108</b>. The upper photosensitive depletion region is closer to the substrate surface <b>110</b> and therefore is more responsive to a blue light which has a shorter wavelength. So, this extra photosensitive depletion region at the top of the N+ region <b>108</b> increases photosensitivity and shifts the sensitivity towards the blue region of the photo spectrum.
The degree of doping on each side of the electrical junction and the ratio of doping on the two sides of the junction determine the extension of the depletion region in each surface direction. The depletion region expands little, along a portion of the outer surface <b>116</b>, into the P+ region <b>114</b>, because of its heavy P-type doping. The depletion region expands slightly further, along a portion of the inner surface <b>118</b> into the N+ region <b>108</b>, because the doping is heavy, but less than the doping of the P+ region <b>114</b>. The depletion region expands more into the P-type well <b>106</b>, where the doping is less heavy than that in either the N+ region <b>108</b> or the P+ region <b>114</b>. The depletion region expands the most, along the bottom portion of the outer surface <b>116</b>, into the P-type substrate <b>102</b>.
The distance <b>112</b> allows space for the depletion to expand, with voltage, into the P-type well <b>106</b>. It is desired to prevent the depletion region from expanding into any damaged region of the P-type well <b>106</b> that is immediately adjacent to the STI <b>104</b>. This damaged region, typically caused by dry etching of the trench, is a substrate crystal in the P-type well <b>106</b> that is immediately adjacent to the STI <b>104</b>. This damaged region would cause. electrical leakage if any portion of the junction depletion region that surrounds the N+ region <b>108</b> extends too near to the damage. In conventional structures, however, the depletion region expands into the damaged region causing electrical leakage.
<figref idref="DRAWINGS">FIG. 2</figref> illustrates a cross section <b>200</b> of an improved design with a pinned photodiode fabricated alongside a STI in accordance with one embodiment of the present invention. A space between a N+ photosensitive region of the pinned photodiode and a P-type well surrounding it is extended to further reduce leakage. Segmenting a semiconductor P-type substrate <b>202</b> is a ring, typically rectangular, of a dielectric STI <b>204</b>. Adjacent to the inner wall and the bottom of the STI <b>204</b> is a ring of diffused P-type well <b>206</b>. A N+ region <b>208</b> is implanted and diffused from a substrate surface <b>210</b> of the P-type substrate <b>202</b>.
With reference to <figref idref="DRAWINGS">FIG. 1</figref>, the distance <b>112</b> separating the N+ region <b>108</b> from the STI <b>104</b>, is the width of the P-type well <b>106</b>. According to an embodiment of the invention illustrated in <figref idref="DRAWINGS">FIG. 2</figref>, a distance <b>212</b> separating the N+ region <b>208</b> from the STI <b>204</b> is the width of the P-type well <b>206</b> plus a space of the P-type substrate <b>202</b>. In an exemplary embodiment, distance <b>212</b> may range from 0.1 um to 0.8 um but may vary in various other exemplary embodiments. The purpose of this space of the P-type substrate <b>202</b> is to provide a longer distance between the N+ photosensitive region and the STI to further reduce electrical leakage. Here, the depletion region expands somewhat with voltage into the space of the P-type substrate <b>202</b> before it encounters the heavier doping of the P-type well <b>206</b>. In this embodiment, a little more voltage means a little additional expansion of the depletion region into the P-type well <b>206</b>. In other words, the space provides additional protection from leakage because the depletion region does not approach as closely to any damaged semiconductor crystal that lies in a boundary between the STI <b>204</b> and the P-type well <b>206</b> as to a conventional pinned photodiode design.
The P-type well <b>206</b>, or other diffusion, has heavier doping than has the P-type substrate <b>202</b>. This heavier doping prevents the depletion region that surrounds the N+ region <b>208</b> from extending to the damaged material at the boundary between the P-type well <b>206</b> and the STI <b>204</b>. Some of the P-type substrate <b>202</b> material can be left to occupy the space. The part of the substrate crystal in the P-type well <b>206</b>, immediately adjacent to the STI <b>204</b>, is damaged by a dry etch operation producing it. This would cause electrical leakage if any portion of the junction depletion region that surrounds the N+ region <b>208</b> extends too near to the damage. The spacing of distance <b>212</b> allows more voltage to be applied to form a larger depletion region to improve sensitivity of the photodiode without concern that the depletion region will expand laterally into the damaged region of the P-type well that is immediately adjacent STI <b>204</b> and cause leakage.
A shallow P+ region <b>214</b> spans the entire substrate surface <b>210</b> of the P-type substrate <b>202</b> interior to the ring of the P-type well <b>206</b>, and further overlaps the P-type well <b>206</b>. This overlapping is essentially the P-type pinning implant of the photodiode. The P+ region <b>214</b> subdues the N+ region <b>208</b> beneath the substrate surface <b>210</b>. The P+ region <b>214</b> advantageously includes a higher impurity concentration than P-type well <b>206</b>. Since this P+ region <b>214</b> is more heavily doped than is the N+ region <b>208</b>, the P+ doping overpowers the N+ doping, while the P+ region <b>214</b> isolates the N+ region <b>208</b> from the substrate surface <b>210</b>. The purpose of isolating the N+ region from the substrate surface <b>210</b> is to further reduce leakage. Here, the junction of the N+ region <b>208</b> does not reach the substrate surface <b>210</b> where it could cause electrical leakage.
The N+ region <b>208</b> is isolated beneath the substrate surface <b>210</b>. The boundary surfaces between the N+ type interior of the N+ region <b>208</b> and the various P-type regions outside it constitute an electrical junction. As shown, the N+ region <b>208</b> is surrounded by a P-type area comprising the P+ region <b>214</b> on top and portions of the P-type substrate <b>202</b> on all other sides. When the electrical junction is reverse-biased, with a positive bias on the N-type interior and a relatively negative bias on the P-type exterior, the depletion region of the electrical junction expands outward to an outer surface <b>216</b> and inward to an inner surface <b>218</b>.. As it can be seen, the depletion region defined by the outer surface <b>216</b> and inner surface <b>218</b> is bigger than that in the prior art, and it helps to absorb short wavelength lights such as the blue light. In an exemplary embodiment, the width of the depletion region, i.e., the perpendicular distance between outer surface <b>216</b> and inner surface <b>218</b>, may range from 0.01 to 0.2 microns. Distance <b>212</b> is chosen so that, when the depletion region expands to a maximum expansion width, it does not reach the damaged region adjacent the STI <b>204</b>, which faces the N+ region <b>208</b>. The maximum expansion width of the depletion region may range from 0.05 to 0.7 microns in one exemplary embodiment, but may vary in other exemplary embodiments.
Provided is a pinned photodiode that isolates the photosensitive junction area from the surface of the semiconductor substrate, thereby reducing the leakage that would otherwise be generated by the meeting of the electrical junction and the imperfect interface between the semiconductor crystal and the oxide. Some structure that provides heavier doping adjacent to the surrounding STI reduces leakage that otherwise would be generated by the meeting of the junction depletion region and the substrate material damaged by the dry etching that produces the STI. By including an additional space between the photodiode and the surrounding heavy doping structure, leakage is reduced, thereby improving image quality produced by the photodiode.
<figref idref="DRAWINGS">FIG. 3</figref> shows another exemplary pinned photodiode in which the N+ region <b>208</b> extends to the same depth as the P-type wells <b>206</b>. Like reference numerals denote like features throughout the specification and it can be seen that N+ region <b>208</b> includes a greater relative depth <b>222</b> than in <figref idref="DRAWINGS">FIG. 2</figref>. The depletion region, described in conjunction with <figref idref="DRAWINGS">FIGS. 1 and 2</figref>, is not shown.
The sensitivities of the various pinned photodiodes may be optimized for detection of different wavelengths of light. Longer wavelength light is absorbed by deeper junctions so the structures and associated depletion regions may be so formed. For example, for the detection of red light, the junction between the N+ region <b>208</b> and the P-type substrate <b>202</b> (depth <b>222</b>) may be about 0.8 microns or greater. For the optimal detection of blue light, the junction between P+ region <b>214</b> and N+ region <b>208</b> (depth <b>220</b>) may be less than about 0.2 microns. In another embodiment illustrated in <figref idref="DRAWINGS">FIG. 3</figref>., a pinned photodiode optimized for the detection of green light may include the N+ region <b>208</b>/P-type substrate <b>202</b> depth being substantially equal to the depth <b>224</b> of the P-type wells and about 0.2 to 0.8 microns.
The above illustration provides many different embodiments or embodiments for implementing different features of the invention. Specific embodiments of components and processes are described to help clarify the invention. These are, of course, merely embodiments and are not intended to limit the invention from that described in the claims.
Although the invention is illustrated and described herein as embodied in one or more specific examples, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the invention, as set forth in the following claims.
Contents4
4 sheets
Sheet 1 Sheet 2 Sheet 3 Sheet 4
Every citation, both ways
| Document | Relation | Office | Cited during |
|---|---|---|---|
| US2008217720A1 | Cited by | United States of America | Pre-grant |
| US7592199B2 | Cited by | United States of America | Applicant |
| US12080733B2 | Cited by | United States of America | Search report |
| US7642608B2 | Cited by | United States of America | Applicant |
| US2008225144A1 | Cited by | United States of America | Pre-grant |
| US2008124829A1 | Cited by | United States of America | Pre-grant |
| US2021005646A1 | Cited by | United States of America | Search report |
| US7724293B2 | Cited by | United States of America | Applicant |
| US2009206429A1 | Cited by | United States of America | Pre-grant |
| US7919797B2 | Cited by | United States of America | Search report |
| US5859450A | Cites | United States of America | Pre-grant |
| US2003169359A1 | Cites | United States of America | Pre-grant |
| US2004021194A1 | Cites | United States of America | Pre-grant |
| US2004021194A1 | Cites | United States of America | Pre-grant |
| US2005045926A1 | Cites | United States of America | Pre-grant |
| US2005045926A1 | Cites | United States of America | Pre-grant |
| US6900484B2 | Cites | United States of America | Pre-grant |
| US2005184321A1 | Cites | United States of America | Pre-grant |
| US6410359B2 | Cites | United States of America | Pre-grant |
| US5859450A | Cites | United States of America | Pre-grant |
| US2005184321A1 | Cites | United States of America | Pre-grant |
| US6297070B1 | Cites | United States of America | Pre-grant |
| US2003169359A1 | Cites | United States of America | Pre-grant |
| US6410359B2 | Cites | United States of America | Pre-grant |
| US6297070B1 | Cites | United States of America | Pre-grant |
| US6900484B2 | Cites | United States of America | Pre-grant |
8 members in 3 offices
Priority claims2
| Document | Office | Kind | Date |
|---|---|---|---|
| 793504 | United States of America | A | |
| US20040007935 | – | – | – |
Members8
| Document | Office | Kind | |
|---|---|---|---|
| CN1787222A | China | A | |
| US2006125035A1 | United States of America | A1 | |
| TW200620399A | Taiwan Province of China | A | |
| TWI269360B | Taiwan Province of China | B | |
| CN100373629C | China | C | |
| US7348651B2 | United States of America | B2 | |
| US2008124829A1 | United States of America | A1 | |
| US7592199B2 | United States of America | B2 |
98 transactions on the USPTO file
Allowed after 1 non-final rejection, 1 final rejection and 1 RCE.
- Non-final rejections
- 1
- Final rejections
- 1
- RCEs
- 1
- Appeals
- 0
Over time
Point at a mark for the transactionTransactions
| Event | Code | |
|---|---|---|
| Expire PatentEXP. | EXP. | |
| Maintenance Fee Reminder MailedREM. | REM. | |
| Post Issue Communication - Certificate of CorrectionN423 | N423 | |
| Post Issue Communication - Certificate of CorrectionN423 | N423 | |
| Recordation of Patent Grant MailedPGM/ | PGM/ | |
| Recordation of Patent Grant MailedPGM/ | PGM/ | |
| Patent Issue Date Used in PTA CalculationAllowedPTAC | PTAC | |
| Patent Issue Date Used in PTA CalculationAllowedPTAC | PTAC | |
| Issue Notification MailedAllowedWPIR | WPIR | |
| Issue Notification MailedAllowedWPIR | WPIR | |
| Dispatch to FDCD1935 | D1935 | |
| Dispatch to FDCD1935 | D1935 | |
| Application Is Considered Ready for IssuePILS | PILS | |
| Application Is Considered Ready for IssuePILS | PILS | |
| Issue Fee Payment VerifiedN084 | N084 | |
| Issue Fee Payment VerifiedN084 | N084 | |
| Issue Fee Payment ReceivedIFEE | IFEE | |
| Issue Fee Payment ReceivedIFEE | IFEE | |
| Mail Notice of AllowanceAllowedMN/=. | MN/=. | |
| Mail Notice of AllowanceAllowedMN/=. | MN/=. | |
| Mail Examiner's AmendmentMEX.A | MEX.A | |
| Mail Examiner's AmendmentMEX.A | MEX.A | |
| Notice of Allowance Data Verification CompletedAllowedN/=. | N/=. | |
| Notice of Allowance Data Verification CompletedAllowedN/=. | N/=. | |
| Case Docketed to Examiner in GAUDOCK | DOCK | |
| Case Docketed to Examiner in GAUDOCK | DOCK | |
| Examiner's Amendment CommunicationEX.A | EX.A | |
| Examiner's Amendment CommunicationEX.A | EX.A | |
| Date Forwarded to ExaminerFWDX | FWDX | |
| Date Forwarded to ExaminerFWDX | FWDX | |
| Date Forwarded to ExaminerFWDX | FWDX | |
| Date Forwarded to ExaminerFWDX | FWDX | |
| Disposal for a RCE / CPA / R129AbandonedABN9 | ABN9 | |
| Disposal for a RCE / CPA / R129AbandonedABN9 | ABN9 | |
| Request for Continued Examination (RCE)RCEX | RCEX | |
| Request for Continued Examination (RCE)RCEX | RCEX | |
| Workflow - Request for RCE - BeginBRCE | BRCE | |
| Workflow - Request for RCE - BeginBRCE | BRCE | |
| Mail Final Rejection (PTOL - 326)Final rejectionMCTFR | MCTFR | |
| Mail Final Rejection (PTOL - 326)Final rejectionMCTFR | MCTFR | |
| Final RejectionFinal rejectionCTFR | CTFR | |
| Final RejectionFinal rejectionCTFR | CTFR | |
| Date Forwarded to ExaminerFWDX | FWDX | |
| Date Forwarded to ExaminerFWDX | FWDX | |
| New or Additional Drawing FiledC614 | C614 | |
| New or Additional Drawing FiledC614 | C614 | |
| Response after Non-Final ActionA... | A... | |
| Response after Non-Final ActionA... | A... | |
| Mail Non-Final RejectionNon-final rejectionMCTNF | MCTNF | |
| Mail Non-Final RejectionNon-final rejectionMCTNF | MCTNF | |
| Non-Final RejectionNon-final rejectionCTNF | CTNF | |
| Non-Final RejectionNon-final rejectionCTNF | CTNF | |
| Date Forwarded to ExaminerFWDX | FWDX | |
| Date Forwarded to ExaminerFWDX | FWDX | |
| Response to Election / Restriction FiledELC. | ELC. | |
| Response to Election / Restriction FiledELC. | ELC. | |
| Mail Restriction RequirementMCTRS | MCTRS | |
| Mail Restriction RequirementMCTRS | MCTRS | |
| Restriction/Election RequirementCTRS | CTRS | |
| Restriction/Election RequirementCTRS | CTRS | |
| Case Docketed to Examiner in GAUDOCK | DOCK | |
| Case Docketed to Examiner in GAUDOCK | DOCK | |
| Case Docketed to Examiner in GAUDOCK | DOCK | |
| Case Docketed to Examiner in GAUDOCK | DOCK | |
| IFW TSS Processing by Tech Center CompleteTSSCOMP | TSSCOMP | |
| IFW TSS Processing by Tech Center CompleteTSSCOMP | TSSCOMP | |
| Case Docketed to Examiner in GAUDOCK | DOCK | |
| Case Docketed to Examiner in GAUDOCK | DOCK | |
| Application Return from OIPEWROIPE | WROIPE | |
| Application Return from OIPEWROIPE | WROIPE | |
| Application Return TO OIPEROIPE | ROIPE | |
| Application Return TO OIPEROIPE | ROIPE | |
| Application Dispatched from OIPEOIPE | OIPE | |
| Application Dispatched from OIPEOIPE | OIPE | |
| Application Is Now CompleteCOMP | COMP | |
| Application Is Now CompleteCOMP | COMP | |
| Correspondence Address ChangeC.AD | C.AD | |
| Correspondence Address ChangeC.AD | C.AD | |
| Additional Application Filing FeesADDFLFEE | ADDFLFEE | |
| Additional Application Filing FeesADDFLFEE | ADDFLFEE | |
| Applicant has submitted new drawings to correct Corrected Papers problemsCORRDRW | CORRDRW | |
| Applicant has submitted new drawings to correct Corrected Papers problemsCORRDRW | CORRDRW | |
| Corrected PaperCPAP | CPAP | |
| Corrected PaperCPAP | CPAP | |
| Cleared by OIPE CSRL194 | L194 | |
| Cleared by OIPE CSRL194 | L194 | |
| IFW Scan & PACR Auto Security ReviewSCAN | SCAN | |
| IFW Scan & PACR Auto Security ReviewSCAN | SCAN | |
| Information Disclosure Statement consideredIDSC | IDSC | |
| Information Disclosure Statement consideredIDSC | IDSC | |
| Reference capture on IDSRCAP | RCAP | |
| Reference capture on IDSRCAP | RCAP | |
| Information Disclosure Statement (IDS) FiledM844 | M844 | |
| Information Disclosure Statement (IDS) FiledM844 | M844 | |
| Information Disclosure Statement (IDS) FiledWIDS | WIDS | |
| Information Disclosure Statement (IDS) FiledWIDS | WIDS | |
| Initial Exam Team nnIEXX | IEXX | |
| Initial Exam Team nnIEXX | IEXX |
18 legal events, as the office reported them to INPADOC
Over the term
Point at a mark for the eventEvents
| Event | Code | |
|---|---|---|
| Lapsed due to failure to pay maintenance feeLapsedFP | FP | |
| Lapsed due to failure to pay maintenance feeLapsedFP | FP | |
| Lapse for failure to pay maintenance feesLapsedPATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITYLAPS | LAPS | |
| Lapse for failure to pay maintenance feesLapsedLAPS | LAPS | |
| Information on status: patent discontinuationPATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362STCH | STCH | |
| Information on status: patent discontinuationSTCH | STCH | |
| Fee payment procedureMAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITYFEPP | FEPP | |
| Fee payment procedureFEPP | FEPP | |
| Fee paymentFPAY | FPAY | |
| Fee paymentFPAY | FPAY | |
| Fee paymentFPAY | FPAY | |
| Fee paymentFPAY | FPAY | |
| Certificate of correctionCC | CC | |
| Certificate of correctionCC | CC | |
| Information on status: patent grantGrantedPATENTED CASESTCF | STCF | |
| Information on status: patent grantGrantedSTCF | STCF | |
| AssignmentAS | AS | |
| AssignmentAS | AS |
Numbers
- Application
- 11007935
Titles
- English
- Pinned photodiode fabricated with shallow trench isolation
Patent term adjustment
- A delay
- +284 daysthe office missed an examination deadline
- Net adjustment
- 284 days
Classification
- CPC, 2
- H10F39/18
- H10F39/807
- IPC, 2
- H01L27 14
- H01L21 00
- USPC, 4
- 257431000
- 257510000
- 438057000
- 438424000