US20060125035A1

Pinned photodiode fabricated with shallow trench isolation

Claim Score by NHIP

Read claim 25, the broadest

Abstract

A method and system is disclosed for reducing or eliminating leakage between a pinned photodiode and shallow trench isolation structure fabricated therewith while optimizing the sensitivity of the photodiode. Provided is a system with an N+ region implanted in a P-type substrate; a P-type well separating the N+ region from the shallow trench isolation (STI) structure; and at least a P+ region over the N+ region, and overlapping at least part of the P-type well and a substrate portion between the N+ region and P-type well. The space between the N+ region and a damaged region adjacent the STI is greater than the distance that the depletion region between the N+ region and the P-type well, expands. The junctions of the various features are optimized to maximize a photosensitive response for the wavelength of the absorbed light as well as reducing or eliminating electrical leakage.

US20060125035A1, drawing sheet 1
Sheet 1 of 4

Term

Term ended

Projected expiry passed 19 September 2025, 1 year ago.

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28 claims: 6 independent, 22 dependent

  1. 1
    A semiconductor structure to reduce or eliminate electrical leakage between a pinned photodiode and a shallow trench isolation structure, the semiconductor structure comprising:a first region of a first impurity type formed beneath a surface of a semiconductor substrate of a second impurity type and disposed between shallow trench isolation (STI) structures;a semiconductor well of a second impurity type laterally separating the first region from each of the STI structures and including a damaged portion adjacent each STI structure and facing the first region;a substrate portion of the semiconductor substrate interposed between the first region and each of the semiconductor wells;a second region of the second impurity type covering the first region and each substrate portion and overlapping at least part of each of the semiconductor wells, the second region formed within the semiconductor substrate and extending downwardly from the surface;an expandable depletion region formed along a boundary between the first region and each substrate portion, a lateral spacing between the first region and each of the adjacent damaged portions sufficient to prevent the depletion region from expanding into the damaged portions at a maximum expansion of the depletion region, and the first region having a lower boundary more than about 0.8 microns below the surface.
  2. 1
    A semiconductor structure to reduce or eliminate electrical leakage between a pinned photodiode and a shallow trench isolation structure, the semiconductor structure comprising:a first region of a first impurity type formed beneath a surface of a semiconductor substrate of a second impurity type and disposed between shallow trench isolation (STI) structures;a semiconductor well of a second impurity type laterally separating the first region from each of the STI structures and including a damaged portion adjacent each STI structure and facing the first region;a substrate portion of the semiconductor substrate interposed between the first region and each of the semiconductor wells;a second region of the second impurity type covering the first region and each substrate portion and overlapping at least part of each of the semiconductor wells, the second region formed within the semiconductor substrate and extending downwardly from the surface;an expandable depletion region formed along a boundary between the first region and each substrate portion, a lateral spacing between the first region and each of the adjacent damaged portions sufficient to prevent the depletion region from expanding into the damaged portions at a maximum expansion of the depletion region, and the first region having a lower boundary more than about 0.8 microns below the surface.
  3. 8
    A semiconductor structure to reduce or eliminate electrical leakage between a pinned photodiode and a shallow trench isolation structure, the semiconductor structure comprising:a first region of a first impurity type formed beneath a surface of a semiconductor substrate of a second impurity type and disposed between shallow trench isolation (STI) structures;a semiconductor well of a second impurity type laterally separating the first region from each of the STI structures and including a damaged portion adjacent each STI structure and facing the first region;a substrate portion of the semiconductor substrate interposed between the first region and each of the semiconductor wells;a second region of the second impurity type covering the first region and each substrate portion and overlapping at least part of each of the semiconductor wells, the second region formed within the semiconductor substrate and extending downwardly from the surface;an expandable depletion region formed along a boundary between the first region and the substrate portion, a lateral spacing between the first region and each of the adjacent damaged portions sufficient to prevent the depletion region from expanding into the damaged portions at a maximum expansion of the depletion region, and the first region having a lower boundary at substantially the same depth as a lower boundary of the semiconductor wells and disposed about 0.2 to 0.8 microns below the surface.
  4. 8
    A semiconductor structure to reduce or eliminate electrical leakage between a pinned photodiode and a shallow trench isolation structure, the semiconductor structure comprising:a first region of a first impurity type formed beneath a surface of a semiconductor substrate of a second impurity type and disposed between shallow trench isolation (STI) structures;a semiconductor well of a second impurity type laterally separating the first region from each of the STI structures and including a damaged portion adjacent each STI structure and facing the first region;a substrate portion of the semiconductor substrate interposed between the first region and each of the semiconductor wells;a second region of the second impurity type covering the first region and each substrate portion and overlapping at least part of each of the semiconductor wells, the second region formed within the semiconductor substrate and extending downwardly from the surface;an expandable depletion region formed along a boundary between the first region and the substrate portion, a lateral spacing between the first region and each of the adjacent damaged portions sufficient to prevent the depletion region from expanding into the damaged portions at a maximum expansion of the depletion region, and the first region having a lower boundary at substantially the same depth as a lower boundary of the semiconductor wells and disposed about 0.2 to 0.8 microns below the surface.
  5. 15
    A semiconductor structure to reduce or eliminate electrical leakage between a pinned photodiode and a shallow trench isolation structure, the semiconductor structure comprising:a first region of a first impurity type formed beneath a surface of a semiconductor substrate of a second impurity type and disposed between shallow trench isolation (STI) structures,;a semiconductor well of a second impurity type laterally separating the first region from each of the STI structures and including a damaged portion adjacent each STI structure and facing the first region;a substrate portion of the semiconductor substrate interposed between the first region and each of the semiconductor wells;a second region of the second impurity type covering the first region and each substrate portion and overlapping at least part of each of the semiconductor wells, the second region formed within the semiconductor substrate and extending downwardly from the surface to a depth no more than about 0.2 microns;an expandable depletion region formed along a boundary between the first region and the substrate portion, and a lateral spacing between the first region and each of the adjacent damaged portions sufficient to prevent the depletion region from expanding into the damaged portions at a maximum expansion of the depletion region, wherein the first impurity type is N-type and the second impurity type is P-type.
  6. 15
    A semiconductor structure to reduce or eliminate electrical leakage between a pinned photodiode and a shallow trench isolation structure, the semiconductor structure comprising:a first region of a first impurity type formed beneath a surface of a semiconductor substrate of a second impurity type and disposed between shallow trench isolation (STI) structures,;a semiconductor well of a second impurity type laterally separating the first region from each of the STI structures and including a damaged portion adjacent each STI structure and facing the first region;a substrate portion of the semiconductor substrate interposed between the first region and each of the semiconductor wells;a second region of the second impurity type covering the first region and each substrate portion and overlapping at least part of each of the semiconductor wells, the second region formed within the semiconductor substrate and extending downwardly from the surface to a depth no more than about 0.2 microns;an expandable depletion region formed along a boundary between the first region and the substrate portion, and a lateral spacing between the first region and each of the adjacent damaged portions sufficient to prevent the depletion region from expanding into the damaged portions at a maximum expansion of the depletion region, wherein the first impurity type is N-type and the second impurity type is P-type.
  7. 21
    A method to reduce or eliminate electrical leakage between a pinned photodiode and shallow trench isolation fabricated therewith, the method comprising:implanting N+ impurities to form an N+ region beneath a surface of a P-type semiconductor substrate;forming at least one shallow trench isolation (STI) structure in the semiconductor substrate;forming at least one P-type well laterally separating the first region from each STI structure wherein a substrate portion of the semiconductor substrate remains interposed between the N+ region and each P-type well and the P-type well includes a damaged portion adjacent the STI and facing the N+ region;forming a P+ region covering the N+ region and each substrate portion and overlapping at least part of each P-type well, the P+ region formed within the semiconductor substrate and extending downwardly from the surface;creating an expandable depletion region along a boundary between the N+ region and the substrate portion, laterally spacing the N+ region from each adjacent damaged portion by a distance sufficient to prevent the depletion region from expanding into the associated damaged portion when the depletion region expands to a maximum expansion width, and the first region having a lower boundary more than about 0.8 microns below the surface.
  8. 21
    A method to reduce or eliminate electrical leakage between a pinned photodiode and shallow trench isolation fabricated therewith, the method comprising:implanting N+ impurities to form an N+ region beneath a surface of a P-type semiconductor substrate;forming at least one shallow trench isolation (STI) structure in the semiconductor substrate;forming at least one P-type well laterally separating the first region from each STI structure wherein a substrate portion of the semiconductor substrate remains interposed between the N+ region and each P-type well and the P-type well includes a damaged portion adjacent the STI and facing the N+ region;forming a P+ region covering the N+ region and each substrate portion and overlapping at least part of each P-type well, the P+ region formed within the semiconductor substrate and extending downwardly from the surface;creating an expandable depletion region along a boundary between the N+ region and the substrate portion, laterally spacing the N+ region from each adjacent damaged portion by a distance sufficient to prevent the depletion region from expanding into the associated damaged portion when the depletion region expands to a maximum expansion width, and the first region having a lower boundary more than about 0.8 microns below the surface.
  9. 25
    Broadest claimClaim Score 42, average(NHIP)A method to reduce or eliminate electrical leakage between a pinned photodiode and shallow trench isolation fabricated therewith, the method comprising:implanting N+ impurities to form an N+ region beneath a surface of a P-type semiconductor substrate;forming at least one shallow trench isolation (STI) structure in the semiconductor substrate;forming at least one P-type well laterally separating the first region from each STI structure wherein a substrate portion of the semiconductor substrate remains interposed between the N+ region and each P-type well and the P-type well includes a damaged portion adjacent the STI and facing the N+ region;forming a P+ region covering the N+ region and each substrate portion and overlapping at least part of each P-type well, the P+ region formed within the semiconductor substrate and extending downwardly from the surface;creating an expandable depletion region along a boundary between the N+ region and the substrate portion, laterally spacing the N+ region from each adjacent damaged portion by a distance sufficient to prevent the depletion region from expanding into the associated damaged portion when the depletion region expands to a maximum expansion, and forming the P+ region to have a lower boundary extending no more than 0.2 microns below the surface.
  10. 25
    Broadest claimClaim Score 42, average(NHIP)A method to reduce or eliminate electrical leakage between a pinned photodiode and shallow trench isolation fabricated therewith, the method comprising:implanting N+ impurities to form an N+ region beneath a surface of a P-type semiconductor substrate;forming at least one shallow trench isolation (STI) structure in the semiconductor substrate;forming at least one P-type well laterally separating the first region from each STI structure wherein a substrate portion of the semiconductor substrate remains interposed between the N+ region and each P-type well and the P-type well includes a damaged portion adjacent the STI and facing the N+ region;forming a P+ region covering the N+ region and each substrate portion and overlapping at least part of each P-type well, the P+ region formed within the semiconductor substrate and extending downwardly from the surface;creating an expandable depletion region along a boundary between the N+ region and the substrate portion, laterally spacing the N+ region from each adjacent damaged portion by a distance sufficient to prevent the depletion region from expanding into the associated damaged portion when the depletion region expands to a maximum expansion, and forming the P+ region to have a lower boundary extending no more than 0.2 microns below the surface.
  11. 27
    A method to reduce or eliminate electrical leakage between a pinned photodiode and shallow trench isolation fabricated therewith, the method comprising:implanting N+ impurities to form an N+ region beneath a surface of a P-type semiconductor substrate;forming at least one shallow trench isolation (STI) structure in the semiconductor substrate;forming at least one P-type well laterally separating the first region from each STI structure wherein a substrate portion of the semiconductor substrate remains interposed between the N+ region and each P-type well and the P-type well includes a damaged portion adjacent the STI and facing the N+ region;forming a P+ region covering the N+ region and each substrate portion and overlapping at least part of each P-type well, the P+ region formed within the semiconductor substrate and extending downwardly from the surface;creating an expandable depletion region along a boundary between the N+ region and the substrate portion, laterally spacing the N+ region from each adjacent damaged portion by a distance sufficient to prevent the depletion region from expanding into the associated damaged portion when the depletion region expands to a maximum expansion, and forming each of the first region and each at least one P-type well to have the substantially same lower boundary being about 0.2 to 0.8 microns below the surface.
  12. 27
    A method to reduce or eliminate electrical leakage between a pinned photodiode and shallow trench isolation fabricated therewith, the method comprising:implanting N+ impurities to form an N+ region beneath a surface of a P-type semiconductor substrate;forming at least one shallow trench isolation (STI) structure in the semiconductor substrate;forming at least one P-type well laterally separating the first region from each STI structure wherein a substrate portion of the semiconductor substrate remains interposed between the N+ region and each P-type well and the P-type well includes a damaged portion adjacent the STI and facing the N+ region;forming a P+ region covering the N+ region and each substrate portion and overlapping at least part of each P-type well, the P+ region formed within the semiconductor substrate and extending downwardly from the surface;creating an expandable depletion region along a boundary between the N+ region and the substrate portion, laterally spacing the N+ region from each adjacent damaged portion by a distance sufficient to prevent the depletion region from expanding into the associated damaged portion when the depletion region expands to a maximum expansion, and forming each of the first region and each at least one P-type well to have the substantially same lower boundary being about 0.2 to 0.8 microns below the surface.