US20050190174A1

Liquid crystal display panel with signal transmission patterns

Claim Score by NHIP

Abstract

A liquid crystal display of compact size is disclosed. The liquid crystal display has a tape carrier package and a single integrated PCB for processing a gate driving signal and data driving signal. The tape carrier package includes a base substrate, a gate driver IC formed on said base substrate, an input pattern formed on said base substrate that applies gate driving signals input from an external device to the gate driver IC, a first output pattern formed on said base substrate that outputs a first gate driving signal processed in said gate driver IC, and a second output pattern formed on said base substrate, that outputs a second gate driving signal bypassing the gate driver IC among the gate driving signals.

US20050190174A1, drawing sheet 1 — Sheet 1 of 8

Term

Term ended

Projected expiry passed 17 April 2020, 6.4 years ago.

20 claims: 3 independent, 17 dependent

27
Broadest claimClaim Score 64, broad(NHIP)A liquid crystal display (LCD) panel, comprising:a substrate;a gate line and a data line formed on the substrate;a gate driving signal transmission pattern formed on the substrate and connected to the gate line for transmitting a gate driving signal thereto;a data driving signal transmission pattern formed on the substrate and connected to the data line for transmitting a data driving signal thereto;and a gate signal transmission pattern formed on the substrate for transmitting a gate signal from a first external device.
43
A liquid crystal display (LCD) panel, comprising:a substrate comprising: a display region;and a peripheral region formed around the display region;a first line formed in the display region for transmitting a first driving signal;a second line formed in the display region and intersecting the first line for transmitting a second driving signal;a first driving signal transmission pattern formed in the peripheral region and connected to the first line for transmitting the first driving signal thereto;a second driving signal transmission pattern formed in the peripheral region and connected to the second line for transmitting the second driving signal thereto;and a first signal transmission pattern formed in the peripheral region for transmitting a first signal.

Independent claims2

117 paragraphs in 4 sections, as filed

BACKGROUND OF THE INVENTION

00011. Field of the Invention

0002The present invention relates to a tape carrier package for a compact size liquid crystal display (LCD), and more particularly to a tape carrier package (TCP) capable of receiving both of gate signal and data signal which are processed in a single integrated printed circuit board and transmitting the processed signals to an LCD panel and another TCP. Further, the invention relates to a liquid crystal display panel to which the tape carrier package is applied.

00032. Description of the Related Art

0004Generally, an LCD is a mostly used type of flat panel display. Especially, the small size, lighter weight and lower power consumption render the LCD to replace the traditional cathode ray tube (CRT). The LCD is currently used as a monitor for a lap-top computer and even for a desktop computer, gaining its popularity.

0005As shown in <figref idref="DRAWINGS">FIG. 1</figref>, an LCD includes an LCD panel 101 and a light supply unit. The LCD panel 101 includes a TFT substrate 10, a color filter substrate 20, multiple gate TCPs 30 connected to gate lines (not shown) of the TFT substrate 10, multiple data TCPs 40 connected to data lines (not shown) of the TFT substrate 10, a gate PCB 50 connected to the multiple gate TCPs 30, a data PCB 60 connected with the multiple data TCPs 40. The light supply unit includes multiple optical sheets such as a light guiding plate 90, a light diffusing plate (not shown), etc., a lamp assembly 80, and a receiving case called as “mold frame”. The light guiding plate 90 has a decreasing thickness as it travels from the lamp unit 80 to the data PCB 60.

0006A power supply unit and a controller that processes gate signals and data signals coming from an external device are mounted on the data PCB 60. A gate voltage supply part is formed on the gate PCB 50 and supplies a gate driving voltage to gate lines by a control signal from the controller on the data PCB 60.

0007To supply the control signal and the gate driving voltage into the gate PCB 50 from the data PCB 60, connectors 55 and 65 are respectively installed in the gate PCB 50 and data PCB 60 and are connected to each other through a connecting member, “flexible printed circuit (FPC)”.

0008Semiconductor fabrication technologies have developed in the areas of thin film formation, and packaging. This allows semiconductor devices to be mounted on the gate PCB 50 and to function as gate power supply source on the data PCB 60.

0009Under such a configuration, the gate PCB 50 only transfers to the gate TCP 30 gate driving signals processed in the data PCB 60.

0010The conventional LCD has following problems.

0011First, in order to apply gate driving signals processed in data PCB 60 to gate PCB 50, gate PCB 50 and data PCB 60 need connectors 55 and 65.

0012The connectors 55 and 56 are generally installed on the front surface or on the rear surface of the PCBs 50 and 60. This increases the thickness of the LCD and makes it difficult to achieve a compact size LCD.

0013And the flexible printed circuit (FPC) 70 that connects the connector 55 and the connector 65 complicates the assembly process and increases the fabrication costs.

0014Finally, a bent type PCB that is mostly used currently bends a gate PCB 50 and data PCB 60 and they are fixed at the rear surface of the reflecting plate of a backlight assembly. In such a configuration, the data PCB 60 is put in a space between a relatively thin side edge 92 of the non-symmetric light guiding plate 90 and the mold frame. Thus the data PCB 69 does not increase the thickness of the LCD much. On the other hand, the gate PCB 50 is put in a space between a thickness varying side of the light guiding plate 90, and the mold frame. Specifically, one side of the gate PCB 50 is attached to a thick portion of the rear surface of the light guiding plate 90, making a thick LCD depending on the thickness of the light guiding plate 90.

SUMMARY OF THE INVENTION

0015The present invention is to provide an integrated PCB that has a gate PCB and a data PCB on one board and is capable of allowing driving signals to be applied to gate lines and data lines without using additional connectors and flexible printed circuits.

0016It is another object of the present invention to allow a tape carrier package that receives a driving signal from the integrated PCB to transmit the received driving signal into another tape carrier package.

0017It is yet another object of the present invention to prevent delays of driving signals when a driving signal processed in the integrated PCB is sent to gate lines or data lines via tape carrier packages.

0018It is still another object of the present invention to provide an improved assembly between tape carrier packages and TFT substrate, thereby attaining an easy carrying and decreasing the thickness of the panel.

0019To achieve these and other advantages in accordance with the purpose of the present invention as embodied and broadly described, a tape carrier package comprises a base substrate, a gate driver IC formed on the base substrate, an input pattern formed on the base substrate that supplies gate driving signals input from an external device to the gate driver IC, a first output pattern formed on said base substrate that outputs a first gate driving signal processed in the gate driver IC, and a second output pattern formed on said base substrate, that outputs a second gate driving signal bypassing the gate driver IC among the gate driving signals.

0020Also a liquid crystal display panel assembly and a liquid crystal display using such an assembly are disclosed.

BRIEF DESCRIPTION OF THE DRAWINGS

0021The above objects and other advantages of the present invention will become more apparent by describing in detail a preferred embodiment with reference to the attached drawings in which:

0022<figref idref="DRAWINGS">FIG. 1</figref> is a perspective view showing a conventional liquid crystal display panel;

0023<figref idref="DRAWINGS">FIG. 2</figref> is an exploded perspective view of the liquid crystal display according to a preferred embodiment of the present invention;

0024<figref idref="DRAWINGS">FIG. 3</figref> is a perspective view of the liquid crystal panel according to a preferred embodiment of the present invention;

0025<figref idref="DRAWINGS">FIG. 4</figref> is a partially exploded perspective view of the liquid crystal display panel according to a preferred embodiment of the present invention;

0026<figref idref="DRAWINGS">FIG. 5</figref> is a schematic view for describing an operation of the liquid crystal display panel according to a preferred embodiment of the present invention;

0027<figref idref="DRAWINGS">FIG. 6</figref> is a perspective view showing an assembly of tape carrier package and TFT substrate of the liquid crystal display panel according to a preferred embodiment of the present invention;

0028<figref idref="DRAWINGS">FIG. 7</figref> is a sectional view taken along the line 7-7′ of <figref idref="DRAWINGS">FIG. 6</figref>; and

0029<figref idref="DRAWINGS">FIG. 8</figref> is a partial sectional view of the liquid crystal display according to a preferred embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

0030Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings.

0031Hereinafter, a liquid crystal display panel, a tape carrier package and a liquid crystal display according to the present invention are described more fully with reference to the accompanying drawings.

0032<figref idref="DRAWINGS">FIG. 2</figref> is an exploded perspective view of the liquid crystal display according to a preferred embodiment of the present invention.

0033The liquid crystal display 601 comprises a liquid crystal display panel assembly 200, a back light assembly 300, a chassis 400 and a cover 500.

0034The back light assembly 300 is comprised of optical sheets 310, a light guiding plate 320, a lamp assembly 330, a light reflecting plate 340 and a mold frame as a receiving container.

0035Hereinafter, the liquid crystal display panel assembly 200 according to the present invention is described referring to the <figref idref="DRAWINGS">FIG. 3</figref> and the liquid crystal display panel is then described more fully referring to <figref idref="DRAWINGS">FIG. 4</figref>.

0036Referring to <figref idref="DRAWINGS">FIG. 3</figref>, the liquid crystal display panel assembly 200 comprises a liquid crystal display panel 202 having a TFT substrate 240 and a color filter substrate 250, a liquid crystal (not shown) interposed between the TFT substrate 240 and the color filter substrate 250, tape carrier packages 210 and 220 and a single integrated PCB 260.

0037Referring to <figref idref="DRAWINGS">FIG. 4</figref>, the liquid crystal display panel 202 comprises a TFT substrate 240 and a color filter substrate 250. The filter substrate 250 is smaller than the TFT substrate 240 and faces the TFT substrate 240. The TFT substrate 240 includes a gate 261, a data line 242, a thin film transistor (not shown) and a pixel electrode (not shown).

0038The tape carrier packages 210, 210′, 226, and 229 are electrically coupled to the TFT substrate 240 and includes gate tape carrier packages 210 and 210′ and data tape carrier packages 226 and 229. The gate tape carrier packages 210 and 210′ are connected to the gate lines on the TFT substrate 240. The data tape carrier packages 226 and 229 are connected to the data lines.

0039The single integrated PCB 260 that is electrically connected to the tape carrier packages 226 and 229 has various driving elements for processing gate driving signals and data driving signals. The gate driving signals are input to the gate tape carrier package 210 and the data driving signals are input to the data tape carrier package 220.

0040The color filter substrate 250 includes a transparent glass substrate 250. The transparent glass substrate 250 has a lattice type black matrix (not shown), an RGB pixel (not shown) and a transparent and conductive ITO (Indium Thin Oxide) electrode. Here, the RGB pixels are formed by patterning a photoresist mixed with RBG pigment. The ITO electrode functions as a common electrode.

0041Meanwhile, the TFT substrate 240 includes a transparent glass substrate. On the transparent glass substrate, a plurality of thin film transistors (not shown) each including a gate, a source, and a drain are formed in a matrix arrangement by the semiconductor thin film formation process.

0042Gate terminals of all the thin film transistors in a row are connected to a gate line 241 that is extended to an end of the one side of the TFT substrate 240. Source terminals of all the thin film transistors in one column are connected to a data line 242 formed at an end of the other side of the TFT substrate 240. The drain terminal of each thin film transistor is connected to an ITO electrode, which is a pixel electrode. Therefore, the ITO electrode faces the common electrode of the color filter substrate 250.

0043Further, the gate lines 241 are disposed in an effective display region 243 at the same interval with respect to each other while they are disposed in a perimeter region with a smaller interval than the interval of the gate line of the effective display region 243, i.e., the gate lines 241 in the perimeter region are concentrated towards output terminals of the TCPs 210 and 210′.

0044The preferred embodiment of the present invention has three gate line groups, although <figref idref="DRAWINGS">FIG. 4</figref> shows only two gate line groups 245.

0045Also, the data lines 242 are disposed in the effective display region 243 at the same interval with respect to each other. The data lines 242 are collected toward output terminals of the TCPs 226 and 229 on the perimeter region 244 and form a data line group 246 on the perimeter region 244 and connected to the data tape carrier packages 226 and 229.

0046The preferred embodiment of the present invention has six data line groups and <figref idref="DRAWINGS">FIG. 6</figref> shows only two data line groups 246.

0047Some lines of a gate line group 245 placed at one edge and some lines of a data line group 246 placed at one edge around a corner of the TFT substrate 240 are connected to each other, thereby forming a first gate driving signal transmission line 247.

0048One end of the first gate driving signal transmission line 247 extends to one side of the TFT substrate 240 in which the end of the outermost gate line group 245 is formed. The other end of the first gate driving signal transmission line 247 extends to one side of the TFT substrate 240 in which the end of the outermost data line group 246 adjacent to the gate line group 245 is disposed.

0049In the first gate driving signal transmission line 247, an input terminal 247a that receives a signal is defined as one end portion of the first gate driving signal transmission line 247 at the side of the TCP 226. And an output terminal 247b is defined as the other end of the first gate driving signal transmission line 247 at the side of the TCP 221.

0050Meanwhile, a second gate driving signal transmission line 248 is formed at the space between the two gate line groups 245.

0051One end of the second gate driving signal transmission line 248 is formed at one side of the TFT substrate 240 and extends to a desired length in parallel with the gate line group 245. The second gate driving signal transmission line 248 is bent perpendicularly to the adjacent gate line group 245 and extends again to a desired length. And the second gate driving signal transmission line 248 is then bent to be parallel with the adjacent gate line group 245 and extends to the other side of the TFT substrate 240.

0052At this time, an input terminal 248a is defined as one end portion of the second gate driving signal transmission line 248 and an output terminal 248b is defined as the other end portion of the second gate driving signal transmission line 248.

0053The gate tape carrier packages 210 and 210′ and data tape carrier packages 226 and 229 will be described more fully referring to the <figref idref="DRAWINGS">FIG. 4</figref>.

0054The gate tape carrier package 210 is comprised of a FPC 211, a gate driver IC 212, a gate driving signal input pattern 213, a first gate driving signal output pattern (or a bypass line) 214, a second gate driving signal output pattern 215.

0055The gate driver IC 212 is disposed at the rear surface of the FPC 211 in a flip chip type manner. The second gate driving signal output pattern 215 is disposed at the FPC 211 on which the gate driver IC 212 is disposed. One end of the second gate driving signal output pattern 215 is connected with output terminals of the gate driver IC 212 and the other end of the second gate driving signal output pattern 215 is connected through an anisotropic conductive film 270 to the gate line group 245.

0056The gate driving signal input pattern 213 receives the gate driving signal from the output terminal 247b of the first gate driving signal transmission line 247 and sends the signal to the gate driver IC 212.

0057Thus, one end of the gate driving signal input pattern 213 is connected through the anisotropic conductive film 270 to the output terminal 247b of the first gate driving signal transmission line 247 and the other end of the gate driving signal input pattern 213 is connected to the input terminals of the gate driver IC 212.

0058The first gate driving signal output pattern 214 relays the gate driving signal from the TCP 226 to the input terminal 248a of the second gate driving signal transmission line 248 formed between the gate line groups 245.

0059To realize this, one end of the first gate driving signal output pattern 214 is connected through the anisotropic conductive film 270 to the input terminal 248a of the second gate driving signal transmission line 248 and the other end the first gate driving signal output pattern 214 is connected to the output terminal 247b of the first gate driving signal transmission line 247.

0060At this time, the first gate driving signal output pattern 214 and the gate driving signal input pattern 213 are formed to be symmetric with respect to the gate driver IC 212.

0061If an output enable signal (OE signal) is ON, the gate driving signal, which is input through the gate driving signal input pattern 213 to the gate driver IC 212, is processed in the corresponding gate driver IC 212, and then applied to the second gate driving signal output pattern 215. If the OE signal is OFF, the gate driving signal is not applied to the second gate driving signal output pattern 215 but to the first gate driving signal output pattern 214.

0062Meanwhile, the data tape carrier package includes a plurality of packages, i.e., a dual functioning tape carrier package 226 for processing the gate driving signals and the data driving signals and a single functioning tape carrier package 229 only for the data driving signal.

0063Referring to <figref idref="DRAWINGS">FIG. 4</figref>, the dual functioning tape carrier package 226 for gate/data driving signals comprises a FPC 221 that is a flexible base film 221, the gate driving signal transmission pattern 223, a data driver IC 222, a data driving signal input pattern 224 and a data driving signal output pattern 225.

0064Further, the data driver IC 222 is disposed at the rear surface of the FPC 221 in a flip chip type manner. One end of the data driving signal input pattern 224 is connected to input terminals of the data driver IC 222. And the other end of the data driving signal input pattern 224 is connected to the single integrated PCB 260.

0065In addition, one end of the data driving signal output pattern 225 is connected to output terminals of the data driver IC 222, and the other end of the data driving signal output pattern 225 is connected through a anisotropic conductive film 270 to the aforementioned data line group 246.

0066On the FPC 221 of the dual functioning tape carrier package 226 for the gate/data driving signals, there are formed the data driving signal output pattern 225, the data driving signal input pattern 224, the data driver IC 222 and the gate driving signal transmission pattern 223 that is separate from the data driver IC 222.

0067One end of the gate driving signal transmission pattern 223 is connected to the single integrated PCB 260. And the other end of the gate driving signal transmission pattern 223 is connected through the anisotropic conductive film 270 to the input terminal 247a of the first gate driving signal transmission line 247.

0068Meanwhile, the single functioning tape carrier package 229 comprises a FPC 227, a data driver IC 222, a data driving signal input pattern 224′ and a data driving signal output pattern 225′.

0069One end of the data driving signal input pattern 224′ is connected to the single integrated PCB 260. And the other end of the data driving signal input pattern 224′ is connected to input terminals of the data driver IC 222. One end of the data driving signal output pattern 225′ is connected to output terminals of data driver IC 222. And the other end of the data driving signal output pattern 225′ is connected through the anisotropic conductive film 270 to the data line group 246.

0070Therefore, the gate driving signal generated from the single integrated PCB 260 is input through the gate driving signal transmission pattern 223 of the dual functioning tape carrier package 226 for the gate/data driving signal, the input terminal 247a of the first gate driving signal transmission line 247, the output terminal 247b of the first gate driving transmission line 247 and the gate driving signal input pattern 213 of the gate tape carrier package 210 to the gate driver IC 212. The gate driving signal is then input through the second gate driving signal output pattern 215 to the gate line group 245 by the OE signal. Meanwhile, some of the gate driving signal generated from the single integrated PCB 260 are input through the first gate driving signal output pattern 214 to the gate driving signal input patter 213′ or the first gate driving signal output pattern 214′ of the adjacent TCP 211′.

0071The signals that come from the single integrated PCB 260 through the above passages to the gate line group 245 are a gate clock, the OE signal, a VON signal which is a turn-on signal of the thin film transistor and a VOFF signal which is a turn-off signal of the thin film transistor.

0072In addition, the data driving signal generated from the single integrated PCB 260 is input through the tape carrier package 221 for the gate/data driving signal and the single functioning tape carrier package 229 only for the data driving signal to the data line group 246 of the TFT substrate 240.

0073The signals input from the single integrated PCB 260 through the data driving signal input patterns 224 and 224′, the data driver IC 222 and the data driving signal output patterns 225 and 225′ to the data line group 246, are a STH (Start Horizontal) signal for exactly latching a color data from an outer data processing unit to the data driver IC 222, a LOAD signal which outputs the signal latched in the data driver IC 222 to the liquid crystal display panel assembly 200, a clock signal for transmitting the data and RGB color data, etc.

0074Next, operations of the liquid crystal display according to the present invention are described with reference to the accompanying drawings.

0075Video signals as well as electric power, control signals, and color data are input from an external information processing unit to the single integrated PCB 260. The single integrated PCB 260 then generates gate driving signals and data driving signals depending on the input video signals. Thereafter, the data driving signals generated from the single integrated PCB 260 are respectively input into the respective data driver IC 222 and 222′ via the data driving signal input patterns 224 and 224′ of data driving signal transmission lines of the dual functioning tape carrier package 226 and the single functioning tape carrier package 229. The processed data driving signals are loaded to selected data lines 242 of the data line group 246 via the data driving signal output patterns 225 and 225′. At this time, gray scale voltages for displaying colors are also applied to respective data lines 242.

0076Simultaneously, among gate driving signals processed in the single integrated PCB 260, a gate voltage is sent to an input terminal 247a of the first gate driving signal transmission line 247 through the gate driving signal transmission pattern. One component of the gate driving signals is a gate voltage. The gate voltage goes along the first gate driving signal transmission line 247 and then is sent to the input terminal of the gate driving signal input pattern 213.

0077The driving signals inputted to the gate driving signal input pattern 213 are also transferred into the gate driving signal input pattern 213′ of the adjacent gate tape carrier package 210′ through the first gate driving signal output pattern 214 connected to the input terminal of the gate driving signal input pattern 213 and the input terminal 248a of the second gate driving signal transmission line 248 printed on the TFT substrate 240. By such signal transmissions, all the gate driver IC 212 and 212′ are prepared to apply the gate driving signals to the gate lines by the OE signal.

0078Next, the OE signal is carried in or carried out into the gate driver ICs 212 and 212′ via the gate driving signal pattern 223 of the TCP 226, the first gate driving signal transmission line 247, the gate driving signal input pattern 213, and the second gate driving signal transmission line 248 in the named order and thereby pre-designated gate voltages, such as turn-on voltage Von and turn-off voltage Voff are applied to all of the gate lines within a period of one frame.

0079As the Von signal is input into gate terminals of thin film transistors placed along the rows through the gate lines 241, the thin film transistors are all turned on and the gray scale voltages which has been already applied to the data lines 242 are applied to the pixel electrodes. This generates an electric field proportional to the gray scale voltage, between the pixel electrode and the common electrode.

0080As the voltages are applied to the pixel electrodes, the liquid crystal interposed between the pixel electrode and the common electrode re-arranges and the light transmittance changes accordingly. As a result, lights may pass through the TFT substrate 240 depending on the light transmittance. Thereafter, the lights pass through the RGB elements formed on the color filter substrate 250 and displays an image. At this time, the electric field between the pixel electrode and the common electrode is maintained for a period of one frame in which all the gate lines 241 are turned on in order.

0081The above-described operations are performed very quickly and, thus, the liquid crystal display appears to display information in full color.

0082The gate driving signals processed in the single integrated PCB 260 are input into all the gate lines 241 via the double functioning tape carrier package 226, the gate tape carrier package 210, and the gate driver IC 212.

0083Then, the transmission pattern and the transmission lines applied to the TFT substrate 240, the gate tape carrier package 210, the dual functioning tape carrier package 226 are formed in a very small space with a fine pitch. This fine pitch pattern and line may form a RC time delay circuit due to a very high resistance of the substrate and the parasitic capacitance formed between the gate transmission lines.

0084The RC time delay circuit may also cause the turn-on voltage Von and the turn-off voltage Voff of the gate driving signals to be modulated. A delay in transmission of the gate driving signals degrade the picture quality, causing flickers in the effective display region of the panel and a divisional appearance on the effective region of the panel.

0085Moreover, the modulation in the turn-on voltage and the turn-off voltage affects the gray scale voltage being input into the data lines 242, resulting in a variation in the gray scale. In other words, both of the gate driving signal delay and the modulation in the turn-on and turn-off voltages significantly degrades the picture quality and display colors.

0086In order to prevent the gate driving signal transmission delay and the modulation of the turn-on voltage and the turn-off voltage, the resistance between the transmission pattern and the transmission lines needs to be decreased. The resistance can be theoretically decreased by enlarging the sectional area of the gate driving signal transmission line and the gate driving signal pattern or sufficiently widening the interval between the gate driving signal transmission lines.

0087However, such a conventional wisdom consumes the scarce resource of real estate on the TFT substrate 240, making it more difficult to produce a compact and lighter LCD product.

0088Accordingly, several preferred embodiments are disclosed to resolve such drawbacks. They are described with reference to the accompanying drawing of <figref idref="DRAWINGS">FIG. 5</figref>.

0089As described referring to FIGS. 2 to 6, the first gate driving signal transmission line 247, the gate driving signal transmission pattern 223, the gate driving signal input pattern 213, the first gate output pattern 214 are grouped in plurality. For example, three gate driving signal line groups comprise a first gate driving signal line group 281, a second gate driving signal line group 282, and a third gate driving signal line group 283. Each of the three groups has a plurality of signal transmission lines.

0090A plurality of gate driving signals are transferred through the respective corresponding gate driving signal line groups 281, 282, and 283 into the respective corresponding gate driver ICs 212. Here, it is natural for the single integrated PCB 260 to have additional output terminals A, B, and C which are connected to the respective gate driving signal transmission groups.

0091Specifically, the first gate driving signal lines group 283 is connected to the first gate driver IC of the first gate tape carrier package, the second gate driving signal line group 282 is connected to the second gate driver IC of the second gate tape carrier package, and the third gate driving signal line group 281 is connected to the third gate driver IC of the third gate tape carrier package.

0092In other words, the plurality of gate driving signal transmission lines are grouped into several groups and respective groups are connected to corresponding gate driver ICs in parallel, thereby minimizing the RC time delay during the transmission of the gate driving signals and preventing the flicker and picture division appearance.

0093As another embodiment, upon considering the length of the respective gate driving signal lines from the single integrated PCB 260, the first gate driving signal line group 281 is longer than the second gate driving signal line group 282. And the second gate driving signal line group 282 is longer than the third gate driving signal line group 283. In the above constitution, since resistance of the lines groups is proportional to the length, the first gate driving signal lines group 281 has the biggest resistance when the diameter of the lines of the respective groups are the same. Therefore, in order to prevent RC time delay due to a difference in the resistance between the three gate driving signal lines, the diameter of each of signal transmission lines of the first gate driving signal line group is bigger than the second gate driving line group and the diameter of each of signal transmission lines of the second gate driving signal line group is bigger than the third gate driving line group.

0094Another embodiment to prevent the flicker and the picture division appearance phenomena applies respective gate driving signals corresponding to the respective gate driving signal line groups 281, 282, and 283 to the corresponding gate driving signal line groups 281, 282, and 283 with a time interval. A first gate driving signal corresponding to the first gate driving signal line group 281 is first applied to the first gate driving signal line group 281. A second gate driving signal corresponding to the second gate driving signal line group 282 is secondly applied to the second gate driving signal line group 282 after a first predetermined time elapses after sending the first gate driving signal. Then, a third gate driving signal corresponding to the third gate driving signal line group 283 is finally applied to the third gate driving signal line group 283 after a second predetermined time elapses after sending the second gate driving signal. The first and second predetermined time is determined by respective resistance values calculated considering the lengths and diameters of the first, second, and third gate driving signal line groups 281, 282, and 283.

0095As still another embodiment to prevent the flicker and the picture division appearance problems, respective gate driving signal line groups 281, 282 and 283 are electrically connected to respective corresponding gate driver ICs in parallel and a turning resistor that controls the timing of the gate driving signals is connected to the respective gate driving signal line groups 281, 282, and 283 or the single integrated PCB 260.

0096Specifically, Voff signal that turns off the thin film transistor proves to be sensitively affected by the substrate resistance and the signal transmission patterns. As described previously, since the substrate resistance and the pattern resistance are determined by the total length and the diameter of the gate driving signal line groups 281, 282, and 283, the gate driving signal line groups have different signal arriving time, generating the flicker and the picture division appearance problems and degrading the picture quality.

0097Therefore, the single integrated PCB 260 generates the Voff signal considering maximum resistance among the resistances applied to the gate driving signal line groups 281, 282, and 283.

0098However, although the Voff signal is input into respective gate driver ICs through the respective corresponding gate driving signal line groups 281, 282, and 283 considering the maximum resistance, the final Voff signal still has a deviation due to the resistance. Accordingly, in order to eliminate the deviation, a turning resistor is provided.

0099The turning resistor is respectively formed in each of the gate driving signal line groups 281, 282, and 283 and enables to output a Voff signal with a minimum deviation, thereby eliminating the flicker and the picture division appearance problems.

0100Next, a method for operating the LCD panel according to the above preferred embodiments is described.

0101First, the single integrated PCB 260 generates a gate driving signal and a data driving signal. The data driving signal is transformed into a source signal including a gray scale voltage through the dual functioning data tape carrier package 226 and the single functioning data tape carrier package 229. The source signal is then applied to the data line group 246.

0102The gate driving signals from the single integrated PCB 260 are concurrently input to all the gate driver ICs 212 of the gate tape carrier packages 210 through the first gate driving signal line group 281 to the third gate driving signal line group 283.

0103The first corresponding gate driving IC receives a first gate driving signal from the single integrated PCB 260 through the third gate driving signal lines group 283 and then applies Von signals to gate lines in portion of “I” of the effective display region in <figref idref="DRAWINGS">FIG. 5</figref> using OE signal. The image of the portion “I” is maintained for one frame.

0104The second corresponding gate driving IC receives a second gate driving signal from the single integrated PCB 260 through the second gate driving signal line group 282 and then applies Von signals to gate lines in portion “II” of the effective display region in <figref idref="DRAWINGS">FIG. 5</figref>. The picture of the portion “II” is also maintained for one frame together with the picture of the portion “I”.

0105The third corresponding gate driving IC receives a third gate driving signal transmitted from the single integrated PCB 260 through the first gate driving signal line group 281 and then applies Von signals into gate lines in portion “III” of the effective 21. display region in <figref idref="DRAWINGS">FIG. 5</figref>. The picture of the portion “III” is also maintained for one frame together with the picture of the portion “I” and portion “II”.

0106Because these steps are performed very quickly, it may display a moving picture or a clean still picture on the panel.

0107The liquid crystal display panel according to the present invention does not need a gate PCB and only the gate tape carrier packages 210 are coupled to the ends of the gate lines 241 formed on the TFT substrate 240.

0108Thus, these gate tape carrier packages 210 are bent and then attached to the rear surface of the TFT substrate 240 as shown in <figref idref="DRAWINGS">FIGS. 6 and 7</figref>. This would produce a compact liquid crystal display panel.

0109<figref idref="DRAWINGS">FIG. 8</figref> is a partial sectional view that can be handled easily showing a part of a liquid crystal display according to the present invention.

0110Referring to <figref idref="DRAWINGS">FIG. 8</figref>, a backlight assembly 300 includes a mold frame 350. The mold frame 350 receives a light reflecting plate 340, a light guiding plate 320, and optical sheets 310 in the named order. The liquid crystal panel of the present invention is mounted on the optical sheets 310 and the perimeter region of the liquid crystal panel 200 is fixed by a chassis 400.

0111Here, a tape carrier package 210 one end of which is connected to the TFT substrate 240 is bent and a gate driver IC 212 of the tape carrier package 210 is attached to the rear surface of the TFT substrate 240 by a fixing means such as a double sided adhesive tape, an adhesive, or a clip.

0112The mold frame 350 has a receiving groove 350a that can accommodate the tape carrier package 210.

0113Meanwhile, although the above described embodiments show and describe the tape carrier packages of the above-described configurations, a chip on flexible (COF) having more flexible base film than the base film of the flexible printed circuit may be also used.

0114Also, although <figref idref="DRAWINGS">FIG. 4</figref> shows and describes that the gate driving signal transmission pattern 223 is integrated together with both of the data driving signal input pattern 224 and the data driving signal output pattern 225 on the data tape carrier package 226 of <figref idref="DRAWINGS">FIG. 4</figref>, only the gate driving signal transmission pattern 223 may be formed on an independent flexible base no having a driving chip.

0115As described above, the present invention can provide a compact size liquid crystal display by integrally processing gate and data driving signals using a single integrated PCB.

0116Moreover, using the single integrated PCB may eliminate the connector and a flexible printed circuit that is used for connecting two PCBs. As a result, spaces for the connector and the flexible printed circuit can be saved. Also, the whole assembly process is simplified.

0117While the present invention has been described in detail, it should be understood that various changes, substitutions and alterations can be made hereto without departing from the spirit and scope of the invention as defined by the appended claims.

Contents4

Every citation, both ways

Citations
Document	Relation	Office	Cited during
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22 members in 3 offices

This recordMember, by publication datePriority claim

Priority claims12

Priority claims
Document	Office	Kind	Date
199913650	Republic of Korea	–	1999-04-16
19990013650	Republic of Korea	A	1999-04-16
55140400	United States of America	A	2000-04-17
69345903	United States of America	A	2003-10-27
10968005	United States of America	A	2005-04-20
09551404	–	–	–
10693459	–	–	–
199913650	–	–	–
KR19990013650	–	–	–
US20000551404	–	–	–
US20030693459	–	–	–
US20050109680	–	–	–

Members22

Family members, oldest first
Document	Office	Kind
KR20000066493A	Republic of Korea	A	2000-11-15
JP2000356783A	Japan	A	2000-12-26
KR20010009044A	Republic of Korea	A	2001-02-05
KR100304261B1	Republic of Korea	B1	2001-09-26
US2002140654A1	United States of America	A1	2002-10-03
US2003103027A1	United States of America	A1	2003-06-05
US6639589B1	United States of America	B1	2003-10-28
US2003201989A1	United States of America	A1	2003-10-30
US6664942B1	United States of America	B1	2003-12-16
US2004085279A1	United States of America	A1	2004-05-06
US2005190174A1	United States of America	A1	2005-09-01
US2005190175A1	United States of America	A1	2005-09-01
KR100599516B1	Republic of Korea	B1	2006-07-13
US7102631B2	United States of America	B2	2006-09-05
US7106317B2	United States of America	B2	2006-09-12
US7133037B2	United States of America	B2	2006-11-07
US7268776B2	United States of America	B2	2007-09-11
US7295196B2	United States of America	B2	2007-11-13
US7339568B2	United States of America	B2	2008-03-04
US2008062109A1	United States of America	A1	2008-03-13
US2009073100A1	United States of America	A1	2009-03-19
US8031150B2	United States of America	B2	2011-10-04

45 transactions on the USPTO file

Allowed after 2 non-final rejections.

Non-final rejections: 2
Final rejections: 0
RCEs: 0
Appeals: 0

Over time

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Transactions

Prosecution transactions, newest first
	Event	Code
2013-10-10	Change in Power of Attorney (May Include Associate POA)PA..	PA..
2013-10-09	Correspondence Address ChangeC.AD	C.AD
2007-11-13	Recordation of Patent Grant MailedPGM/	PGM/
2007-11-13	Patent Issue Date Used in PTA CalculationAllowedPTAC	PTAC
2007-10-24	Issue Notification MailedAllowedWPIR	WPIR
2007-10-11	Dispatch to FDCD1935	D1935
2007-10-10	Application Is Considered Ready for IssuePILS	PILS
2007-10-04	Issue Fee Payment VerifiedN084	N084
2007-10-04	Issue Fee Payment ReceivedIFEE	IFEE
2007-07-10	Mail Notice of AllowanceAllowedMN/=.	MN/=.
2007-07-05	Notice of Allowance Data Verification CompletedAllowedN/=.	N/=.
2007-06-04	Correspondence Address ChangeC.ADB	C.ADB
2007-05-04	Date Forwarded to ExaminerFWDX	FWDX
2007-04-27	Response after Non-Final ActionA...	A...
2007-01-29	Mail Notice of Withdrawn ActionMW/AC	MW/AC
2007-01-29	Mail Non-Final RejectionNon-final rejectionMCTNF	MCTNF
2007-01-24	Non-Final RejectionNon-final rejectionCTNF	CTNF
2007-01-24	Withdrawing/Vacating Office Action LetterW/AC	W/AC
2007-01-16	Mail Miscellaneous Communication to ApplicantMM327	MM327
2007-01-12	Miscellaneous Communication to Applicant - No Action CountM327	M327
2006-07-11	Miscellaneous Incoming LetterLET.	LET.
2006-05-03	Correspondence Address ChangeC.AD	C.AD
2006-05-03	Change in Power of Attorney (May Include Associate POA)PA..	PA..
2006-03-22	Case Docketed to Examiner in GAUDOCK	DOCK
2006-02-17	Mail Non-Final RejectionNon-final rejectionMCTNF	MCTNF
2006-02-15	Non-Final RejectionNon-final rejectionCTNF	CTNF
2005-10-05	IFW TSS Processing by Tech Center CompleteTSSCOMP	TSSCOMP
2005-10-05	Case Docketed to Examiner in GAUDOCK	DOCK
2005-05-20	Application Return from OIPEWROIPE	WROIPE
2005-05-20	Application Is Now CompleteCOMP	COMP
2005-05-20	Application Return TO OIPEROIPE	ROIPE
2005-05-20	Application Is Now CompleteCOMP	COMP
2005-05-20	Application Is Now CompleteCOMP	COMP
2005-05-19	Application Return from OIPEWROIPE	WROIPE
2005-05-19	Application Return TO OIPEROIPE	ROIPE
2005-05-19	Application Dispatched from OIPEOIPE	OIPE
2005-05-10	Cleared by L&R (LARS)L128	L128
2005-05-06	Referred to Level 2 (LARS) by OIPE CSRL198	L198
2005-04-30	IFW Scan & PACR Auto Security ReviewSCAN	SCAN
2005-04-20	Information Disclosure Statement consideredIDSC	IDSC
2005-04-20	Reference capture on IDSRCAP	RCAP
2005-04-20	Information Disclosure Statement (IDS) FiledM844	M844
2005-04-20	Information Disclosure Statement (IDS) FiledWIDS	WIDS
2005-04-20	Preliminary AmendmentA.PE	A.PE
2005-04-20	Initial Exam Team nnIEXX	IEXX

9 legal events, as the office reported them to INPADOC

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Events

Legal events, newest first
	Event	Code
2019-04-23	Maintenance fee paymentMAFP	MAFP
2015-04-30	Fee paymentFPAY	FPAY
2014-01-07	AssignmentAS	AS
2012-09-22	AssignmentAS	AS
2011-04-19	Fee paymentFPAY	FPAY
2010-12-01	Fee payment procedurePAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITYFEPP	FEPP
2010-12-01	Fee payment procedurePAYER NUMBER DE-ASSIGNED (ORIGINAL EVENT CODE: RMPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITYFEPP	FEPP
2007-12-04	Fee payment procedurePAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITYFEPP	FEPP
2007-10-24	Information on status: patent grantGrantedPATENTED CASESTCF	STCF