Silicon layer for uniformizing temperature during photo-annealing

BACKGROUND OF THE INVENTION

00011. Field of the Invention

0002The present invention pertains to semiconductor processing, and in particular to a method of improving the temperature uniformity when photon-annealing a semiconductor substrate.

00032. Description of the Prior art

0004In order to fabricate high-performance semiconductor devices such as integrated circuits (ICs), the manufacturing process typically includes an annealing process. The annealing process serves to activate dopants in the semiconductor wafer along the way to forming the final devices (e.g., transistors). One annealing technique involves irradiating the semiconductor wafer with short, intense pulses of radiation. This is referred to herein as “photo-annealing.” The short duration of the annealing radiation pulses allows for the fabrication of transistors with very low sheet resistance and ultra-shallow junctions, which translates into optimal device performance.

0005When lasers are used to perform the annealing, the photo-annealing process is referred to as “laser thermal processing” (LTP), or alternatively “laser thermal annealing” (LTA). One method of LTA applied to semiconductor manufacturing involves using a short-pulsed laser to thermally anneal the source and drain of the transistor to activate the implanted dopants therein. Under the appropriate conditions, i.e. melting of the junction material followed by rapid solidification, it is possible to produce source and drain junctions with activated dopant levels that are above the solid solubility limit. This produces transistors with greater speeds and higher drive currents. This LTP technique is disclosed in U.S. Pat. No. 5,956,603, which patent is incorporated by reference herein.

0006Other techniques for photo-annealing semiconductor substrates involve the use of flash lamps to create the pulse of radiation. For example, U.S. Pat. No. 4,151,008, entitled, “Method Involving Pulsed Light Processing of Semiconductor Devices,” discloses a method in which a pulsed laser or flash lamp produces a short duration pulse of light for thermal processing of selected regions of a semiconductor device. The light pulse is directed towards the semiconductor device and irradiates selected surface regions of the device to be processed. Energy from the absorbed light pulse momentarily elevates the temperature of the selected regions above threshold processing temperatures for rapid, effective annealing, sintering or other thermal processing. The characteristics of the light pulse are such that only those surface regions in the immediate vicinity of the flash, i.e. at the top of the substrate and within 100 microns of the edge of the field, are elevated to a high temperature. The remaining mass of the semiconductor device is not subjected to unnecessary or undesirable high temperature exposure and serves to quickly cool the heated area.

0007However, a shortcoming of this technique is that the dopant concentration cannot go beyond the solid solubility limit. Also, the technique suffers from temperature non-uniformities due to the different reflectivity properties of the transistor and related structures formed in and on the semiconductor substrate, prior to the annealing step.

0008Modern ICs contain a variety of device geometries and materials, and the accompanying structures formed in the semiconductor wafer have different reflectivities. To achieve uniform performance in each device, it is necessary that all devices be heated (annealed) to essentially the same temperature. This constrains the permissible variation in reflectivity of each device (e.g., transistor) in the circuit and constrains the spatial variations in the density of devices throughout the circuit. High-frequency spatial variations in reflectivity tend to be smoothed out by thermal conduction, but low frequency variations create similar variations in annealing temperature. For certain semiconductor processes, such as the process for activating dopants without melting the substrate (i.e., a non-melt process), the temperature of the surface of the semiconductor substrate must be kept very uniform (<±10° C.) and remain below the melting point of silicon (assuming the junction is not amorphized).

0009U.S. Pat. No. 6,635,588 (the '588 patent) and U.S. Pat. No. 6,495,390 (the '390 patent) describe respective techniques for controlling the amount of heat transferred to a process region of a workpiece (wafer) from exposure with a pulse of radiation. The '588 patent uses a thermally induced phase switch layer, and the '390 patent uses a thermally induced reflectivity layer. The phase switch layer is a film stack that includes an absorber layer and a layer of material that undergoes a phase transition. The absorber and phase transition layers are deposited atop a silicon wafer. The absorber layer absorbs radiation and converts the absorbed radiation into heat.

0010The phase transition layer can be deposited above or below the absorber layer and is chosen to have a phase transition temperature slightly above the desired maximum temperature of the underlying layers. The phase switch layer may include other layers, such as a thermal insulator layer and a layer to simplify stripping the phase switch layer once its function is completed. In some circumstances it is possible to combine some of the layers into a single layer serving multiple functions. The close proximity, of the phase switch layer and the device process region ensures that their temperatures are always very close. The high latent heat of the phase change holds the temperature of the phase switch layer constant once the phase transition temperature (T_P) is reached. Provided the radiation dose has reasonable limits so that some, but not all, of the phase transition material is converted to the second phase by the radiation pulse, then tight control of the maximum temperature seen by the process region may be expected.

0011The reflectivity switch layer of the '390 patent operates in a similar manner, except that the reflectivity layer transitions from a non-reflective state to a reflective state at a fixed reflectivity transition temperature. The reflective state strongly inhibits the further absorption of heat by the switch layer and consequently, the process region.

0012While the inventions of the '588 patent and the '390 patent are effective in controlling the maximum temperature seen by the process region during LTP, each requires the use of an absorbing layer and an active layer that undergoes a transition at some temperature. For the melt annealing process, there are material combinations that work very well. However, for non-melt annealing, there are few if any desirable materials for the phase transition layer and it is highly desirable to minimize the number of layers that have to be added and removed from the substrate for the annealing step.

0013Accordingly, it would be desirable to have simpler, more cost effective, methods of controlling the amount of heat delivered to a semiconductor wafer and to improve temperature uniformity during photo-annealing. In particular, it would be desirable to reduce the number of layers and restrict the layers to materials commonly employed in silicon semiconductor fabrication.

SUMMARY OF THE INVENTION

0014A first aspect of the invention is a method of annealing a silicon wafer having an upper surface and process regions formed therein. The method includes forming a silicon layer directly atop the wafer surface and covering the process regions. The method also includes irradiating the layer of silicon with one or more pulses of radiation. The radiation has a wavelength that is absorbed by the silicon layer. Also, each of the one or more radiation pulses has sufficient energy to raise the temperature of the wafer upper surface to a critical temperature corresponding to activating the process regions.

0015A second aspect of the invention is an apparatus for achieving a uniform temperature across the upper surface of a semiconductor wafer having process regions formed therein, during irradiation with annealing radiation. The apparatus includes a silicon layer formed directly upon the upper surface of the wafer and covering the process regions. The silicon layer absorbs a substantial amount of the annealing radiation and transmits heat from the absorbed radiation to the process regions in order to uniformly raise the temperature of the process regions to a critical temperature.

BRIEF DESCRIPTION OF THE DRAWINGS

0016<figref idref="DRAWINGS">FIG. 1</figref> is a cross-sectional schematic diagram of a semiconductor wafer having a region to be processed and a silicon layer formed directly atop the wafer surface to improve the temperature uniformity when heated by a pulse of radiation;

0017<figref idref="DRAWINGS">FIG. 2</figref> is a close-up of the semiconductor wafer of <figref idref="DRAWINGS">FIG. 1</figref> illustrating the absorption of radiation by the silicon layer and transfer of heat to the wafer and regions formed therein, in the process of activating dopants in the regions;

0018<figref idref="DRAWINGS">FIG. 3</figref> is a plot of the real and imaginary parts of the index of refraction of silicon as a function of wavelength taken from the Handbook of Optical Constants of Solids, Edited by Edward D. Palik, Academic Press, page 554; and

0019<figref idref="DRAWINGS">FIG. 4</figref> is a plot of the spectral emission of a xenon flash lamp filled to a pressure of 390 torr at low electrical loading (100-microfarad capacitor charged to 500 V) as a function of wavelength.

0020The various elements depicted in the drawings are merely representational and are not necessarily drawn to scale. Certain proportions thereof may be exaggerated, while others may be minimized. The drawings are intended to illustrate various implementations of the invention, which can be understood and appropriately carried out by those of ordinary skill in the art.

DETAILED DESCRIPTION OF THE INVENTION

0021The basic concept of the apparatus and method of the present invention is illustrated in <figref idref="DRAWINGS">FIGS. 1 and 2</figref> with regard to processing a semiconductor wafer as part of the process of manufacturing semiconductor devices such as transistors.

0022With reference to <figref idref="DRAWINGS">FIG. 1</figref>, there is shown a semiconductor (silicon) wafer (“wafer”) <b>10</b> having an upper surface <b>12</b>. Wafer <b>10</b> includes one or more process regions (“regions”) <b>20</b> formed therein. The size of regions <b>20</b> is exaggerated in <figref idref="DRAWINGS">FIG. 1</figref> for the sake of illustration. Regions <b>20</b> each have an upper surface <b>22</b> that, in an example embodiment, is defined by wafer surface <b>12</b>. Generally speaking, regions <b>20</b> are formed at or near wafer upper surface <b>12</b>.

0023In an example embodiment, regions <b>20</b> are formed by implantation, oxidation and polysilicon deposition. Typically, this results in films that include doped crystalline silicon junction regions, oxide trenches formed to isolate the junction regions and doped polysilicon layers to serve as electrical interconnects. It is worth noting that in a non-melt annealing process, amorphization of the junction regions is not mandatory as it is with the melt-process.

0024Dopants <b>14</b> (<figref idref="DRAWINGS">FIG. 2</figref>) implanted into the junctions in regions <b>20</b> may be activated by temperatures ranging from 800 to 1100° C., with annealing times ranging from hours to seconds. However very shallow, state-of-the-art junctions require annealing temperatures greater than 1100° C., e.g., in the range from about 1200° C. to about 1400° C. for times in the millisecond or shorter time frame. This short annealing time virtually stops the diffusion of dopants and assures the creation of very shallow junctions and very abrupt junction dopant profiles.

0025Regions <b>20</b> are to be annealed as part of the manufacturing process for forming a semiconductor device, as described below. For example, regions <b>20</b> may form the source and drain of a transistor, or may be suicide regions. In an example embodiment, regions <b>20</b> include silicon with implanted dopants <b>14</b> that are unactivated prior being annealed.

0026Formed directly atop wafer surface <b>12</b> and covering regions <b>20</b> is a silicon layer <b>40</b> having an upper surface <b>42</b>. In an example embodiment, silicon layer <b>40</b> has a thickness of between about 300 Angstroms and about 20,000 Angstroms. It is desirable that the thickness of silicon layer <b>40</b> be sufficient to form a uniform, optically opaque layer that renders the underlying process layer invisible. The thickness required to achieve opacity depends, in turn, on the exposing wavelength spectrum. Undoped or lightly doped silicon at room temperature is relatively clear to radiation longer than 600 nm, however is an efficient absorber for wavelengths below 600 nm. Thus, if we restrict the silicon coating thickness to one micron or less, the usable wavelengths are shorter than 600 nm.

0027<figref idref="DRAWINGS">FIG. 3</figref> is a plot of the real and imaginary parts of the index of refraction of silicon as a function of wavelength taken from the Handbook of Optical Constants of Solids, Edited by Edward D. Palik, Academic Press, page 554. <figref idref="DRAWINGS">FIG. 3</figref> shows the variation in the n and k values (i.e., the real and imaginary values of the complex index of refraction) of silicon over a very wide range of wavelengths. The absorption coefficient μ can be calculated from the relationship: <br />μ=4π<i>k/λ</i><br /> where λ is the wavelength.

0028The transmission T through a thickness δ is given by: <br />T=e^−μδ

0029In an example embodiment, silicon layer <b>40</b> is formed using PVD, LPCVD or PECVD techniques. Silicon layer <b>40</b> can be deposited in amorphous or polycrystalline form. In an example embodiment, silicon layer <b>40</b> is formed directly atop wafer upper surface <b>12</b>, however a thin oxide layer may be sandwiched between the process layer and the silicon layer to facilitate stripping the silicon absorber coating once its function is completed.

0030Where silicon layer <b>40</b> is amorphous silicon, a maximum temperature in the 1100° C.-1200° C. range will cause it to transform into a polysilicon coating. Thus, amorphous silicon coatings can be employed in a number of ways: they can be used at temperatures well below the amorphous to crystalline transformation temperature, or they can be used at annealing temperatures above the transition temperature where the amorphous layer will turn into polycrystalline silicon, and generate a temperature close to the silicon melting temperature of 1410° C.

0031Note that the melting temperature of silicon layer <b>40</b> is greater than the typical annealing temperatures used for regions <b>20</b>. In the case where the desired annealing temperature is high (e.g., 1100° C.-1350° C.), directly deposited polycrystalline silicon can be used for silicon layer <b>40</b> to ensure that the amorphous to crystalline transformation process does not interfere with achieving the desired annealing temperature.

0032<figref idref="DRAWINGS">FIG. 1</figref> further includes a radiation source <b>60</b> arranged to expose wafer <b>10</b> and silicon layer <b>40</b> with radiation <b>66</b> having a wavelength that is substantially (or completely) absorbed by silicon layer <b>40</b>. In a preferred embodiment, radiation source <b>60</b> is adapted to emit radiation <b>66</b> having wavelengths shorter than 600 nm. In another example embodiment, a filter <b>68</b> is used to filter out or otherwise substantially attenuate wavelengths longer than 600nm that are not substantially absorbed by silicon layer <b>40</b>.

0033In an example embodiment, radiation source <b>60</b> is a flash lamp, such as a Xenon flash lamp. Also in an example embodiment, radiation filter <b>68</b> is arranged in front of radiation source <b>60</b>, wherein the radiation filter is one that removes all or most of the portion of radiation <b>66</b> having a wavelength above 600 nm.

0034<figref idref="DRAWINGS">FIG. 4</figref> is a plot of the output of a Xenon flash lamp as a function of wavelength. As can be seen from <figref idref="DRAWINGS">FIG. 4</figref>, an advantage of using a flash lamp for radiation source <b>60</b> is that it has a relatively large spectral band with wavelengths shorter than 600 nm so that it generates a large amount of useful energy per pulse. As mentioned above, filter <b>68</b> can be used to filter out wavelengths longer than 600 nm. In an example embodiment of the present invention, the flash lamp delivers an amount of energy in the range between about 5 J/cm²and about 100 J/cm². A large flash lamp or flash lamp array is capable of irradiating a large area such as an entire semiconductor wafer, which nowadays has a diameter of 300 mm. In one of the preferred embodiments of the present invention, the entire wafer <b>10</b> is annealed in a single pulse of radiation from a flash lamp or flash lamp array. A radiation filter <b>68</b> can be adapted to filter out or attenuate unwanted wavelengths from the flash lamp.

0035In another preferred embodiment, radiation source <b>60</b> is a pulsed laser having a wavelength that is readily absorbed by silicon layer <b>40</b> and which is used to process only a portion of the substrate at any one time. In particular, radiation source <b>60</b> can be an excimer laser or a frequency-multiplied YAG laser.

0036The method of the present invention includes irradiating silicon layer <b>40</b> with one or more pulses of radiation <b>66</b> to photo-anneal wafer <b>10</b>, or specifically the one or more regions <b>20</b> formed therein. Without silicon layer <b>40</b>, wafer <b>10</b> will not be uniformly heated at or near upper surface <b>12</b> because of the different reflectivities of region surfaces <b>22</b>, which include structures on the wafer such as interconnections, gates, etc., (not shown). Such structures are typically present on the wafer during processing and contribute to the reflectivity disparities over the wafer upper surface. The heating non-uniformity translates into annealing non-uniformity, which can result in non-functioning or sub-standard-functioning devices.

0037With reference also to <figref idref="DRAWINGS">FIG. 2</figref>, silicon layer <b>40</b> serves to absorb radiation <b>66</b> and convert it to heat <b>82</b>. Heat <b>82</b> is then communicated by thermal diffusion to wafer <b>10</b> at upper surface <b>12</b> across the wafer. This heat serves to uniformly increase the temperature of wafer upper surface <b>12</b> and regions <b>20</b> across the wafer to a critical temperature, e.g., to a temperature where inactivated dopants <b>14</b> are transformed to activated dopants <b>14</b>*. In an example embodiment, the critical temperature is between about 1100° C. and about 1410° C., and in another example embodiment is between 1200° C. and 1400° C.

0038Silicon layer <b>40</b> is uniformly heated by radiation <b>66</b> because, unlike wafer surface <b>12</b>, silicon layer <b>40</b> has uniform reflectivity and absorbance.

0039Silicon layer <b>40</b> is able to serve as an absorbing layer for wafer <b>10</b> because it has the same coefficient of expansion as the wafer. Accordingly, neither the silicon layer <b>40</b> nor the wafer <b>10</b> will crack because there will be no differential stress between the two when heated up to the high annealing temperatures, e.g., 1350° C. or even up to near the melting point of silicon (1410° C.).

0040A goal of the present invention is to uniformly heat upper surface <b>12</b> of substrate <b>10</b> with either one radiation pulse <b>66</b> or multiple radiation pulses <b>66</b> to a critical temperature while remaining below a predetermined temperature. For a non-melt process (i.e., wherein the region <b>20</b> is not melted to achieve activation), the predetermined temperature is preferably the melt temperature of the region. However, in this case the predetermined temperature can be any temperature greater than the activation temperature of the region. For a melt process (i.e., wherein region <b>20</b> is melted to achieve activation), the predetermined temperature can be anywhere between the region melt temperature and the substrate and silicon layer melt temperatures (which typically will be essentially the same).

0041Once the irradiation process is complete, silicon layer <b>40</b> is removed using conventional etching techniques. In an example embodiment, a thin silicon dioxide coating is formed between the wafer and the silicon coating to serve as an etch stop.

0042In the foregoing Detailed Description, various features are grouped together in various example embodiments for ease of understanding. The many features and advantages of the present invention are apparent from the detailed specification, and, thus, it is intended by the appended claims to cover all such features and advantages of the described apparatus that follow the true spirit and scope of the invention. Furthermore, since numerous modifications and changes will readily occur to those of skill in the art, it is not desired to limit the invention to the exact construction and operation described herein. Accordingly, other embodiments are within the scope of the appended claims.