Managing a secure platform using a hierarchical executive architecture in isolated execution mode

CROSS-REFERENCES TO RELATED APPLICATIONS

0001This is a continuation-in-part of U.S. patent application Ser. No. 09/539,344 filed Mar. 31, 2000.

BACKGROUND

00021. Field of the Invention

0003This invention relates to microprocessors. In particular, the invention relates to processor security.

00042. Description of Related Art

0005Advances in microprocessor and communication technologies have opened up many opportunities for applications that go beyond the traditional ways of doing business. Electronic commerce (E-commerce) and business-to-business (B2B) transactions are now becoming popular, reaching the global markets at a fast rate. Unfortunately, while modern microprocessor systems provide users convenient and efficient methods of doing business, communicating and transacting, they are also vulnerable for unscrupulous attacks. Examples of these attacks include theft of data, virus, intrusion, security breach, and tampering, to name a few. Computer security, therefore, is becoming more and more important to protect the integrity of the computer systems and increase the trust of users.

0006Threats caused by unscrupulous attacks may be in a number of forms. An invasive remote-launched attack by hackers may disrupt the normal operation of a system connected to thousands or even millions of users. A virus program may corrupt code and/or data of a single-user platform.

0007Existing techniques to protect against attacks have a number of drawbacks. Anti-virus programs can only scan and detect known viruses. Security co-processors or smart cards using cryptographic or other security techniques have limitations in speed performance, memory capacity, and flexibility. Redesigning operating systems creates software compatibility issues and causes tremendous investment in development efforts.

BRIEF DESCRIPTION OF THE DRAWINGS

0008The features and advantages of the present invention will become apparent from the following detailed description of the present invention in which:

0009<figref idref="DRAWINGS">FIG. 1A</figref> is a diagram illustrating a logical architecture according to one embodiment of the invention.

0010<figref idref="DRAWINGS">FIG. 1B</figref> is a diagram illustrating accessibility of various elements in the operating system and the processor according to one embodiment of the invention.

0011<figref idref="DRAWINGS">FIG. 1C</figref> is a diagram illustrating a computer system in which one embodiment of the invention can be practiced.

0012<figref idref="DRAWINGS">FIG. 2</figref> is a diagram illustrating an executive subsystem according to one embodiment of the invention.

0013<figref idref="DRAWINGS">FIG. 3</figref> is a diagram illustrating a processor executive handler shown in <figref idref="DRAWINGS">FIG. 2</figref> according to one embodiment of the invention.

0014<figref idref="DRAWINGS">FIG. 4</figref> is a diagram illustrating a processor executive shown in <figref idref="DRAWINGS">FIG. 2</figref> according to one embodiment of the invention.

0015<figref idref="DRAWINGS">FIG. 5</figref> is a diagram illustrating an operating system executive shown in <figref idref="DRAWINGS">FIG. 2</figref> according to one embodiment of the invention.

0016<figref idref="DRAWINGS">FIG. 6</figref> is a diagram illustrating a boot-up code shown in <figref idref="DRAWINGS">FIG. 2</figref> according to one embodiment of the invention.

0017<figref idref="DRAWINGS">FIG. 7</figref> is a flowchart illustrating a process to manage a secure platform according to one embodiment of the invention.

0018<figref idref="DRAWINGS">FIG. 8</figref> is a flowchart illustrating a process to boot up platform according to one embodiment of the invention.

0019<figref idref="DRAWINGS">FIG. 9</figref> is a flowchart illustrating a process to execute an isolated create instruction according to one embodiment of the invention.

0020<figref idref="DRAWINGS">FIG. 10</figref> is a flowchart illustrating a process to handle a processor executive according to one embodiment of the invention.

0021<figref idref="DRAWINGS">FIG. 11</figref> is a flowchart illustrating a process to handle an operating system executive according to one embodiment of the invention.

DESCRIPTION

0022The present invention is a method and apparatus to manage a secure platform. A processor executive (PE) handles an operating system executive (OSE) in a secure environment. The secure environment has a platform key (PK) and is associated with an isolated memory area in the platform. The OSE manages a subset of an operating system (OS) running on the platform. The platform has a processor operating in one of a normal execution mode and an isolated execution mode. The isolated memory area is accessible to the processor in the isolated execution mode. A PE supplement supplements the PE with a PE manifest representing the PE and a PE identifier to identify the PE. A PE handler handles the PE using the PK and the PE supplement.

0023A boot-up code boots up the platform following a power on. The secure environment includes an OSE supplement to supplement the OSE with an OSE manifest representing the OSE and an OSE identifier to identify the OSE. The PE handler includes a PE loader, a PE manifest verifier, a PE verifier, a PE key generator, a PE identifier logger, and a PE entrance/exit handler. The PE loader loads the PE and the PE supplement from a PE memory into the isolated memory area using a parameter block provided by the boot-up code. The PE manifest verifier verifies the PE manifest. The PE verifier verifies the PE using the PE manifest and a constant derived from the PK. The PE key generator generates a PE key using the PK. The PE key generator includes a PE key combiner to combine the PE identifier and the PK. The combined PE identifier and the PK correspond to the PE key. The PE identifier logger logs the PE identifier in a storage. The PE entrance/exit handler handles a PE entry and a PE exit.

0024The OSE handler includes an OSE loader, an OSE manifest verifier, an OSE verifier, an OSE key generator, an OSE identifier logger, and an OSE entrance/exit handler. The OSE loader loads the OSE and the OSE supplement into the isolated memory area. The OSE manifest verifier verifies the OSE manifest. The OSE verifier verifies the OSE. The OSE key generator generates an OSE key. The OSE identifier logger logs the OSE identifier in a storage. The OSE entrance/exit handler handles an OSE entry and an OSE exit. The OSE key generator includes a binding key generator and an OSE key combiner. The binding key generator generates a binding key (BK) using the PE key. The OSE key combiner combines the OSE identifier and the BK. The combined OSE identifier and the BK correspond to the OSE key.

0025The OSE includes a module loader and evictor, a key binder and unbinder, a page manager, an interface handler, a scheduler and balancer, and an interrupt handler. The module loader and evictor loads and evicts a module into and out of the isolated memory area, respectively. The module is one of an application module, an applet module, and a support module. The page manager manages paging in the isolated memory area. The interface handler handles interface with the OS. The key binder and unbinder includes an applet key generator to generate an applet key associating with the applet module. The applet key generator includes an applet key combiner to combine the OSE key with an applet identifier identifying the applet module. The combined OSE key and the applet identifier correspond to the applet key.

0026The boot up code includes a PE locator, a PE recorder, and an instruction invoker. The PE locator locates the PE and the PE supplement. The PE locator transfers the PE and the PE supplement into the PE memory at a PE address. The PE recorder records the PE address in the parameter block. The instruction invoker executes an isolated create instruction which loads the PE handler into the isolated memory area. The isolated create instruction performs an atomic non-interruptible sequence. The atomic sequence includes a number of operations: a physical memory operation, an atomic read-and-increment operation, an isolated memory area control operation, a processor isolated execution operation, an PE handler loading operation, a PE handler verification, and an exit operation. The physical memory operation verifies if the processor is in a flat physical page mode. The atomic read-and-increment operation reads and increments a thread count register in a chipset. The read-and-increment operation determines if the processor is the first processor in the isolated execution mode. The isolated memory area control operation configures the chipset using a configuration storage. The processor isolated execution operation configures the processor in the isolated execution mode. The processor isolated execution operation includes a chipset read operation and a processor configuration operation. The chipset read operation reads the configuration storage in the chipset when the processor is not a first processor in the isolated execution mode. The processor configuration operation configures the processor according to the configuration storage when the processor is not a first processor in the isolated execution mode. The PE handler loading operation loads the PE handler into the isolated memory area. The PE handler verification verifies the loaded PE handler. The exit operation transfers control to the loaded PE handler.

0027The chipset includes at least one of a memory controller hub (MCH) and an input/output controller hub (ICH). The storage is in an input/output controller hub (ICH) external to the processor.

0028In the following description, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to one skilled in the art that these specific details are not required in order to practice the present invention. In other instances, well-known electrical structures and circuits are shown in block diagram form in order not to obscure the present invention.

0000Architecture Overview

0029One principle for providing security in a computer system or platform is the concept of an isolated execution architecture. The isolated execution architecture includes logical and physical definitions of hardware and software components that interact directly or indirectly with an operating system of the computer system or platform. An operating system and the processor may have several levels of hierarchy, referred to as rings, corresponding to various operational modes. A ring is a logical division of hardware and software components that are designed to perform dedicated tasks within the operating system. The division is typically based on the degree or level of privilege, namely, the ability to make changes to the platform. For example, a ring-<b>0</b> is the innermost ring, being at the highest level of the hierarchy. Ring-<b>0</b> encompasses the most critical, privileged components. In addition, modules in Ring-<b>0</b> can also access to lesser privileged data, but not vice versa. Ring-<b>3</b> is the outermost ring, being at the lowest level of the hierarchy. Ring-<b>3</b> typically encompasses users or applications level and executes the least trusted code. It is noted that the level of the ring hierarchy is independent to the level of the security protection of that ring.

0030<figref idref="DRAWINGS">FIG. 1A</figref> is a diagram illustrating a logical operating architecture <b>50</b> according to one embodiment of the invention. The logical operating architecture <b>50</b> is an abstraction of the components of an operating system and the processor. The logical operating architecture <b>50</b> includes ring-<b>0</b><b>10</b>, ring-<b>1</b><b>20</b>, ring-<b>2</b><b>30</b>, ring-<b>3</b><b>40</b>, and a processor nub loader <b>52</b>. The processor nub loader <b>52</b> is an instance of a processor executive (PE) handler. The PE handler is used to handle and/or manage a processor executive (PE) as will be discussed later. The logical operating architecture <b>50</b> has two modes of operation: normal execution mode and isolated execution mode. Each ring in the logical operating architecture <b>50</b> can operate in both modes. The processor nub loader <b>52</b> operates only in the isolated execution mode.

0031Ring-<b>0</b><b>10</b> includes two portions: a normal execution Ring-<b>0</b><b>11</b> and an isolated execution Ring-<b>0</b><b>15</b>. The normal execution Ring-<b>0</b><b>11</b> includes software modules that are critical for the operating system, usually referred to as kernel. These software modules include primary operating system (e.g., kernel) <b>12</b>, software drivers <b>13</b>, and hardware drivers <b>14</b>. The isolated execution Ring-<b>0</b><b>15</b> includes an operating system (OS) nub <b>16</b> and a processor nub <b>18</b>. The OS nub <b>16</b> and the processor nub <b>18</b> are instances of an OS executive (OSE) and processor executive (PE), respectively. The OSE and the PE are part of executive entities that operate in a secure environment associated with the isolated area <b>70</b> and the isolated execution mode. The processor nub loader <b>52</b> is a protected bootstrap loader code held within a chipset in the system and is responsible for loading the processor nub <b>18</b> from the processor or chipset into an isolated area as will be explained later.

0032Similarly, ring-<b>1</b><b>20</b>, ring-<b>2</b><b>30</b>, and ring-<b>3</b><b>40</b> include normal execution ring-<b>1</b><b>21</b>, ring-<b>2</b><b>31</b>, ring-<b>3</b><b>41</b>, and isolated execution ring-<b>1</b><b>25</b>, ring-<b>2</b><b>35</b>, and ring-<b>3</b><b>45</b>, respectively. In particular, normal execution ring-<b>3</b> includes N applications <b>42</b>₁to <b>42</b>_Nand isolated execution ring-<b>3</b> includes K applets <b>46</b>₁to <b>46</b>_K.

0033One concept of the isolated execution architecture is the creation of an isolated region in the system memory, referred to as an isolated area, which is protected by both the processor and chipset in the computer system. Portions of the isolated region may also be in cache memory. Access to this isolated region is permitted only from a front side bus (FSB) of the processor, using special bus (e.g., memory read and write) cycles, referred to as isolated read and write cycles. The special bus cycles are also used for snooping. The isolated read and write cycles are issued by the processor executing in an isolated execution mode when accessing the isolated area. The isolated execution mode is initialized using a privileged instruction in the processor, combined with the processor nub loader <b>52</b>. The processor nub loader <b>52</b> verifies and loads a ring-<b>0</b> nub software module (e.g., processor nub <b>18</b>) into the isolated area. The processor nub <b>18</b> provides hardware-related services for the isolated execution.

0034One task of the processor nub loader <b>52</b> and processor nub <b>18</b> is to verify and load the ring-<b>0</b> OS nub <b>16</b> into the isolated area, and to generate the root of a key hierarchy unique to a combination of the platform, the processor nub <b>18</b>, and the operating system nub <b>16</b>. The operating system nub <b>16</b> provides links to services in the primary OS <b>12</b> (e.g., the unprotected operating system), provides page management within the isolated area, and has the responsibility for loading ring-<b>3</b> application modules <b>45</b>, including applets <b>46</b>₁to <b>46</b>_K, into protected pages allocated in the isolated area. The operating system nub <b>16</b> may also load ring-<b>0</b> supporting modules.

0035The operating system nub <b>16</b> may choose to support paging of data between the isolated area and ordinary (e.g., non-isolated) memory. If so, then the operating system nub <b>16</b> is also responsible for encrypting and hashing the isolated area pages before evicting the page to the ordinary memory, and for checking the page contents upon restoration of the page. The isolated mode applets <b>46</b>₁to <b>46</b>_Kand their data are tamper-resistant and monitor-resistant from all software attacks from other applets, as well as from non-isolated-space applications (e.g., <b>42</b>₁to <b>42</b>_N), drivers and even the primary operating system <b>12</b>. The only software that can interfere with or monitor the applet's execution is the processor nub loader <b>52</b>, processor nub <b>18</b> or the operating system nub <b>16</b>.

0036<figref idref="DRAWINGS">FIG. 1B</figref> is a diagram illustrating accessibility of various elements in the operating system <b>10</b> and the processor according to one embodiment of the invention. For illustration purposes, only elements of ring-<b>0</b><b>10</b> and ring-<b>3</b><b>40</b> are shown. The various elements in the logical operating architecture <b>50</b> access an accessible physical memory <b>60</b> according to their ring hierarchy and the execution mode.

0037The accessible physical memory <b>60</b> includes an isolated area <b>70</b> and a non-isolated area <b>80</b>. The isolated area <b>70</b> includes applet pages <b>72</b> and nub pages <b>74</b>. The non-isolated area <b>80</b> includes application pages <b>82</b> and operating system pages <b>84</b>. The isolated area <b>70</b> is accessible only to elements of the operating system and processor operating in isolated execution mode. The non-isolated area <b>80</b> is accessible to all elements of the ring-<b>0</b> operating system and to the processor.

0038The normal execution ring-<b>0</b><b>11</b> including the primary OS <b>12</b>, the software drivers <b>13</b>, and the hardware drivers <b>14</b>, can access both the OS pages <b>84</b> and the application pages <b>82</b>. The normal execution ring-<b>3</b>, including applications <b>42</b>₁to <b>42</b>_N, can access only to the application pages <b>82</b>. Generally applications can only access to their own pages, however, the OS typically provides services for sharing memory in controlled methods. Both the normal execution ring-<b>0</b><b>11</b> and ring-<b>3</b><b>41</b>, however, cannot access the isolated area <b>70</b>.

0039The isolated execution ring-<b>0</b><b>15</b>, including the OS nub <b>16</b> and the processor nub <b>18</b>, can access to both of the isolated area <b>70</b>, including the applet pages <b>72</b> and the nub pages <b>74</b>, and the non-isolated area <b>80</b>, including the application pages <b>82</b> and the OS pages <b>84</b>. The isolated execution ring-<b>3</b><b>45</b>, including applets <b>46</b>₁to <b>46</b>_K, can access only applet pages <b>72</b>. The applets <b>46</b>₁to <b>46</b>_Kreside in the isolated area <b>70</b>. In general, applets can only access their own pages; however, the OS nub <b>16</b> can also provides services for the applet to share memory (e.g., share memory with other applets or with non-isolated area applications).

0040<figref idref="DRAWINGS">FIG. 1C</figref> is a diagram illustrating a computer system <b>100</b> in which one embodiment of the invention can be practiced. The computer system <b>100</b> includes a processor <b>110</b>, a host bus <b>120</b>, a memory controller hub (MCH) <b>130</b>, a system memory <b>140</b>, an input/output controller hub (ICH) <b>150</b>, a non-volatile memory, or system flash, <b>160</b>, a mass storage device <b>170</b>, input/output devices <b>175</b>, a token bus <b>180</b>, a motherboard (MB) token <b>182</b>, a reader <b>184</b>, and a token <b>186</b>. The MCH <b>130</b> may be integrated into a chipset that integrates multiple functionalities such as the isolated execution mode, host-to-peripheral bus interface, memory control. Similarly, the ICH <b>150</b> may also be integrated into a chipset together or separate from the MCH <b>130</b> to perform I/O functions. For clarity, not all the peripheral buses are shown. It is contemplated that the system <b>100</b> may also include peripheral buses such as Peripheral Component Interconnect (PCI), accelerated graphics port (AGP), Industry Standard Architecture (ISA) bus, and Universal Serial Bus (USB), etc. The “token bus” may be part of the USB bus, e.g., it may be hosted on the USB bus.

0041The processor <b>110</b> represents a central processing unit of any type of architecture, such as complex instruction set computers (CISC), reduced instruction set computers (RISC), very long instruction word (VLIW), or hybrid architecture. In one embodiment, the processor <b>110</b> is compatible with an Intel Architecture (IA) processor, such as the Pentium™ series, the IA-<b>32</b>™ and the IA-<b>64</b>™. The processor <b>110</b> includes a normal execution mode <b>112</b> and an isolated execution circuit <b>115</b>. The normal execution mode <b>112</b> is the mode in which the processor <b>110</b> operates in a non-secure environment, or a normal environment without the security features provided by the isolated execution mode. The isolated execution circuit <b>115</b> provides a mechanism to allow the processor <b>110</b> to operate in an isolated execution mode. The isolated execution circuit <b>115</b> provides hardware and software support for the isolated execution mode. This support includes configuration for isolated execution, definition of an isolated area, definition (e.g., decoding and execution) of isolated instructions, generation of isolated access bus cycles, and access checking.

0042In one embodiment, the computer system <b>100</b> can be a single processor system, such as a desktop computer, which has only one main central processing unit, e.g. processor <b>110</b>. In other embodiments, the computer system <b>100</b> can include multiple processors, e.g. processors <b>110</b>, <b>110</b><i>a</i>, <b>110</b><i>b</i>, etc., as shown in <figref idref="DRAWINGS">FIG. 1C</figref>. Thus, the computer system <b>100</b> can be a multi-processor computer system having any number of processors. For example, the multi-processor computer system <b>100</b> can operate as part of a server or workstation environment. The basic description and operation of processor <b>110</b> will be discussed in detail below. It will be appreciated by those skilled in the art that the basic description and operation of processor <b>110</b> applies to the other processors <b>110</b><i>a </i>and <b>110</b><i>b</i>, shown in <figref idref="DRAWINGS">FIG. 1C</figref>, as well as any number of other processors that may be utilized in the multi-processor computer system <b>100</b> according to one embodiment of the present invention.

0043The processor <b>110</b> may also have multiple logical processors. A logical processor, sometimes referred to as a thread, is a functional unit within a physical processor having an architectural state and physical resources allocated according to some partitioning policy. Within the context of the present invention, the terms “thread” and “logical processor” are used to mean the same thing. A multi-threaded processor is a processor having multiple threads or multiple logical processors. A multi-processor system (e.g., the system comprising the processors <b>110</b>, <b>110</b><i>a</i>, and <b>110</b><i>b</i>) may have multiple multi-threaded processors.

0044The host bus <b>120</b> provides interface signals to allow the processor <b>110</b> or processors <b>110</b>, <b>100</b><i>a</i>, and <b>110</b><i>b </i>to communicate with other processors or devices, e.g., the MCH <b>130</b>. In addition to normal mode, the host bus <b>120</b> provides an isolated access bus mode with corresponding interface signals for memory read and write cycles. The isolated access bus mode is asserted on memory accesses initiated while the processor <b>110</b> is in the isolated execution mode and it is accessing memory within the isolated area. The isolated access bus mode is also asserted on instruction pre-fetch and cache write-back cycles if the address is within the isolated area address range. The isolated access bus mode is configured within the processor <b>110</b>. The processor <b>110</b> responds to a snoop cycle to a cached address when the isolated access bus mode on the FSB matches the mode of the cached address.

0045The MCH <b>130</b> provides control and configuration of system memory <b>140</b>. The MCH <b>130</b> provides interface circuits to recognize and service isolated access assertions on memory reference bus cycles, including isolated memory read and write cycles. In addition, the MCH <b>130</b> has memory range registers (e.g., base and length registers) to represent the isolated area in the system memory <b>140</b>. Once configured, the MCH <b>130</b> aborts any access to the isolated area that does not have the isolated access bus mode asserted.

0046The system memory <b>140</b> stores system code and data. The system memory <b>140</b> is typically implemented with dynamic random access memory (DRAM) or static random access memory (SRAM). The system memory <b>140</b> includes the accessible physical memory <b>60</b> (shown in <figref idref="DRAWINGS">FIG. 1B</figref>). The accessible physical memory includes a loaded operating system <b>142</b>, the isolated area <b>70</b> (shown in <figref idref="DRAWINGS">FIG. 1B</figref>), and an isolated control and status space <b>148</b>. The loaded operating system <b>142</b> is the portion of the operating system that is loaded into the system memory <b>140</b>. The loaded OS <b>142</b> is typically loaded from a mass storage device via some boot code in a boot storage such as a boot read only memory (ROM). The isolated area <b>70</b>, as shown in <figref idref="DRAWINGS">FIG. 1B</figref>, is the memory area that is defined by the processor <b>110</b> when operating in the isolated execution mode. Access to the isolated area <b>70</b> is restricted and is enforced by the processor <b>110</b> and/or the MCH <b>130</b> or other chipset that integrates the isolated area functionalities. The isolated control and status space <b>148</b> is an input/output (I/O)-like, independent address space defined by the processor <b>110</b>. The isolated control and status space <b>148</b> contains mainly the isolated execution control and status registers. The isolated control and status space <b>148</b> does not overlap any existing address space and is accessed using the isolated bus cycles. The system memory <b>140</b> may also include other programs or data that are not shown.

0047The ICH <b>150</b> represents a known single point in the system having the isolated execution functionality. For clarity, only one ICH <b>150</b> is shown. The system <b>100</b> may have many ICH's similar to the ICH <b>150</b>. When there are multiple ICH's, a designated ICH is selected to control the isolated area configuration and status. In one embodiment, this selection is performed by an external strapping pin. As is known by one skilled in the art, other methods of selecting can be used, including using programmable configuring registers. The ICH <b>150</b> has a number of functionalities that are designed to support the isolated execution mode in addition to the traditional I/O functions. In particular, the ICH <b>150</b> includes an isolated bus cycle interface <b>152</b>, the processor nub loader <b>52</b> (shown in <figref idref="DRAWINGS">FIG. 1A</figref>), a digest memory <b>154</b>, a cryptographic key storage <b>155</b>, an isolated execution logical processor manager <b>156</b>, and a token bus interface <b>159</b>.

0048The isolated bus cycle interface <b>152</b> includes circuitry to interface to the isolated bus cycle signals to recognize and service isolated bus cycles, such as the isolated read and write bus cycles. The processor nub loader <b>52</b>, as shown in <figref idref="DRAWINGS">FIG. 1A</figref>, includes a processor nub loader code and its digest (e.g., cryptographic hash) value. The processor nub loader <b>52</b> is invoked by execution of an appropriate isolated instruction (e.g., Iso_Init) and is transferred to the isolated area <b>70</b>. From the isolated area <b>80</b>, the processor nub loader <b>52</b> copies the processor nub <b>18</b> from the system flash memory (e.g., the processor nub code <b>18</b> in non-volatile memory <b>160</b>) into the isolated area <b>70</b>, verifies and logs its integrity, and manages a symmetric key used to protect the processor nub's secrets. In one embodiment, the processor nub loader <b>52</b> is implemented in read only memory (ROM). For security purposes, the processor nub loader <b>52</b> is unchanging, tamper-resistant and non-substitutable. The digest memory <b>154</b>, typically implemented in RAM, stores the digest (e.g., cryptographic hash) values of the loaded processor nub <b>18</b>, the operating system nub <b>16</b>, and any other supervisory modules (e.g., ring-<b>0</b> modules) loaded into the isolated execution space. The cryptographic key storage <b>155</b> holds a symmetric encryption/decryption key that is unique for the platform of the system <b>100</b>. In one embodiment, the cryptographic key storage <b>155</b> includes internal fuses that are programmed at manufacturing. Alternatively, the cryptographic key storage <b>155</b> may also be created during manufacturing with a cryptographic random number generator. The isolated execution logical processor manager <b>156</b> manages the operation of logical processors configuring their isolated execution mode support. In one embodiment, the isolated execution logical processor manager <b>156</b> includes a logical processor count register that tracks the number of logical processors participating in the isolated execution mode. The token bus interface <b>159</b> interfaces to the token bus <b>180</b>. A combination of the processor nub loader digest, the processor nub digest, the operating system nub digest, and optionally additional digests, represents the overall isolated execution digest, referred to as isolated digest. The isolated digest is a fingerprint identifying the all supervisory code involved in controlling the isolated execution configuration and operation. The isolated digest is used to attest or prove the state of the current isolated execution environment.

0049The non-volatile memory <b>160</b> stores non-volatile information. Typically, the non-volatile memory <b>160</b> is implemented in flash memory. In one embodiment, the non-volatile memory <b>160</b> includes the processor nub <b>18</b>. The processor nub <b>18</b> provides set-up and low-level management of the isolated area <b>70</b> (in the system memory <b>140</b>), including verification, loading, and logging of the operating system nub <b>16</b>, and the management of the symmetric key used to protect the operating system nub's secrets. The processor nub loader <b>52</b> performs some part of the setup and manages/updates the symmetric key before the processor nub <b>18</b> and the OS nub <b>16</b> are loaded. The processor nub <b>18</b> The processor nub <b>18</b> may also provide interface abstractions to low-level security services provided by other hardware. The processor nub <b>18</b> may also be distributed by the original equipment manufacturer (OEM) or operating system vendor (OSV).

0050The mass storage device <b>170</b> stores archive information such as code (e.g., processor nub <b>18</b>), programs, files, data, applications (e.g., applications <b>42</b>₁to <b>42</b>_N), applets (e.g., applets <b>46</b>₁to <b>46</b>_K) and operating systems. The mass storage device <b>170</b> may include compact disk (CD) ROM <b>172</b>, floppy diskettes <b>174</b>, and hard drive <b>176</b>, and any other storage devices. The mass storage device <b>170</b> provides a mechanism to read machine-readable media. When implemented in software, the elements of the present invention are the code segments to perform the necessary tasks. The program or code segments can be stored in a processor readable medium or transmitted by a computer data signal embodied in a carrier wave, or a signal modulated by a carrier, over a transmission medium. The “processor readable medium” may include any medium that can store or transfer information. Examples of the processor readable medium include an electronic circuit, a semiconductor memory device, a ROM, a flash memory, an erasable programmable ROM (EPROM), a floppy diskette, a compact disk CD-ROM, an optical disk, a hard disk, a fiber optical medium, a radio frequency (RF) link, etc. The computer data signal may include any signal that can propagate over a transmission medium such as electronic network channels, optical fibers, air, electromagnetic, RF links, etc. The code segments may be downloaded via computer networks such as the Internet, an Intranet, etc.

0051I/O devices <b>175</b> may include any I/O devices to perform I/O functions. Examples of I/O devices <b>175</b> include a controller for input devices (e.g., keyboard, mouse, trackball, pointing device), media card (e.g., audio, video, graphics), a network card, and any other peripheral controllers.

0052The token bus <b>180</b> provides an interface between the ICH <b>150</b> and various tokens in the system. A token is a device that performs dedicated input/output functions with security functionalities. A token has characteristics similar to a smart card, including at least one reserved-purpose public/private key pair and the ability to sign data with the private key. Examples of tokens connected to the token bus <b>180</b> include a motherboard token <b>182</b>, a token reader <b>184</b>, and other portable tokens <b>186</b> (e.g., smart card). The token bus interface <b>159</b> in the ICH <b>150</b> connects through the token bus <b>180</b> to the ICH <b>150</b> and ensures that when commanded to prove the state of the isolated execution, the corresponding token (e.g., the motherboard token <b>182</b>, the token <b>186</b>) signs only valid isolated digest information. For purposes of security, the token should be connected to the digest memory via the token bus <b>180</b>.

0000A Hierarchical Executive Architecture to Manage a Secure Platform

0053The overall architecture discussed above provides a basic insight into a hierarchical executive architecture to manage a secure platform. The elements shown in <figref idref="DRAWINGS">FIGS. 1A, 1B</figref>, and <b>1</b>C are instances of an abstract model of this hierarchical executive architecture. The implementation of this hierarchical executive architecture is a combination of hardware and software. In what follows, the processor executive, the processor executive handler, and the operating system executive are abstract models of the processor nub <b>18</b>, the processor nub loader <b>52</b>, and the operating system nub <b>16</b> (<figref idref="DRAWINGS">FIGS. 1A, 1B</figref>, and <b>1</b>C), respectively.

0054<figref idref="DRAWINGS">FIG. 2</figref> is a diagram illustrating an executive subsystem <b>200</b> according to one embodiment of the invention. The executive subsystem <b>200</b> includes a processor executive (PE) <b>210</b>, a PE supplement <b>220</b>, a PE handler <b>230</b>, a boot-up code <b>240</b>, and a secure environment <b>250</b>.

0055The processor executive (PE) <b>210</b> handles an operating system executive (OSE) <b>270</b> in the secure environment <b>250</b>. The PE supplement <b>220</b> supplements the PE with a PE manifest <b>222</b> representing the PE and a PE identifier <b>224</b> to identify the PE. The PE handler <b>230</b> handles the PE <b>210</b> using a platform key (PK) <b>260</b> in the secure environment <b>250</b> and the PE supplement <b>220</b>. The PE <b>210</b> and the PE supplement <b>220</b> are located in a PE memory <b>215</b>. The PE memory <b>215</b> is located in the non-isolated memory area <b>80</b>.

0056The PE handler <b>230</b> handles the PE <b>210</b> using the PK <b>260</b> and the PE supplement <b>220</b>. The PE handler <b>230</b> obtains information to locate the PE memory <b>215</b> via a parameter block <b>242</b> provided by the boot-up code <b>240</b>.

0057The boot-up code <b>240</b> boots up the platform following a power on. The boot-up code <b>240</b> obtains an original PE <b>246</b> and an original PE supplement <b>248</b> from a system ROM (e.g., system flash <b>160</b> as shown in <figref idref="DRAWINGS">FIG. 1C</figref>)

0058The secure environment <b>250</b> includes a platform key (PK) <b>260</b>, an operating system executive (OSE) <b>270</b>, and an OSE supplement <b>280</b>. The OSE supplement <b>280</b> supplements the OSE <b>270</b> with an OSE manifest <b>282</b> representing the OSE and an OSE identifier <b>284</b> to identify the OSE. The secure environment <b>250</b> is associated with an isolated memory area <b>70</b> (<figref idref="DRAWINGS">FIG. 1C</figref>) in the platform. The OSE <b>270</b> manages a subset <b>295</b> of an operating system (OS) <b>290</b> running on the platform. The platform has a processor <b>110</b> operating in one of a normal execution mode <b>112</b> and an isolated execution mode <b>115</b> as shown in <figref idref="DRAWINGS">FIG. 1C</figref>. The isolated memory area <b>70</b> is accessible to the processor <b>110</b> in the isolated execution mode <b>115</b>.

0059<figref idref="DRAWINGS">FIG. 3</figref> is a diagram illustrating the PE handler <b>230</b> shown in <figref idref="DRAWINGS">FIG. 2</figref> according to one embodiment of the invention. The PE handler <b>230</b> includes a PE loader <b>310</b>, a PE manifest verifier <b>320</b>, a PE verifier <b>330</b>, a PE Error Generator <b>340</b>, a Constant Driver <b>350</b>, a PE key generator <b>360</b>, a PE identifier logger <b>370</b>, and a PE entrance/exit handler <b>380</b>.

0060The PE loader <b>310</b> loads the PE <b>210</b> and the PE supplement <b>220</b> from the PE memory <b>215</b> (<figref idref="DRAWINGS">FIG. 2</figref>) into the isolated memory area <b>70</b> using a PE address in the parameter block <b>242</b> (<figref idref="DRAWINGS">FIG. 2</figref>) provided by the boot-up code <b>240</b>. The PE loader <b>310</b> provides a loaded PE manifest <b>322</b> and a loaded PE <b>312</b> located in the isolated memory area <b>70</b> and corresponding to the PE manifest <b>322</b> and the PE <b>312</b>, respectively.

0061The PE manifest verifier <b>320</b> verifies the PE manifest <b>222</b> by comparing the PE manifest <b>222</b> with the loaded PE manifest <b>322</b> and generates a result to a PE error generator <b>340</b>. If the verification fails, the error generator <b>340</b> generates a failure or fault condition with an error code associated with the PE manifest verification.

0062The PE verifier <b>330</b> verifies the PE <b>210</b> using the verified loaded PE manifest <b>322</b> and a constant <b>355</b> derived from the PK <b>260</b> by a constant deriver <b>350</b>. Essentially, the PE verifier <b>330</b> compares the PE <b>210</b> with the loaded PE <b>312</b>. In addition, the PE verifier <b>330</b> determines a manifest of the loaded PE <b>312</b> using the constant <b>355</b> and compares the determined PE manifest with the verified loaded PE manifest <b>322</b>. The PE verifier <b>330</b> then generates a result to the PE error generator <b>340</b>. If the verification fails, the error generator <b>340</b> generates a failure or fault condition with an error code associated with the PE verification.

0063The PE key generator <b>360</b> generates a PE key <b>365</b> using the PK <b>260</b>. The PE key generator <b>360</b> includes a PE key combiner <b>364</b> to combine the PE identifier <b>224</b> and the PK <b>260</b>. The combined PE identifier <b>224</b> and the PK <b>260</b> correspond to the PE key <b>365</b>.

0064The PE identifier logger <b>370</b> logs the PE identifier <b>224</b> in a storage <b>375</b>. The PE identifier logger <b>370</b> writes the PE identifier <b>224</b> into the storage <b>375</b>. The storage <b>375</b> is a register located inside a chipset such as the ICH <b>150</b> shown in <figref idref="DRAWINGS">FIG. 1C</figref>.

0065The PE entrance/exit handler <b>380</b> handles a PE entrance and a PE exit. The PE entrance includes obtaining the entry point in the configuration buffer of the processor <b>110</b> to represent the PE's entry handler. The PE exit returns control to the boo-up code <b>240</b>.

0066<figref idref="DRAWINGS">FIG. 4</figref> is a diagram illustrating the PE <b>210</b> shown in <figref idref="DRAWINGS">FIG. 2</figref> according to one embodiment of the invention. The PE <b>210</b> includes an OSE loader <b>410</b>, an OSE manifest verifier <b>420</b>, an OSE verifier <b>430</b>, an OSE Error Generator <b>440</b>, an OSE key generator <b>460</b>, an OSE identifier logger <b>470</b>, and an OSE entrance/exit handler <b>480</b>.

0067The OSE loader <b>410</b>loads the OSE <b>270</b> and the OSE supplement <b>280</b> into the isolated memory area <b>70</b> as shown in <figref idref="DRAWINGS">FIG. 2</figref> using an OSE parameter block <b>405</b> provided by the OS <b>290</b>. The OSE loader <b>410</b> provides a loaded OSE manifest <b>422</b> and a loaded OSE <b>412</b> located in the isolated memory area <b>70</b> and corresponding to the OSE manifest <b>282</b> and the OSE <b>270</b>, respectively.

0068The OSE manifest verifier <b>420</b> verifies the OSE manifest <b>282</b> by comparing the OSE manifest <b>282</b> with the loaded OSE manifest <b>422</b>. The OSE manifest verifier <b>420</b> generates a result to an OSE error generator <b>440</b>. If the verification fails, the OSE error generator <b>440</b> generates a failure or fault condition with an error code associated with the OSE manifest verification.

0069The OSE verifier <b>430</b> verifies the OSE <b>270</b>. Essentially, the OSE verifier <b>430</b> compares the OSE <b>270</b> with the loaded OSE <b>412</b>. In addition, the OSE verifier <b>430</b> determines a manifest of the loaded OSE <b>412</b> using a root key and compares the determined OSE manifest with the verified loaded OSE manifest <b>422</b>. The OSE verifier <b>430</b> then generates a result to the OSE error generator <b>440</b>. If the verification fails, the OSE error generator <b>440</b> generates a failure or fault condition with an error code associated with the OSE verification.

0070The OSE key generator <b>460</b> generates an OSE key <b>465</b>. The OSE key generator <b>460</b> includes a binding key (BK) generator <b>462</b> and an OSE key combiner <b>464</b>. The binding key generator <b>462</b> generates a binding key (BK) <b>463</b> using the PE key <b>365</b> (<figref idref="DRAWINGS">FIG. 3</figref>). The OSE key combiner <b>464</b> combines the OSE identifier <b>284</b> and the BK <b>463</b>. The combined OSE identifier <b>284</b> and the BK <b>463</b> correspond to the OSE key <b>465</b>.

0071The OSE identifier logger <b>470</b> logs the OSE identifier <b>284</b> in the storage <b>375</b>. The storage <b>375</b> is a register located inside a chipset such as the ICH <b>150</b> shown in <figref idref="DRAWINGS">FIG. 1C</figref>.

0072The OSE entrance/exit handler <b>480</b> handles an OSE entrance and an OSE exit. The OSE entrance initializes parameters in a frame buffer and saves appropriate control parameters and transfers control to an entrance handler. The OSE exit clears and creates appropriate return parameters and then transfers control to the exit handler,

0073<figref idref="DRAWINGS">FIG. 5</figref> is a diagram illustrating the OSE <b>270</b> shown in <figref idref="DRAWINGS">FIG. 2</figref> according to one embodiment of the invention. The OSE <b>270</b> includes a module loader and evictor <b>510</b>, a page manager <b>520</b>, an interface handler <b>530</b>, a key binder and unbinder <b>540</b>, a scheduler and balancer <b>550</b>, and an interrupt handler <b>560</b>.

0074The module loader and evictor <b>510</b> loads and evicts a module into and out of the isolated memory area <b>70</b>, respectively. The module is one of an application module <b>512</b>, an applet module <b>514</b>, and a support module <b>516</b>. The page manager <b>520</b> manages paging in the isolated memory area <b>70</b>. The interface handler <b>530</b> handles interface with the subset <b>295</b> in the OS <b>290</b> (<figref idref="DRAWINGS">FIG. 2</figref>). The key binder and unbinder <b>540</b> includes an applet key generator <b>542</b> to generate an applet key <b>545</b> associated with the applet module <b>514</b>. The applet key generator <b>542</b> includes an applet key combiner <b>544</b> combines the OSE key <b>465</b> (<figref idref="DRAWINGS">FIG. 4</figref>) with an applet identifier <b>518</b> identifying the applet module <b>514</b>. The combined OSE key <b>465</b> and the applet identifier <b>518</b> correspond to the applet key <b>545</b>.

0075The scheduler and balancer <b>550</b> schedules execution of the loaded modules and balances the load of the isolated execution mode. The interrupt handler <b>560</b> handles interrupts and exceptions generated in the isolated execution mode.

0076<figref idref="DRAWINGS">FIG. 6</figref> is a diagram illustrating a boot-up code shown in <figref idref="DRAWINGS">FIG. 2</figref> according to one embodiment of the invention. The boot up code includes a PE locator <b>610</b>, a PE recorder <b>620</b>, and an instruction invoker <b>630</b>.

0077The PE locator <b>610</b> locates the original PE <b>246</b> and the original PE supplement <b>248</b>. The PE locator <b>610</b> transfers the original PE <b>246</b> and the original PE supplement <b>248</b> into the PE memory <b>215</b> at a PE address <b>625</b>. The PE recorder <b>620</b> records the PE address <b>625</b> in the PE parameter block <b>242</b>. As discussed above, the PE handler <b>230</b> obtains the PE address <b>625</b> from the PE parameter block <b>242</b> to locate the PE <b>210</b> and the PE supplement <b>220</b> in the PE memory <b>215</b>.

0078The instruction invoker <b>630</b> invokes and executes an isolated create instruction <b>632</b> which loads the PE handler <b>230</b> into the isolated memory area <b>70</b>. The isolated create instruction <b>632</b> performs an atomic non-interruptiblle sequence <b>640</b>. The atomic sequence <b>640</b> includes a number of operations: a physical memory operation <b>652</b>, an atomic read-and-increment operation <b>654</b>, an isolated memory area control operation <b>656</b>, a processor isolated execution operation <b>658</b>, an PE handler loading operation <b>663</b>, a PE handler verification <b>664</b>, and an exit operation <b>666</b>.

0079The physical memory operation <b>652</b> verifies if the processor is in a flat physical page mode. The atomic read-and-increment operation <b>654</b> reads and increments a thread count register in a chipset. The read-and-increment operation <b>654</b> determines if the processor is the first processor in the isolated execution mode. The isolated memory area control operation <b>656</b> configures the chipset using a configuration storage. The processor isolated execution operation <b>658</b> configures the processor in the isolated execution mode. The processor isolated execution operation <b>658</b> includes a chipset read operation <b>672</b> and a processor configuration operation <b>674</b>. The chipset read operation <b>672</b> reads the configuration storage in the chipset when the processor is not a first processor in the isolated execution mode. The processor configuration operation <b>674</b> configures the processor according to the configuration storage read by the chipset read operation <b>672</b> when the processor is not a first processor in the isolated execution mode. The PE handler loading operation <b>662</b> loads the PE handler <b>230</b> into the isolated memory area <b>70</b>. The PE handler verification <b>664</b> verifies the loaded PE handler. The exit operation <b>666</b> transfers control to the loaded PE handler.

0080<figref idref="DRAWINGS">FIG. 7</figref> is a flowchart illustrating a process <b>700</b> to manage a secure platform according to one embodiment of the invention.

0081Upon START, the process <b>700</b> boots up the platform following power on (Block <b>710</b>). The platform has a secure environment. The secure environment includes a platform key, an operating system executive (OSE), and an OSE supplement. The details of the Block <b>710</b> are shown in <figref idref="DRAWINGS">FIG. 8</figref>. Then, the process <b>700</b> handles a processor executive (PE) using the platform key and the PE supplement (Block <b>720</b>). The details of the Block <b>720</b> are shown in <figref idref="DRAWINGS">FIG. 10</figref>. Then, the process <b>700</b> handles the OSE in the secure environment (Block <b>730</b>). The details of the Block <b>730</b> are shown in <figref idref="DRAWINGS">FIG. 11</figref>.

0082Next, the process <b>700</b> manages a subset of an operating system running on the platform (Block <b>740</b>). The process <b>700</b> is then terminated.

0083<figref idref="DRAWINGS">FIG. 8</figref> is a flowchart illustrating the process <b>710</b> to boot up platform according to one embodiment of the invention.

0084Upon START, the process <b>710</b> locates the PE and the PE supplement (Block <b>810</b>). Then, the process <b>710</b> transfers the PE and the PE supplement into the PE memory at a PE address (Block <b>820</b>). Next, the process <b>710</b> records the PE address in a PE parameter block (Block <b>830</b>). Then, the process <b>710</b> executes the isolated create instruction (Block <b>840</b>). The details of the Block <b>840</b> are shown in <figref idref="DRAWINGS">FIG. 9</figref>. The process <b>710</b> is then terminated.

0085<figref idref="DRAWINGS">FIG. 9</figref> is a flowchart illustrating the process <b>840</b> to execute an isolated create instruction according to one embodiment of the invention.

0086Upon START, the process <b>840</b> determines if the processor is in a flat physical page mode (Block <b>910</b>). If not, the process <b>840</b> sets the processor in the flat physical page mode (Block <b>915</b>) and proceeds to Block <b>920</b>. Otherwise, the process <b>840</b> determines if the thread count register is zero (Block <b>920</b>). This is done by reading the thread count register in the chipset to determine if the processor is the first processor in the isolated execution mode. If not, the process <b>840</b> determines that the processor is not the first processor in the system to be in the isolated execution mode. The process <b>840</b> then reads the configuration storage from the chipset (Block <b>925</b>). Then, the process <b>840</b> configured the processor using the chipset configuration storage (Block <b>930</b>). Then, the process <b>840</b> proceeds to Block <b>960</b>.

0087If the thread count register is zero, the process <b>840</b> determines that the processor is the first processor in the system to be booted up with isolated execution mode. The process <b>840</b> then increments the thread count register to inform to other processors that there is already a processor being booted up in isolated execution mode (Block <b>935</b>). Then, the process <b>840</b> configures the chipset and the processor in isolated execution mode by writing appropriate setting values (e.g., isolated mask and base values) in the chipset and processor configuration storage (Block <b>940</b>). To configure the processor, the process <b>840</b> may also need to set up the isolated execution mode word in the control register of the processor.

0088Next, the process <b>840</b> loads the PE handler from the ROM internal to the chipset to the isolated memory area (Block <b>945</b>). Then, the process <b>840</b> determines if the loaded PE handler is the same as the original PE handler in the ROM (Block <b>950</b>). If not, the process <b>840</b> generates a failure or fault condition with an appropriate error code (Block <b>955</b>) and is then terminated. Otherwise, the process <b>840</b> transfers control to the loaded PE handler (Block <b>960</b>). The process <b>840</b> is then terminated.

0089<figref idref="DRAWINGS">FIG. 10</figref> is a flowchart illustrating the process <b>720</b> to handle a processor executive according to one embodiment of the invention.

0090Upon START, the process <b>720</b> loads the PE and the PE supplement from a PE memory into the isolated memory area using a parameter block provided by the boot-up code (Block <b>1010</b>). Next, the process <b>720</b> determines if the loaded PE manifest is the same as the original PE manifest (Block <b>1015</b>). If not, the process <b>720</b> generates a failure or fault condition with appropriate error code (Block <b>1020</b>) and is then terminated. Otherwise, the process <b>720</b> determines if the loaded PE has the same manifest as the loaded PE manifest (Block <b>1025</b>). If not, the process <b>720</b> goes to Block <b>1020</b> and is then terminated. Otherwise, the process <b>720</b> generates a PE key using the platform key in the secure environment (Block <b>1030</b>).

0091Then, the process <b>720</b> logs the PE identifier in a storage (Block <b>1035</b>). This log storage is typically a register in an ICH. Then, the process <b>720</b> changes the entry point in the configuration buffer of the processor to prepare for an OSE entrance (Block <b>1040</b>). Then, the process <b>720</b> returns to the boot-up code (Block <b>1045</b>). The process <b>720</b> is then terminated.

0092<figref idref="DRAWINGS">FIG. 11</figref> is a flowchart illustrating the process <b>730</b> to handle the OSE according to one embodiment of the invention.

0093Upon START, the OS boots and locates the OSE and the OSE supplement in the OSE memory at an OSE address (Block <b>1110</b>). Then the OS records the OSE address in an OSE parameter block (Block <b>1115</b>). Next, the process <b>730</b> determines if an OSE has already been loaded (Block <b>1120</b>). If yes, the process <b>730</b> is terminated. Otherwise, the process <b>730</b> loads the OSE and the OSE supplement into the isolated memory area (Block <b>1125</b>).

0094Next, the process <b>730</b> determines if the loaded OSE manifest is the same as the original OSE manifest (Block <b>1130</b>). If not, the process <b>730</b> generates a failure or fault condition with an appropriate error code (Block <b>1135</b>) and is then terminated. Otherwise, the process <b>730</b> determines if the loaded OSE has the same manifest as the loaded OSE manifest (Block <b>1140</b>). If not, the process <b>730</b> goes to block <b>1135</b> and is then terminated. Otherwise, the process <b>730</b> generates the OSE key using the PE key and the OSE identifier (Block <b>1145</b>).

0095Then, the process <b>730</b> logs the OSE identifier in a storage (Block <b>1150</b>). Typically, this log storage is a register in a chipset such as the ICH. Next, the process <b>730</b> clears any PE secrets or services that are not needed (Block <b>1155</b>). Then, the process <b>730</b> returns to the PE's exit handler (Block <b>1160</b>). The process <b>730</b> is then terminated.

0096While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications of the illustrative embodiments, as well as other embodiments of the invention, which are apparent to persons skilled in the art to which the invention pertains are deemed to lie within the spirit and scope of the invention.