Integrally packaged imaging module
Claim Score by NHIP
Abstract
An integrally packaged imaging module includes an integrated circuit (IC), including an image sensing device formed on a semiconductor substrate, and wafer level packaging enclosing the IC. The wafer level packaging includes a transparent enclosure portion adapted to permit image acquisition of an image by the image sensing device over a desired range of wavelengths, and a first spacing structure providing a cavity between an inner surface of the transparent enclosure portion and the image sensing device. A depth of the cavity is configurable along an axis perpendicular to the semiconductor substrate to control a distance between an outer surface of the transparent enclosure portion and the image sensing device.

Term
Term ended
Projected expiry passed 29 August 2024, 2.1 years ago.
- Priority and filed
- Published
- Projected expiry
- Today
20 claims: 3 independent, 17 dependent
- 1An integrally packaged imaging module, comprising:an integrated circuit (IC) including an image sensing device formed on a semiconductor substrate;wafer-level packaging enclosing the IC, and including: a transparent enclosure portion adapted to permit image acquisition of an image by the image sensing device over a desired range of wavelengths;and a first spacing structure providing a cavity between an inner surface of the transparent enclosure portion and the image sensing device, wherein a depth of the cavity is configurable along an axis perpendicular to the semiconductor substrate to control a distance between an outer surface of the transparent enclosure portion and the image sensing device.
- 8A method of fabricating integrally packaged imaging modules, the method comprising:forming an array of integrated circuits (ICs) on a semiconductor wafer, each IC including an image sensing device;integrally packaging the array of ICs, the packaging step comprising: enclosing the array of ICs on a first side with a transparent enclosure layer so that each image sensing device of each IC in the array can detect an image consisting of a desired range of wavelengths through the transparent enclosure layer;aligning and attaching an array of lens supports to another packaging layer such that lenses used with the array of lens supports are optically aligned with corresponding image sensing devices;and dicing the packaged array of ICs into individual integrally packaged imaging modules.
- 11Broadest claimClaim Score 67, broad(NHIP)An integrally packaged imaging module, comprising:an integrated circuit (IC) including an image sensing device formed on a semiconductor substrate;wafer-level packaging enclosing the IC, and including: a transparent enclosure portion adapted to permit image acquisition of an image by the image sensing device over a desired range of wavelengths;a first lens support adapted to suspend a first lens so that the first lens directs the image onto the image sensing device;and a first spacing structure adapted to provide a spacing between the suspended first lens and the image sensing device.
Independent claims3
76 paragraphs in 5 sections, as filed
THE FIELD OF THE INVENTION
0001The present invention relates generally to imaging modules, and more particularly to an integrally-packaged imaging module.
BACKGROUND OF THE INVENTION
0002Digital imaging technology is being used in an increasing variety of mass-produced applications and in increasing production volumes. For example, miniature fixed-focus digital camera modules are being incorporated into end products such as portable telephones and personal digital assistants (PDA's). Given the new high volume applications for imaging modules, it is a continuing objective for imaging module fabricators to reduce their size and cost, and to provide imaging module designs that simplify incorporating the imaging modules into end products made by original equipment manufacturers (OEMs).
0003Imaging modules generally include an image sensor that detects an image and converts it into an electrical signal representation. An image processor is employed to further manipulate the image signal into an image of a suitable quality for output. Electrical contacts provide connectivity between the imaging modules and the end products incorporating the imaging modules.
0004One type of imaging module is commonly referred to as a camera module. Camera modules are known in the art as miniature complete camera assemblies for incorporation into end products. A camera module generally includes an image sensor, an image processor, interface circuitry and hardware, and a lens for focusing incoming light onto the image sensor. A conventional camera module also typically includes a chassis and/or enclosure for mounting the various electronic and optical components and for protecting the components from particulate and spurious light contamination. A typical chassis/enclosure includes focusing features for aligning the lens and image sensor during fabrication. The focusing features are commonly in the form of mating pieces as part of the main chassis/enclosure, and lens assembly piece. During fabrication, the mating pieces are specially aligned so that the lens directs an image onto the image sensor. This assembly step is typically performed on each individual camera module fabricated. Therefore, the assembly step is time consuming and labor-intensive, and therefore costly.
0005End products that incorporate imaging modules include a mechanism for mechanically and electrically attaching the imaging modules to the host devices. Conventional mechanisms for attaching the imaging modules to the host devices tend to be costly when compared to the costs of attaching other types of electronic/electrical hardware, such as integrated circuits (IC's). Conventional imaging modules are not suitable for automatic assembly. A conventional imaging module is typically located on a circuit board that is enclosed by the host device's housing. The imaging module is secured to the circuit board with adhesive, mounting hardware, or structural features. In other types of conventional designs, the imaging module attaches mechanically to the housing of the host device. In these examples, an electrical connection between the imaging module and the host device is typically accomplished with a multi-conductor cable and mating electrical connectors on the circuit board. Such features are expensive, not well suited for automatic assembly, bulky, and less reliable than soldered connections.
0006Standard automatic electronic assembly processes are not readily adaptable to support automatic mounting and connecting of conventional imaging modules. Thus, assembly of host devices involves manual operations to mount and electrically connect the imaging modules. For example, conventional digital camera modules are mounted to the host device by hand, and the connector is inserted by hand. By nature, manual operations are slow, labor-intensive, and prone to error; therefore, manual assembly steps are expensive. Furthermore, the material costs of conventional imaging modules include the costs of the mounting and connecting hardware. Moreover, the space within the host device needed to accommodate conventional imaging modules includes space for the mounting and connecting mechanism. Additional space requirements inhibit host device miniaturization, cost reduction, and marketability.
0007By contrast, electrical/electronic hardware such as integrate circuits is typically assembled onto a host device's circuit board automatically. Most commonly, surface-mount technology (SMT) is employed, where each component is robotically placed and automatically soldered onto the circuit board using solder wave or re-flow processing. The soldered joints accomplish a mechanical and electrical attachment.
0008In a typical SMT process, a circuit board is first prepared to accept solderable components. Most commonly, solder paste is applied selectively to electrical pads that accept contacts of the electrical components to be mounted thereupon. Next, the electrical components are automatically placed into their appropriate positions on the circuit boards using robotics. This process is referred to as pick-and-place, or onsertion. The electrical components are temporarily held in place on the circuit board pads by the solder paste's adhesive properties. Next, the circuit board with components positioned thereupon is subjected to a solder re-flow process in order to create permanent solder joints at all electrical contact/pad interfaces.
0009A solder re-flow process involves heating the solder paste to a temperature where the solder melts and flows thoroughly onto both the mounting pads and electrical component contacts. The temperature of the solder is then allowed to drop, causing the solder to solidify into solder joints that mechanically and electrically bond the components to the circuit board. The temperature at the molten solder joints during the re-flow process is on the order of 250° C. Such temperatures can be reached by a variety of means, including conductive, convective, or radiant heating of the solder joint sites.
0010Components for use on circuit boards assembled using a re-flow process must be able to withstand the process temperatures. However, as with any manufactured product in mass production, conventional digital camera modules are constructed from low-cost materials whenever possible. Enclosure materials and lens materials are often made from various plastics. Although certain plastic materials can withstand re-flow temperatures for short periods of time, presently available materials are not suitable as lens material, which must have particular optical characteristics.
0011Recent advances in the art have achieved fully integrated imaging modules. These modules are essentially fully packaged integrated circuits having an optically transparent window that allows the image sensor IC to capture an image. In camera module applications, such imaging modules reduce cost, parts count and camera module assembly costs with their smaller size and increased level of integration. Still, camera modules incorporating these imaging modules use separate housings and lens assemblies, and lens alignment procedures as part of their manufacture. To date, no practical solution has been proposed for a fully integrated camera module, or a low-cost imaging module that can easily be assembled into a camera module.
SUMMARY OF THE INVENTION
0012Embodiments of the present invention provide an improved integrally packaged imaging module, which includes an integrated circuit (IC), including an image sensing device formed on a semiconductor substrate, and wafer level packaging enclosing the IC. The wafer level packaging includes a transparent enclosure portion adapted to permit image acquisition of an image by the image sensing device over a desired range of wavelengths, and a first spacing structure providing a cavity between an inner surface of the transparent enclosure portion and the image sensing device. A depth of the cavity is configurable along an axis perpendicular to the semiconductor substrate to control a distance between an outer surface of the transparent enclosure portion and the image sensing device.
BRIEF DESCRIPTION OF THE DRAWINGS
0013<figref idref="DRAWINGS">FIG. 1A</figref> illustrates an integrally-packaged imaging module according to one aspect of the present invention.
0014<figref idref="DRAWINGS">FIG. 1B</figref> is an exploded-view diagram illustrating one embodiment of the imaging module of <figref idref="DRAWINGS">FIG. 1A</figref>.
0015<figref idref="DRAWINGS">FIG. 1C</figref> is a diagram illustrating one embodiment of a spacing structure that is a part of one embodiment of the imaging module of <figref idref="DRAWINGS">FIG. 1A</figref>.
0016<figref idref="DRAWINGS">FIG. 2A</figref> illustrates a cross-section of an array of partially assembled imaging modules just prior to singulation according to one embodiment of the present invention.
0017<figref idref="DRAWINGS">FIG. 2B</figref> illustrates one embodiment of a wafer-level packaging process for the imaging module of <figref idref="DRAWINGS">FIG. 1A</figref>.
0018<figref idref="DRAWINGS">FIG. 3A</figref> illustrates one embodiment of a camera module that includes a transparent enclosure portion in the form of a lens.
0019<figref idref="DRAWINGS">FIG. 3B</figref> is a diagram illustrating another embodiment of a transparent enclosure portion of the camera module of <figref idref="DRAWINGS">FIG. 3A</figref>.
0020<figref idref="DRAWINGS">FIG. 4</figref> illustrates an embodiment of an imaging module that includes a lens support.
0021<figref idref="DRAWINGS">FIG. 5A</figref> illustrates one embodiment of a camera module that includes a lens assembly and a cavity within the wafer level packaging.
0022<figref idref="DRAWINGS">FIG. 5B</figref> is a diagram illustrating one embodiment of a wafer level packaging process for assembling the camera module of <figref idref="DRAWINGS">FIG. 5A</figref>, the process including attaching a contiguous array of lens assemblies onto an un-singulated array of imaging modules.
0023<figref idref="DRAWINGS">FIG. 5C</figref> illustrates another embodiment of a wafer level packaging process for assembling camera module of <figref idref="DRAWINGS">FIG. 5A</figref>, the process including attaching an array of individual lens assemblies onto an un-singulated array of imaging modules.
0024<figref idref="DRAWINGS">FIG. 5D</figref> is a cross-sectional view diagram illustrating one embodiment of an individual lens assembly used in the wafer level packaging process of <figref idref="DRAWINGS">FIG. 5C</figref>.
0025<figref idref="DRAWINGS">FIG. 5E</figref> illustrates one embodiment of a method for positioning an array of the individual lens assemblies in the wafer level packaging process of <figref idref="DRAWINGS">FIG. 5C</figref>.
0026<figref idref="DRAWINGS">FIG. 6</figref> illustrates one embodiment of a camera module that includes a lens assembly but that does not include a cavity.
0027<figref idref="DRAWINGS">FIG. 7</figref> illustrates another embodiment of a camera module that includes a transparent enclosure portion positioned over a lens assembly.
0028<figref idref="DRAWINGS">FIG. 8</figref> is a diagram illustrating one embodiment of a camera module incorporating a dual lens optical system.
0029<figref idref="DRAWINGS">FIG. 9</figref> illustrates another embodiment of a dual lens camera module.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
0030In the following detailed description of the preferred embodiments, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.
0031<figref idref="DRAWINGS">FIG. 1A</figref> illustrates an integrally-packaged imaging module <b>100</b> according to one aspect of the present invention. Imaging module <b>100</b> includes semiconductor substrate <b>102</b>. In one embodiment, the surface of semiconductor substrate <b>102</b> includes an active area <b>104</b> containing integrated circuitry <b>106</b>, which includes an image sensing device <b>107</b>, an image processor, interface logic, and power conditioning circuitry. In one embodiment, image sensing device <b>107</b> includes an array of charge-coupled devices (CCDs). In another embodiment, image sensing device <b>107</b> is a CMOS technology image sensor. In one embodiment, image sensing device <b>107</b> includes microlenses, with each microlens situated over a corresponding pixel of the image sensing device <b>107</b> for focusing incoming light onto the corresponding pixel.
0032Imaging module <b>100</b> includes wafer-level packaging enclosing the semiconductor substrate <b>102</b>. Wafer-level packaging technology is generally known in the art, and is sometimes referred to as chip-scale packaging (CSP). Wafer-level packaging technology permits integrated circuits formed on a wafer to be packaged for end-product use before being individually separated from the wafer by a dicing process. Thus, an entire wafer containing hundreds or thousands of integrated circuit die is processed in a single wafer-level packaging process to simultaneously package every integrated circuit on the wafer.
0033The wafer-level packaging of the imaging module <b>100</b> includes packaging substrate <b>108</b> attached to semiconductor substrate <b>102</b> with an adhesive layer <b>110</b>. In one embodiment, packaging substrate <b>108</b> is formed from glass. In another embodiment, packaging substrate <b>108</b> is formed from silicon. In one embodiment, adhesive layer <b>110</b> includes an epoxy compound situated between the interfacing surfaces of semiconductor substrate <b>102</b> and packaging substrate <b>108</b>.
0034The wafer-level packaging of the imaging module <b>100</b> further includes electrical contacts <b>112</b><i>a</i>, <b>112</b><i>b</i>, <b>112</b><i>c</i>, and <b>112</b><i>d</i>, collectively referred to as electrical contacts <b>112</b>. In one embodiment, electrical contacts <b>112</b> are adapted for mounting imaging module <b>100</b> onto a printed circuit board (PCB) of an end product. In one embodiment, electrical contacts <b>112</b> are solder bumps situated in a standard ball grid array (BGA) configuration. In another embodiment, electrical contacts <b>112</b> are in the form of pins for through-hole insertion. It will be recognized by one skilled in the art that electrical contacts <b>112</b> can have numerous other forms. For connecting electrical contacts <b>112</b> to integrated circuitry <b>106</b>, imaging module <b>100</b> employs redistribution structures <b>114</b>. In one embodiment, redistribution structures <b>114</b> are formed from deposited metallic material along the surfaces of semiconductor substrate <b>102</b>, packaging substrate <b>108</b>, and adhesive layer <b>110</b>. In another embodiment, the redistribution structures <b>114</b> are formed using thin film fabrication technology that is known in the art. In yet another embodiment, redistribution structures <b>114</b> include wire bonds. It will be recognized by one skilled in the art that a variety of wafer level/CSP technologies can be used for creating redistribution structures <b>114</b> that connect input/output nodes of the integrated circuitry <b>106</b> to the electrical contacts <b>112</b> within the wafer-level packaging.
0035The wafer-level packaging of imaging module <b>100</b> facilitates image acquisition by the image sensing device <b>107</b> while providing an enclosure protecting the integrated circuitry <b>106</b> from contamination. Imaging module <b>100</b> includes a transparent enclosure portion <b>116</b> situated to permit light to enter the packaging of imaging module <b>100</b> and reach the image sensing device <b>107</b> of integrated circuitry <b>106</b>. In one embodiment, the transparent enclosure portion <b>116</b> is formed from glass. In another embodiment, transparent enclosure portion <b>116</b> is formed from plastic having sufficient optical properties to permit image acquisition of a desired image quality. It will be recognized by one skilled in the art that a variety of known moldable and/or machinable materials can be used to form transparent enclosure portion <b>116</b>. In one embodiment, the transparent enclosure portion is capable of temporarily withstanding temperatures on the order of 250° C., to which electronic components are commonly exposed during solder re-flow processing in circuit card assembly processes.
0036In one embodiment, transparent enclosure portion <b>116</b> includes an optical filter to permit only a certain range of desired frequencies to pass through it. In one form of this embodiment, an optical filtering film <b>118</b> is applied to a surface of transparent enclosure portion <b>116</b>. In one embodiment, optical filtering film <b>118</b> is a reflective infrared (IR) filter deposited on a surface of transparent enclosure portion <b>116</b>. In another embodiment, the material from which transparent enclosure portion <b>116</b> is formed has filtering properties with respect to undesired wavelengths.
0037In one embodiment, imaging module <b>100</b> includes a cavity <b>120</b> within its package. Cavity <b>120</b> is a space between the image sensing device <b>107</b> and the innermost surface of transparent enclosure portion <b>116</b>. In one embodiment, cavity <b>120</b> is void of any solid or liquid material. In one embodiment, cavity <b>120</b> has an index of refraction that is different from that of the transparent enclosure portion <b>116</b>. In one embodiment, cavity <b>120</b> has an index of refraction of approximately 1.0. In one embodiment, cavity <b>120</b> contains atmospheric gasses. In another embodiment, cavity <b>120</b> is a vacuum.
0038One advantage provided by cavity <b>120</b> is to permit the image sensing device <b>107</b> to function optimally. For example, where image sensing device <b>107</b> includes microlenses and is designed to operate in a medium having an index of refraction of 1, cavity <b>120</b>, in one embodiment, provides a space adjacent to the microlenses that has an index refraction of about 1.
0039Another advantage provided by cavity <b>120</b> is realized in one embodiment where cavity <b>120</b> provides a spacing between the outer surface of transparent enclosure portion <b>116</b> and the image sensing device <b>107</b> that has a distance greater than the thickness of transparent enclosure portion <b>116</b>. A spacing between the outer surface of transparent enclosure portion <b>116</b> and the image sensing device <b>107</b> is desirable because it reduces the effects of particulate contamination on the surface of the transparent enclosure portion <b>116</b>. For example, consider a dust particle on the transparent enclosure portion <b>116</b> between the image sensing device <b>107</b> and a light source. When the dust particle is closer to the image sensing device <b>107</b>, less light is unable to pass around the particle to illuminate the blocked pixels, resulting in a darker shadow over the pixels. By contrast, when the dust particle is farther from the image sensing device <b>107</b>, more light is able to pass around the dust particle to illuminate the blocked pixels. Therefore, cavity <b>120</b> permits imaging module <b>100</b> to have a greater spacing distance between the outer surface of transparent enclosure portion <b>116</b> and image sensing device <b>107</b> while keeping fixed the thickness of transparent enclosure portion <b>116</b>. Benefits of improved immunity to particulate contamination provided by cavity <b>120</b> include an ability to perform further fabrication processes on imaging module <b>100</b> in a less stringent cleanroom environment.
0040Cavity <b>120</b> provides a further advantage by facilitating an ability to easily control the distance between the outer surface of transparent enclosure portion <b>116</b> and the image sensing device <b>107</b>. One example of a situation where controlling this distance is desirable is in the fabrication of a camera module according to one aspect of the present invention that is described below. One embodiment of such a camera module includes an integrally packaged lens aligned to focus an image onto the image sensing device <b>107</b>, wherein the focusing is achieved through the controlled cavity height controlled to within +/−10 microns.
0041In one embodiment, cavity <b>120</b> is formed by a spacing structure indicated at <b>122</b>. In one embodiment, spacing structure <b>122</b> is situated between semiconductor substrate <b>102</b> and transparent enclosure portion <b>116</b>, and forms a wall enclosing the image sensing device <b>107</b>. <figref idref="DRAWINGS">FIG. 1B</figref> is an exploded-view diagram illustrating one embodiment of imaging module <b>100</b>. In the embodiment of <figref idref="DRAWINGS">FIG. 1B</figref>, spacing structure <b>122</b><i>a </i>is one embodiment of spacing structure <b>122</b> (<figref idref="DRAWINGS">FIG. 1A</figref>). Spacing structure <b>122</b><i>a </i>is a four-walled spacer rim surrounding the perimeter of integrated circuitry <b>106</b> and image sensing device <b>107</b>.
0042<figref idref="DRAWINGS">FIG. 1C</figref> illustrates a spacing structure set <b>122</b><i>b</i>, which is another embodiment of spacing structure <b>122</b>. Spacing structure set <b>122</b><i>b </i>is comprised of four non-contiguous pieces <b>125</b><i>a</i>-<b>125</b><i>d</i>. In one embodiment of the imaging module <b>100</b>, spacing structure set <b>122</b><i>b </i>is employed.
0043Referring back to <figref idref="DRAWINGS">FIG. 1A</figref>, spacing structure <b>122</b> is sandwiched between semiconductor substrate <b>102</b> and transparent enclosure portion <b>116</b>. In one embodiment, spacing structure <b>122</b> is formed from plastic. In another embodiment, spacing structure <b>122</b> is formed from glass. In yet another embodiment, spacing structure <b>122</b> is formed from silicon. It will be understood by one skilled in the art that spacing structure <b>122</b> can be formed from a variety of moldable and/or machinable materials suitable for wafer-level packaging.
0044In one embodiment, spacing structure <b>122</b> is attached to semiconductor substrate <b>102</b> with an adhesive layer <b>124</b>, and to transparent enclosure portion <b>116</b> with an adhesive layer <b>126</b>. In one embodiment, adhesive layers <b>124</b> and <b>126</b> are both layers of a selectively-applied epoxy compound. In another embodiment, spacing structure <b>122</b> is fastened to semiconductor substrate <b>102</b> with a hot press process, and a separate adhesive layer is not used. In one embodiment, spacing structure <b>122</b> is welded to transparent enclosure portion <b>116</b> via one or more welded joints.
0045In one embodiment, the height of spacing structure <b>122</b> is adjusted during the assembly of the imaging module <b>100</b> as part of controlling the spacing between the outer surface of transparent enclosure portion <b>116</b> and image sensing device <b>107</b>. In one embodiment, the height of spacing structure <b>122</b> is reduced based on a measured thickness of transparent enclosure portion <b>116</b>, thereby correcting for any variance in the thickness of the transparent enclosure portion that exceeds a required tolerance. In one embodiment, the height of the spacing structure <b>122</b> defining cavity <b>120</b> along an axis perpendicular to the image sensing device <b>107</b> is controllable to within +/−50 microns.
0046The controlling of the height of spacing structure <b>122</b> can be accomplished in a variety of ways, as understood by one skilled in the art. For example, in one embodiment, spacing structure <b>122</b> is deformed in a controlled manner during a hot press process of adhering spacing structure <b>122</b> to semiconductor substrate <b>102</b>. In another embodiment, spacing structure <b>122</b> is machined to a desired height.
0047In another embodiment, the controlling of the height of cavity <b>120</b> includes dynamically adjusting the thickness of adhesive layers <b>124</b> and/or <b>126</b> during the attachment of the spacing structure <b>122</b> to the semiconductor substrate <b>102</b>. In one such embodiment, adhesive layer <b>124</b> is a curable adhesive compound applied to the upper surface of semiconductor substrate <b>102</b>. The adhesive compound is applied such that it has an initial thickness greater than the desired spacing between the upper surface of semiconductor substrate <b>102</b> and the spacing structure <b>122</b>. Next, while the adhesive compound is uncured and in a liquid state, the spacing structure is controllably positioned into the volume of the initial adhesive compound application according to specified tolerances, thereby displacing some of the adhesive compound, and held in place. Finally, the adhesive compound cures, and permanently holds the spacing structure substantially in the controllably positioned location.
0048<figref idref="DRAWINGS">FIG. 2A</figref> illustrates a cross-section of an array <b>150</b> of partially assembled imaging modules <b>100</b><i>a</i>, <b>100</b><i>b</i>, and <b>100</b><i>c </i>(collectively referred to as imaging modules <b>100</b>) just prior to singulation. Array <b>150</b> is assembled from a single semiconductor wafer <b>101</b> that has been separated into individual semiconductor substrates <b>102</b><i>a</i>, <b>102</b><i>b</i>, and <b>102</b><i>c</i>. Likewise, packaging substrates <b>108</b><i>a</i>, <b>108</b><i>b</i>, and <b>108</b><i>c </i>are each separated out from a single packaging substrate layer <b>109</b> attached to the semiconductor wafer <b>101</b> at adhesive layer <b>111</b>. Transparent enclosure portions <b>116</b><i>a</i>, <b>116</b><i>b</i>, and <b>116</b><i>c </i>of imaging modules <b>100</b><i>a</i>, <b>100</b><i>b</i>, and <b>100</b><i>c</i>, respectively, have not yet been separated from one another and are thus shown as a single transparent enclosure layer <b>115</b>. In one embodiment, final singulation is accomplished with dicing blades <b>152</b><i>a </i>and <b>152</b><i>b </i>along dicing planes indicated at <b>154</b><i>a </i>and <b>154</b><i>b. </i>
0049<figref idref="DRAWINGS">FIG. 2B</figref> illustrates a wafer-level packaging process for imaging modules <b>100</b>. An exploded-view diagram of a partially-assembled array <b>150</b> of imaging modules <b>100</b> is shown in <figref idref="DRAWINGS">FIG. 2B</figref>. A spacer array <b>121</b> of spacing structures <b>122</b><i>a </i>includes a spacing structure <b>122</b><i>a </i>for each corresponding image sensing device <b>107</b> formed on wafer <b>101</b>. A transparent enclosure layer <b>115</b> is assembled over spacer array <b>121</b>. Later, during singulation, each imaging module <b>100</b> is separated out from array <b>150</b>. In one packaging process embodiment, each IC <b>104</b> (<figref idref="DRAWINGS">FIG. 1A</figref>) is electrically separated prior to physical part singulation so that each IC <b>104</b> can be electrically tested at the wafer level.
0050<figref idref="DRAWINGS">FIG. 3A</figref> illustrates a camera module <b>200</b><i>a </i>according to one aspect of the present invention. The camera module <b>200</b><i>a </i>is similar to imaging module <b>100</b> in that camera module <b>200</b><i>a </i>includes semiconductor substrate <b>102</b>, image sensing device <b>107</b>, packaging substrate <b>108</b>, electrical contacts <b>112</b>, and redistribution structures <b>114</b>. However, camera module <b>200</b><i>a </i>is characterized by a transparent enclosure portion <b>216</b> that includes a lens <b>217</b> adapted to direct an image onto image sensing device <b>107</b>. In one embodiment, lens <b>217</b> is optically coupled to a multiplicity of pixels of image sensing device <b>107</b>. In one form of such an embodiment, lens <b>217</b> directs an image onto image sensing device <b>107</b>, illuminating all of the functional pixels of image sensing device <b>107</b>.
0051Transparent enclosure portion <b>216</b> also includes a spacing structure <b>219</b> coupled to lens <b>217</b> and adapted to hold lens <b>217</b> at a selected distance and orientation relative to image sensing device <b>107</b>. Transparent enclosure portion <b>216</b> also functions as an enclosure portion enclosing image sensing device <b>107</b>. In one embodiment, spacing structure <b>219</b>, lens <b>217</b>, and semiconductor substrate <b>102</b> together define a cavity <b>220</b>, which is similar to cavity <b>120</b> (<figref idref="DRAWINGS">FIG. 1A</figref>).
0052Similarly to transparent enclosure portion <b>116</b>, transparent enclosure portion <b>216</b> can be formed from a variety of suitable materials. In one embodiment, transparent enclosure portion <b>216</b>, including lens <b>217</b> and spacing structure <b>219</b>, is molded from a contiguous piece of glass. In another embodiment, transparent enclosure portion <b>216</b> is molded from high-temperature plastic. In another embodiment, transparent enclosure portion <b>216</b> is assembled from separate parts including separate pieces for lens <b>217</b> and spacing structure <b>219</b>.
0053In one embodiment of camera module <b>200</b><i>a</i>, the surface of image sensing device <b>107</b> includes an optical filter indicated at <b>218</b> in <figref idref="DRAWINGS">FIG. 3A</figref>. In another embodiment, illustrated in <figref idref="DRAWINGS">FIG. 3B</figref>, transparent enclosure portion <b>216</b> of camera module <b>200</b><i>b </i>includes an optical filter <b>221</b> on the surface of the lens <b>217</b>.
0054According to another aspect of the present invention, an integrally-packaged imaging module with a lens support is provided. <figref idref="DRAWINGS">FIG. 4</figref> illustrates one such partial camera module embodiment, indicated at <b>250</b>. Partial camera module <b>250</b> includes imaging module <b>100</b>. Partial camera module <b>250</b> also includes a lens support <b>252</b>, which is attached to transparent enclosure portion <b>116</b> of imaging module <b>100</b>. Lens support <b>252</b> includes a spacing structure <b>253</b> having coupling features <b>255</b> for coupling a lens <b>254</b> to spacing structure <b>253</b>.
0055The attachment of spacing structure <b>253</b> to imaging device <b>100</b> is provided by adhesive layer <b>256</b>. In one embodiment, adhesive layer <b>256</b> is achieved with an epoxy compound. In another embodiment, spacing structure <b>253</b> is welded to transparent enclosure portion <b>116</b> of imaging module <b>100</b>. One skilled in the art will recognize that there are a variety of ways in which spacing structure <b>253</b> can be attached to imaging module <b>100</b>.
0056In one embodiment, lens <b>254</b> is not a part of partial camera module <b>250</b>. Rather, lens <b>254</b> is attached to lens support <b>252</b> at the tail end of the end product assembly process. Excluding lens <b>254</b> from partial camera module <b>250</b> permits lens <b>254</b> to be made from low cost materials that are unable to withstand re-flow soldering conditions. Partial camera module <b>250</b> is first assembled into the end product using solder re-flow processing. Later, lens <b>254</b> is installed into lens support <b>252</b>. Once lens <b>254</b> is installed, partial camera module <b>250</b> effectively becomes a complete camera module.
0057The positioning of lens <b>254</b> relative to image sensing device <b>107</b> adjusts a focus of the optical system of partial camera module <b>250</b>. The positioning is important for the image quality of the partial camera module <b>250</b>. In one embodiment, the spacing distance of spacing structure <b>253</b> is adjusted during partial camera module <b>250</b> fabrication. In one embodiment, the spacing structure <b>253</b> is machined to an appropriate height. In another embodiment, the height of adhesive layer <b>256</b> is controlled. In another embodiment, as presented above, the height of spacing structure <b>122</b> is adjusted to control the distance between image sensing device <b>107</b> and the position of lens <b>254</b>.
0058<figref idref="DRAWINGS">FIG. 5A</figref> illustrates a camera module <b>300</b> according to one aspect of the present invention. Camera module <b>300</b> includes imaging module <b>100</b>, to which a lens assembly <b>302</b> is attached. Lens assembly <b>302</b> includes a spacing structure <b>303</b> coupled to a lens <b>304</b>. Spacing structure <b>303</b> and its coupling features for coupling to lens <b>304</b> are collectively referred to herein as a lens support <b>305</b>. Lens <b>304</b> is adapted for directing an image onto image sensing device <b>107</b> of imaging module <b>100</b>. Lens support <b>305</b> is adapted for maintaining a fixed positioning of lens <b>304</b> relative to the outer surface of transparent enclosure portion <b>116</b>. In one embodiment, lens support <b>305</b> and lens <b>304</b> are formed from a single moldable material, such as glass or clear plastic.
0059In order for lens <b>304</b> to function effectively, the volume <b>308</b> under the inner surface of lens <b>304</b> has an index of refraction that is different from that of lens <b>304</b>. Spacing structure <b>303</b> is adapted to be attached to transparent enclosure portion <b>116</b>. The points of attachment are defined by an adhesive layer <b>306</b>. In one embodiment, adhesive layer <b>306</b> includes an epoxy compound. In another embodiment, spacing structure <b>303</b> is attached to transparent enclosure portion <b>116</b> via one or more welded joints.
0060In one embodiment of camera module <b>300</b>, during assembly, spacing structure <b>303</b> is machined or re-formed to focus the optical system including lens <b>304</b> and image sensing device <b>107</b> within an acceptable tolerance of ±15 μm. In another embodiment, spacing structure <b>122</b> of imaging module <b>100</b> is machined or re-formed during assembly to provide the appropriate lens/image sensing device positioning. Adjusting the relative positioning of lens <b>304</b> and image sensing device <b>107</b> by changing the spacing dimensions of one or more spacing structures permits higher-tolerance/lower cost materials to be used. For example, controlling the distance between lens <b>304</b> and image sensing device <b>107</b> allows the use of a low-cost transparent enclosure portion material <b>116</b> having a thickness tolerance of ±50 μm, while maintaining the lens <b>304</b> and image sensing device <b>107</b> positioning tolerance of ±15 μm.
0061In one embodiment, camera module <b>300</b> is assembled in its entirety by a wafer-level packaging process similar to the process illustrated in <figref idref="DRAWINGS">FIG. 2B</figref>. In one embodiment, the spacing adjustment is performed on spacer array <b>121</b> automatically as part of the wafer-level packaging process. In another embodiment, the spacing adjustment is performed on the spacing structure <b>303</b>.
0062<figref idref="DRAWINGS">FIG. 5B</figref> is a diagram illustrating a wafer level packaging process for assembling camera modules <b>300</b><i>a</i>, <b>300</b><i>b</i>, and <b>300</b><i>c</i>. A lens assembly array <b>310</b> is attached to the outer surface of the transparent enclosure layer <b>115</b> of array <b>150</b>. Lens assembly array <b>310</b> includes contiguous lens assemblies <b>302</b><i>a</i>, <b>302</b><i>b</i>, and <b>302</b><i>c </i>arranged so that lenses <b>304</b><i>a</i>, <b>304</b><i>b</i>, and <b>304</b><i>c </i>are positioned over corresponding image sensing devices <b>107</b><i>a</i>, <b>107</b><i>b</i>, and <b>107</b><i>c</i>. In one embodiment, lens assembly array <b>310</b> is formed from a single molded piece of material. Later, during singulation, camera modules <b>300</b><i>a</i>, <b>300</b><i>b</i>, and <b>300</b><i>c </i>are separated along dicing planes <b>312</b><i>a </i>and <b>312</b><i>b. </i>
0063<figref idref="DRAWINGS">FIG. 5C</figref> illustrates another embodiment of a wafer level packaging process for assembling camera modules <b>300</b><i>a</i>, <b>300</b><i>b</i>, and <b>300</b><i>c</i>. In this embodiment, lens assemblies <b>302</b><i>d</i>, <b>302</b><i>e</i>, and <b>302</b><i>f </i>are each individual, discontiguous lens assemblies. Lens assembly spacers <b>314</b><i>a </i>and <b>314</b><i>b </i>are situated between each adjacent pair of lens assemblies, and provide positioning of lens assemblies <b>302</b><i>d</i>, <b>302</b><i>e</i>, and <b>302</b><i>f </i>along axes parallel to the plane of image sensing devices <b>107</b><i>a</i>, <b>107</b><i>b</i>, and <b>107</b><i>c </i>so that each lens <b>304</b><i>d</i>, <b>304</b><i>e</i>, and <b>304</b><i>f</i>, is centered over each corresponding image sensing device <b>107</b><i>a</i>, <b>107</b><i>b</i>, and <b>107</b><i>c </i>by a distance controlled by spacing structures <b>303</b><i>d</i>, <b>303</b><i>e</i>, and <b>303</b><i>f</i>. <figref idref="DRAWINGS">FIG. 5D</figref> is a cross-sectional diagram illustrating one form of lens assembly <b>302</b><i>d</i>. The embodiment of lens assembly <b>302</b><i>d </i>illustrated in <figref idref="DRAWINGS">FIG. 5D</figref> is a single molded piece combining the lens <b>304</b><i>d </i>and the spacing structure <b>303</b><i>d. </i>
0064In one embodiment, lens assemblies <b>302</b><i>d</i>, <b>302</b><i>e</i>, and <b>302</b><i>f </i>are simultaneously positioned over the transparent enclosure layer <b>115</b> of array <b>150</b>. <figref idref="DRAWINGS">FIG. 5E</figref> is a diagram illustrating an assembly method according to this aspect of the invention. In this embodiment, lens assembly spacers <b>314</b><i>a </i>and <b>314</b><i>b </i>(<figref idref="DRAWINGS">FIG. 5C</figref>) are each a part of a lens assembly spacer tray <b>314</b>, which is made up of lens assembly spacers. In this embodiment, each individual lens assembly <b>302</b><i>d</i>, <b>302</b><i>e</i>, and <b>302</b><i>f</i>, arrives to the wafer level assembly process in tray <b>314</b>. After the lens assemblies <b>302</b><i>d</i>, <b>302</b><i>e</i>, and <b>302</b><i>f </i>are attached to transparent enclosure layer <b>115</b>, tray <b>314</b> is removed.
0065In one embodiment, tray <b>314</b> is made from a material, such as Kovar®, having the same coefficient of thermal expansion (CTE) as silicon. In one embodiment, tray <b>314</b> has an accurately machined recess/cavity feature such as a tapered hole for each lens assembly position.
0066In one embodiment, tray <b>314</b> is used as an alignment tool for aligning each lens assembly with its corresponding image sensing device. In one form of this embodiment, tray <b>314</b> has fiducial marks suitable for optical alignment with features on the semiconductor wafer <b>101</b>. Alignment can be achieved using automated vision systems or manual alignment. In one embodiment, where it is impractical to create fiducial marks especially for alignment purposes, existing features on the wafer <b>101</b> are used as fiducial marks. A portion of the lithographic pattern of the active area of an IC <b>104</b> can be as a sufficiently distinct feature for alignment. Since the repeated lithographic pattern of each IC <b>104</b> often extends past the edge of the wafer, incomplete and unusable IC patterns are formed at the wafer edge. In one embodiment, these partial IC sites are used for fiducial points without sacrificing a potentially good IC. In one embodiment, mating fiducial marks in the tray <b>314</b> are formed in a transparent portion of tray <b>314</b>. For example, a lens recess in tray <b>314</b> corresponding to the position of a partial IC site is used for the window instead of a lens.
0067Depth of focus is balanced against field of view in alignment optics. Higher resolution alignment is possible with a larger field of view but with a shallow depth of focus. In one embodiment, the fiducial marks of tray <b>314</b> and of the semiconductor wafer <b>101</b> are located as close to the same plane as possible during alignment in order to reduce the depth of focus required in the alignment optical system. In one embodiment of an optical system, a depth of focus of 0.5 mm is used to provide good alignment resolution (<5 microns).
0068In another embodiment, an alignment method is employed that is based on silicon's transparency in the infrared wavelengths. In this embodiment, IR wavelengths are used in the optical alignment system to align the wafer <b>101</b> and tray <b>314</b> by viewing the fiducial marks through the wafer from behind.
0069In one embodiment of a manufacturing process for camera module <b>300</b>, after singulation, the individual camera modules are kept in the tray <b>314</b> for further manufacturing and testing processes. In an alternative embodiment, tray <b>314</b> is diced up together with the wafer-level packaged array of camera modules <b>300</b>.
0070In one embodiment, lens assembly <b>310</b> is a hybrid of the contiguous lens assembly array of <figref idref="DRAWINGS">FIG. 5B</figref> and the array of individual lens assemblies <b>302</b> of <figref idref="DRAWINGS">FIG. 5C</figref>. The hybrid lens array <b>310</b> is a molded array of individual lens assemblies <b>302</b> that are compliantly-interconnected such that compliant connecting elements extend between adjacent lens assemblies. The compliant connecting elements interconnect all the lens assemblies to be mounted on the semiconductor wafer <b>101</b> to form an array of lens assemblies that can be handled as a single entity. This greatly increases the convenience of handling the lens assemblies during wafer level packaging. The compliant interconnecting elements permit the lens assemblies to move easily in the plane in which the lens assemblies are arrayed to allow for aligning the assemblies with their corresponding image sensing devices. In one embodiment, the aligning is achieved using a lens assembly spacer tray <b>314</b>.
0071<figref idref="DRAWINGS">FIG. 6</figref> illustrates a camera module <b>400</b> that is a variation of camera module <b>300</b>. Camera module <b>400</b> includes an imaging module <b>402</b> that is similar to imaging module <b>100</b>, except that imaging module <b>402</b> does not include the cavity <b>120</b> of imaging module <b>100</b>. In one embodiment of imaging module <b>402</b>, transparent enclosure portion <b>116</b> is assembled over the image sensing device <b>107</b>, and any gaps therebetween are filled with a transparent encapsulant having an index of refraction similar to that of transparent enclosure portion <b>116</b>.
0072Another variation of camera module <b>300</b> is illustrated in <figref idref="DRAWINGS">FIG. 7</figref> and indicated at <b>500</b>. In camera module <b>500</b>, lens assembly <b>302</b> is situated between semiconductor substrate <b>102</b> and transparent enclosure portion <b>116</b>, which includes IR filter <b>118</b>. In one embodiment, spacing structure <b>122</b> is situated between lens assembly <b>302</b> and semiconductor substrate <b>102</b>. As with the embodiments presented above, spacing structure <b>122</b> is configurable during fabrication of camera module <b>500</b> to achieve a proper focus of lens <b>304</b>.
0073According to one aspect of the present invention, an integrally packaged camera module employing a dual-lens system is presented. <figref idref="DRAWINGS">FIG. 8</figref> illustrates one such embodiment, indicated at <b>600</b>. Camera module <b>600</b> includes imaging module <b>100</b>, over which are mounted inner lens assembly <b>302</b><i>i </i>and outer lens assembly <b>302</b><i>o</i>. The mounting points are defined, respectively, by inner adhesive layer <b>306</b><i>i</i>, and outer adhesive layer <b>306</b><i>o</i>. Outer lens assembly <b>302</b><i>o </i>includes outer lens <b>304</b><i>o </i>adapted and positioned to direct an image onto image sensing device <b>107</b> through inner lens <b>304</b><i>i </i>of inner lens assembly <b>302</b><i>i</i>. Outer lens assembly <b>302</b><i>o </i>and inner lens assembly <b>302</b><i>i </i>each include, respectively, outer lens spacing structure <b>303</b><i>o </i>and inner lens spacing structure <b>303</b><i>i</i>. In one embodiment, both of the lens spacing structures <b>303</b><i>o </i>and <b>303</b><i>i </i>are configurable in the assembly process of camera module <b>600</b> to achieve a proper focus for the camera module <b>600</b>. In one embodiment, the spacing distance provided by outer lens spacing structure <b>303</b><i>o </i>is adjusted by grinding back the material, but the inner lens spacing structure <b>303</b><i>i </i>is not adjusted in this manner. Instead, spacing structure <b>122</b> is adjusted to position the inner lens <b>304</b><i>i. </i>
0074In one embodiment, inner lens <b>304</b><i>i </i>is formed from low-cost transparent plastic that does not need to be capable of withstanding re-flow soldering process temperatures. In this embodiment, the outer lens assembly <b>302</b><i>o </i>is formed from glass or high-temperature plastic material capable of withstanding the re-flow soldering processing temperatures. Therefore, the outer lens assembly <b>302</b><i>o </i>protects the inner lens <b>304</b><i>i </i>from the high temperatures.
0075Another embodiment of a dual lens camera module is illustrated in <figref idref="DRAWINGS">FIG. 9</figref> and indicated at <b>650</b>. Camera module <b>650</b> includes an inner lens assembly <b>302</b><i>i </i>having inner lens <b>304</b><i>i </i>suspended over imaging module <b>100</b> by spacing structure <b>303</b><i>i</i>. Camera module <b>650</b> also includes an outer lens support indicated at <b>352</b>. Outer lens support <b>353</b> is adapted to couple with an outermost lens <b>354</b>. In one embodiment, lens <b>354</b> is not fabricated as part of wafer level packaged camera module <b>650</b>. Instead, lens <b>354</b> is installed into lens support <b>352</b> in a separate assembly step.
0076Although specific embodiments have been illustrated and described herein for purposes of description of the preferred embodiment, it will be appreciated by those of ordinary skill in the art that a wide variety of alternate and/or equivalent implementations calculated to achieve the same purposes may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. Those with skill in the mechanical, electro-mechanical, electrical, materials, and optical arts will readily appreciate that the present invention may be implemented in a very wide variety of embodiments. This application is intended to cover any adaptations or variations of the preferred embodiments discussed herein. Therefore, it is manifestly intended that this invention be limited only by the claims and the equivalents thereof.
Contents5
19 sheets
Sheet 1 Sheet 2 Sheet 3 Sheet 4 Sheet 5 Sheet 6 Sheet 7 Sheet 8 Sheet 9 Sheet 10 Sheet 11 Sheet 12 Sheet 13 Sheet 14 Sheet 15 Sheet 16 Sheet 17 Sheet 18 Sheet 19
Every citation, both ways
| Document | Relation | Office | Cited during |
|---|---|---|---|
| WO2013079705A1 | Cited by | World Intellectual Property Organization (WIPO) | Applicant |
| KR20190133235A | Cited by | Republic of Korea | Search report |
| US8848301B2 | Cited by | United States of America | Applicant |
| US11619772B2 | Cited by | United States of America | Applicant |
| CN103229084A | Cited by | China | Search report |
| US2023282661A1 | Cited by | United States of America | Search report |
| CN106024821A | Cited by | China | Search report |
| US8410577B2 | Cited by | United States of America | Applicant |
| JP2010517432A | Cited by | Japan | Examiner |
| EP3226540A3 | Cited by | European Patent Office (EPO) | Search report |
| EP1798769A2 | Cited by | European Patent Office (EPO) | Search report |
| US2021199931A1 | Cited by | United States of America | Search report |
| US8822258B2 | Cited by | United States of America | Search report |
| WO2010074743A1 | Cited by | World Intellectual Property Organization (WIPO) | International search |
| WO2012022000A1 | Cited by | World Intellectual Property Organization (WIPO) | International search |
| US2017133240A1 | Cited by | United States of America | Pre-grant |
| US8524521B2 | Cited by | United States of America | Search report |
| US7723741B2 | Cited by | United States of America | Search report |
| US2012188629A1 | Cited by | United States of America | Pre-grant |
| US2005275746A1 | Cited by | United States of America | Pre-grant |
| US2009213262A1 | Cited by | United States of America | Pre-grant |
| US10134794B2 | Cited by | United States of America | Applicant |
| US7262412B2 | Cited by | United States of America | Search report |
| TWI495919B | Cited by | Taiwan Province of China | Examiner |
| US11394861B2 | Cited by | United States of America | Applicant |
| US2016322312A1 | Cited by | United States of America | Pre-grant |
| US8456560B2 | Cited by | United States of America | Search report |
| US2011037886A1 | Cited by | United States of America | Pre-grant |
| US9634053B2 | Cited by | United States of America | Search report |
| US11605659B2 | Cited by | United States of America | Applicant |
| US2017110641A1 | Cited by | United States of America | Pre-grant |
| US2016066774A1 | Cited by | United States of America | Search report |
| US9972584B2 | Cited by | United States of America | Search report |
| US2011012220A1 | Cited by | United States of America | Pre-grant |
| US11742255B2 | Cited by | United States of America | Search report |
| US9606016B2 | Cited by | United States of America | Applicant |
| US2009294639A1 | Cited by | United States of America | Pre-grant |
| US2010053423A1 | Cited by | United States of America | Pre-grant |
| US11048028B2 | Cited by | United States of America | Search report |
| US8730369B2 | Cited by | United States of America | Search report |
| KR20130108297A | Cited by | Republic of Korea | Search report |
| US9467606B2 | Cited by | United States of America | Search report |
| KR20120087154A | Cited by | Republic of Korea | Search report |
| US2007145420A1 | Cited by | United States of America | Pre-grant |
| US2007145590A1 | Cited by | United States of America | Pre-grant |
| EP4047920A1 | Cited by | European Patent Office (EPO) | Search report |
| US11094727B2 | Cited by | United States of America | Search report |
| US2009026610A1 | Cited by | United States of America | Pre-grant |
| US2013242182A1 | Cited by | United States of America | Pre-grant |
| US10868061B2 | Cited by | United States of America | Search report |
| US10677656B2 | Cited by | United States of America | Applicant |
| US8106979B2 | Cited by | United States of America | Search report |
| US8885257B2 | Cited by | United States of America | Applicant |
| US2016066774A1 | Cited by | United States of America | Search report |
| WO2010091053A1 | Cited by | World Intellectual Property Organization (WIPO) | International search |
| US2008180566A1 | Cited by | United States of America | Pre-grant |
| CN102356463A | Cited by | China | Search report |
| EP3668078A4 | Cited by | European Patent Office (EPO) | Search report |
| US12100720B2 | Cited by | United States of America | Applicant |
| US2021225726A1 | Cited by | United States of America | Search report |
| US11764239B2 | Cited by | United States of America | Applicant |
| US2005275750A1 | Cited by | United States of America | Pre-grant |
| US10147750B2 | Cited by | United States of America | Applicant |
| EP1765002A3 | Cited by | European Patent Office (EPO) | Search report |
| US2011181854A1 | Cited by | United States of America | Pre-grant |
| US2009002532A1 | Cited by | United States of America | Pre-grant |
| US9118825B2 | Cited by | United States of America | Search report |
| US9826132B2 | Cited by | United States of America | Search report |
| JP2013535708A | Cited by | Japan | Examiner |
| US11329083B2 | Cited by | United States of America | Search report |
| US7633133B2 | Cited by | United States of America | Applicant |
| US9419032B2 | Cited by | United States of America | Search report |
| US2007236591A1 | Cited by | United States of America | Pre-grant |
| WO2011049635A1 | Cited by | World Intellectual Property Organization (WIPO) | International search |
| US2009050946A1 | Cited by | United States of America | Pre-grant |
| US9237264B2 | Cited by | United States of America | Search report |
| US7944015B2 | Cited by | United States of America | Applicant |
| US11709348B2 | Cited by | United States of America | Search report |
| US2008043134A1 | Cited by | United States of America | Pre-grant |
| US2008258258A1 | Cited by | United States of America | Pre-grant |
| US2005146018A1 | Cited by | United States of America | Pre-grant |
| US7663221B2 | Cited by | United States of America | Search report |
| US9177905B2 | Cited by | United States of America | Search report |
| CN107039469A | Cited by | China | Search report |
| US2020052020A1 | Cited by | United States of America | Search report |
| US2014084458A1 | Cited by | United States of America | Pre-grant |
| US7375331B2 | Cited by | United States of America | Applicant |
| EP1798769A3 | Cited by | European Patent Office (EPO) | Search report |
| EP1765002A2 | Cited by | European Patent Office (EPO) | Search report |
| EP1890479A1 | Cited by | European Patent Office (EPO) | Search report |
| US2006234422A1 | Cited by | United States of America | Pre-grant |
| US7986021B2 | Cited by | United States of America | Applicant |
| US2012094066A1 | Cited by | United States of America | Pre-grant |
| US12068344B2 | Cited by | United States of America | Applicant |
| JP2010517432A | Cited by | Japan | Search report |
| US2018348415A1 | Cited by | United States of America | Search report |
| US2007152139A1 | Cited by | United States of America | Pre-grant |
| US2007262407A1 | Cited by | United States of America | Pre-grant |
| US2006124831A1 | Cited by | United States of America | Pre-grant |
| US2006044450A1 | Cites | United States of America | Pre-grant |
2 members in 1 office; this record represents the family
Members2
| Document | Office | Kind | |
|---|---|---|---|
| US2005077458A1 | United States of America | A1 | |
| US7329861B2 | United States of America | B2 |
64 transactions on the USPTO file
Allowed after 3 non-final rejections, 2 final rejections and 2 RCEs.
- Non-final rejections
- 3
- Final rejections
- 2
- RCEs
- 2
- Appeals
- 0
Over time
Point at a mark for the transactionTransactions
| Event | Code | |
|---|---|---|
| Payment of Maintenance Fee, 12th Year, Large EntityM1553 | M1553 | |
| Recordation of Patent Grant MailedPGM/ | PGM/ | |
| Patent Issue Date Used in PTA CalculationAllowedPTAC | PTAC | |
| Issue Notification MailedAllowedWPIR | WPIR | |
| Dispatch to FDCD1935 | D1935 | |
| Application Is Considered Ready for IssuePILS | PILS | |
| Issue Fee Payment VerifiedN084 | N084 | |
| Issue Fee Payment ReceivedIFEE | IFEE | |
| Correspondence Address ChangeC.AD | C.AD | |
| Electronic ReviewELC_RVW | ELC_RVW | |
| Email NotificationEML_NTF | EML_NTF | |
| Mail Notice of AllowanceAllowedMN/=. | MN/=. | |
| Notice of Allowance Data Verification CompletedAllowedN/=. | N/=. | |
| Date Forwarded to ExaminerFWDX | FWDX | |
| Response after Non-Final ActionA... | A... | |
| Mail Non-Final RejectionNon-final rejectionMCTNF | MCTNF | |
| Non-Final RejectionNon-final rejectionCTNF | CTNF | |
| Date Forwarded to ExaminerFWDX | FWDX | |
| Disposal for a RCE / CPA / R129AbandonedABN9 | ABN9 | |
| Request for Continued Examination (RCE)RCEX | RCEX | |
| Workflow - Request for RCE - BeginBRCE | BRCE | |
| Mail Advisory Action (PTOL - 303)MCTAV | MCTAV | |
| Advisory Action (PTOL-303)CTAV | CTAV | |
| Date Forwarded to ExaminerFWDX | FWDX | |
| Response after Final ActionA.NE | A.NE | |
| Mail Final Rejection (PTOL - 326)Final rejectionMCTFR | MCTFR | |
| Final RejectionFinal rejectionCTFR | CTFR | |
| Date Forwarded to ExaminerFWDX | FWDX | |
| Response after Non-Final ActionA... | A... | |
| Mail Non-Final RejectionNon-final rejectionMCTNF | MCTNF | |
| Non-Final RejectionNon-final rejectionCTNF | CTNF | |
| Date Forwarded to ExaminerFWDX | FWDX | |
| Date Forwarded to ExaminerFWDX | FWDX | |
| Disposal for a RCE / CPA / R129AbandonedABN9 | ABN9 | |
| Case Docketed to Examiner in GAUDOCK | DOCK | |
| Request for Continued Examination (RCE)RCEX | RCEX | |
| Workflow - Request for RCE - BeginBRCE | BRCE | |
| Mail Advisory Action (PTOL - 303)MCTAV | MCTAV | |
| Advisory Action (PTOL-303)CTAV | CTAV | |
| Date Forwarded to ExaminerFWDX | FWDX | |
| Response after Final ActionA.NE | A.NE | |
| Mail Final Rejection (PTOL - 326)Final rejectionMCTFR | MCTFR | |
| Final RejectionFinal rejectionCTFR | CTFR | |
| Date Forwarded to ExaminerFWDX | FWDX | |
| Response after Non-Final ActionA... | A... | |
| Correspondence Address ChangeC.ADB | C.ADB | |
| Mail Non-Final RejectionNon-final rejectionMCTNF | MCTNF | |
| Non-Final RejectionNon-final rejectionCTNF | CTNF | |
| Case Docketed to Examiner in GAUDOCK | DOCK | |
| IFW TSS Processing by Tech Center CompleteTSSCOMP | TSSCOMP | |
| Case Docketed to Examiner in GAUDOCK | DOCK | |
| Transfer Inquiry to GAUTI1050 | TI1050 | |
| Transfer Inquiry to GAUTI1050 | TI1050 | |
| Application Is Now CompleteCOMP | COMP | |
| Application Return from OIPEWROIPE | WROIPE | |
| Application Return TO OIPEROIPE | ROIPE | |
| Application Dispatched from OIPEOIPE | OIPE | |
| Cleared by OIPE CSRL194 | L194 | |
| IFW Scan & PACR Auto Security ReviewSCAN | SCAN | |
| Information Disclosure Statement consideredIDSC | IDSC | |
| Reference capture on IDSRCAP | RCAP | |
| Information Disclosure Statement (IDS) FiledM844 | M844 | |
| Information Disclosure Statement (IDS) FiledWIDS | WIDS | |
| Initial Exam Team nnIEXX | IEXX |
21 legal events, as the office reported them to INPADOC
Over the term
Point at a mark for the eventEvents
| Event | Code | |
|---|---|---|
| Maintenance fee paymentMAFP | MAFP | |
| AssignmentAS | AS | |
| AssignmentAS | AS | |
| Fee paymentFPAY | FPAY | |
| Fee paymentFPAY | FPAY | |
| AssignmentAS | AS | |
| AssignmentAS | AS | |
| AssignmentAS | AS | |
| Information on status: patent grantGrantedPATENTED CASESTCF | STCF | |
| Fee payment procedurePAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITYFEPP | FEPP | |
| AssignmentAS | AS | |
| AssignmentAS | AS | |
| Not any more in us assignment databaseCORRECTED COVER SHEET TO ADD PORTION OF THE PAGE THAT WAS PREVIOUSLY OMITTED FROM THE NOTICE AT REEL/FRAME 018757/0183 (ASSIGNMENT OF ASSIGNOR'S INTEREST);ASSIGNOR:AVAGO TECHNOLOGIES IMAGING HOLDING CORPORATION;REEL/FRAME:019028/0237XAS | XAS | |
| AssignmentAS | AS | |
| AssignmentAS | AS | |
| AssignmentAS | AS | |
| AssignmentAS | AS | |
| AssignmentAS | AS | |
| AssignmentAS | AS | |
| AssignmentAS | AS | |
| AssignmentAS | AS |
Numbers
- Publication
- 20050077458
- Application
- 10684619
Titles
- English
- Integrally packaged imaging module
Patent term adjustment
- A delay
- +322 daysthe office missed an examination deadline
- Applicant delay
- −2 days
- Net adjustment
- 320 days
Classification
- CPC, 11
- H04N23/57
- H10F39/804
- H04N23/55
- H10F39/806
- H10F77/407
- H10W72/20
- H10W70/656
- H10W72/923
- H10W72/9223
- H10W72/942
- H10W72/922
- IPC, 2
- H01L31 0232
- H04N5 225