Active polyphase inverter filter for quadrature signal generation
Claim Score by NHIP
Abstract
A quadrature signal generator receives a differential input signal and generates quadrature output signals that are 90 degrees out-of-phase with each other. The quadrature generator includes a coarse stage and a plurality of refinement stages. The coarse stage generates quadrature signals that may have some phase error, and the refinement stages process the quadrature signals to reduce any phase error. The refinement stages receive quadrature signals from the output of the coarse stage, and processes the quadrature signals to reduce the phase errors. The coarse stage and the refinement stages are configured using delay circuits that can be implemented with inverter circuits, such as, for example, CMOS inverter circuits. In the refinement stages, corresponding outputs of the delay stages are averaged together to reduce the quadrature phase error.
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22 claims: 6 independent, 16 dependent
- 1Broadest claimClaim Score 48, average(NHIP)A quadrature signal generator, comprising:a coarse stage for generating output signals that have substantially a quadrature phase relationship, said coarse stage having at least one 90/180 delay circuit having a first set of inverters and a second set of inverters, said second set of inverters having an approximate delay of 90 degrees relative to said first set of inverters;and at least one refinement stage for refining said quadrature phase relationship of said output signals from said coarse stage, said refinement stage having at least one 0/180 delay circuit, said 0/180 delay circuit having a third series of inverters and a fourth series of inverters, said fourth series of inverters having an approximate delay of 180 degrees relative to said third series of inverters.
- 5A quadrature signal generator, comprising:a coarse stage capable of generating quadrature output signals that have substantially a 90-degree phase relationship based on a differential input signal;and at least one refinement stage for refining said 90 degree phase relationship of said output signals from said coarse stage, said refinement stage having, a plurality of 0/180 delay circuits each receiving a corresponding quadrature output signal and having a 0-degree output and a 180-degree output, wherein a 0-degree output of a first 0/180 delay circuit is coupled to a 180 degree output of a second 0/180 delay circuit, and a plurality of 90/180 delay circuits having inputs coupled to corresponding 0-degree outputs of said plurality of 0/180 delay circuits, wherein a 90-degree output of a first 90/180 delay circuit is coupled to a 180 degree output of a second 90/180 delay circuit.
- 14A quadrature signal generator, comprising:a coarse stage capable generating quadrature output signals that have substantially a 90 degree phase relationship;and at least one refinement stage for refining said 90 degree phase relationship of said output signals, said at least one refinement stage including, a first 0/180 delay circuit having an input that receives a first output signal of said quadrature output signals, and having a 0 degree output and an 180 degree output, a second 0/180 delay circuit having an input that receives a second output signal of said quadrature output signals, and having a 0 degree output and an 180 degree output, a third 0/180 delay circuit having an input that receives a third output signal of said quadrature output signals, and having a 0 degree output and an 180 degree output, a fourth 0/180 delay circuit having an input that receives a fourth output signal of said quadrature output signals, and having a 0 degree output and an 180 degree output, a first 90/180 delay circuit having an input coupled to said 0 degree output of said first 0/180 delay circuit, and having a 90 degree output and a 180 degree output, a second 90/180 delay circuit having an input coupled to said 0 degree output of said second 0/180 delay circuit, and having a 90 degree output and a 180 degree output, a third 90/180 delay circuit having an input coupled to said 0 degree output of said third 0/180 delay circuit, and having a 90 degree output and a 180 degree output, a fourth 90/180 delay circuit having an input coupled to said 0 degree output of said fourth 0/180 delay circuit, and having a 90 degree output and a 180 degree output, wherein said 0 degree output of said first 0/180 delay circuit is coupled to said 180 degree output of said third 0/180 delay circuit, wherein said 180 degree output of said first 0/180 delay circuit is coupled to a 0 degree output of said third 0/180 delay circuit, wherein said 0 degree output of said second 0/180 delay circuit is coupled to said 180 output of said fourth 0/180 delay circuit, wherein a 180 degree output of said second 0/180 delay circuit is coupled to a 0 degree output of said fourth 0/180 delay circuit, wherein said 90 degree output of said first 90/180 delay circuit is coupled to said 180 degree output of said fourth 0/180 delay circuit, wherein said 180 degree output of said first 90/180 delay circuit is coupled to said 90 degree output of said second 90/180 delay circuit, wherein a 180 degree output of said second 90/180 delay circuit is coupled to said 90 degree output of said third 0/180 delay circuit, and wherein a 180 degree output of said third 90/180 delay circuit is coupled to said 90 degree output of said fourth 0/180 delay circuit.
- 15A quadrature signal generator, comprising:a coarse stage capable of generating quadrature output signals that have substantially a 90-degree phase relationship based on a differential input signal;and at least one refinement stage for refining said quadrature phase relationship of said output signals from said coarse stage, said refinement stage having, a plurality of 0/180 delay circuits each receiving a corresponding quadrature output signal and having a O-degree output and a 180-degree output, wherein a 0-degree output of a first 0/180 delay circuit is averaged with a 180 degree output of a second 0/180 delay circuit, said first 0/180 delay circuit and said second 0/180 delay circuit separated by a third 0/180 delay circuit, a plurality of 90/180 delay circuits having inputs coupled to corresponding 0-degree outputs of said plurality of 0/180 delay circuits, wherein a 90-degree output of a first 90/180 delay circuit is averaged with a 180 degree output of a second 90/180 delay circuit, said first 90/180 delay circuit adjacent to said second 90/180 delay circuit.
- 16A method of quadrature signal generation, comprising:receiving a differential input signal;delaying first and second components of said differential input signal to produce a first set of quadrature signals;and refining said first set of quadrature signals to reduce phase errors, including generating second and third sets of quadrature signals based on said first set of quadrature signals, said second set of quadrature signals substantially in-phase with said first set of quadrature signals, said third set of quadrature signals substantially delayed by 180 degrees relative to said first set of quadrature signals, averaging said second set of quadrature signals with corresponding signals in said third set of quadrature signals, so as to produce a fourth set of quadrature signals, generating fifth and six sets of quadrature signals based on said fourth set of quadrature signals, said fifth set of quadrature signals delayed by approximately 90 degrees relative to said fourth set of quadrature signals, and said six set of quadrature signals delayed by approximately 180 degrees relative to said first set of quadrature signals, averaging said fifth set of quadrature signals with corresponding signals in said six set of quadrature signals, so as to produce a seventh set of quadrature signals, whereby said seventh set of quadrature signals has less phase error than said first set of quadrature signals.
- 22A quadrature signal generator, comprising:a differential input having a first and second terminals;a coarse stage including a first 90/180 delay circuit coupled to said first terminal of said differential input, and a second 90/180 degree delay circuit coupled to said second terminal of said differential input;and a refinement stage coupled to an output of said coarse stage including, a plurality of 0/180 delay circuits having inputs coupled to corresponding outputs of said first and second 90/180 delay circuits, each 0/180 delay circuit having a 0 degree output and a 180 degree output, said 0 degree output of each delay circuit connected with said 180 degree output of another 0/180 delay circuit that is substantially in-phase with said 0 degree output, and a plurality of 90/180 delay circuits having inputs coupled to corresponding outputs of said 0/180 delay circuits, each 90/180 degree delay circuit having a 90 degree output and a 180 degree output, said 90 degree output of each delay circuit connected with said 180 degree output of another 0/180 delay circuit that is substantially in-phase with said 90 degree output.
Independent claims6
156 paragraphs in 4 sections, as filed
[0001] The present application claims the benefit of U.S. Provisional Patent Application No. 60/386,484, filed on Jun. 7, 2002, which is incorporated herein by reference in its entirety.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention generally relates to signal generation, and more specifically to quadrature signal generation using an active polyphase inverter filter.
[0004] 2. Background Art
[0005] In electronic communications, it is often useful to send and receive information using two or more signals that have a quadrature relationship. For instance, one information signal is designated the in-phase signal (I), and the other information signal is designated the quadrature signal (Q), where the Q signal is 90 degrees out of phase with the I signal. More specifically, the Q signal is delayed (or advanced) relative to the I signal (in-time) by 90 degrees.
[0006] Quadrature amplitude modulation (QAM) and quadrature phase shift keying (QPSK) are two well known specific examples of quadrature modulation.
[0007] The advantage of the quadrature signal transmission is that the bandwidth of a transmission medium is effectively doubled. In other words, if a particular transmission medium has a bandwidth of B (Hz), then quadrature modulation permits 2B (Hz) of information to be effectively transmitted through the medium without signal interference. This occurs because the I and Q signals occupy the transmission medium simultaneously, but are phase shifted with respect to each. At the receiver, the I and Q information can be discerned from each other by sampling the I and Q signals at the proper time based on the known 90 degree phase delay. However, the I and Q sampling times must be properly timed. Any error in sampling time will cause signal distortion and/or interference between the I and Q channels.
[0008] What is needed is a circuit and method to generate control signals that have precise timing to control sampling of I and Q signals. Furthermore, the circuit that generates the control signals should be able to be integrated on an integrated circuit.
BRIEF SUMMARY OF THE INVENTION
[0009] The present invention is related to a quadrature signal generator that receives a differential input signal and generates quadrature output signals that are 90 degrees out-of-phase with each other. The quadrature signal generator is an open-loop architecture that utilizes active inverters for delay elements. The invention is also related to subcomponents and methods related to the same.
[0010] The quadrature signal generator includes a coarse stage and a plurality of refinement stages. The coarse stage receives a differential input signal and generates a plurality of quadrature signals that are substantially phase-shifted by 90 degrees with respect to each other, but which may have some phase errors. The refinement stages receive quadrature signals from the output of the coarse stage, and process the quadrature signals to reduce the phase error between the quadrature signals. Any number of refinement stages can be utilized. The greater the number of refinement stages, the more the phase error is reduced, but subject to a point of diminishing returns.
[0011] Each coarse stage includes a pair of 90/180 delay circuits that delay the differential signal, and generate quadrature output signals that may have some phase error.
[0012] Each refinement stage includes a plurality of 0/180 delay circuits that each receive a corresponding quadrature output signal from the coarse stage generator, and have a 0-degree output and a 180-degree output. The 0-degree output of a first 0/180 delay circuit is averaged with a 180 degree output of a second 0/180 delay circuit. Likewise, a 0-degree output of a third 0/180 delay circuit is averaged with a 180 degree output of a fourth 0/180 delay circuit. The averaging of the delay circuit outputs has the effect of reducing the phase error. Furthermore, the refinement stage also includes a plurality of 90/180 delay circuits having inputs coupled to corresponding 0-degree outputs of the 0/180 delay circuits. The 90-degree output of a first 90/180 delay circuit is averaged with a 180 degree output of a second 90/180 delay circuit. Likewise, the 90-degree output of a third 90/180 delay circuit is coupled to a 180 degree output of a fourth 90/180 delay circuit.
[0013] Each delay circuit 0/180 includes a first series of inverters and a second series of inverters, where the second series of inverters has an approximate total delay of 180 degrees relative to said first series of inverters. Each delay circuit 90/180 includes a third series of inverters and a fourth series of inverters, where the fourth series of inverters has a delay of 90 degrees relative the third series of inverters.
[0014] An advantage of the quadrature generator described herein is that it is an open loop architecture that is not prone to oscillation because there is no feedback signal to cause an unwanted oscillation. Whereas, the conventional closed-loop architectures utilize at least one feedback signal that can result in unwanted signal oscillation. Furthermore, the delay circuits are implemented using active inverter circuits, which can be implemented in standard semiconductor processes, such as CMOS. CMOS inverters on a common substrate have similar semiconductor characteristics that are repeatable from inverter-to-inverter, which improves the phase accuracy of the quadrature output signals. Furthermore, CMOS inverters are more area efficient than passive capacitors and passive resistors. Therefore, the entire quadrature generator is more area efficient than a conventional phase generator, which increases overall chip-yield.
[0015] Further features and advantages of the invention, as well as the structure and operation of various embodiments of the invention, are described in detail below with reference to the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS/FIGURES
[0016] The present invention is described with reference to the accompanying drawings. In the drawings, like reference numbers indicate identical or functionally similar elements. Additionally, the left-most digit(s) of a reference number identifies the drawing in which the reference number first appears.
[0017]FIG. 1 illustrates an example IQ transmitter <b>100</b> configured to transmit complex I Q waveforms in a balanced manner using quadrature control signals.
[0018]FIG. 2A illustrates an exemplary frequency spectrum for an I harmonically rich signal.
[0019]FIG. 2B illustrates an exemplary frequency spectrum for a Q harmonically rich signal.
[0020]FIG. 2C illustrates an exemplary frequency spectrum for an IQ harmonically rich signal, where a single IQ harmonic is selected from a number of IQ harmonics.
[0021]FIG. 3 illustrates the function of an exemplary generic phase generator.
[0022]FIG. 4 illustrates the function of an exemplary quadrature phase generator.
[0023]FIG. 5 illustrates a conventional polyphase filter configured using passive resistors and capacitors.
[0024]FIG. 6 illustrates a quadrature phase generator according to embodiments of the present invention.
[0025]FIG. 7 illustrates a coarse stage according to embodiments of the present invention.
[0026]FIG. 8 illustrates a refinement stage according to embodiments of the present invention.
[0027]FIG. 9 illustrates 0/180 delay circuit according to embodiments of the present invention.
[0028]FIG. 10 illustrates 90/180 delay circuit according to embodiments of the present invention.
[0029]FIG. 11 illustrates a flowchart related to the quadrature generator according to embodiments of the present invention.
[0030]FIG. 12 illustrates the functional operation of refinement stages according to embodiments of the present invention.
[0031] FIGS. <b>13</b>A-<b>13</b>D illustrate the effect of averaging inverter outputs together according to embodiments of the present invention.
[0032]FIG. 14 illustrates an operational flowchart for the refinement stages according to embodiments of the present invention.
[0033]FIG. 15 illustrates pulsed signals according to embodiments of the present invention.
[0034]FIG. 16 illustrates an example LO generation circuit that generates quadrature pulsed control signals based on a differential input signal.
[0035]FIG. 17 illustrates phase error verses FET area for a representative 815 MHz application.
[0036]FIG. 18 illustrates a flowchart related to coarse quadrature signal generation according to embodiments of the present invention.
DETAILED DESCRIPTION OF THE INVENTION
[0037] 1. Example Transmitter Application
[0038] Before describing the invention in detail, it is useful to describe an example transmitter environment for the invention. The polyphase filter invention is not limited to the transmitter environment that is described here, as the polyphase filter invention is applicable to other transmitter and non-transmitter applications as will be understood to those skilled in the relevant arts based on the discussions given herein.
[0039]FIG. 1 illustrates an IQ transmitter <b>100</b> that is useful for transmitting complex I Q waveforms and does so in a balanced manner to control DC offset and carrier insertion. The IQ transmitter <b>100</b> includes an IQ balanced modulator <b>102</b>, an optional filter <b>104</b>, and an optional amplifier <b>106</b>. In doing so, the modulator <b>102</b> receives an I baseband signal <b>110</b> and a Q baseband signal <b>112</b> and up-converts these signals to generate a combined harmonically rich signal <b>103</b>. The harmonically rich signal <b>103</b> includes multiple harmonics images, where each image contains the baseband information in the I signal <b>110</b> and the Q signal <b>112</b>. The optional bandpass filter <b>104</b> may be included to select a harmonic of interest (or subset of harmonics) from the signal <b>103</b> for transmission. The optional amplifier <b>106</b> may be included to amplify the selected harmonic prior to transmission, to generate the IQ output signal <b>107</b>.
[0040] As stated above, the balanced IQ modulator <b>102</b> up-converts the I baseband signal <b>110</b> and the Q baseband signal <b>112</b> in a balanced manner to generate the combined harmonically rich signal <b>103</b> that carriers the I and Q baseband information. To do so, the modulator <b>102</b> utilizes two balanced modulators <b>114</b><i>a </i>and <b>114</b><i>b </i>that have a common output node <b>138</b>. The balanced modulator <b>114</b><i>a </i>receives the I baseband signal <b>110</b> and shunts the baseband signal <b>110</b> to ground in a differential and balanced fashion to generate a harmonically rich signal <b>136</b><i>a</i>. The harmonically rich signal <b>136</b><i>a </i>includes multiple harmonic images, where each image contains the baseband information in the baseband signal <b>110</b>. In other words, each harmonic image includes the necessary amplitude, frequency, and phase information to reconstruct the baseband signal <b>110</b>. Similarly, the balanced modulator <b>114</b><i>b </i>receives the Q baseband signal <b>112</b> and shunts the baseband signal <b>112</b> to ground in a differential and balanced fashion to generate a harmonically rich signal <b>136</b><i>b</i>. The harmonically rich signal <b>136</b><i>b </i>includes multiple harmonic images, where each image contains the baseband information in the baseband signal <b>112</b>. In other words, each harmonic image includes the necessary amplitude, frequency, and phase information to reconstruct the Q baseband signal <b>112</b>. The harmonically rich signal <b>136</b><i>a </i>and the harmonically rich signal <b>136</b><i>b </i>are then combined at the node <b>138</b> to generate the harmonically rich signal <b>103</b>.
[0041] Each balanced modulator <b>114</b> includes the following components: a buffer/inverter <b>118</b>; optional impedances <b>120</b>, <b>122</b>; controlled switches <b>126</b> and <b>130</b>; blocking capacitors <b>124</b> and <b>132</b>; and a terminal <b>128</b> that is tied to ground. During operation of the modulator <b>114</b><i>a</i>, the buffer/inverter <b>118</b><i>a </i>receives the I baseband signal <b>110</b> and generates I signal <b>119</b> and inverted I signal <b>121</b>. I signal <b>119</b> is substantially similar to the baseband signal <b>110</b>, and the inverted I signal <b>121</b> is an inverted version of signal <b>110</b>. As such, the buffer/inverter <b>118</b> converts the (single-ended) baseband signal <b>110</b> into differential signals <b>119</b> and <b>121</b>. The controlled switch <b>126</b><i>a </i>shunts the I signal <b>119</b><i>a </i>to the terminal <b>128</b><i>a </i>according to the control signal <b>108</b><i>a</i>, and the controlled switch <b>130</b><i>a </i>shunts the inverted I signal <b>121</b><i>a </i>to ground according to the control signal <b>108</b><i>b</i>. The control signals <b>108</b><i>a </i>and <b>108</b><i>b </i>are pulse trains that are 180 degrees out-of-phase so that only one of the switches <b>126</b><i>a </i>or <b>130</b><i>a </i>is closed at any given time. The periodic sampling of the I signal <b>119</b> and the inverted I signal <b>121</b> generates the I harmonically rich signal <b>136</b><i>a</i>. As shown, the terminal <b>128</b><i>a </i>is tied to ground and ties together the switches <b>126</b><i>a </i>and <b>128</b><i>a</i>. This prevents any DC offset voltages from developing between the switches <b>126</b><i>a </i>and <b>130</b><i>a</i>, which can lead to undesired carrier insertion in the harmonically rich signal <b>136</b><i>a. </i>
[0042] In the modulator <b>114</b><i>b</i>, the buffer/inverter <b>118</b><i>b </i>receives the Q baseband signal <b>112</b> and generates Q signal <b>119</b><i>b </i>and inverted Q signal <b>121</b><i>b</i>. Q signal <b>119</b><i>b </i>is substantially similar to the Q baseband signal <b>112</b>, and the inverted Q signal <b>121</b><i>b </i>is an inverted version of signal <b>110</b>. As such, the buffer/inverter <b>118</b><i>b </i>converts the (single-ended) baseband signal <b>112</b> into differential signals <b>119</b><i>b </i>and <b>121</b><i>b</i>. The controlled switch <b>126</b><i>a </i>shunts the I signal <b>119</b><i>b </i>to the ground terminal <b>128</b><i>a </i>according to the control signal <b>108</b><i>c</i>, and the controlled switch <b>130</b><i>b </i>shunts the inverted I signal <b>121</b><i>b </i>to ground terminal <b>128</b><i>b </i>according to the control signal <b>108</b><i>d</i>. The control signals <b>108</b><i>c </i>and <b>108</b><i>d </i>are pulse trains that are 180 degrees out-of-phase so that only one of the switches <b>126</b><i>b </i>or <b>130</b><i>b </i>is closed at any given time. Furthermore, the control signal s <b>108</b><i>c </i>and <b>108</b><i>d </i>are phase shifted by <b>90</b> relative to the control signals <b>108</b><i>a </i>and <b>108</b><i>b</i>. The periodic sampling of the Q signal <b>119</b><i>b </i>and the inverted Q signal <b>121</b><i>b </i>generates the Q harmonically rich signal <b>136</b><i>a</i>. The terminal <b>128</b><i>b </i>is tied to ground and prevents any DC offset voltages from developing between the switches <b>126</b><i>b </i>and <b>130</b><i>b</i>, which can lead to undesired carrier insertion in the harmonically rich signal <b>136</b><i>b. </i>
[0043]FIG. 2A illustrates an exemplary frequency spectrum for the harmonically rich signal <b>136</b><i>a </i>having harmonic images <b>202</b><i>a</i>-<i>n</i>. The images <b>202</b> repeat at harmonics of the sampling frequency 1/T<sub>s</sub>, at infinitum, where each image <b>202</b> contains the necessary amplitude, frequency, and phase information to reconstruct the baseband signal <b>110</b>. Similarly, FIG. 2B illustrates an exemplary frequency spectrum for the harmonically rich signal <b>136</b><i>b </i>having harmonic images <b>204</b><i>a</i>-<i>n</i>. Each image <b>204</b> contains the necessary amplitude, frequency, and phase information to reconstruct the Q baseband signal <b>112</b>. FIG. 2C illustrates an exemplary frequency spectrum for the IQ harmonically rich signal <b>103</b> having images <b>206</b><i>a</i>-<i>n</i>. Each image <b>206</b> carries the I baseband information and the Q baseband information from the corresponding images <b>202</b> and <b>204</b>, respectively, without substantially increasing the frequency bandwidth occupied by each image <b>206</b>.
[0044] As stated above, the control signals <b>108</b><i>a </i>and <b>108</b><i>b </i>are phased by 180 degrees relative to each other. Likewise, the control signals <b>108</b><i>c </i>and <b>108</b><i>d </i>are phase-shifted by 180 degrees relative to each other, and are phase-shifted by 90 degrees relative to the control signals <b>108</b><i>a </i>and <b>108</b><i>b</i>, respectively. As a result the control signals <b>108</b><i>a</i>-<i>d </i>have a relative phase relationship of 0, 180, 90, and 270 degrees, respectively.
[0045] 2. Quadrature Signal Generation
[0046]FIG. 3 illustrates the function of a generalized phase generator <b>304</b>. Phase generator <b>304</b> generates output signals <b>306</b><i>a</i>-<i>d </i>based on input signals <b>302</b><i>a </i>and <b>302</b><i>b</i>. The output signal <b>306</b><i>a </i>is arbitrarily chosen as a reference signal and the output signals <b>306</b><i>b</i>-<b>306</b><i>d </i>are phase-shifted relative to signal <b>306</b><i>a</i>. In other words, the signal <b>406</b><i>b </i>is phase-shifted by φ<sub>1 </sub>degrees relative to signal <b>406</b><i>a</i>, the signal <b>406</b><i>c </i>is phase-shifted by φ<sub>2 </sub>degrees relative to signal <b>406</b><i>a</i>, and signal <b>406</b><i>d </i>is phase shifted by φ<sub>3 </sub>degrees relative to signal <b>406</b><i>c</i>. The phase shift angles φ are arbitrary in FIG. 3 and can be determined as desired.
[0047]FIG. 4 illustrates a quadrature generator <b>404</b> that generates signals <b>406</b><i>a</i>-<i>d </i>based on input signals <b>402</b><i>a</i>-<i>b</i>. Signal <b>306</b><i>a </i>is arbitrarily chosen as a reference signal and signals <b>306</b><i>b</i>-<b>306</b><i>d </i>are phase shifted relative to signal <b>306</b><i>a </i>by increments of 90 degrees. In other words, signal <b>406</b><i>b </i>is phase-shifted by <b>90</b> relative to signal <b>406</b><i>a</i>. Signal <b>406</b><i>c </i>is phase-shifted by 180 degrees relative to signal <b>406</b><i>a</i>. Signal <b>406</b><i>d </i>is phase-shifted 270 degrees relative to signal <b>406</b><i>a. </i>
[0048] The invention is directed to the quasi phase generator <b>304</b> of FIG. 3, and the specific quadrature generator <b>404</b> of FIG. 4.
[0049] 3. Conventional Quadrature Generator
[0050]FIG. 5 illustrates a conventional quadarature generator <b>500</b> that is driven by a source <b>502</b>. Quadrature generator <b>500</b> includes multiple parallel RC circuits <b>504</b>, where each RC circuit <b>504</b> includes a capacitor <b>506</b> and a resistor <b>508</b>. The quadrature generator <b>500</b> receives a sinusoidal signal from the source <b>502</b>, and generates output signals <b>510</b><i>a</i>-<i>d </i>that have approximately a 90 degree phase relationship between the signals. In other words, the output signal <b>510</b><i>b </i>is phase shifted by 90 degrees relative to signal <b>510</b><i>a</i>, signal <b>510</b><i>c </i>is phase-shifted by 180 degrees relative to output signal <b>510</b><i>a</i>, and signal <b>510</b><i>d </i>is phase-shifted by <b>270</b> degrees relative to output signal <b>510</b><i>a. </i>
[0051] As illustrated, the quadrature generator <b>500</b> includes multiple capacitors <b>506</b>. More specifically, the quadrature generator <b>500</b> includes <b>12</b> capacitors <b>506</b>. Capacitors in integrated circuit occupy substrate area that is proportional to the amount of capacitance. Therefore, the <b>12</b> capacitors <b>506</b> occupy significant substrate area, which increases the size and of an individual IC and reduces overall yield.
[0052] 4. Quadrature Generator According to the Present Invention
[0053]FIG. 6 illustrates a quadrature generator <b>600</b> according to embodiments of the present invention. The quadrature generator <b>600</b> receives a differential signal <b>602</b> (having components <b>602</b><i>a </i>and <b>602</b><i>b</i>) and generates output signals <b>608</b><i>a</i>-<i>d </i>that have the desired 90 degree phase relationship between the output signals <b>406</b><i>a</i>-<b>406</b><i>d</i>, with minimal phase error.
[0054] The quadrature generator <b>600</b> includes a coarse stage <b>604</b>, and refinement stages <b>606</b><i>a</i>-<i>n</i>. The coarse stage <b>604</b> generates signals <b>605</b><i>a</i>-<i>d </i>that substantially have the desired quadratrure relationship, but which may not be in exact quadrature with each other. For instance, the signal <b>605</b><i>b </i>can be delayed relative to the signal <b>605</b><i>a </i>by 90 degrees+/− an error (E<sub>1</sub>). Likewise, the signal <b>605</b><i>c </i>can be delayed relative to the signal <b>605</b><i>a </i>by 180 degrees+/− an error (E<sub>2</sub>). Finally, the signal <b>605</b><i>a </i>can be delayed relative to the signal <b>605</b><i>c </i>by 270 degrees+/− an error (E<sub>3</sub>). The mentioned phase errors can result from component and/or process variations, or can result from noise voltage, including thermal noise. The error signals E<sub>1</sub>, E<sub>2</sub>, and E<sub>3 </sub>can be identical or they can be different from each other.
[0055] The refinement stages <b>606</b><i>a </i>receive the signals <b>605</b><i>a</i>-<i>d </i>and refine the quadrature relationship between the signals <b>605</b><i>a</i>-<i>d </i>so as to reduce the phase errors E<sub>1</sub>, E<sub>2</sub>, and E<sub>3</sub>. There can be any number of refinement stages <b>606</b>, and the quadrature accuracy increases with the number of stages <b>606</b>, up to a point. As a result, the output signals <b>608</b><i>a</i>-<i>d </i>have a more accurate quadrature relationship between them. In one embodiment of the invention, the number of refinement stages <b>606</b> is chosen so that the quadrature accuracy is equal to or less than 1 degree between the output signals <b>608</b>. In other words, the signal <b>606</b><i>b </i>is delayed relative to signal <b>606</b><i>a </i>by 90 degrees+/−1 degree, the signal <b>606</b><i>c </i>is delayed relative to the signal <b>606</b><i>a </i>by 180 degree+/−1 degree, and the signal <b>606</b><i>d </i>is delayed relative to the signal <b>606</b><i>a </i>by 270+/−1 degree.
[0056]FIG. 11 illustrates a flowchart <b>1100</b> that further describes the operation of the quadrature generator <b>600</b>, according to embodiments of the present invention.
[0057] Referring to flowchart <b>1100</b>, in step <b>1102</b> a differential signal is received. For example, a differential signal <b>602</b> is received by the quadrature generator <b>600</b> having components <b>602</b><i>a </i>and <b>602</b><i>b </i>that are 180 degrees out-of-phase.
[0058] In step <b>1104</b>, coarse quadrature signals are generated having an approximately 90 degree relationship relative to each and offset by some error. For example, the coarse stage <b>604</b> generates signals <b>605</b><i>a</i>-<i>d </i>that substantially have the desired quadratrure relationship, but have phase errors that offset the respective signals from perfect quadrature.
[0059] In step <b>1106</b>, the coarse quadrature signals are refined to reduce the phase errors between the quadrature signals. For example, the output signals <b>605</b><i>a</i>-<i>d </i>are refined using the refinement stages <b>606</b> to reduce the phase error between the quadrature relationship. Step <b>1104</b> is repeated until the phase error is reduced below some desired threshold. For example, the refinement stages <b>606</b> can be added until the quadrature phase error falls below some threshold, for example +/−1 degree.
[0060] An advantage of the architecture for the quadrature generator <b>600</b> is that it is an open-loop architecture, which relies on component matching to achieve low phase error between signals. An open loop architecture is not prone to oscillation because there is no feedback signal to cause an unwanted oscillation. Whereas, conventional closed-loop architectures utilize at least one feedback signal that can result in unwanted signal oscillation.
[0061]FIG. 7 further illustrates the coarse stage <b>602</b> that generates the coarse quadrature signals <b>605</b><i>a</i>-<i>d</i>. As stated above, the coarse stage <b>602</b> receives differential input signals <b>602</b><i>a </i>and <b>602</b><i>b </i>that are 0 and 180 degrees out-of-phase, and generates quadrature output signals <b>605</b><i>a</i>-<i>d</i>. The coarse stage includes a first 90/180 delay circuit <b>702</b><i>a </i>and a second 90/180 delay circuit <b>702</b><i>b</i>. The first 90/180 delay circuit <b>702</b><i>a </i>receives the 0-degree signal <b>602</b><i>a </i>and generates output signals <b>605</b><i>b </i>and <b>605</b><i>d</i>. The second 90/180 delay circuit <b>702</b><i>b </i>receives the 180 degree signal <b>602</b><i>b </i>and generates output signals <b>605</b><i>b </i>and <b>605</b><i>d</i>. The signal <b>605</b><i>a </i>is arbitrarily chosen as a reference output signal at 0 degrees. The output signal <b>605</b><i>b </i>is phase shifted by 90 degrees relative to the reference signal <b>605</b><i>a</i>, plus some error signal E<sub>1</sub>. The output signal <b>605</b><i>c </i>is phase-shifted by 180 degrees relative to the reference signal <b>605</b><i>a</i>, plus some error signal E<sub>2</sub>. Finally, the output signal <b>605</b><i>d </i>is phase-shifted by 270 degrees relative to the reference signal <b>605</b><i>a</i>, plus some error signal E<sub>3</sub>.
[0062]FIG. 18 illustrates a flowchart <b>1800</b> that further describes coarse quadrature signal generation according to embodiments of the present invention. For instance, flowchart <b>1800</b> describes the operation of the coarse stage <b>604</b> in the generation of the coarse quadrature signals <b>605</b><i>a</i>-<b>605</b><i>d. </i>
[0063] In step <b>1802</b>, a differential signal is received having a first component and a second component, where the second component is 180 degrees out-of-phase from the first component. The first component can be referred to as the positive component of a differential signal, and the second component can be referred to as the negative component of a differential signal. For example, referring to FIG. 7, the first component can be the 0-degree component <b>602</b><i>a </i>and the second component can be the 180-degree component <b>602</b><i>b</i>, as shown in FIG. 7.
[0064] In step <b>1804</b>, the first component of the differential input signal is delayed by approximately 90 degrees and also by 180 degrees, to generate a 90 degree output signal and a 180 degree output signal, respectively. The 90 degree output signal is phase-shifted by 90 degrees relative to the first component of the differential input signal, plus some error signal. The 180 degree output signal is phase-shifted by 180 degrees relative to the first component of the differential input signal, plus some error signal. For example, in FIG. 7, the output signal <b>605</b><i>b </i>is phase-shifted by approximately 90 degrees relative to the input signal <b>602</b><i>a</i>, plus an error signal E<sub>1</sub>. The output signal <b>605</b><i>c </i>is phase-shifted by 180 degrees relative to the input signal <b>602</b><i>a</i>, plus an error signal E<sub>2</sub>.
[0065] In step <b>1806</b>, the second component of the differential input signal is delayed by approximately 90 degrees and 180 degrees, to generate a 270 degree output signal and a 0 degree output signal, respectively. The 270 degree output signal is phase-shifted by approximately 270 degrees relative to the first component of the differential input signal, plus some error signal. The 0 degree output signal is phase shifted by approximately 0 degrees relative to the first component of the differential input signal, plus some error signal. For example, in FIG. 7, the output signal <b>605</b><i>d </i>is phase-shifted by approximately 270 degrees relative to the input signal <b>602</b><i>a</i>, plus an error signal E<sub>3</sub>. The output signal <b>605</b><i>a </i>is phase-shifted by 0 degrees relative to the input signal <b>602</b><i>a</i>. As mentioned above, the output signal <b>605</b><i>a </i>is arbitrarily chosen as the reference for the output signals <b>605</b><i>a</i>-<i>d</i>, so there is no error signal for the output signal <b>605</b><i>a. </i>
[0066]FIG. 8 illustrates a refinement stage <b>606</b> that receives input signals <b>801</b>-<b>1</b> to <b>801</b>-<b>4</b> from a prior stage (e.g. the coarse stage <b>604</b> or another refinement stage <b>606</b>), and generates output signals <b>805</b>-<b>1</b> to <b>805</b>-<b>4</b>. The input signals <b>801</b>-<b>1</b> to <b>801</b>-<b>4</b> have a quadrature relationship, but have some input phase error E<sub>IN</sub>. For example, the signal <b>801</b>-<b>2</b> is phase-shifted relative to the signal <b>801</b>-<b>1</b> by 90 degrees+/− an error (E<sub>IN1</sub>). The signal <b>801</b>-<b>3</b> is phase-shifted relative to the signal <b>801</b>-<b>1</b> by 180 degrees+/− an error (E<sub>IN2</sub>). The signal <b>801</b>-<b>3</b> is phase-shifted relative to the signal <b>801</b>-<b>1</b> by 270 degrees+/− an error (E<sub>IN3</sub>). The output signals <b>805</b> also have a quadrature relationship, but have some output phase error E<sub>OUT</sub>. For example, the signal <b>801</b>-<b>2</b> is phase-shifted relative to the signal <b>801</b>-<b>1</b> by 90 degrees+/− an error (E<sub>OUT1</sub>). The signal <b>801</b>-<b>3</b> is phase-shifted relative to the signal <b>801</b>-<b>1</b> to by 180 degrees+/− an error (E<sub>OUT2</sub>). The output signal <b>801</b>-<b>4</b> is phase-shifted relative to the signal <b>801</b>-<b>1</b> by 270 degrees+/− an error (E<sub>OUT3</sub>). Preferably, E<sub>OUT </sub>for each output signal <b>805</b> is less than the E<sub>IN </sub>for each corresponding signal <b>801</b>, so that the output of the refinement stage <b>606</b> has a more accurate quadrature relationship than the input signals <b>801</b>. For example, preferably, E<sub>OUT1 </sub>is less than E<sub>IN</sub>, E<sub>OUT2 </sub>is less than E<sub>IN2</sub>, and E<sub>OUT3 </sub>is less than E<sub>IN3</sub>. Thus, as more and more refinement stages <b>606</b> are added, the quadrature phase error continues to reduce toward zero degrees.
[0067] The refinement stage <b>606</b> in FIG. 8 includes four 0/180 delay circuits <b>802</b>-<b>1</b> to <b>802</b>-<b>4</b>, and four 90/180 delay circuits <b>702</b>-<b>1</b> to <b>702</b>-<b>4</b>. The number of delay circuits <b>802</b> and <b>702</b> are determined by the number of input signals <b>801</b><i>a</i>-<i>d</i>, which is four in this case.
[0068] Each delay circuit <b>802</b> receives a corresponding input signal <b>801</b>, and has a 0 degree output and a 180 degree output. The 0 degree output of the first delay circuit <b>802</b>-<b>1</b> is connected to the 180 degree output of the delay circuit <b>802</b>-<b>3</b>. The 180 degree output of the delay circuit <b>801</b>-<b>1</b> is connected to the 0 degree output of the delay circuit <b>801</b>-<b>3</b>. Similarly, the 0 degree output of the delay circuit <b>802</b>-<b>2</b> is connected to the 180 degree output of the delay circuit <b>802</b>-<b>4</b>, and the 180 degree output of the delay circuit <b>802</b>-<b>2</b> is connected to the 0 degree output of the delay circuit <b>802</b>-<b>4</b>. Stated another way, each odd numbered delay circuit <b>802</b> has its outputs connected together, but 180 degrees out-of-phase with each other. Likewise, each even-numbered delay circuit <b>801</b> has its outputs connected together, but is 180-degrees out-of-phase with each other.
[0069] The input of 90/180 delay circuits <b>702</b> receives the 0-degree output of the corresponding delay circuit <b>802</b>. For example, the input of the delay circuit <b>702</b>-<b>1</b> is connected to the 0-degree output of the delay circuit <b>802</b>-<b>1</b>, and the input of the delay circuit <b>702</b>-<b>2</b> is connected to the 0-degree output of the delay circuit <b>802</b>-<b>2</b>, and so on.
[0070] Still referring to the delay circuits <b>702</b>, the 180-degree output of the first delay circuit <b>702</b>-<b>1</b> is connected to the 90 degree output of the delay circuit <b>702</b>-<b>2</b>. The 180-degree output of the delay circuit <b>702</b>-<b>2</b> is connected to the 90-degree output of the delay circuit <b>702</b>-<b>3</b>. Similarly, 180-degree output of the delay circuit <b>702</b>-<b>3</b> is connected to the 90-degree output of the delay circuit <b>702</b>-<b>4</b>. Stated another way, the <b>180</b>-degree output of the n<sup>th </sup>delay circuit <b>702</b> is connected to the 90-degree output of the (n+1)<sup>th </sup>delay circuit <b>702</b>. The 180-degree output of the 4<sup>th </sup>delay circuit <b>702</b>-<b>4</b> is connected back to the 90 degree output of the first delay circuit <b>702</b>-<b>1</b>, as it is the last delay circuit <b>702</b> in the set.
[0071]FIG. 9 further illustrates the 0/180 degree delay circuit <b>802</b> that is utilized in the refinement stages <b>606</b>, according to an embodiment of the invention. The 0/180 degree delay circuit <b>802</b> includes a first signal path <b>902</b> and a second signal path <b>904</b> that receive an input signal <b>901</b>. The first signal path <b>902</b> includes inverters <b>904</b><i>a </i>and <b>904</b><i>b</i>. The inverters <b>902</b><i>a </i>and <b>902</b><i>b </i>receive the input signal <b>901</b>, invert the signal twice, so that the output signal <b>906</b><i>a </i>is in-phase with the input signal <b>901</b>. In other words, the signal <b>906</b><i>a </i>is phase-shifted by 0 degrees with respect to the input signal <b>901</b>, except for the parasitic delay of the inverters <b>902</b> and <b>902</b><i>b</i>. Herein, parasitic delay or parasitic phase shift is the unintentional signal delay caused by the physical parameters of a semiconductor device(s) that make-up the inverter <b>906</b>. For example, larger field effect transistors (FETs) are known to have a larger parasitic delay than smaller devices because they have a larger parasitic reactance, and because they have a longer channel that the signal must travel through.
[0072] The second signal path <b>904</b> includes a transmission gate <b>908</b> and an inverter <b>904</b><i>c</i>. The transmission gate <b>908</b> is a 0-degree phase-shifter, but is designed to have the same parasitic delay as an inverter <b>906</b>. Therefore, the input signal <b>901</b> is phase shifted by 0 degrees and then is phase-shifted by 180 degrees to produce an output signal <b>906</b><i>b </i>that is delayed 180 degrees with respect to the output signal <b>906</b><i>a</i>. The transmission gate <b>908</b> replicates and copies the parasitic delay of the inverter <b>906</b><i>a </i>into the signal path <b>904</b>. Without the transmission gate <b>908</b>, the output signal <b>906</b><i>b </i>would be skewed-off the desired 180 degree phase shift by the parasitic delay of the inverter <b>906</b><i>a</i>.
[0073]FIG. 10 further illustrates the 90/180 degree delay <b>702</b> according to an embodiment of the invention, which is used in both the coarse stage <b>604</b> and the fine stage <b>606</b>. The 90/180 degree delay includes a first path <b>1002</b> that includes inverters <b>906</b><i>a</i>-<b>906</b><i>d</i>, and a second path <b>1004</b> that only includes the inverter <b>906</b><i>e</i>. Ignoring any parasitic delay for the moment, the first path <b>1002</b> inverts the input signal <b>1001</b> four times, so that the output signal <b>1006</b><i>a </i>is in-phase with the input signal <b>1001</b>. Likewise, the second path <b>1004</b> includes a single inverter <b>906</b><i>e</i>, so that the output signal <b>1006</b><i>b </i>is 180 degrees out-of-phase with the input signal <b>1001</b>. Therefore, absent any parasitic delay, the output signal <b>1006</b><i>b </i>would be phase-shifted by 180 degrees relative to the output signal <b>1006</b><i>a</i>. However, the desired result is that the output signal <b>1006</b><i>b </i>should be delayed by only 90 degrees relative to the output signal <b>1006</b><i>a. </i>
[0074] Now considering the parasitic delay of the inverters <b>906</b>, the first path <b>1002</b> has 3 more inverters <b>906</b> than the second path <b>1004</b>. Therefore, the inverters <b>906</b> are sized so that the parasitic delay of the 3 inverters <b>906</b> is equal to 90 degrees at the frequency of interest. In other words, the parasitic delay of the 3 additional inverters <b>906</b> in path <b>1002</b> causes an additional 90 degrees worth of phase shift at the frequency of interest, so that the output <b>1006</b><i>b </i>only lags the output <b>1006</b><i>a </i>by 90 degrees, as is desired.
[0075] In one embodiment, the frequency-of-interest for the input signal <b>1001</b> is 800 MHz, which has a period of 1250 pS. Therefore, 90 degrees of phase-shift equates to about 1250 pS/4, or 312 pS. Therefore, each of the three inverters <b>906</b> should provide approximately 104 pS of delay at 800 MHz, for this example.
[0076] The time delay for an inverter <b>906</b> can be shown to be equal to
<i>t</i><sub>DELAY</sub><i>=R</i><sub>eq</sub><i>C</i><sub>LOAD </sub>
[0077] where R<sub>eq </sub>and C<sub>LOAD </sub>are the equivalent resistance and capacitance for a digital FET. The equivalent resistance of a digital FET can be shown to be: <maths id="MATH-US-00001" num="1"><math overflow="scroll"><mtable><mtr><mtd><mrow><msub><mi>R</mi><mi>eq</mi></msub><mo>=</mo><mrow><mfrac><msub><mi>V</mi><mi>DD</mi></msub><mrow><mfrac><msup><mi>K</mi><mi>′</mi></msup><mn>2</mn></mfrac><mo></mo><mfrac><mi>W</mi><mi>L</mi></mfrac><mo></mo><msup><mrow><mo>(</mo><mrow><msub><mi>V</mi><mi>DD</mi></msub><mo>-</mo><msub><mi>V</mi><mi>TH</mi></msub></mrow><mo>)</mo></mrow><mn>2</mn></msup></mrow></mfrac><mo>=</mo><mrow><msubsup><mi>R</mi><mi>eq</mi><mi>′</mi></msubsup><mo></mo><mfrac><mi>L</mi><mi>W</mi></mfrac></mrow></mrow></mrow></mtd><mtd><mrow><mo>(</mo><mrow><mn>1</mn><mo></mo><mi>a</mi></mrow><mo>)</mo></mrow></mtd></mtr><mtr><mtd><mrow><msub><mi>R</mi><mrow><mi>o</mi><mo></mo><mstyle><mtext> </mtext></mstyle><mo></mo><mi>n</mi></mrow></msub><mo>=</mo><mfrac><mi>L</mi><mrow><msup><mi>K</mi><mi>′</mi></msup><mo></mo><mrow><mi>W</mi><mo></mo><mrow><mo>(</mo><mrow><msub><mi>V</mi><mi>gs</mi></msub><mo>-</mo><msub><mi>V</mi><mi>T</mi></msub></mrow><mo>)</mo></mrow></mrow></mrow></mfrac></mrow></mtd><mtd><mrow><mo>(</mo><mrow><mn>1</mn><mo></mo><mi>b</mi></mrow><mo>)</mo></mrow></mtd></mtr></mtable></math><img file="US20030227983A1-20031211-M00001.TIF" id="EMI-M00001" he="51.11505" wi="216.027" img-format="tif" img-content="mf" /><attachments><attachment idref="MATHEMATICA-00001" attachment-type="nb" file="US20030227983A1-20031211-M00001.NB" /></attachments></maths>
[0078] wherein,
[0079] L=FET channel length,
[0080] W=FET channel width,
[0081] R′<sub>eq</sub>=is a constant dependent on the particular semiconductor process that is utilized.
[0082] The equivalent capacitance for a digital FET can be shown to be: <maths id="MATH-US-00002" num="2"><math overflow="scroll"><mtable><mtr><mtd><mrow><msub><mi>C</mi><mi>LOAD</mi></msub><mo>=</mo><mrow><mrow><msub><mi>C</mi><mi>IN</mi></msub><mo>+</mo><msub><mi>C</mi><mi>OUT</mi></msub></mrow><mo>=</mo><mrow><mrow><mfrac><mn>3</mn><mn>2</mn></mfrac><mo></mo><mrow><msubsup><mi>C</mi><mi>OX</mi><mi>′</mi></msubsup><mo></mo><mrow><mo>(</mo><mrow><msub><mrow><mo>(</mo><mi>WL</mi><mo>)</mo></mrow><mi>N</mi></msub><mo>+</mo><msub><mrow><mo>(</mo><mi>WL</mi><mo>)</mo></mrow><mi>P</mi></msub></mrow><mo>)</mo></mrow></mrow></mrow><mo>+</mo><mrow><msubsup><mi>C</mi><mi>OX</mi><mi>′</mi></msubsup><mo></mo><mrow><mo>(</mo><mrow><msub><mrow><mo>(</mo><mi>WL</mi><mo>)</mo></mrow><mi>N</mi></msub><mo>+</mo><msub><mrow><mo>(</mo><mi>WL</mi><mo>)</mo></mrow><mi>P</mi></msub></mrow><mo>)</mo></mrow></mrow></mrow></mrow></mrow></mtd><mtd><mrow><mo>(</mo><mn>2</mn><mo>)</mo></mrow></mtd></mtr></mtable></math><img file="US20030227983A1-20031211-M00002.TIF" id="EMI-M00002" he="29.9943" wi="216.027" img-format="tif" img-content="mf" /><attachments><attachment idref="MATHEMATICA-00002" attachment-type="nb" file="US20030227983A1-20031211-M00002.NB" /></attachments></maths>
[0083] wherein,
[0084] C<sub>ox </sub>is dependent on the gate oxide thickness of the digital FET.
[0085] By substituting the expression for R<sub>eq </sub>and C<sub>Load </sub>for the t<sub>DELAY </sub>equation: <maths id="MATH-US-00003" num="3"><math overflow="scroll"><mtable><mtr><mtd><mrow><msub><mi>t</mi><mi>DELAY</mi></msub><mo>=</mo><mrow><mrow><msub><mi>R</mi><mi>eq</mi></msub><mo></mo><msub><mi>C</mi><mi>LOAD</mi></msub></mrow><mo>=</mo><mrow><mrow><mrow><msub><mrow><msubsup><mi>R</mi><mi>eqP</mi><mi>′</mi></msubsup><mo></mo><mrow><mo>(</mo><mfrac><mi>L</mi><mi>W</mi></mfrac><mo>)</mo></mrow></mrow><mi>P</mi></msub><mo>·</mo><mfrac><mn>5</mn><mn>2</mn></mfrac></mrow><mo></mo><msub><mrow><msubsup><mi>C</mi><mi>OX</mi><mi>′</mi></msubsup><mo></mo><mrow><mo>(</mo><mi>WL</mi><mo>)</mo></mrow></mrow><mi>P</mi></msub><mo></mo><mrow><mo>(</mo><mrow><mn>1</mn><mo>+</mo><mfrac><msubsup><mi>K</mi><mi>P</mi><mi>′</mi></msubsup><msubsup><mi>K</mi><mi>N</mi><mi>′</mi></msubsup></mfrac></mrow><mo>)</mo></mrow></mrow><mo>=</mo><mrow><mfrac><mn>5</mn><mn>2</mn></mfrac><mo></mo><msubsup><mi>R</mi><mi>eqP</mi><mi>′</mi></msubsup><mo></mo><mrow><msubsup><mi>C</mi><mi>OX</mi><mi>′</mi></msubsup><mo></mo><mrow><mo>(</mo><mrow><mn>1</mn><mo>+</mo><mfrac><msubsup><mi>K</mi><mi>P</mi><mi>′</mi></msubsup><msubsup><mi>K</mi><mi>N</mi><mi>′</mi></msubsup></mfrac></mrow><mo>)</mo></mrow></mrow><mo></mo><mstyle><mtext> </mtext></mstyle><mo></mo><msubsup><mi>L</mi><mi>P</mi><mn>2</mn></msubsup></mrow></mrow></mrow></mrow></mtd><mtd><mrow><mo>(</mo><mn>3</mn><mo>)</mo></mrow></mtd></mtr></mtable></math><img file="US20030227983A1-20031211-M00003.TIF" id="EMI-M00003" he="31.9221" wi="216.027" img-format="tif" img-content="mf" /><attachments><attachment idref="MATHEMATICA-00003" attachment-type="nb" file="US20030227983A1-20031211-M00003.NB" /></attachments></maths>
[0086] Equation 3 can be solved for channel length to achieve a desired delay. Solving for a 104 pS delay results in channel length of L=0.62 um. Additionally, devices with a given length can be used in conjunction with a variable capacitive load to achieve a desired delay for a specific application. This will permit tuning of the filter.
[0087] As shown in Equation (3), the device width W is canceled out, and the device delay is largely independent of device width. Since the device delay is largely independent of device width, it is tempting to select minimum width devices to reduce layout area. Minimum width devices also result in lower power consumption due to a lower transconductance and lower current draw during moments of paralleled inverter output averaging. However, the quadrature generator <b>600</b> relies on stage-to-stage matching to achieve high phase accuracy. The CMOS process can be characterized for device-to-device variations in threshold voltage, transconductance, and other parameters. In most cases improved parameter matching is achieved by increasing the device area. As a result, the FET channel width is increased to achieve the necessary device-to-device uniformity required to meet the phase imbalance specification. Larger devices require more layout area and also more power, as will be understood by those skilled in the arts. As a result, power consumption and layout area are being traded for phase accuracy.
[0088]FIG. 17 illustrates the tradeoff between phase error and FET size and current. Curve <b>1702</b> depicts phase error vs. FET size, and illustrates that the phase error decreases as the FET size increases. Curve <b>1704</b> depicts drain current vs. FET size and illustrates that drain current increases with FET size. Therefore, in one embodiment, the FET size at <b>1706</b> is chosen as a compromise between low phase error and moderate power consumption.
[0089] It can be shown that a threshold voltage standard deviation/mean of about 1.8% would produce phase errors of less than 1 degree RMS. While a threshold voltage (V<sub>TH0</sub>) deviation can be assigned directly to the PSpice model, beta variations were included by allowing gate oxide thickness (t<sub>ox</sub>) to vary. The variation of t<sub>ox </sub>affects several parameters besides the transconductance (including threshold voltage), but provides a likely worst case analysis for phase sensitivity. A standard deviation/mean of 2% was assigned to t<sub>OX</sub>.
[0090] The course quadrature signals are further refined with each correction stage. However, at some point the phase error will be limited by the component matching of the final stage, and additional stages provide little or no improvement in phase error. For example, the quadrature generator in FIG. 6 includes 4 refinement stages. The phase error is rapidly reduced to less than 2 degrees (from an initial 15-20 degrees) by the first two stages <b>606</b><i>a </i>and <b>606</b><i>b</i>. The third stage <b>606</b><i>c </i>drops phase error to about 1.5 degrees, and the fourth stage provides enough improvement to the reduce phase error +/−1 degree, which is desired for one embodiment of the invention.
[0091] As discussed herein, the delay circuits <b>802</b> and <b>702</b> are implemented using active inverter circuits, which can be implemented in standard semiconductor processes, such as CMOS. CMOS inverters on a common substrate have similar semiconductor characteristics that are repeatable from inverter-to-inverter, which improves the phase accuracy of the quadrature output signals. Furthermore, CMOS inverters are more area efficient than passive capacitors and passive resistors. Therefore, the entire quadrature generator <b>600</b> is more area efficient than the conventional delay circuit <b>500</b>, which increases overall chip-yield. Similar concepts can be applied using ECL (emitter coupled logic) for the inverters with improved matching and accuracy.
[0092]FIG. 12 further illustrates the operation of refinement stage <b>606</b>. More specifically, FIG. 12 depicts a functional description of the refinement stage <b>606</b>. Referring to FIG. 12, an input signal Vs <b>1208</b> is sub-divided into an in-phase signal <b>1206</b> and a quadrature signal <b>1212</b>, producing an angle <b>1222</b> between the in-phase signal <b>1206</b> and the quadrature <b>1212</b>. Due to the component inaccuracies in the refinement stage <b>606</b>, the angle <b>1222</b> between the in-phase signal <b>1206</b> and the quadarature signal <b>1212</b> is not exactly 90 degrees, but is 90 degrees+/− some error. The in-phase signal <b>1206</b> is further sub-divided into an in-phase signal <b>1202</b> and a quadrature signal <b>1204</b>, producing an angle <b>1220</b> between the signals <b>1202</b> and <b>1204</b>. The quadrature signal <b>1212</b> is also further sub-divided into in-phase signal <b>1210</b> and quadrature signal <b>1216</b>, producing an angle <b>1224</b> between the signals <b>1210</b> and <b>1216</b>. The angles <b>1220</b> and <b>1224</b> are also not exactly 90, and have substantially the same error as the angle <b>1222</b>. The error is substantially the same because component inaccuracies are substantially the same in the refinement stage <b>606</b>, due to the repeated use of inverters <b>906</b>.
[0093] The in-phase signals <b>1204</b> and <b>1210</b> are substantially in-phase with each other and are added together to produce a combined in-phase signal <b>1226</b>. Likewise, the signal <b>1218</b> is subtracted from the signal <b>1216</b> to produce a combined quadrature signal <b>1228</b>. The combined in-phase signal <b>1226</b> is substantially in quadrature with the combined quadrature signal <b>1228</b>, so that the resulting angle <b>1230</b> is substantially 90 degrees, or at least has a final error component that is less than the error associated with the angles <b>1220</b> and <b>1224</b>. The final error component is less because the corresponding inverters <b>906</b> in the 0/180 delay circuits are connected together. Therefore, any phase error signal at the output of the 0/180 delay circuits <b>802</b> is averaged together and reduced. For example, the 0-degree output of the delay circuit <b>802</b>-<b>1</b> is connected together with the 180 degree output of the delay circuit <b>802</b>-<b>3</b>. Since the delay circuit <b>802</b>-<b>3</b> has a 180 degree input <b>801</b>-<b>3</b>, the 180 degree output of the delay circuit <b>802</b>-<b>3</b> should be at 0 degree, and in-phase with the 0-degree output of the 0/180 delay circuit <b>802</b>-<b>1</b>. Likewise, the 180 degree output of the delay circuit <b>802</b>-<b>1</b> is connected to the 0-degree output of the delay circuit <b>802</b>-<b>3</b>, to average any phase error at these outputs. The outputs of the delay circuits <b>802</b>-<b>2</b> and <b>802</b>-<b>4</b> are connected together in a similar manner, to average any phase error at their outputs. Likewise, the corresponding outputs of the 90/180 delay circuits <b>702</b> are also connected together to average any phase error at their respective outputs.
[0094] FIGS. <b>13</b>A-C further describe the signal averaging performed by the connecting the outputs of the inverters <b>906</b> together. FIG. 13A illustrates substantially identical inverters <b>906</b><i>a </i>and <b>906</b><i>b </i>that are output inverters of either a 0/180 delay circuit <b>802</b>, or are the output of a 90/180 delay circuit <b>702</b>. For example, the inverter <b>906</b><i>a </i>can be the output inverter <b>906</b> of the 0/180 degree delay circuit <b>802</b>-<b>1</b>, and the inverter <b>906</b><i>b </i>can be the output inverter <b>906</b> of the 0/180 degree delay circuit <b>802</b>-<b>3</b>. Inverter <b>906</b><i>a </i>has an output <b>1302</b><i>a </i>and the inverter <b>906</b><i>b </i>has an output <b>1302</b><i>b</i>. Referring to FIG. 13C, each output <b>1302</b><i>a </i>and <b>1302</b><i>b </i>has some phase error, but the output <b>1302</b><i>a </i>leads the output <b>1302</b><i>b. </i>
[0095]FIG. 13B illustrates the inverters <b>906</b><i>a </i>and <b>906</b><i>b </i>having their outputs connected together at an output <b>1304</b>. Referring again to FIG. 13C, the output <b>1304</b> is substantially an average of the signals <b>1302</b><i>a </i>and <b>1302</b><i>b</i>, which reduces the phase error compared with the outputs <b>1302</b><i>a </i>and <b>1302</b><i>b. </i>
[0096] Still referring to FIG. 13B, the inverters <b>906</b><i>a </i>and <b>906</b><i>b </i>with corresponding outputs <b>1302</b><i>a </i>and <b>1302</b><i>b </i>produce the averaged output <b>1304</b> when their respective outputs are tied together because of the source impedance and the load impedance of the inverters. Referring to FIG. 13D, each inverter <b>906</b><i>a </i>possesses a finite source impedance and it can be viewed that each inverter <b>906</b> drives a load impedance. Accordingly, <tables id="TABLE-US-00001" num="1"><table frame="none" colsep="0" rowsep="0"><tgroup align="left" colsep="0" rowsep="0" cols="4"><colspec colname="OFFSET" colwidth="14PT" align="left" /><colspec colname="1" colwidth="28PT" align="left" /><colspec colname="2" colwidth="21PT" align="left" /><colspec colname="3" colwidth="154PT" align="left" /><thead><row><entry /><entry /></row><row><entry /><entry namest="OFFSET" nameend="3" align="center" rowsep="1" /></row></thead><tbody valign="top"><row><entry /><entry>V<sub>A,B</sub></entry><entry><u>Δ</u></entry><entry>voltage at inverter outputs</entry></row><row><entry /><entry>Z<sub>906A</sub></entry><entry><u>Δ</u></entry><entry>output impedance of 906A inverter</entry></row><row><entry /><entry>Z<sub>906B</sub></entry><entry><u>Δ</u></entry><entry>output impedance of 906B inverter</entry></row><row><entry /><entry>Z<sub>MI</sub></entry><entry><u>Δ</u></entry><entry>branch impedance which may be distributed or</entry></row><row><entry /><entry /><entry /><entry>lumped and may be related to passive or active</entry></row><row><entry /><entry /><entry /><entry>circuitry associated with the load or matching</entry></row><row><entry /><entry /><entry /><entry>networks</entry></row><row><entry /><entry>Z<sub>M2</sub></entry><entry /><entry>branch impedance which may be distributed or</entry></row><row><entry /><entry /><entry /><entry>lumped and may be related to passive or active</entry></row><row><entry /><entry /><entry /><entry>circuitry associated with the load or matching</entry></row><row><entry /><entry /><entry /><entry>networks</entry></row><row><entry /><entry>Z<sub>L</sub></entry><entry><u>Δ</u></entry><entry>load impedance</entry></row><row><entry /><entry namest="OFFSET" nameend="3" align="center" rowsep="1" /></row></tbody></tgroup></table></tables>
[0097] The effective load from the perspective of inverter <b>906</b><i>a </i>is therefore;
Z<sub>LOAD-906A</sub><u>Δ</u>Z<sub>M1</sub>+Z<sub>L</sub>//Z<sub>M2 </sub>
[0098] Likewise, the effective load from the perspective of inverter <b>906</b><i>b </i>is
Z<sub>LOAD-906B </sub><u>Δ</u>Z<sub>M2</sub>+Z<sub>L</sub>//Z<sub>M1 </sub>
[0099] Now the voltages across Z<sub>L </sub>and the currents through Z<sub>L </sub>are proportioned to the outputs of the inverters and the values for Z<sub>906A,B </sub>and Z<sub>LOAD-906A,B</sub>. Therefore: <maths id="MATH-US-00004" num="4"><math overflow="scroll"><mtable><mtr><mtd><mrow><msub><mi>V</mi><mrow><mi>O</mi><mo></mo><mstyle><mtext> </mtext></mstyle><mo></mo><mrow><mo>(</mo><mi>s</mi><mo>)</mo></mrow></mrow></msub><mo>=</mo><mrow><mrow><msub><mi>V</mi><mrow><mi>A</mi><mo></mo><mrow><mo>(</mo><mi>s</mi><mo>)</mo></mrow></mrow></msub><mo></mo><mfrac><msub><mi>Z</mi><mi>L</mi></msub><mrow><msub><mi>Z</mi><mrow><mn>906</mn><mo></mo><mi>A</mi></mrow></msub><mo>+</mo><msub><mi>Z</mi><mrow><mi>LOAD</mi><mo>-</mo><mrow><mn>906</mn><mo></mo><mi>A</mi></mrow></mrow></msub></mrow></mfrac></mrow><mo>+</mo><mrow><msub><mi>V</mi><mrow><mi>B</mi><mo></mo><mrow><mo>(</mo><mi>s</mi><mo>)</mo></mrow></mrow></msub><mo></mo><mfrac><msub><mi>Z</mi><mi>L</mi></msub><mrow><msub><mi>Z</mi><mrow><mn>906</mn><mo></mo><mi>B</mi></mrow></msub><mo>+</mo><msub><mi>Z</mi><mrow><mi>LOAD</mi><mo>-</mo><mrow><mn>906</mn><mo></mo><mi>B</mi></mrow></mrow></msub></mrow></mfrac></mrow></mrow></mrow></mtd><mtd><mrow><mo>(</mo><mrow><mn>3</mn><mo></mo><mi>a</mi></mrow><mo>)</mo></mrow></mtd></mtr></mtable></math><img file="US20030227983A1-20031211-M00004.TIF" id="EMI-M00004" he="18.96615" wi="216.027" img-format="tif" img-content="mf" /><attachments><attachment idref="MATHEMATICA-00004" attachment-type="nb" file="US20030227983A1-20031211-M00004.NB" /></attachments></maths>
[0100] This equation (<b>3</b><i>a</i>) indicates the transfer function in the frequency domain using Laplace transforms. The transient response my be obtained from the inverse Laplace transform. It is evident that V<sub>O </sub>can be manipulated by tailoring a number of items such as:
[0101] a) voltage swing of each inverter which could be accomplished via varying the power supply and a host of other techniques,
[0102] b) changing the inverter source impedances,
[0103] c) changing branch impedances Z<sub>M1</sub>, Z<sub>M2</sub>,
[0104] d) altering the load impedance.
[0105] In summary, the averaging of the inverters <b>906</b> could be weighted equally or in an arbitrary manner. Furthermore, this weighting could be altered in situations to compensate for differing phase alignments. Moreover, N such circuits could be combined in parallel using the super position principles illustrated for the two branch circuit.
[0106]FIG. 14 illustrates a flowchart <b>1400</b> that further describes the operation of the refinement stages <b>606</b>, and the phase error averaging performed by the refinement stages <b>606</b>.
[0107] In step <b>1402</b>, a first set of quadrature signals are received having some quadrature phase error. For example, referring to FIG. 8, input quadrature signals <b>801</b><i>a</i>-<b>801</b><i>d </i>are received that have some quadrature phase error E<sub>IN</sub>.
[0108] In step <b>1404</b>, a second set and a third set of quadrature signals are generated based on the first set of quadrature signals using inverters. The second set of quadrature signals are substantially in-phase with the first set of quadrature signals, and the third set of quadrature signals are substantially delayed by 180 degrees relative to the first set of quadrature signals. For example, 0-degree outputs of the 0/180 delay circuits <b>802</b> are generated based on the first set of signals <b>801</b>, and represent the second set of quadrature signals. The 0-degree outputs of the delay circuit <b>802</b> are substantially in-phase with the inputs <b>801</b>, and have a quadrature relationship with each other because the quadrature signals <b>801</b> have a quadrature relationship with each other. The 180 degree outputs of the 0/180 delay circuits <b>802</b> are based on the first set of quadrature signals, and represent the third set of quadrature signals. The 180 degree outputs of the 0/180 delay circuits <b>802</b> are substantially 180 degrees out of phase with the corresponding inputs <b>801</b>.
[0109] In step <b>1406</b>, the second set of quadrature signals and the third set of quadrature signals are averaged together, to generate a fourth set of quadrature signals that have less phase error than the first set of quadrature signals. More specifically, corresponding signals of the second set of quadrature signals and the third set of quadrature signals are averaged together, to reduce the phase error in the fourth set of quadrature signals. For example, the 0-degree outputs of the 0/180 delay circuits <b>802</b> are averaged with the corresponding 180 degree outputs of the delay circuit <b>802</b> to generate averaged signals <b>804</b>. For example, the 0 degree output of the 0/180 delay circuit <b>802</b>-<b>1</b> is averaged with the 180 degree output of the delay circuit <b>802</b>-<b>3</b>, to generate an averaged signal <b>804</b>-<b>1</b> that is the input to the 90/180 degree delay circuit <b>702</b>-<b>1</b>. Likewise, the 0-degree output of the delay circuit <b>802</b>-<b>2</b> is averaged with the 180 degree output of the delay circuit <b>802</b>-<b>4</b>, to generate an averaged signal <b>804</b>-<b>2</b>. Likewise, the 0-degree output of the delay circuit <b>802</b>-<b>3</b> is averaged with the 180 degree output of the delay circuit <b>802</b>-<b>1</b>, to generate an averaged signal <b>804</b>-<b>3</b>. Likewise, the 0-degree output of the delay circuit <b>802</b>-<b>4</b> is averaged with the 180 degree output of the delay circuit <b>802</b>-<b>2</b>, to generate an averaged signal <b>804</b>-<b>4</b>.
[0110] In step <b>1408</b>, a fifth set and a sixth set of quadrature signals is generated based on the fourth set of quadrature signals. The fifth set of quadrature signals is delayed by 90 degrees relative to the fourth set of quadrature signals. The sixth set of quadrature signals is delayed by 180 degrees relative to the fourth set of quadrature signals, and therefore is delayed by 90 degrees relative to the fifth set of quadrature signals. For example, 90-degree outputs of the 90/180 delay circuits <b>702</b> represent the fifth set of quadrature signals, and are delayed by 90 degrees relative to the corresponding averaged signals <b>804</b>-<b>1</b> to <b>804</b>-<b>4</b>. The 180 degree outputs of the 90/180 delay circuits <b>702</b> are also based on the fourth set of quadrature signals, and are delayed by 180 degrees relative to the corresponding averaged signals <b>804</b>-<b>1</b> to <b>804</b>-<b>4</b>.
[0111] In step <b>1410</b>, the fifth set of quadrature signals and the sixth set of quadrature signals are averaged together, to generate a seventh set of quadrature signals that have less phase error than the fourth set of quadrature signals. More specifically, corresponding signals of the fifth set of quadrature signals and the sixth set of quadrature signals are averaged together, to reduce the phase error in the seventh set of quadrature signals. For example, the 0-degree outputs of the 90/180 delay circuits <b>702</b> are averaged with the corresponding 180 degree outputs of the delay circuits <b>702</b>, to generate averaged output signals <b>805</b>. For example, the 90 degree output of the 90/180 delay circuit <b>702</b>-<b>1</b> is averaged with the 180 degree output of the delay circuit <b>702</b>-<b>3</b>, to generate the quadrature output signal <b>805</b>-<b>1</b>. Likewise, the 90-degree output of the delay circuit <b>702</b>-<b>2</b> is averaged with the 180 degree output of the delay circuit <b>702</b>-<b>1</b>, to generate the quadrature output signal <b>805</b>-<b>2</b>. Likewise, the 90-degree output of the delay circuit <b>702</b>-<b>3</b> is averaged with the 180 degree output of the delay circuit <b>702</b>-<b>4</b>, to generate the quadrature output signal <b>804</b>-<b>3</b>. Likewise, the 90-degree output of the delay circuit <b>702</b>-<b>4</b> is averaged with the 180 degree output of the delay circuit <b>702</b>-<b>3</b>, to generate the quadrature output signal <b>805</b>-<b>4</b>.
[0112] The phase error of the quadrature output signals <b>805</b> is less than the phase error of the quadrature input signals <b>801</b>, due to the averaging performed by steps <b>1406</b> and <b>1408</b>. In embodiments, phase error is less than 1 degree at the frequency of interest.
[0113] 5. Mathematical Description
[0114] A system level mathematical description of the operation of the refinement stage <b>606</b> is given as follows. In order to facilitate the equation manipulation in the following description, the delay circuits <b>802</b>-<b>1</b> to <b>802</b>-<b>4</b> in FIG. 8 will be referred to as delay circuits A-<b>1</b> to A-n, respectively. Likewise, the delay circuits <b>702</b>-<b>1</b> to <b>702</b>-<b>4</b> in FIG. 8 will be referred to as delay circuits B-<b>1</b> to B-n. This is in accordance with the “A” placed over the row of delay circuit <b>802</b>, and the “B” placed over the row of delay circuits <b>702</b> in FIG. 8. Furthermore, the input signals <b>801</b>-<b>1</b> to <b>801</b>-<b>4</b> will be referred to as in0, in90, in180, and in270, respectively. Furthermore, the output signals <b>805</b>-<b>1</b> through <b>805</b>-<b>4</b> will be referred to as out0, out90, out180, and out270.
[0115] The four input and output waveforms of the refinement stage <b>606</b> can be approximately modeled as square waves although this is not strictly required. A Fourier decomposition can also be used to compare spectral components and their relative phases. The phase accuracy of the refinement stage <b>606</b> is measured by the relative time delay between rising or falling edges of each of the four output waveforms <b>805</b>. Timing uncertainties result from input phase error and variability of propagation delay through each of the delay circuit <b>802</b> and <b>702</b> of the refinement stages <b>606</b>. A mathematical model is constructed and described below that preserves the individual timing errors and demonstrates the self-regulating nature of the refinement stage <b>606</b>.
[0116] A unit rectangular pulse is defined as: <maths id="MATH-US-00005" num="5"><math overflow="scroll"><mtable><mtr><mtd><mrow><mrow><mover><mo>∏</mo><mstyle><mtext> </mtext></mstyle></mover><mo></mo><mrow><mo>(</mo><mi>t</mi><mo>)</mo></mrow></mrow><mo>=</mo><mrow><mo>{</mo><mrow><mn>1</mn><mo>,</mo><mrow><mrow><mrow><mo></mo><mi>t</mi><mo></mo></mrow><mo><</mo><mfrac><mn>1</mn><mn>2</mn></mfrac></mrow><mo>;</mo><mrow><mn>0</mn><mo></mo><mstyle><mtext> </mtext></mstyle><mo></mo><mi>otherwise</mi></mrow></mrow></mrow></mrow></mrow></mtd><mtd><mrow><mo>(</mo><mn>4</mn><mo>)</mo></mrow></mtd></mtr></mtable></math><img file="US20030227983A1-20031211-M00005.TIF" id="EMI-M00005" he="18.00225" wi="216.027" img-format="tif" img-content="mf" /><attachments><attachment idref="MATHEMATICA-00005" attachment-type="nb" file="US20030227983A1-20031211-M00005.NB" /></attachments></maths>
[0117] Each of the input waveforms can be described by periodic rectangular pulse functions of fixed amplitude, A, and distinct timing with a periodicity of T, a pulse width of T/2, and first rising edge occurring at time t<sub>0</sub>, as shown in FIG. 15. The equations for the input waveforms <b>801</b> based on this unit pulse description are as follows: <maths id="MATH-US-00006" num="6"><math overflow="scroll"><mtable><mtr><mtd><mrow><mrow><mi>i</mi><mo></mo><mstyle><mtext> </mtext></mstyle><mo></mo><mi>n</mi><mo></mo><mstyle><mtext> </mtext></mstyle><mo></mo><mn>0</mn></mrow><mo>=</mo><mrow><munderover><mo>∑</mo><mrow><mi>n</mi><mo>=</mo><mn>0</mn></mrow><mi>∞</mi></munderover><mo></mo><mstyle><mtext> </mtext></mstyle><mo></mo><mrow><mi>A</mi><mo></mo><mrow><mover><mo>∏</mo><mstyle><mtext> </mtext></mstyle></mover><mo></mo><mrow><mo>(</mo><mfrac><mrow><mn>2</mn><mo></mo><mrow><mo>(</mo><mrow><mi>t</mi><mo>-</mo><mi>nT</mi><mo>-</mo><msub><mi>t</mi><mn>0</mn></msub></mrow><mo>)</mo></mrow></mrow><mi>T</mi></mfrac><mo>)</mo></mrow></mrow></mrow></mrow></mrow></mtd><mtd><mrow><mo>(</mo><mn>5</mn><mo>)</mo></mrow></mtd></mtr><mtr><mtd><mrow><mrow><mi>i</mi><mo></mo><mstyle><mtext> </mtext></mstyle><mo></mo><mi>n</mi><mo></mo><mstyle><mtext> </mtext></mstyle><mo></mo><mn>90</mn></mrow><mo>=</mo><mrow><munderover><mo>∑</mo><mrow><mi>n</mi><mo>=</mo><mn>0</mn></mrow><mi>∞</mi></munderover><mo></mo><mstyle><mtext> </mtext></mstyle><mo></mo><mrow><mi>A</mi><mo></mo><mrow><mover><mo>∏</mo><mstyle><mtext> </mtext></mstyle></mover><mo></mo><mrow><mo>(</mo><mfrac><mrow><mn>2</mn><mo></mo><mrow><mo>(</mo><mrow><mi>t</mi><mo>-</mo><mi>nT</mi><mo>-</mo><msub><mi>t</mi><mn>90</mn></msub></mrow><mo>)</mo></mrow></mrow><mi>T</mi></mfrac><mo>)</mo></mrow></mrow></mrow></mrow></mrow></mtd><mtd><mrow><mo>(</mo><mn>6</mn><mo>)</mo></mrow></mtd></mtr><mtr><mtd><mrow><mrow><mi>i</mi><mo></mo><mstyle><mtext> </mtext></mstyle><mo></mo><mi>n</mi><mo></mo><mstyle><mtext> </mtext></mstyle><mo></mo><mn>180</mn></mrow><mo>=</mo><mrow><munderover><mo>∑</mo><mrow><mi>n</mi><mo>=</mo><mn>0</mn></mrow><mi>∞</mi></munderover><mo></mo><mstyle><mtext> </mtext></mstyle><mo></mo><mrow><mi>A</mi><mo></mo><mrow><mover><mo>∏</mo><mstyle><mtext> </mtext></mstyle></mover><mo></mo><mrow><mo>(</mo><mfrac><mrow><mn>2</mn><mo></mo><mrow><mo>(</mo><mrow><mi>t</mi><mo>-</mo><mi>nT</mi><mo>-</mo><msub><mi>t</mi><mn>180</mn></msub></mrow><mo>)</mo></mrow></mrow><mi>T</mi></mfrac><mo>)</mo></mrow></mrow></mrow></mrow></mrow></mtd><mtd><mrow><mo>(</mo><mn>7</mn><mo>)</mo></mrow></mtd></mtr><mtr><mtd><mrow><mrow><mi>i</mi><mo></mo><mstyle><mtext> </mtext></mstyle><mo></mo><mi>n</mi><mo></mo><mstyle><mtext> </mtext></mstyle><mo></mo><mn>270</mn></mrow><mo>=</mo><mrow><munderover><mo>∑</mo><mrow><mi>n</mi><mo>=</mo><mn>0</mn></mrow><mi>∞</mi></munderover><mo></mo><mstyle><mtext> </mtext></mstyle><mo></mo><mrow><mi>A</mi><mo></mo><mrow><mover><mo>∏</mo><mstyle><mtext> </mtext></mstyle></mover><mo></mo><mrow><mo>(</mo><mfrac><mrow><mn>2</mn><mo></mo><mrow><mo>(</mo><mrow><mi>t</mi><mo>-</mo><mi>nT</mi><mo>-</mo><msub><mi>t</mi><mn>270</mn></msub></mrow><mo>)</mo></mrow></mrow><mi>T</mi></mfrac><mo>)</mo></mrow></mrow></mrow></mrow></mrow></mtd><mtd><mrow><mo>(</mo><mn>8</mn><mo>)</mo></mrow></mtd></mtr></mtable></math><img file="US20030227983A1-20031211-M00006.TIF" id="EMI-M00006" he="108.0135" wi="216.027" img-format="tif" img-content="mf" /><attachments><attachment idref="MATHEMATICA-00006" attachment-type="nb" file="US20030227983A1-20031211-M00006.NB" /></attachments></maths>
[0118] wherein,
[0119] in0 represents the 0 degree waveform <b>801</b>-<b>1</b>,
[0120] in90 represents the 90 degree waveform <b>801</b>-<b>2</b>,
[0121] in180 represents the 180 degree waveform <b>801</b>-<b>3</b>, and
[0122] in270 represents the 270 degree waveform <b>801</b>-<b>4</b>.
[0123] The primary function of each of the individual delay circuits A1-AN and B1-BN in FIG. 8 is to provide an approximate delay to each signal and combine the two hard-wired outputs, creating timing characteristics which are an average of the individual waveforms, where the averaging effect is shown in FIG. 13B. For example, the input to the delay circuit B-<b>1</b> comes from two hardwired outputs with inputs of in0 and in180 from the delay circuits A-<b>1</b> and A-<b>3</b>, respectively. Assuming that in<b>0</b> is defined as the zero degree reference, the timing of inB<b>1</b> will be determined by the following:
[0124] in-to-out0 propagation delay of the delay circuit A-<b>1</b> (where the delay is referenced as DA1:0 in the equations below)
[0125] Timing uncertainties associated with in180 (where the timing is represented in t<sub>180 </sub>in the equations below)
[0126] in-to-out180 propagation delay of delay circuit A<b>3</b> (where the delay is referenced as DA3:180 in the equations below)
[0127] The input signals and delays are viewed as random variables whose probability density functions (PDF) are uniformily distributed (in a worst case) over some range about their expected values or means. In some applications, the PDFs may be much more complex but the uniform assumption contemplates a worst case scenario of practical concern. Since components of the delays and waveforms are random variables, we may employ ideas from probability and statistics to address the method by which averaged phase values are obtained at the circuit output. For arbitrary PDFs associated with sums of random variables, the central limit theorm may be invoked to facilitate an understanding of how final averages or expected values of phases can be extracted.
[0128] Understanding the periodic nature of the rectangular pulse function where a delay of integer periods (T) produces like timing and amplitudes, and dropping the amplitude (A), the out0 rising edge of the delay circuit A-<b>3</b> in FIG. 8 can be described in a modified notation as:
A1out0=Π<sub>RE</sub>(in0+DA1:0) (9)
[0129] This represents a unity amplitude pulse whose rising edge occurs at a time determined by the input timing (i<b>0</b>) and the effective delay through delay circuit A<b>1</b>(DA<b>1</b>:<b>0</b>), which in turn is related to the driving point and load impedances as well as the branch impedances of the circuit. Likewise, the other component of inB<b>1</b> is derived from in180:
A3out180=Π<sub>RE</sub>(in180+DA3:180) (10)
[0130] The hard-wired combination of these two signals is a unity amplitude pulse whose rising edge occurs at the average time of the two components. Also, since this is actually a periodic pulse with period T, the subtraction or addition of integer periods will not alter the edge timing, but assists in the analysis using the modified pulse notation. One period is subtracted from any single delay path which produces an approximate delay of 1 period (360 degrees) or more. The following expressions are therefore equivalent:
A3out180=Π<sub>RE</sub>(in180+DA3:180)=Π<sub>RE</sub>(in180+DA3:180−T) (11)
[0131] The input to the delay circuit B<b>1</b> can now be described as averaging A<b>1</b>out0 with A<b>3</b>out 180: <maths id="MATH-US-00007" num="7"><math overflow="scroll"><mtable><mtr><mtd><mrow><mrow><mi>inB</mi><mo></mo><mstyle><mtext> </mtext></mstyle><mo></mo><mn>1</mn></mrow><mo>=</mo><mrow><munder><mo>∏</mo><mi>RE</mi></munder><mo></mo><mfrac><mrow><mo>(</mo><mrow><mrow><mo>(</mo><mrow><mrow><mi>i</mi><mo></mo><mstyle><mtext> </mtext></mstyle><mo></mo><mi>n</mi><mo></mo><mstyle><mtext> </mtext></mstyle><mo></mo><mn>0</mn></mrow><mo>+</mo><mrow><mi>DA1</mi><mo>:</mo><mn>0</mn></mrow></mrow><mo>)</mo></mrow><mo>+</mo><mrow><mo>(</mo><mrow><mrow><mi>i</mi><mo></mo><mstyle><mtext> </mtext></mstyle><mo></mo><mi>n</mi><mo></mo><mstyle><mtext> </mtext></mstyle><mo></mo><mn>180</mn></mrow><mo>+</mo><mrow><mi>DA3</mi><mo>:</mo><mrow><mn>180</mn><mo>-</mo><mi>T</mi></mrow></mrow></mrow><mo>)</mo></mrow></mrow><mo>)</mo></mrow><mn>2</mn></mfrac></mrow></mrow></mtd><mtd><mrow><mo>(</mo><mn>12</mn><mo>)</mo></mrow></mtd></mtr></mtable></math><img file="US20030227983A1-20031211-M00007.TIF" id="EMI-M00007" he="22.08465" wi="216.027" img-format="tif" img-content="mf" /><attachments><attachment idref="MATHEMATICA-00007" attachment-type="nb" file="US20030227983A1-20031211-M00007.NB" /></attachments></maths>
[0132] This is a unit amplitude pulse whose rising edge occurs at a time: <maths id="MATH-US-00008" num="8"><math overflow="scroll"><mtable><mtr><mtd><mrow><mi>t</mi><mo>=</mo><mfrac><mrow><mo>(</mo><mrow><mrow><mo>(</mo><mrow><mrow><mrow><mi>i</mi><mo></mo><mstyle><mtext> </mtext></mstyle><mo></mo><mi>n</mi><mo></mo><mstyle><mtext> </mtext></mstyle><mo></mo><mn>0</mn></mrow><mo>+</mo><mrow><mi>DA</mi><mo></mo><mstyle><mtext> </mtext></mstyle><mo></mo><mn>1</mn></mrow></mrow><mo>:</mo><mn>0</mn></mrow><mo>)</mo></mrow><mo>+</mo><mrow><mo>(</mo><mrow><mrow><mrow><mi>i</mi><mo></mo><mstyle><mtext> </mtext></mstyle><mo></mo><mi>n</mi><mo></mo><mstyle><mtext> </mtext></mstyle><mo></mo><mn>180</mn></mrow><mo>+</mo><mrow><mi>DA</mi><mo></mo><mstyle><mtext> </mtext></mstyle><mo></mo><mn>3</mn></mrow></mrow><mo>:</mo><mrow><mn>180</mn><mo>-</mo><mi>T</mi></mrow></mrow><mo>)</mo></mrow></mrow><mo>)</mo></mrow><mn>2</mn></mfrac></mrow></mtd><mtd><mrow><mo>(</mo><mn>13</mn><mo>)</mo></mrow></mtd></mtr></mtable></math><img file="US20030227983A1-20031211-M00008.TIF" id="EMI-M00008" he="18.00225" wi="216.027" img-format="tif" img-content="mf" /><attachments><attachment idref="MATHEMATICA-00008" attachment-type="nb" file="US20030227983A1-20031211-M00008.NB" /></attachments></maths>
[0133] where:
[0134] in0, in180=edge timing of the inputs in0 and in180
[0135] DA1:0, DA3:180=propagation delay through the blocks A<b>1</b> and A<b>3</b>
[0136] T=period of the input waveforms
[0137] The timing associated with in180 would ideally be shifted by 180 degrees (T/2) from in<b>0</b>. If in<b>0</b> were defined as zero for an 800 MHz system: <maths id="MATH-US-00009" num="9"><math overflow="scroll"><mtable><mtr><mtd><mrow><mrow><mi>i</mi><mo></mo><mstyle><mtext> </mtext></mstyle><mo></mo><mi>n</mi><mo></mo><mstyle><mtext> </mtext></mstyle><mo></mo><mn>180</mn></mrow><mo>=</mo><mrow><mrow><mrow><mi>i</mi><mo></mo><mstyle><mtext> </mtext></mstyle><mo></mo><mi>n</mi><mo></mo><mstyle><mtext> </mtext></mstyle><mo></mo><mn>0</mn></mrow><mo>+</mo><mfrac><mi>T</mi><mn>2</mn></mfrac></mrow><mo>=</mo><mrow><mrow><mn>0</mn><mo>+</mo><mfrac><mrow><mn>1.25</mn><mo></mo><mstyle><mtext> </mtext></mstyle><mo></mo><mi>n</mi><mo></mo><mstyle><mtext> </mtext></mstyle><mo></mo><mi>S</mi></mrow><mn>2</mn></mfrac></mrow><mo>=</mo><mrow><mn>625</mn><mo></mo><mi>pS</mi></mrow></mrow></mrow></mrow></mtd><mtd><mrow><mo>(</mo><mn>14</mn><mo>)</mo></mrow></mtd></mtr></mtable></math><img file="US20030227983A1-20031211-M00009.TIF" id="EMI-M00009" he="18.00225" wi="216.027" img-format="tif" img-content="mf" /><attachments><attachment idref="MATHEMATICA-00009" attachment-type="nb" file="US20030227983A1-20031211-M00009.NB" /></attachments></maths>
[0138] The actual timing of in180 will vary due to timing inaccuracies, noise, and temperature/process variations. Referring to FIG. 8, the inputs to each of the delay circuits in column B can be defined: <maths id="MATH-US-00010" num="10"><math overflow="scroll"><mtable><mtr><mtd><mrow><mrow><mi>inB</mi><mo></mo><mstyle><mtext> </mtext></mstyle><mo></mo><mn>1</mn></mrow><mo>=</mo><mrow><munder><mo>∏</mo><mi>RE</mi></munder><mo></mo><mfrac><mrow><mo>(</mo><mrow><mrow><mo>(</mo><mrow><mrow><mrow><mi>i</mi><mo></mo><mstyle><mtext> </mtext></mstyle><mo></mo><mi>n</mi><mo></mo><mstyle><mtext> </mtext></mstyle><mo></mo><mn>0</mn></mrow><mo>+</mo><mrow><mi>DA</mi><mo></mo><mstyle><mtext> </mtext></mstyle><mo></mo><mn>1</mn></mrow></mrow><mo>:</mo><mn>0</mn></mrow><mo>)</mo></mrow><mo>+</mo><mrow><mo>(</mo><mrow><mrow><mrow><mi>i</mi><mo></mo><mstyle><mtext> </mtext></mstyle><mo></mo><mi>n</mi><mo></mo><mstyle><mtext> </mtext></mstyle><mo></mo><mn>1</mn><mo></mo><mstyle><mtext> </mtext></mstyle><mo></mo><mn>80</mn></mrow><mo>+</mo><mrow><mi>D</mi><mo></mo><mstyle><mtext> </mtext></mstyle><mo></mo><mi>A</mi><mo></mo><mstyle><mtext> </mtext></mstyle><mo></mo><mn>3</mn></mrow></mrow><mo>:</mo><mrow><mn>180</mn><mo>-</mo><mi>T</mi></mrow></mrow><mo>)</mo></mrow></mrow><mo>)</mo></mrow><mn>2</mn></mfrac></mrow></mrow></mtd><mtd><mrow><mo>(</mo><mn>15</mn><mo>)</mo></mrow></mtd></mtr><mtr><mtd><mrow><mrow><mi>inB</mi><mo></mo><mstyle><mtext> </mtext></mstyle><mo></mo><mn>2</mn></mrow><mo>=</mo><mrow><munder><mo>∏</mo><mi>RE</mi></munder><mo></mo><mfrac><mrow><mo>(</mo><mrow><mrow><mo>(</mo><mrow><mrow><mrow><mi>i</mi><mo></mo><mstyle><mtext> </mtext></mstyle><mo></mo><mi>n</mi><mo></mo><mstyle><mtext> </mtext></mstyle><mo></mo><mn>90</mn></mrow><mo>+</mo><mrow><mi>DA</mi><mo></mo><mstyle><mtext> </mtext></mstyle><mo></mo><mn>2</mn></mrow></mrow><mo>:</mo><mn>0</mn></mrow><mo>)</mo></mrow><mo>+</mo><mrow><mo>(</mo><mrow><mrow><mrow><mi>i</mi><mo></mo><mstyle><mtext> </mtext></mstyle><mo></mo><mi>n2</mi><mo></mo><mstyle><mtext> </mtext></mstyle><mo></mo><mn>70</mn></mrow><mo>+</mo><mrow><mi>D</mi><mo></mo><mstyle><mtext> </mtext></mstyle><mo></mo><mi>A</mi><mo></mo><mstyle><mtext> </mtext></mstyle><mo></mo><mn>4</mn></mrow></mrow><mo>:</mo><mrow><mn>180</mn><mo>-</mo><mi>T</mi></mrow></mrow><mo>)</mo></mrow></mrow><mo>)</mo></mrow><mn>2</mn></mfrac></mrow></mrow></mtd><mtd><mrow><mo>(</mo><mn>16</mn><mo>)</mo></mrow></mtd></mtr><mtr><mtd><mrow><mrow><mi>inB</mi><mo></mo><mstyle><mtext> </mtext></mstyle><mo></mo><mn>3</mn></mrow><mo>=</mo><mrow><munder><mo>∏</mo><mi>RE</mi></munder><mo></mo><mfrac><mrow><mo>(</mo><mrow><mrow><mo>(</mo><mrow><mrow><mrow><mi>i</mi><mo></mo><mstyle><mtext> </mtext></mstyle><mo></mo><mi>n</mi><mo></mo><mstyle><mtext> </mtext></mstyle><mo></mo><mn>18</mn><mo></mo><mstyle><mtext> </mtext></mstyle><mo></mo><mn>0</mn></mrow><mo>+</mo><mrow><mi>DA</mi><mo></mo><mstyle><mtext> </mtext></mstyle><mo></mo><mn>3</mn></mrow></mrow><mo>:</mo><mn>0</mn></mrow><mo>)</mo></mrow><mo>+</mo><mrow><mo>(</mo><mrow><mrow><mrow><mi>i</mi><mo></mo><mstyle><mtext> </mtext></mstyle><mo></mo><mi>n</mi><mo></mo><mstyle><mtext> </mtext></mstyle><mo></mo><mn>0</mn></mrow><mo>+</mo><mrow><mi>DA</mi><mo></mo><mstyle><mtext> </mtext></mstyle><mo></mo><mn>1</mn></mrow></mrow><mo>:</mo><mn>180</mn></mrow><mo>)</mo></mrow></mrow><mo>)</mo></mrow><mn>2</mn></mfrac></mrow></mrow></mtd><mtd><mrow><mo>(</mo><mn>17</mn><mo>)</mo></mrow></mtd></mtr><mtr><mtd><mrow><mrow><mi>inB</mi><mo></mo><mstyle><mtext> </mtext></mstyle><mo></mo><mn>4</mn></mrow><mo>=</mo><mrow><munder><mo>∏</mo><mi>RE</mi></munder><mo></mo><mfrac><mrow><mo>(</mo><mrow><mrow><mo>(</mo><mrow><mrow><mrow><mi>i</mi><mo></mo><mstyle><mtext> </mtext></mstyle><mo></mo><mi>n</mi><mo></mo><mstyle><mtext> </mtext></mstyle><mo></mo><mn>270</mn></mrow><mo>+</mo><mrow><mi>DA</mi><mo></mo><mstyle><mtext> </mtext></mstyle><mo></mo><mn>4</mn></mrow></mrow><mo>:</mo><mn>0</mn></mrow><mo>)</mo></mrow><mo>+</mo><mrow><mo>(</mo><mrow><mrow><mrow><mi>i</mi><mo></mo><mstyle><mtext> </mtext></mstyle><mo></mo><mi>n</mi><mo></mo><mstyle><mtext> </mtext></mstyle><mo></mo><mn>90</mn></mrow><mo>+</mo><mrow><mi>DA</mi><mo></mo><mstyle><mtext> </mtext></mstyle><mo></mo><mn>2</mn></mrow></mrow><mo>:</mo><mn>180</mn></mrow><mo>)</mo></mrow></mrow><mo>)</mo></mrow><mn>2</mn></mfrac></mrow></mrow></mtd><mtd><mrow><mo>(</mo><mn>18</mn><mo>)</mo></mrow></mtd></mtr></mtable></math><img file="US20030227983A1-20031211-M00010.TIF" id="EMI-M00010" he="100.10385" wi="216.027" img-format="tif" img-content="mf" /><attachments><attachment idref="MATHEMATICA-00010" attachment-type="nb" file="US20030227983A1-20031211-M00010.NB" /></attachments></maths>
[0139] Hard-wiring the appropriate outputs of the blocks in column B and time averaging the edge transitions produces the final outputs of the refinement stage, out0, out90, out180, and out270: <maths id="MATH-US-00011" num="11"><math overflow="scroll"><mtable><mtr><mtd><mrow><mi>out90</mi><mo>=</mo><mfrac><mrow><mrow><msub><mo>∏</mo><mi>RE</mi></msub><mo></mo><mrow><mo>{</mo><mrow><mfrac><mrow><mo>(</mo><mrow><mrow><mo>(</mo><mrow><mi>i0</mi><mo>+</mo><mrow><mi>DA1</mi><mo>:</mo><mn>0</mn></mrow></mrow><mo>)</mo></mrow><mo>+</mo><mrow><mo>(</mo><mrow><mi>i180</mi><mo>+</mo><mrow><mi>DA3</mi><mo>:</mo><mrow><mn>180</mn><mo>-</mo><mi>T</mi></mrow></mrow></mrow><mo>)</mo></mrow></mrow><mo>)</mo></mrow><mn>2</mn></mfrac><mo>+</mo><mrow><mi>DB1</mi><mo>:</mo><mrow><mn>90</mn><mo>+</mo><mfrac><mrow><mo>(</mo><mrow><mrow><mo>(</mo><mrow><mi>i270</mi><mo>+</mo><mrow><mi>DA4</mi><mo>:</mo><mn>0</mn></mrow></mrow><mo>)</mo></mrow><mo>+</mo><mrow><mo>(</mo><mrow><mi>i90</mi><mo>+</mo><mrow><mi>DA2</mi><mo>:</mo><mrow><mn>180</mn><mo>-</mo><mi>T</mi></mrow></mrow></mrow><mo>)</mo></mrow></mrow><mo>)</mo></mrow><mn>2</mn></mfrac><mo>+</mo><mrow><mi>DB4</mi><mo>:</mo><mrow><mn>180</mn><mo>-</mo><mi>T</mi></mrow></mrow></mrow></mrow></mrow><mo>}</mo></mrow></mrow><mo></mo><mstyle><mtext> </mtext></mstyle></mrow><mn>2</mn></mfrac></mrow></mtd></mtr><mtr><mtd><mrow><mi>out180</mi><mo>=</mo><mfrac><mrow><mrow><msub><mo>∏</mo><mi>RE</mi></msub><mo></mo><mrow><mo>{</mo><mrow><mfrac><mrow><mo>(</mo><mrow><mrow><mo>(</mo><mrow><mi>i90</mi><mo>+</mo><mrow><mi>DA2</mi><mo>:</mo><mn>0</mn></mrow></mrow><mo>)</mo></mrow><mo>+</mo><mrow><mo>(</mo><mrow><mi>i270</mi><mo>+</mo><mrow><mi>DA4</mi><mo>:</mo><mrow><mn>180</mn><mo>-</mo><mi>T</mi></mrow></mrow></mrow><mo>)</mo></mrow></mrow><mo>)</mo></mrow><mn>2</mn></mfrac><mo>+</mo><mfrac><mrow><mo>(</mo><mrow><mrow><mo>(</mo><mrow><mi>i90</mi><mo>+</mo><mrow><mi>DA2</mi><mo>:</mo><mn>0</mn></mrow></mrow><mo>)</mo></mrow><mo>+</mo><mrow><mo>(</mo><mrow><mi>i270</mi><mo>+</mo><mrow><mi>DA4</mi><mo>:</mo><mrow><mn>180</mn><mo>-</mo><mi>T</mi></mrow></mrow></mrow><mo>)</mo></mrow></mrow><mo>)</mo></mrow><mn>2</mn></mfrac></mrow><mo>}</mo></mrow></mrow><mo></mo><mstyle><mtext> </mtext></mstyle></mrow><mn>2</mn></mfrac></mrow></mtd></mtr></mtable></math><img file="US20030227983A1-20031211-M00011.TIF" id="EMI-M00011" he="53.04285" wi="390.0393" img-format="tif" img-content="mf" /><attachments><attachment idref="MATHEMATICA-00011" attachment-type="nb" file="US20030227983A1-20031211-M00011.NB" /></attachments></maths>
[0140] In one embodiment, the out90 and out180 are random variables also since their components can be viewed as random variables. A significant number of processing stages will result in the observable possessing a Gaussian-like random variable which implies that the expected value is easily extracted by averaging, which also reduces the variance of the final estimate.
[0141] Ideally, the time difference between rising edges of these two signals should be one fourth the period or 90 degrees. Subtracting the time difference between the 180 and 90 degree output results in: <maths id="MATH-US-00012" num="12"><math overflow="scroll"><mtable><mtr><mtd><mrow><mrow><mi>Δ</mi><mo></mo><mstyle><mtext> </mtext></mstyle><mo></mo><mi>t</mi></mrow><mo>=</mo><mrow><mfrac><mrow><mfrac><mrow><mo>(</mo><mrow><mrow><mo>(</mo><mrow><mi>i0</mi><mo>+</mo><mrow><mi>DA1</mi><mo>:</mo><mn>0</mn></mrow></mrow><mo>)</mo></mrow><mo>+</mo><mrow><mo>(</mo><mrow><mi>i180</mi><mo>+</mo><mrow><mi>DA3</mi><mo>:</mo><mrow><mn>180</mn><mo>-</mo><mi>T</mi></mrow></mrow></mrow><mo>)</mo></mrow></mrow></mrow><mn>2</mn></mfrac><mo>+</mo><mrow><mi>DB1</mi><mo>:</mo><mrow><mn>90</mn><mo>+</mo><mfrac><mrow><mo>(</mo><mrow><mrow><mo>(</mo><mrow><mi>i270</mi><mo>+</mo><mrow><mi>DA4</mi><mo>:</mo><mn>0</mn></mrow></mrow><mo>)</mo></mrow><mo>+</mo><mrow><mo>(</mo><mrow><mi>i90</mi><mo>+</mo><mrow><mi>DA2</mi><mo>:</mo><mn>180</mn></mrow></mrow><mo>)</mo></mrow></mrow></mrow><mn>2</mn></mfrac><mo>+</mo><mrow><mi>DB4</mi><mo>:</mo><mrow><mn>180</mn><mo>-</mo><mi>T</mi></mrow></mrow></mrow></mrow></mrow><mn>2</mn></mfrac><mo>-</mo></mrow></mrow></mtd></mtr><mtr><mtd><mfrac><mrow><mfrac><mrow><mo>(</mo><mrow><mrow><mo>(</mo><mrow><mi>i90</mi><mo>+</mo><mrow><mi>DA2</mi><mo>:</mo><mn>0</mn></mrow></mrow><mo>)</mo></mrow><mo>+</mo><mrow><mo>(</mo><mrow><mi>i270</mi><mo>+</mo><mrow><mi>DA4</mi><mo>:</mo><mrow><mn>180</mn><mo>-</mo><mi>T</mi></mrow></mrow></mrow><mo>)</mo></mrow></mrow></mrow><mn>2</mn></mfrac><mo>+</mo><mfrac><mrow><mo>(</mo><mrow><mrow><mo>(</mo><mrow><mi>i90</mi><mo>+</mo><mrow><mi>DA2</mi><mo>:</mo><mn>0</mn></mrow></mrow><mo>)</mo></mrow><mo>+</mo><mrow><mo>(</mo><mrow><mi>i270</mi><mo>+</mo><mrow><mi>DB4</mi><mo>:</mo><mrow><mn>180</mn><mo>-</mo><mi>T</mi></mrow></mrow></mrow><mo>)</mo></mrow></mrow><mo>)</mo></mrow><mn>2</mn></mfrac></mrow><mn>2</mn></mfrac></mtd></mtr></mtable></math><img file="US20030227983A1-20031211-M00012.TIF" id="EMI-M00012" he="53.04285" wi="332.2053" img-format="tif" img-content="mf" /><attachments><attachment idref="MATHEMATICA-00012" attachment-type="nb" file="US20030227983A1-20031211-M00012.NB" /></attachments></maths>
[0142] Assuming the delay circuits in column and column B are well matched (DA1:0=DA2:0=DA3:0=DA4:0 and DB1:0=DB2:0=DB3:0=DB4:0) and simplifying: <maths id="MATH-US-00013" num="13"><math overflow="scroll"><mtable><mtr><mtd><mrow><mrow><mi>Δ</mi><mo></mo><mstyle><mtext> </mtext></mstyle><mo></mo><mi>t</mi></mrow><mo>=</mo><mrow><mo>-</mo><mrow><mfrac><mi>T</mi><mn>4</mn></mfrac><mo>.</mo></mrow></mrow></mrow></mtd><mtd><mrow><mo>(</mo><mn>22</mn><mo>)</mo></mrow></mtd></mtr></mtable></math><img file="US20030227983A1-20031211-M00013.TIF" id="EMI-M00013" he="18.00225" wi="216.027" img-format="tif" img-content="mf" /><attachments><attachment idref="MATHEMATICA-00013" attachment-type="nb" file="US20030227983A1-20031211-M00013.NB" /></attachments></maths>
[0143] Equation 22 indicates the relative phase between output signals <b>805</b> is substantially close to 90 degrees. The statistical mean of the result is a weak function of the initial phase error at the inputs <b>801</b>. Furthermore, the result is also a statistical mean of individual delays through the delay circuits <b>802</b> and <b>702</b> in FIG. 8. Whereas, conventional quadrature generators need to have identical delay circuits in order to produce perfect phase. From the equations above, it is seen that the timing imperfections (all inputs and delay blocks) that form the outputs are summed and averaged and applied equally to each output. Although the absolute delay from the input to the output of the refinement stage will still vary with temperature, process, etc., the difference in delays between adjacent outputs is forced to T/4 by the circuit architecture.
[0144] Furthermore, the refinement stage <b>606</b> has a wide bandwidth since any of the individual delays (<b>802</b> or <b>702</b>) are not significant unless it affects the systems ability to perform waveform averaging. The ability to accurately perform averaging breaks down if the delay circuits are not in the neighborhood of the ideal delay. In one embodiment, for example, the bandwidth of a 4 stage 800 MHz quadrature generator was found to be over 500 MHz. Additional refinement stages can provide additional bandwidth.
[0145]FIG. 16 illustrates an example LO generation circuit <b>1600</b>, capable of generating quadrature pulsed control signals <b>1614</b>, based a differential input signal <b>1601</b>. A differential amplifier <b>1602</b> receives the input signal <b>1601</b> and amplifies the input signal <b>1601</b>, to generate an amplified signal <b>1603</b>. The differential amplifier <b>1602</b> is included because the differential input signal <b>1601</b> can have a variable amplitude, and it is desirable to have a constant amplitude signal <b>1603</b> during quadrature signal generation. A divide-by-two circuit <b>1604</b> frequency divides the differential amplified signal <b>1603</b> by two, to generate a frequency divided signal <b>1605</b>. For example, in one embodiment, the differential input signal has a frequency of 1.6 GHz, and the divide by two circuit divides the frequency down to 800 MHz. A level-shift circuit <b>1606</b> DC level shifts the signal <b>1605</b> to generate a level-shifted output signal <b>1607</b> that is appropriate for the quadrature generator <b>600</b>. The quadrature generator <b>600</b> generates quadrature signals <b>1609</b> based on the level-shifted signal <b>1607</b>. The pulse generator <b>1610</b> receives the signals <b>1609</b>, and generates output pulses <b>1614</b> that have a quadrature relationship and have a desired pulse width. The differential amplifier <b>1602</b> and the divide-by-two circuit <b>1604</b> are biased using the bias regulator <b>1612</b>.
[0146] The output pulses <b>1614</b> can be used as the control signals <b>108</b><i>a</i>-<i>d </i>that control the switches <b>126</b> in the balanced modulator <b>100</b> of FIG. 1. The pulse width of the output pulses <b>1614</b> can be set to provide a desired sampling period for the switches <b>126</b> in the balanced modulator <b>100</b> to improve energy transfer to a desired harmonic in the harmonically rich signal <b>103</b>.
[0147] 6. Performance
[0148] Operating on 800 MHz signals, the quadrature signal generator in FIG. 6 has shown to produce quadrature signals with less than +/−1 degree of phase error. Furthermore, the quadrature generator <b>600</b> is also resistant to input phase error. Experiments have shown that the phase error can vary from +/−12 degrees, and the output phase error only varies from +/−150 milli-degree. Still further, the quadrature generator <b>600</b> is also resistant to input frequency error. Experiments have shown that the input frequency can vary can vary 1.2 GHz to 2.2 GHz, and the output phase error varies minimally.
[0149] 7. Conclusion
[0150] Example embodiments of the methods, systems, and components of the present invention have been described herein. As noted elsewhere, these example embodiments have been described for illustrative purposes only, and are not limiting. Other embodiments are possible and are covered by the invention. Such other embodiments will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. Thus, the breadth and scope of the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.
Contents4
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2 members in 1 office
Priority claims5
| Document | Office | Kind | Date |
|---|---|---|---|
| 38648402 | United States of America | P | |
| 45362203 | United States of America | A | |
| 60386484 | – | – | – |
| US20020386484P | – | – | – |
| US20030453622 | – | – | – |
Members2
| Document | Office | Kind | |
|---|---|---|---|
| US2003227983A1 | United States of America | A1 | |
| US7321640B2 | United States of America | B2 |
8 legal events, as the office reported them to INPADOC
Over the term
Point at a mark for the eventEvents
| Event | Code | |
|---|---|---|
| Lapsed due to failure to pay maintenance feeLapsedFP | FP | |
| Lapse for failure to pay maintenance feesLapsedPATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITYLAPS | LAPS | |
| Information on status: patent discontinuationPATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362STCH | STCH | |
| Fee payment procedureMAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITYFEPP | FEPP | |
| Fee paymentFPAY | FPAY | |
| Fee paymentFPAY | FPAY | |
| Information on status: patent grantGrantedPATENTED CASESTCF | STCF | |
| AssignmentAS | AS |
Numbers
- Publication, DOCDB
- 2003227983
- Publication, EPODOC
- US2003227983
- Application
- 10453622
- Application, DOCDB
- 45362203
- Application, EPODOC
- US20030453622
Titles
- English
- Active polyphase inverter filter for quadrature signal generation
Classification
- CPC, 1
- H04L27/364
- IPC, 1
- H04L27 36
- USPC, 1
- 375302000