Semiconductor device and method for driving the same

P-0001[0001] This is a continuation of Application PCT/JP02/06250, filed Jun. 21, 2002, now abandoned.

BACKGROUND OF THE INVENTION

P-0002[0002] The present invention relates to semiconductor devices and methods for driving the same. More particularly, the present invention relates to semiconductor devices which are applicable to neural network computers (neurocomputers), for example, and allows multilevel information to be stored therein, and also relates to methods for driving the devices.

P-0003[0003] As multimedia has been developed, semiconductor devices are more and more required to improve their performance. For example, to process a large capacity of digital information, even CPUs of personal computers operating at high speeds of 1 GHz or more have come onto the market.

P-0004[0004] To meet such a demand for improving the performance of semiconductor devices, semiconductor fabricators have improved the performance mainly with techniques of downsizing the semiconductor devices.

P-0005[0005] However, even physical limitations are now pointed out in downsizing the semiconductor devices, and therefore, improvement in the semiconductor devices by further downsizing is not expected in consideration of fabrication cost.

P-0006[0006] To solve this problem, in place of digital information processing techniques to date that perform computations using a binary signal of “1” or “0”, multilevel cell technologies for converting information into three or four levels, technologies for computers (neurocomputers) that perform computation by mimicking the behavior of the brain of an animal with the application of the multilevel cell technologies, and the like, have been researched.

P-0007[0007] The brain of an animal is basically composed of nerve cells, which are called neurons and have a computing function, and nerve fibers, each of which transmits a computing result of a neuron to another neuron, i.e., serves as so-called wiring.

P-0008[0008] A neurocomputer is composed of a large number of neuron units, which are made of semiconductor elements corresponding to neurons, and a large number of synapse units, which transmits signals to the neuron units and add weights to the signals. Combinations of the neuron units and the synapse units are hereinafter referred to as neuron elements.

P-0009[0009] When information signals having different “weights” and being output from a plurality of previous-stage neuron elements are input to a neuron element, the information signals are added to this neuron element. When the sum of the information signals exceeds a threshold value, the neuron element “fires” to allow a signal to be output to a subsequent-stage neuron element. Information is processed by repeating this operation.

P-0010[0010] A process by which the brain of an animal learns is considered a process of varying weights on synaptic connections. That is to say, the weights are gradually modified with respect to various input signals so as to obtain an appropriate output, and finally the weights stay at appropriate values.

P-0011[0011] To configure a neural network having such a leaning function, it is necessary to vary the strength on each synaptic connection as required and to store the varied strength. Therefore, the multilevel cell technologies have become essential for implementing neurocomputers.

P-0012[0012] The neurocomputer described above is an example of application of the multilevel cell technologies. Naturally, multilevel memories in which multilevel information is stored therein with stability have been researched actively. As is evident from these factors, the multilevel cell technologies for information have become extremely important for future semiconductor devices.

P-0013[0013] As an example of such multilevel cell technologies, a known technique for allowing information with at least three levels to be stored in a single memory cell was disclosed in Japanese Laid-Open Publication No. 8-124378.

P-0014[0014]FIG. 49 is a cross-sectional view showing a known semiconductor device functioning as a multilevel memory. As shown in FIG. 49, the known semiconductor device includes: a silicon substrate <b>1107</b>; well lines BUL<b>1</b> and BUL <b>2</b> buried in the silicon substrate <b>1107</b>; PZT films <b>1109</b> made of a ferroelectric and formed on the well lines BUL<b>1</b> and BUL <b>2</b>, respectively; a word line WL<b>1</b> formed on the PZT films <b>1109</b>; a bit line BL<b>1</b> formed over the word line WL<b>1</b> and the well line BUL<b>1</b>; and a bit line BL<b>2</b> formed over the word line WL<b>1</b> and the well line BUL<b>2</b>. Although not shown, source and drain are provided in each of the well lines BUL<b>1</b> and BUL<b>2</b>. The bit line BL<b>1</b> is connected to the drain in the well line BUL<b>1</b> via a bit contact (not shown), while the bit line BL<b>2</b> is connected to the drain in the well line BUL<b>2</b> via a bit contact.

P-0015[0015] Information is written by changing the polarization in the PZT film <b>1109</b> upon the application of a voltage to the word line WL<b>1</b> and the well lines BUL<b>1</b> and BUL<b>2</b>.

P-0016[0016]FIG. 50 is a graph showing a relationship between a voltage VGB applied to the gate electrode (=the potential at the gate electrode-the potential at the well) and the magnitude of the polarization of the ferroelectric (i.e., hysteresis characteristics) in each memory cell of the known device. Since the ferroelectric has hysteresis characteristics, the polarization state changes depending on the history of the applied voltage, and even after the voltage has been removed, the polarization state remains as indicated by a point A, B or C in FIG. 50. If a voltage V=V₁, at which the ferroelectric is in a saturated polarization state is applied and then removed, the polarization is at the point A. When a voltage is removed after the application of a voltage V=−V₂, the polarization is at the point C. If a voltage V=−V₁is applied and then removed, the polarization is at the point B.

P-0017[0017]FIG. 51 is a graph showing the relationship between a drain current I and a gate voltage VGB in a memory cell when the ferroelectric is in the state indicated by the point A, C or B in FIG. 50. In FIG. 51, the left-side curve, the middle curve and the right-side curve correspond to the states indicated by the points A, C and B, respectively. In the state indicated by the point A, the ferroelectric exhibits a large positive polarization, so that a threshold voltage VtA of the memory cell is lower than a threshold voltage VtC in the state indicated by the point C at which no polarization is exhibited. In the state indicated by the point B, the ferroelectric exhibits a large negative polarization, so that a threshold voltage VtB of the memory cell is higher than the threshold voltage VtC in the state indicated by the point C at which no polarization is exhibited. By thus providing the ferroelectric with the three polarization states indicated by the point A, C and B, the memory cell can be controlled to have three different levels of threshold voltages. Therefore, it is possible to store information with three levels in the memory cell corresponding to the values of these threshold voltages. The known technique described above indicates that if a polarization state between the points A and C is used, the number of levels can be further increased.

P-0018[0018] However, the known technique has a basic problem that the polarization state “C” is difficult to obtain accurately. Specifically, in the known technique, when a voltage is removed after the ferroelectric has exhibited a small polarization upon the application of an appropriate voltage, the polarization comes close to zero. However, as shown in FIG. 50, the hysteresis of the ferroelectric changes greatly in the vicinity of a coercive voltage Vc, while the absolute value of the voltage −V₂is essentially close to the coercive voltage Vc. Thus, the polarization of the ferroelectric is extremely difficult to control, resulting in that the polarization value after the removal of the voltage changes greatly only by a small variation in the voltage V₂caused by noise or the like. In addition to such a variation in the write voltage, variations in the crystal state and the thickness of the ferroelectric, for example, also vary the coercive voltage Vc. This results in difficulty in obtaining stable multilevel storage properties with high reliability and excellent reproducibility. The coercive voltage herein refers to a voltage required for changing the hysteresis of the ferroelectric largely to alter the distribution of the charge in a ferroelectric capacitor.

SUMMARY OF THE INVENTION

P-0019[0019] An object of the present invention is providing a highly reliable semiconductor device in which information can be stored with stability and which is applicable as a neuron element for a neurocomputer and a method for driving the semiconductor device.

P-0020[0020] A first semiconductor device of the present invention includes: a semiconductor substrate; and a memory in which a first capacitor, including a first upper electrode, a first dielectric layer and a first lower electrode and formed over the semiconductor substrate, and a second capacitor, including a second upper electrode, a second dielectric layer and a second lower electrode and formed over the semiconductor substrate, are disposed. The semiconductor device can store information with three or more levels. The first and second dielectric layers have hysteresis characteristics exhibiting mutually differing coercive voltages.

P-0021[0021] In this device, a metastable point is created on a hysteresis loop of the whole of the capacitors, thus allowing information with three or more levels to be stored with stability even when a write voltage varies.

P-0022[0022] The first and second capacitors may be polarized in one direction during operation. Then, at least one metastable point is created on the hysteresis loop due to the difference in coercive voltage between the first and second capacitors. As a result, information with three or more levels can be stored with stability.

P-0023[0023] The semiconductor device may further include a transistor including: a gate insulating film formed on the semiconductor substrate; and a gate electrode formed on the gate insulating film and made of a conductor film. Both of the first and second lower electrodes may be united with the gate electrode. Then, the number of process steps for fabricating a semiconductor device in which multilevel information can be stored with stability is reduced, thus reducing the fabrication cost.

P-0024[0024] The semiconductor device may further include: a gate insulating film formed on the semiconductor substrate; and a gate electrode formed on the gate insulating film and made of a conductor film. Each of the first and second lower electrodes may be connected to the gate electrode. Then, a voltage applied to the capacitors is transmitted to the gate electrode so that a drain current flowing upon the application of the gate voltage is varied depending on the state of the memory. As a result, multilevel information can be stored with stability.

P-0025[0025] In respective first-half stages in ranges in which the polarizations of the first and second capacitors are from zero to saturation, the polarizations of the first and second capacitors may vary at mutually different rates with change in voltage. Then, a metastable point can be created on the hysteresis loop of the whole of the capacitors as intended. That is to say, the storing operation is performed with stability even when the write voltage is varied by noise or the like.

P-0026[0026] Each of the first and second dielectric layers may include a ferroelectric layer. Then, polarization states corresponding to multiple levels are created depending on a remanent polarization after the application of the voltage to the capacitors, thus allowing a multilevel storing operation.

P-0027[0027] The first and second upper electrodes may be connected to each other. Then, write voltages can be applied using an identical line.

P-0028[0028] The first and second dielectric layers are preferably formed out of an identical film. Then, the area of the memory can be reduced, as compared to the case where the first and second dielectric layers are separately formed. In addition, the number of fabricating process steps can be also reduced.

P-0029[0029] The first and second dielectric layers are preferably made of an identical material, and the semiconductor device may further include a paraelectric capacitor connected in parallel with the first and second capacitors.

P-0030[0030] The semiconductor device preferably includes a capacitor interposed between the second capacitor and the gate electrode. Then, an apparent coercive voltage of the second capacitor can be varied, thus further enhancing the flexibility in designing.

P-0031[0031] The first and second dielectric layers may differ mutually in area. Then, the coercive voltages of the capacitors can be varied.

P-0032[0032] The first and second dielectric layers may be made of mutually different materials. Then, the first and second capacitors can be formed to have mutually different coercive voltages.

P-0033[0033] The first and second dielectric layers may differ mutually in thickness. Then, the first and second capacitors can be formed to have mutually different coercive voltages.

P-0034[0034] The area ratio between the electrodes of the first and second capacitors, i.e., (the area of the first capacitor)/(the area of the second capacitor), is in the range of 0.2 to 2, both inclusive. Then, if the first and second dielectric layers are made of an identical material, separation of stored information is excellent, resulting that information with three levels can be held with stability.

P-0035[0035] In particular, the area ratio between the electrodes of the first and second capacitors, i.e., (the area of the first capacitor)/(the area of the second capacitor), is in the range of 0.5 to 2, both inclusive. Then, separation of stored information is excellent, resulting that even information with four or more levels can be held with stability in the semiconductor device.

P-0036[0036] A second semiconductor device of the present invention includes: a control-voltage supply unit; a field-effect transistor including a gate electrode having a function of accumulating a charge; and a capacitor and a resistor, disposed in parallel and interposed between the control-voltage supply unit and the gate electrode. The semiconductor device can store multilevel information.

P-0037[0037] In this device, current flows through the resistor upon the application of a write voltage to the resistor, so that a charge is accumulated in the gate electrode to vary the threshold value of the field-effect transistor. In addition, the field-effect transistor has a plurality of states which are held for a given period, so that multilevel information can be stored. Furthermore, the information is read out according to the variation in a drain current in the field-effect transistor. Thus, the semiconductor device is usable not only as a multilevel memory but also as an element for assigning weights to signals in a neurocomputer.

P-0038[0038] A charge may be injected from the control-voltage supply unit into the gate electrode. Then a charge can be injected in a manner different from that in a flash memory.

P-0039[0039] The semiconductor device may function as an analog memory in which multilevel information can be stored continuously according to the amount of the charge accumulated in the gate electrode. Then, the device is usable for various purposes such as weighing in a neurocomputer, as compared to a flash memory, for example.

P-0040[0040] The resistor may be made of a dielectric material. Then, the charge accumulated in the gate electrode is unlikely to leak. Thus, input information can be held for a longer period than in the case where the resistor is made of undoped silicon, for example. In addition, since the resistor can be formed on the transistor, the cell size can be reduced.

P-0041[0041] The control-voltage supply unit may be as an upper electrode. The gate electrode of the field-effect transistor may be connected to an intermediate electrode. The capacitor may be a dielectric capacitor including the upper electrode, the intermediate electrode and a dielectric layer interposed between the upper electrode and the intermediate electrode. The dielectric layer may have a resistance component functioning as the resistor. For example, the dielectric layer of the dielectric capacitor and the resistor may be one and the same. In such a case, the area of the device is reduced, as compared to the case where the resistor and the dielectric layer are separately provided.

P-0042[0042] The resistor preferably has a resistance value that varies according to the strength of an electric field applied to the resistor. Then, the amount of the charge accumulated in the gate electrode can be adjusted.

P-0043[0043] The resistor preferably has a resistance value which is almost constant when the strength of an electric field applied to the resistor is at a level equal to or smaller than a given level and which decreases when the strength of the electric field exceeds the given level. Then, the device can be driven by a plurality of methods, e.g., by accumulating a charge in the gate electrode in a short time by applying an electric field exceeding a given value or by accumulating a charge for a relatively long time by applying an electric field not higher than the given value.

P-0044[0044] A pass current flowing through the resistor preferably increases substantially in proportion to a voltage applied to both ends of the resistor when the absolute value of the applied voltage is equal to or smaller than a given value, while the pass current preferably increases exponentially when the absolute value of the applied voltage exceeds the given value. Then, the device can be driven by a plurality of methods as described above.

P-0045[0045] A pass current flowing per unit area of the resistor is preferably 100 [mA/cm²] or less in a voltage range in which the pass current flowing through the resistor increases substantially in proportion to the voltage. Then, written information or the history of the written information can be held for a given period. The smaller the pass current is, the longer the holding time (the recovery time) of the information is required.

P-0046[0046] The capacitor may include a ferroelectric layer, and the resistor may be made of a ferroelectric material. Then, the amount of the charge accumulated in each of the intermediate electrode and the gate electrode can be also varied depending on the polarization direction in the ferroelectric layer. As a result, the semiconductor device of the present invention is usable as a multilevel memory with more levels than in the case where a capacitor including a paraelectric layer is used. In addition, the inventive device is applicable as a neuron element with extremely high flexibility in weighting.

P-0047[0047] The semiconductor device preferably further includes at least one resistor provided separately from the capacitor. Then, materials having various properties are usable for the resistor, thereby easily ensuring a semiconductor device holding multilevel information more effectively.

P-0048[0048] The resistor provided separately from the capacitor is preferably a variable resistor that includes an oxide containing an element selected from the group consisting of Ba, Sr, Ti, Zn, Fe and Cu, or includes an element selected from the group consisting of SiC, Si and Se. Then, the following controls can be performed. That is to say, a charge is injected in the gate electrode in a voltage range in which the resistance value of the resistor is small, while the charge injection is finely controlled in a voltage range in which the resistance value is large.

P-0049[0049] The resistors are preferably diodes that are connected in parallel and disposed in opposite orientations.

P-0050[0050] The semiconductor device preferably further includes an MIS transistor which has an ON resistance functioning as the resistor provided separately from the capacitor.

P-0051[0051] The resistor provided separately from the capacitor is preferably a variable resistance element made of a variable resistance material having a resistance value that varies depending on the crystallinity of the material.

P-0052[0052] The semiconductor device is preferably used as a synapse unit in a neurocomputer. Then, a high-performance neurocomputer is implementable.

P-0053[0053] An inventive method for driving a semiconductor device including a controlvoltage supply unit, a field-effect transistor including a gate electrode having a function of accumulating a charge, a capacitor, and a resistor, the capacitor and the resistor being disposed in parallel and interposed between the control-voltage supply unit and the gate electrode, includes the steps of: a) applying a write voltage to both ends of the resistor to vary the amount of the charge accumulated in the gate electrode via the resistor, thereby changing a threshold voltage of the field-effect transistor; and b) reading out information according to variation in a drain current in the field-effect transistor.

P-0054[0054] According to this method, information written by applying a voltage to a capacitor and a resistor in the step a) is held for a given time period. In addition, in the step b), multilevel information according to a variation in a drain current in a field-effect transistor can be read out. Thus, the semiconductor device of the present invention can be driven as a multilevel memory. If the semiconductor device of the present invention is applied to a neurocomputer, the device is usable as an element having a function of adding weights to input information.

P-0055[0055] The capacitor may include a dielectric layer. Then, the charge accumulated in the gate electrode is unlikely to leak. Therefore, input information can be held for a longer time than in the case where the resistor is made of an undoped silicon having a smaller resistance value.

P-0056[0056] In the step a), a pass current flowing through the resistor preferably increases substantially in proportion to the write voltage when the absolute value of the write voltage is equal to or smaller than a give value; and the pass current preferably increases exponentially as the write voltage increases, when the absolute value of the write voltage exceeds the given value. Then, the operation of writing information performed in a short time by applying a pulse voltage exceeding a given value, and the operation of writing information by applying a voltage equal to or lower than the given voltage, can be used properly. In particular, in the case where the device is used as a neuron element, the threshold value of the field-effect transistor is varied by applying a voltage exceeding a given voltage, thereby executing learning with a storing operation replayed at a relatively low voltage.

P-0057[0057] In the step a), when the absolute value of the write voltage is equal to or smaller than the given value, the amount of the charge accumulated in the gate electrode is preferably controlled depending on the length of a time period over which the write voltage is applied. That is to say, multilevel information can be written by a relatively simple manner.

P-0058[0058] In the step a), when the absolute value of the write voltage is equal to or smaller than the given value, a pass current flowing per unit area of the resistor is preferably 100 [mA/cm²] or less. Then, the recovery time of the semiconductor device, i.e., the holding time of information, can be ensured for a given period of time or longer.

P-0059[0059] In the step a), when the absolute value of the write voltage exceeds the given value, the write voltage is preferably set to have an uniform pulse width and the amount of the charge accumulated in the gate electrode is preferably controlled depending on the magnitude of the absolute value of the write voltage. Thus, multilevel information can be written also depending on the magnitude of the absolute value of the write voltage. In this case, the time period required for writing can be reduced, thereby allowing information to be stored for a short time.

P-0060[0060] In the step a), when the absolute value of the write voltage exceeds the given value, the amount of the charge accumulated in the gate electrode is preferably subjected to a coarse control, and when the absolute value of the write voltage is lower than the give value, the amount of the charge accumulated in the gate electrode is preferably subjected to a fine control.

P-0061[0061] In the step a), the write voltage is preferably in positive- and negative-voltage ranges that extend to an identical absolute value. Then, the drain current characteristic of the field-effect transistor differs between the application of a positive voltage and the application of a negative voltage. As a result, a larger amount of information can be stored in the semiconductor device, than in the case of application of only a positive voltage.

BRIEF DESCRIPTION OF DRAWINGS

P-0062[0062]FIG. 1 is a top plan view showing a multilevel memory according to a first embodiment of the present invention.

P-0063[0063]FIG. 2 is a cross-sectional view of the multilevel memory of the first embodiment, taken along the line II-II in FIG. 1.

P-0064[0064]FIG. 3 is a cross-sectional view of the multilevel memory of the first embodiment, taken along the line III-III in FIG. 1.

P-0065[0065]FIGS. 4A through 4E are cross-sectional views showing respective process steps for fabricating the multilevel memory of the first embodiment.

P-0066[0066]FIG. 5 is an equivalent circuit diagram showing the multilevel memory of the first embodiment.

P-0067[0067]FIG. 6 is a graph showing a polarization-voltage hysteresis characteristic (P-V characteristic) of a capacitor MFM<b>1</b>.

P-0068[0068]FIG. 7 is a graph showing a P-V characteristic of a capacitor MFM<b>2</b>.

P-0069[0069]FIG. 8 is a graph showing the P-V characteristics of the capacitors MFM<b>1</b> and MFM<b>2</b> and a P-V characteristic of the whole of the capacitors.

P-0070[0070]FIG. 9 is a graph showing a P-V characteristic of the whole of three capacitors.

P-0071[0071]FIG. 10 is a graph showing a voltage applied between an upper gate electrode and a lower electrode and the effective polarizations of ferroelectric capacitors in the multilevel memory of the first embodiment.

P-0072[0072]FIG. 11 is a graph showing a gate voltage-drain current characteristic with respect to respective write voltages in the multilevel of the first embodiment.

P-0073[0073]FIG. 12 is a graph for describing a correlation between swings in write voltage and shifts in polarization value in a known multilevel memory.

P-0074[0074]FIG. 13 is a graph showing a portion A in FIG. 12 under magnification for the known multilevel memory.

P-0075[0075]FIG. 14 is a graph for describing a correlation between swings in write voltage and shifts in polarization value in the multilevel memory of the first embodiment.

P-0076[0076]FIG. 15 shows a portion B in FIG. 14 under magnification of the multilevel memory of the first embodiment.

P-0077[0077]FIGS. 16A through 16D are graphs showing effective polarization values when the area of the capacitor MFM<b>2</b> is changed with respect to the capacitor MFM<b>1</b> in the multilevel memory of the present invention.

P-0078[0078]FIGS. 17A through 17D are graphs showing effective polarization values when the area of the capacitor MFM<b>1</b> is changed with respect to the capacitor MFM<b>2</b> in the multilevel memory of the present invention.

P-0079[0079]FIG. 18 is a cross-sectional view showing a modified example of the multilevel memory of the first embodiment.

P-0080[0080]FIG. 19 is a cross-sectional view showing a structure of a multilevel memory according to a second embodiment of the present invention.

P-0081[0081]FIG. 20 is a circuit diagram schematically showing a multilevel memory according to a third embodiment of the present invention.

P-0082[0082]FIG. 21 is an equivalent circuit diagram showing a multilevel memory according a fourth embodiment of the present invention.

P-0083[0083]FIG. 22 is an equivalent circuit diagram showing a semiconductor device according to a fifth embodiment of the present invention.

P-0084[0084]FIG. 23 is a top plan view showing the semiconductor device of the fifth embodiment.

P-0085[0085]FIG. 24 is a cross-sectional view showing the semiconductor device of the fifth embodiment, taken along the line XXIV-XXIV in FIG. 23.

P-0086[0086]FIG. 25 is a cross-sectional view showing the semiconductor device of the fifth embodiment, taken along the line XXV-XXV in FIG. 23.

P-0087[0087]FIGS. 26A through 26D are cross-sectional views showing respective process steps for fabricating the semiconductor device of the fifth embodiment.

P-0088[0088]FIG. 27 is a graph showing an applied voltage-pass current characteristic of a dielectric capacitor used in the semiconductor device of the fifth embodiment.

P-0089[0089]FIG. 28 is a graph showing an applied voltage-drain current characteristic of the semiconductor device of the fifth embodiment.

P-0090[0090]FIG. 29 shows a correlation between a pass current flowing through the dielectric capacitor and a recovery time in the semiconductor device of the fifth embodiment.

P-0091[0091]FIG. 30 is a graph showing an applied voltage-drain current characteristic of a dielectric capacitor used in a semiconductor device according to a sixth embodiment of the present invention.

P-0092[0092]FIG. 31 is a graph showing an applied voltage-drain current characteristic of the semiconductor device of the sixth embodiment.

P-0093[0093]FIG. 32 is an equivalent circuit diagram showing a semiconductor device according to a seventh embodiment of the present invention.

P-0094[0094]FIGS. 33A through 33D are cross-sectional views showing respective process steps for fabricating the semiconductor device of the seventh embodiment.

P-0095[0095]FIG. 34A is a diagram showing an equivalent circuit in a coarse control in which stored information is changed largely in the semiconductor device of the seventh embodiment. FIG. 34B is a graph showing an equivalent circuit in a fine control in which stored information is changed slightly in the semiconductor device of the seventh embodiment.

P-0096[0096]FIG. 35 is a graph showing an applied voltage-pass current characteristic of a ferroelectric capacitor used in the semiconductor device of the seventh embodiment.

P-0097[0097]FIG. 36 is a graph showing an example of a method for applying a voltage in the semiconductor device of the seventh embodiment.

P-0098[0098]FIG. 37 is graph showing an applied voltage-drain current characteristic of the semiconductor device of the seventh embodiment in an initial state.

P-0099[0099]FIG. 38 is a graph showing a drain current in the case where a voltage of +6 V is applied and then a pulse voltage is continuously applied in the semiconductor device of the seventh embodiment.

P-0100[0100]FIG. 39 is a graph showing an applied voltage-drain current characteristic of the semiconductor device of the seventh embodiment when scanned in the applied-voltage range of ±2 V after the application of a voltage of +6V.

P-0101[0101]FIG. 40 is a graph showing a drain current in the case where a voltage of −6 V is applied and then a pulse voltage is continuously applied in the semiconductor device of the seventh embodiment.

P-0102[0102]FIG. 41 is a graph showing an applied voltage-drain current characteristic of the semiconductor device of the seventh embodiment when scanned in the applied-voltage range of ±2 V after the input of a pulse voltage of −6 V.

P-0103[0103]FIG. 42A is a circuit diagram showing a semiconductor device according to an eighth embodiment of the present invention. FIG. 42B is a graph showing a varistor characteristic of a resistor.

P-0104[0104]FIG. 43 is a cross-sectional view showing a structure of the semiconductor device of the eighth embodiment.

P-0105[0105]FIG. 44 is a circuit diagram showing a semiconductor device according to a ninth embodiment of the present invention.

P-0106[0106]FIG. 45 is a circuit diagram showing a semiconductor device according to a tenth embodiment of the present invention.

P-0107[0107]FIG. 46 is a circuit diagram showing a semiconductor device according to an eleventh embodiment of the present invention.

P-0108[0108]FIG. 47 is a diagram schematically showing a fundamental structure of a neurocomputer according to a twelfth embodiment of the present invention.

P-0109[0109]FIG. 48 is a diagram showing a model representing a simplified structure of a fundamental unit of the brain of an animal.

P-0110[0110]FIG. 49 is a cross-sectional view showing a known semiconductor device functioning as a multilevel memory.

P-0111[0111]FIG. 50 is a graph showing hysteresis characteristics of the known semiconductor device functioning as a multilevel memory.

P-0112[0112]FIG. 51 is a graph showing the relationship between a gate voltage and a drain current in a memory cell of the known semiconductor device.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

P-0113[0113] Embodiment 1

P-0114[0114] Hereinafter, a first embodiment of the present invention will be described with reference to the drawings.

P-0115[0115]FIG. 1 is a top plan view of a multilevel memory according to the first embodiment of the present invention. FIG. 2 is a cross-sectional view taken along the line II-II in FIG. 1. FIG. 3 is a cross-sectional view taken along the line III-III in FIG. 1. In FIGS. 1, 2 and <b>3</b>, identical components are denoted by respectively identical reference numerals. In FIG. 1, only the components located on the uppermost surface are indicated by solid lines. Some of reference numerals of the portions that are commonly shown in FIGS. 2 and 3 are omitted for better viewability.

P-0116[0116] As shown in FIG. 2, the multilevel memory of this embodiment includes: a p-type Si substrate <b>1</b>; an isolation film <b>5</b> of silicon oxide formed by a LOCOS process in the Si substrate <b>1</b>; a gate insulating film <b>7</b> of silicon oxide having a thickness of 3 nm and formed on an active region of the Si substrate <b>1</b> defined by the isolation film <b>5</b>; a gate electrode <b>9</b> formed on the gate insulating film and made of polysilicon containing an n-type impurity; drain and source regions <b>3</b><i>a </i>and <b>3</b><i>b </i>that are formed in the Si substrate <b>1</b> to the sides of the gate electrode <b>9</b>, are in contact with the isolation film <b>5</b> and contain an n-type impurity; a plug interconnect <b>13</b><i>c </i>connecting the drain region <b>3</b><i>a </i>to a pad <b>15</b><i>a</i>; a plug interconnect <b>13</b><i>d </i>connecting the source region <b>3</b><i>b </i>to a pad <b>15</b><i>b</i>; a first interlevel dielectric film <b>11</b> filling in the gap between the plug interconnects <b>13</b><i>c </i>and <b>13</b><i>d</i>; a first ferroelectric layer <b>16</b> of bismuth titanate (BIT) formed on the first interlevel dielectric film <b>11</b> and having a thickness of 100 nm; a second ferroelectric layer <b>18</b> of BIT formed on the first ferroelectric layer <b>16</b> and having a thickness of 400 nm; a second interlevel dielectric film <b>21</b> of silicon oxide formed on the second ferroelectric layer <b>18</b>; an interconnect <b>25</b><i>c </i>formed on the second interlevel dielectric film <b>21</b>; an interconnect <b>25</b><i>a </i>formed through the first and second ferroelectric layers <b>16</b> and <b>18</b> and the second interlevel dielectric film <b>21</b> to connect the pad <b>15</b><i>a </i>to the interconnect <b>25</b><i>c</i>; and an interconnect <b>25</b><i>b </i>connected to the pad <b>15</b><i>b </i>through the first and second ferroelectric layers <b>16</b> and <b>18</b> and the second interlevel dielectric film <b>21</b>. In this embodiment, the gate length of the gate electrode <b>9</b> is 0.5 μm and the gate width thereof is 5 μm.

P-0117[0117] As shown in FIG. 3, the multilevel memory of this embodiment includes: the p-type Si substrate <b>1</b>; the isolation film <b>5</b> made of a silicon oxide film formed by a LOCOS process in the Si substrate <b>1</b>; the gate insulating film <b>7</b> of silicon oxide having a thickness of 3 nm and formed on the active region of the Si substrate <b>1</b> defined by the isolation film <b>5</b>; the gate electrode <b>9</b> formed on the gate insulating film <b>7</b> and made of polysilicon containing an n-type impurity; the first interlevel dielectric film <b>11</b> of silicon oxide formed on the gate electrode <b>9</b> and the isolation film <b>5</b>; a first intermediate electrode <b>14</b><i>a </i>of Pt/TiN formed on the first interlevel dielectric film <b>11</b> and having a size of 0.5 μm×0.5 μm; a second intermediate electrode <b>14</b><i>b </i>of Pt/TiN formed on the first interlevel dielectric film <b>11</b> and having a size of 0.5 μm×0.5 μm; a plug interconnect <b>13</b><i>a </i>formed through the first interlevel dielectric film <b>11</b> to connect the gate electrode <b>9</b> to the first intermediate electrode <b>14</b><i>a</i>; a plug interconnect <b>13</b><i>b </i>formed through the first interlevel dielectric film <b>11</b> to connect the gate electrode <b>9</b> to the second intermediate electrode <b>14</b><i>b</i>; the first ferroelectric layer <b>16</b> of BIT formed on the first interlevel dielectric film <b>11</b> and the first and second intermediate electrodes <b>14</b><i>a </i>and <b>14</b><i>b </i>and having a thickness of 100 nm; a first upper electrode <b>17</b> of Pt/TiN that is formed on the first ferroelectric layer <b>16</b>, is in parallel with the first intermediate electrode <b>14</b><i>a </i>to face the first intermediate electrode <b>14</b><i>a</i>, and has a size of 0.5 μm×0.5 μm; the second ferroelectric layer <b>18</b> of BIT formed on the first ferroelectric layer <b>16</b> and having a thickness of 400 nm; a second upper electrode <b>19</b> of Pt/TiN that is formed on the second ferroelectric layer <b>18</b>, is in parallel with the second intermediate electrode <b>14</b><i>b </i>to face the second intermediate electrode <b>14</b><i>b</i>, and has a size of 0.5 μm×0.5 μm; the second interlevel dielectric film <b>21</b> of silicon oxide formed on the second ferroelectric layer <b>18</b>; and the interconnect <b>25</b><i>c</i>, which penetrates through the second ferroelectric layer <b>18</b> and the second interlevel dielectric film <b>21</b> to connect with the first upper electrode <b>17</b> and penetrates through the second interlevel dielectric film <b>21</b> to connect with the second upper electrode <b>19</b> by way of the upper face of the second interlevel dielectric film <b>21</b>.

P-0118[0118] A ferroelectric capacitor made up of a part of the first ferroelectric layer <b>16</b> and the first intermediate electrode <b>14</b><i>a </i>and the first upper electrode <b>17</b>, between which the first ferroelectric layer <b>16</b> is sandwiched, is herein referred to as a capacitor MFM<b>1</b>. A ferroelectric capacitor made up of a part of the first and second ferroelectric layers <b>16</b> and <b>18</b>, the second intermediate electrode <b>14</b><i>b </i>and the second upper electrode <b>19</b>, between which the first and second ferroelectric layers <b>16</b> and <b>18</b> are sandwiched, is herein referred to as a capacitor MFM<b>2</b>. The capacitors MFM<b>1</b> and MFM<b>2</b> together form a capacitor MFMs.

P-0119[0119]FIG. 5 is an equivalent circuit diagram showing the multilevel memory of this embodiment.

P-0120[0120] As shown in FIG. 5, the multilevel memory of this embodiment has a structure in which the two ferroelectric capacitors are disposed in parallel and connected to each other above the gate electrode of the MOS transistor. In FIG. 5, the ferroelectric layer of the capacitor MFM<b>1</b> has a thickness of 100 nm and the electrode thereof has a size of 0.5 μm ×0.5 μm. The ferroelectric layers of the capacitor MFM<b>2</b> have a thickness of 500 nm and the electrode thereof has a size of 0.5 μm×0.5 μm.

P-0121[0121]FIGS. 4A through 4E are cross-sectional views showing respective process steps for fabricating the multilevel memory of this embodiment. The cross-sectional views in FIGS. 4A through 4E are taken along the line III-III in FIG. 1. Hereinafter, a method for fabricating the multilevel memory of this embodiment will be described with reference to FIGS. 4A through 4E.

P-0122[0122] First, in a process step shown in FIG. 4A, a p-type Si substrate <b>1</b> is subjected to oxidation using silicon nitride (not shown) as a mask through a LOCOS process, thereby forming an isolation film <b>5</b>. Thereafter, the silicon nitride (not shown) is dissolved by heated phosphoric acid, for example. Then, the Si substrate <b>1</b> is thermally oxidized at 900° C., for example, thereby forming a silicon oxide film with a thickness of <b>3</b> nm on the Si substrate <b>1</b>. This silicon oxide film is a gate insulating film <b>7</b>. Then, polycrystalline silicon doped with phosphorus is deposited by a LPCVD process to form a gate electrode <b>9</b>. Subsequently, the gate electrode <b>9</b> and the gate insulating film <b>7</b> are patterned through dry etching. Boron ions are then implanted into portions on the sides of the gate electrode <b>9</b> using the gate electrode <b>9</b> as a mask, and then heat treatment is performed at 900° C. for 30 minutes, thereby forming drain and source regions <b>3</b><i>a </i>and <b>3</b><i>b </i>shown in FIG. 2. The MOS transistor fabricated in this process step has a gate length of 0.5 μm and a gate width of 5 μm.

P-0123[0123] Next, in a process step shown in FIG. 4B, silicon dioxide (SiO₂) is deposited over the substrate by an LPCVD process, thereby forming a first interlevel dielectric film <b>11</b>. Then, dry etching is performed using a resist mask formed on the first interlevel dielectric film <b>11</b> so that contact holes are formed, and thereafter, polysilicon is deposited by an LPCVD process in the contact holes. Subsequently, the polysilicon is planarized by a CMP process, thereby forming plug interconnects <b>13</b><i>a</i>, <b>13</b><i>b</i>, <b>13</b><i>c </i>and <b>13</b><i>d</i>. Then, after titanium nitride has been deposited by a sputtering process to a thickness of 20 nm over the first interlevel dielectric film <b>11</b>, a Pt layer is deposited by a sputtering process to a thickness of 50 nm. Subsequently, silicon oxide that has been deposited by a sputtering process over the Pt layer is patterned to form a hard mask (not shown). The Pt/TiN layer is patterned by Ar milling using the hard mask as a mask, thereby forming first and second intermediate electrodes <b>14</b><i>a </i>and <b>14</b><i>b </i>and pads <b>15</b><i>a </i>and <b>15</b><i>b </i>shown in FIG. 2. Thereafter, the hard mask made of silicon oxide, for example, is removed by diluted hydrofluoric acid or the like.

P-0124[0124] Then, in a process step shown in FIG. 4C, BIT is deposited by a sputtering process to a thickness of 100 nm over the substrate under conditions that the substrate temperature is 550° C., the partial pressure of oxygen is 20% and the RF power is 100 W, thereby forming a first ferroelectric layer <b>16</b>. Then, a Pt layer is deposited by a sputtering process and then is patterned by Ar milling using a hard mask of silicon oxide (not shown), thereby forming a first upper electrode <b>17</b>. Thereafter, the hard mask of silicon oxide (not shown) is removed by diluted hydrofluoric acid or the like. In this embodiment, each of the first intermediate electrode <b>14</b><i>a </i>and the first upper electrode <b>17</b> has a size of 0.5 μm×0.5 μm.

P-0125[0125] Then, in a process step shown in FIG. 4D, BIT is deposited by a sputtering process to a thickness of 400 nm over the substrate under conditions that the substrate temperature is 550° C., the partial pressure of oxygen is 20% and the RF power is 100 W, thereby forming a second ferroelectric layer <b>18</b>. Then, a Pt layer is deposited by a sputtering process over the second ferroelectric layer <b>18</b> and then is patterned by Ar milling using a hard mask of silicon oxide (not shown), thereby forming a second upper electrode <b>19</b>. Thereafter, the hard mask (not shown) is removed by diluted hydrofluoric acid or the like. In this embodiment, each of the second intermediate electrode <b>14</b><i>b </i>and the second upper electrode <b>19</b> has a size of 0.5 μm×0.5 μm.

P-0126[0126] Then, in a process step shown in FIG. 4E, a silicon oxide film is deposited over the substrate by plasma CVD using TEOS, and then is planarized by a CMP process, thereby forming a second interlevel dielectric film <b>21</b>. Thereafter, the second interlevel dielectric film <b>21</b> is dry-etched using a resist mask formed on the second interlevel dielectric film so that a contact hole reaching the second upper electrode <b>19</b> is formed. On the other hand, the second interlevel dielectric film <b>21</b> and the second ferroelectric layer <b>18</b> are dry-etched using a resist mask formed on the second interlevel dielectric film so that a contact hole reaching the first upper electrode <b>17</b> is formed. If the etching selectivity of the second ferroelectric layer <b>18</b> to the upper electrode <b>19</b> is sufficiently high, the contact hole reaching the second upper electrode <b>19</b> and the contact hole reaching the first upper electrode <b>17</b> can be formed simultaneously. Then, an AlSiCu alloy is deposited by a sputtering process in the contact holes and then is dry-etched, thereby forming interconnects <b>25</b><i>a</i>, <b>25</b><i>b </i>and <b>25</b><i>c</i>, respectively.

P-0127[0127] In this manner, the multilevel memory of this embodiment is fabricated.

P-0128[0128]FIG. 6 is a graph showing a polarization-voltage hysteresis characteristic (P-V characteristic) of the capacitor MFM<b>1</b>. FIG. 6 shows a hysteresis characteristic when only the capacitor MFM<b>1</b> is connected to a power source.

P-0129[0129] Referring to FIG. 6, it is found that since the thickness of the capacitor MFM<b>1</b> is as small as about 100 nm, the coercive voltage thereof is low, while the polarization value at a voltage of 0 V after the application of a voltage of about 5V or higher (i.e., remanent polarization) is about 4 μC/cm², reflecting properties of the BIT material.

P-0130[0130]FIG. 7 is a graph showing a P-V characteristic of the capacitor MFM<b>2</b>. Though the capacitor MFM<b>2</b> is made of the same ferroelectric material, i.e., BIT, as that of the capacitor MFM<b>1</b>, the thickness of the capacitor MFM<b>2</b> is as thick as 500 nm in total. Therefore, the coercive voltage thereof is about five times higher than that of the capacitor MFM<b>1</b> as shown in FIG. 7. However, since remanent polarization values are determined by the material, the remanent polarization value of the capacitor MFM<b>2</b> is about 4 μC/cm², which is substantially equal to that of the capacitor MFM<b>1</b>.

P-0131[0131] A method for driving the multilevel memory of this embodiment with the structure in which two ferroelectric capacitors having mutually different hysteresis characteristics are connected in parallel as described above, and operation of the multilevel memory will be described with reference to FIGS. 8 through 10.

P-0132[0132]FIG. 10 is a graph showing a voltage applied between the upper gate electrode and the lower electrode and the effective polarizations of the two ferroelectric capacitors in the multilevel memory of this embodiment. As shown in FIG. 10, since the capacitors used in the multilevel memory of this embodiment are connected to each other in parallel, the polarization of the whole of the capacitors has an average value corresponding exactly to the ratio between areas for the polarizations of the capacitors MFM<b>1</b> and MFM<b>2</b>.

P-0133[0133]FIG. 8 is a graph for describing hysteresis characteristics of polarization in the whole of the capacitors (i.e., the capacitor MFMs) made up of the capacitors MFM<b>1</b> and MFM<b>2</b> connected in parallel. In FIG. 8, the average value of the polarizations of the two capacitors indicated by broken lines determines the polarization of the capacitor MFMs. That is to say, the polarization of the capacitor MFMs exhibits the hysteresis characteristics shown in FIG. 10.

P-0134[0134] In a range x shown in FIG. 8, the polarization of the capacitor MFM<b>2</b> hardly varies with the change in the voltage V. On the other hand, the polarization of the capacitor MFM<b>1</b> increases abruptly in the first half of the range x and varies slightly in the latter half, with the change in the voltage V. As a result, the synthesized value of these polarizations changes abruptly in the first half of the range x and varies gently in the latter half of the range x. On the other hand, in a range y, the polarization of the capacitor MFM<b>2</b> changes abruptly with the change in the voltage V, while the polarization of the capacitor MFM<b>1</b> hardly varies with the change in the voltage V. As a result, the synthesized value of these polarizations changes abruptly in the first half of the range y but more gently than the polarization value of the capacitor MFM<b>2</b> alone.

P-0135[0135] The multilevel memory of this embodiment includes the two ferroelectric capacitors having mutually different coercive voltages as described above. Thus, unlike the general hysteresis loops as shown in FIG. 6, the hysteresis loop of the multilevel memory of this embodiment has a metastable point as indicated by a point C in FIG. 10. Therefore, the polarization changes gently with the change in voltage in the vicinity of 4 V of a write voltage. As a result, even if the write voltage is swung by noise, for example, the change in polarization can be suppressed.

P-0136[0136] To achieve this effect, ranges in which hysteresis loops exhibit abrupt changes in polarizations with the change in voltage should not coincide with each other. Thus, the coercive voltages of the capacitors are required to differ from each other. In particular, in the first half stage of the range in which the polarization are from zero to saturation, if two dielectric materials exhibiting mutually different rates of changes in polarizations with the change in voltage are used, a metastable point can be created as intended. In the same manner, in the case where three or more capacitors are arranged in parallel, the difference between the coercive voltages of the capacitors is also required to differ sufficiently.

P-0137[0137]FIG. 9 is a graph showing a P-V characteristic of capacitors in the case where a capacitor MFM<b>3</b> having the same area as that of the capacitor MFM<b>1</b> or MFM<b>2</b> is added to the capacitors MFM<b>1</b> and MFM<b>2</b>. The P-V characteristic of the whole of the capacitors is indicated by broken lines in FIG. 9. As in the case where two capacitors are provided, the coercive voltages of the capacitors are mutually different from each other. Thus, a metastable point F is additionally created on the hysteresis loop. In this case, the point C shifts to the point C′. In this manner, information can be stored with stability using at least four levels.

P-0138[0138] Next, a method for conducting a multilevel operation of the ferroelectric capacitors arranged in parallel in this embodiment will be described.

P-0139[0139] First, in FIG. 10, the line connecting points A, S, C, D and P indicates the polarization of the capacitors upon the application of respective voltages. When the applied voltage is increased from −8 V, the polarization of the capacitors shifts from the point A to the point S and then to the point C along the direction shown by the allows. When a voltage of 8 V is applied, the polarization of the capacitors is saturated and does not increase, so that the polarization state remains at the point D even upon the application of higher voltages. When the voltage applied to the capacitors is once increased to 8 V and then is decreased, the polarization state of the capacitors approaches the point A by way of the point P. When the applied voltage is −8 V, the polarization state returns to the point A.

P-0140[0140] Hereinafter, respective states of the capacitors MFM<b>1</b> and MFM<b>2</b> will be described. At the point A at which a voltage of −8 V is applied to the capacitors, the polarizations of the capacitors MFM<b>1</b> and MFM<b>2</b> are saturated, being negatively charged, as shown in FIGS. 6 and 7. In this state, when the voltage applied to the capacitors is removed, the applied voltage becomes 0 V so that the polarizations state is at the point S. Since the capacitors MFM<b>1</b> and MFM<b>2</b> have the same size, the polarization of the capacitor MFMs takes the average value of the capacitors MFM<b>1</b> and MFM<b>2</b> shown in FIGS. 6 and 7 (see FIG. 8).

P-0141[0141] Next, when the applied voltage at the point S is increased to about 4V, the polarization of the capacitor MFM<b>1</b> is saturated, being positively charged, while the polarization of the capacitor MFM<b>2</b> is positively charged but is not saturated. The polarizations of the two capacitors are averaged at the point C, which is a metastate point. FIG. 10 shows that a voltage of 3.5 V is applied to the capacitors in consideration of a noise margin, so that the polarization state is at the point B. Then, the applied voltage is removed, so that the state indicated by the point Q at which the polarization is substantially 0 μC/cm²is created.

P-0142[0142] Then, when the voltage applied to the capacitors is increased to 8 V, the polarization state of the capacitors is at the point D at which polarizations of the capacitors MFM<b>1</b> and MFM<b>2</b> are both saturated with a positive charge. Thereafter, the voltage is removed, so that the polarization state of the capacitors is at the point P.

P-0143[0143] Then, the voltage applied to the capacitors is decreased to −8 V, so that the polarization state of the capacitors returns to the point A.

P-0144[0144] In this manner, by applying three levels of write voltages such as −8 V, 3.5 V and 8V, the multilevel memory of this embodiment can perform a stable storing operation toward noise, for example.

P-0145[0145]FIG. 11 is a graph showing a drain current in the case where a gate voltage, which is a read voltage, is changed after write operations at voltages of +8 V, +3.5 V and −8 V, respectively, have been performed in the multilevel memory of this embodiment.

P-0146[0146] As shown in FIG. 11, in the read voltage range of 2 V to 3 V, values of a current flowing into drain in the respective polarization states may differ by one or more orders of magnitude, and stored information can be read out with stability.

P-0147[0147] Next, a write operation at a point on a hysteresis loop at which the write operation is likely to be unstable will be described, with the case where a write voltage of half of the saturation voltage swings 10% taken as an example.

P-0148[0148]FIG. 12 is a graph for describing how much the polarization value shifts when a write voltage swings 10% in the known multilevel memory provided with a single ferroelectric capacitor.

P-0149[0149]FIG. 13 is a graph showing a portion A in FIG. 12 under magnification.

P-0150[0150] As can be understood from FIGS. 12 and 13, the known technique has no other choice but to use a portion in the hysteresis loop where the polarization changes abruptly in order to obtain a polarization state at a point on the hysteresis loop, and therefore the polarization value shifts greatly between 1.4 μC/cm²and 2.0 μC/cm², which is originally expected to be 1.7 μC/cm², with respect to the shifts of 10% (see FIG. 13).

P-0151[0151]FIG. 14 is a graph for describing shifts in the polarization when a write voltage swings in the multilevel memory of this embodiment, as in FIGS. 12 and 13. FIG. 15 shows a portion B in FIG. 14 under magnification.

P-0152[0152] As can be understood from FIGS. 14 and 15, abrupt change in polarization with the swings in the write voltage is greatly improved in the multilevel memory of this embodiment as compared to the known technique. For example, the polarization value shifts in the range of −0.1 μC/cm²to −0.2 μC/cm², both inclusive, which is originally expected to be −0.15 μC/cm², with respect to voltage swings of ±10%. That is to say, the range of the shift in polarization value is considerably improved to be 0.1 μC/cm²or less, as compared to the known technique in which the range of the shift in polarization value is 0.6 μC/cm². This is because the ferroelectric capacitors are connected in parallel and the respective coercive voltages are made different from one another, resulting in creating a metastable point on the hysteresis loop.

P-0153[0153] Swings in a write voltage (electric field strength in writing) may be caused by variations such as variation in thickness of a ferroelectric layer and variation in dielectric constant due to the difference in crystallinity of the ferroelectric layer as well as noise. The write voltage swings of ±10% possibly occur in practical application.

P-0154[0154] Accordingly, the structure of the multilevel memory of this embodiment can enlarge a margin in a process by suppressing the shift in polarization value, and therefore is useful for actual device fabrication.

P-0155[0155]FIGS. 16 and 17 are graphs showing effective polarization values when the ratio between the areas of the capacitors MFM<b>1</b> and MFM<b>2</b> is changed in the case where the ferroelectric film of the capacitor MFM<b>1</b> has a thickness of 100 nm and the ferroelectric film of the capacitor MFM<b>2</b> has a thickness of 1000 nm. At points D, A, B and E in FIGS. 16A through 16D and FIGS. 17A through 17D, voltages are applied such that a positive-side maximum polarization, a negative-side maximum polarization, a positive-side intermediate polarization and a negative-side intermediate polarization are written, respectively. The polarization values after the removal of these voltages are indicated by points P, S, Q and R, respectively.

P-0156[0156]FIGS. 16A through 16D are graphs showing effective polarizations in the case where the area of the capacitor MFM<b>2</b> is increased gradually with respect to the area of the capacitor MFM<b>1</b>. As shown in FIGS. 16A through 16D, as the area ratio of the capacitor MFM<b>2</b> increases, the polarization changes abruptly with the voltage change in the ranges where the hysteresis loop passes through the points B and E.

P-0157[0157] On the other hand, FIGS. 17A through 17D are graphs showing effective polarizations in the case where the area ratio of the capacitor MFM<b>1</b> is increased. As shown in FIGS. 17A through 17D, the polarization varies gently with the voltage change in the ranges where the hysteresis loop passes through the points B and E. This fact shows that, as for the area ratio between the capacitors MFM<b>1</b> and MFM<b>2</b>, if the area of the capacitor MFM<b>1</b> is larger than that of the capacitor MFM<b>2</b>, a multilevel memory which is more stable to swings in a write voltage can be implemented. However, as can be seen from FIG. 17D, if the area ratio of the capacitor MFM<b>1</b> is extremely high, the points P and Q approach each other and the points S and R approach each other, resulting in that it is difficult to determine data. Accordingly, in this embodiment, even if the area ratio between the capacitors MFM<b>1</b> and MFM<b>2</b> (the area of the capacitor MFM<b>1</b>/the area of the capacitor MFM<b>2</b>) is set substantially in the range of 0.5 to 2, separation of stored information is maintained excellent, and a stable multilevel operation is achieved.

P-0158[0158] If the effective polarization value is not at the points Q and R, but is 0 μC/cm², i.e., if three states of polarizations are used, separation of stored information is maintained excellent even with the area ratio between the capacitors MFM<b>1</b> and MFM<b>2</b> (the area of the capacitor MFM<b>1</b>/the area of the capacitor MFM<b>2</b>) substantially in the range of 0.2 to 2.

P-0159[0159] As has been described above, according to this embodiment, if two or more ferroelectric capacitors having the same polarization direction and having mutually different coercive voltages are connected to the gate electrode of a field-effect transistor, it is possible to achieve a multilevel memory in which a drain current varies only slightly with the small variation in a write voltage.

P-0160[0160] According to this embodiment, a stable highly-integrated semiconductor memory can be provided. In addition, the memory is expected to be applied, as a nonvolatile transistor having a plurality of resistance values, to neuron elements mimicking neurons of the brain.

P-0161[0161]FIG. 18 is a cross-sectional view showing a modified example of the multilevel memory of this embodiment. This multilevel memory has the same structure as that of the multilevel memory of this embodiment shown in FIG. 3 except for the second ferroelectric layer <b>18</b>, and thus the description of the structure is herein omitted.

P-0162[0162] The multilevel memory of this modified example includes a paraelectric instead of the second ferroelectric layer <b>18</b> used in the multilevel memory of this embodiment shown in FIG. 3.

P-0163[0163] For example, in this modified example of this embodiment, tantalum oxide having a thickness of 100 nm and formed by a sputtering process is used as a paraelectric layer <b>20</b>. The tantalum oxide layer has a relative dielectric constant of about 25 in this modified example of this embodiment. In this case, the paraelectric layer has a capacitance of about one-fourth of that of the ferroelectric layer, so that one-fifth of the voltage applied to the capacitor MFM<b>2</b> is applied to the ferroelectric. Therefore, the apparent coercive voltage increases fivefold, and thus a metastable point can be created before the polarization of the whole of the capacitors is saturated.

P-0164[0164] In this embodiment, in obtaining the ferroelectric capacitors having mutually difference coercive voltages, the thicknesses of the ferroelectric layers are 100 nm and 500 nm, respectively, or 100 nm and 1000 nm, respectively. Alternatively, the thicknesses may take arbitrary values as well as the values described above. In such a case, the coercive voltages of the capacitors can be made differ from each other.

P-0165[0165] Alternatively, ferroelectrics made of different materials may be respectively applied to the ferroelectric capacitors. Then, the same effect is obtained as in the case where the thicknesses of the ferroelectric layers are made different from each other. For example, BIT used in this embodiment has a coercive force of about 20 kV/cm and PZT has a different coercive force, i.e., about 40 kV/cm. Thus, the coercive voltage of the capacitor using PZT is twice as large as that of the capacitor using BIT so long as the ferroelectric layers of the capacitors have the same thickness.

P-0166[0166] The multilevel memory of this embodiment has been described particularly in the case where two ferroelectric capacitors are provided. Alternatively, three or more ferroelectric capacitors having different coercive voltages may be connected as shown in FIG. 9. In such a case, the number of metastable points created on the hysteresys increases in the same manner, so that a ferroelectric gate memory with more levels can be implemented.

P-0167[0167] In the multilevel memory of this embodiment, the positive and negative states of the polarizations of the capacitors MFM<b>1</b> and MFM<b>2</b> coincide with each other. Alternatively, these capacitors may be polarized in opposite orientations.

P-0168[0168] Embodiment 2

P-0169[0169]FIG. 19 is a cross-sectional view showing a structure of a multilevel memory according to a second embodiment of the present invention. As shown in FIG. 19, the multilevel memory of this embodiment includes: a p-type substrate <b>1</b>; an isolation film (not shown) of silicon oxide formed in the Si substrate <b>1</b>; a gate insulating film <b>7</b> of silicon oxide formed on the Si substrate <b>1</b>; gate and lower electrodes <b>26</b> of Pt/TiN formed on the gate insulating film <b>7</b>; a first ferroelectric layer <b>27</b> of BIT formed on the gate and lower electrodes <b>26</b> and having a thickness of 100 nm; a first upper electrode <b>29</b> which is formed on the first ferroelectric layer <b>27</b> and is not longer than half of the gate electrode in width; a second ferroelectric layer <b>28</b> of BIT which is formed on the first ferroelectric layer <b>27</b>, is not longer than half of the gate electrode in width and has a thickness of 400 nm; a second upper electrode <b>30</b> formed on the second ferroelectric layer <b>28</b>; an interlevel dielectric film <b>31</b> formed on the gate insulating film <b>7</b> and filling in the gap located on the sides of the gate and lower electrodes <b>26</b>, first ferroelectric layer <b>27</b>, first upper electrode <b>29</b>, second ferroelectric layer <b>28</b>, and first and second upper electrodes <b>29</b> and <b>30</b>; and a plug interconnect <b>32</b> formed through the interlevel dielectric film to connect with the first and second upper electrodes <b>29</b> and <b>30</b>. In this embodiment, the gate and lower electrodes <b>26</b> are formed by merging a gate electrode with a lower electrode of a capacitor.

P-0170[0170] In this embodiment, a capacitor MFM<b>1</b> made up of the first upper electrode <b>29</b>, the first ferroelectric layer <b>27</b> and the lower electrode <b>26</b> and a capacitor MFM<b>2</b> made up of the second upper electrode <b>30</b>, the second ferroelectric layer <b>28</b>, the first ferroelectric layer <b>26</b> and the lower electrode <b>26</b> have mutually different coercive voltages. Thus, a metastable point is created on a hysteresis loop of the whole of the capacitors. Therefore, the multilevel memory of this embodiment achieves a stable multilevel operation exhibiting excellent separation of stored information, as the multilevel memory of the first embodiment.

P-0171[0171] In the multilevel memory of this embodiment, no intermediate electrode is needed. Therefore, the number of fabrication process steps can be reduced as compared to the multilevel memory of the first embodiment, thus reducing the fabrication cost.

P-0172[0172] A paraelectric layer may be used instead of the second ferroelectric layer <b>28</b> used in this embodiment. In such a case, the capacitors MFM<b>1</b> and MFM<b>2</b> also have mutually different coercive voltages.

P-0173[0173] Embodiment 3

P-0174[0174]FIG. 20 is a circuit diagram showing a multilevel memory according to a third embodiment of the present invention. As shown in FIG. 20, the multilevel memory of this embodiment includes: a selecting transistor Tr<b>1</b> whose gate is connected to a word line WL and whose drain is connected to a bit line BL; and capacitors MFM<b>1</b> and MFM<b>2</b> arranged in parallel and connected to source of the selecting transistor Tr and each including a ferroelectric. In the multilevel memory of this embodiment, the capacitors MFM<b>1</b> and MFM<b>2</b> have mutually different coercive voltages.

P-0175[0175] The multilevel memory of this embodiment is a memory called an FeRAM that reads out information depending on the amount of current flowing when the polarization of the capacitors is inverted. In this case, in the multilevel memory of this embodiment, a plurality of remanent polarization values can be obtained with stability by connecting the capacitors having mutually different coercive voltages in parallel, as described in the first and second embodiments. In the read operation of the multilevel memory of this embodiment, while a given voltage, e.g., 8V, is kept on the word line WL, the amount of current that has flowed through the selecting transistor Tr<b>1</b> is determined depending on the degree of a voltage drop at the word line WL caused when the selecting transistor Tr<b>1</b> is turned ON (conductive), thereby reading out information. In this case, the amount of polarization inversion varies depending on the state of the remanent polarization of the ferroelectric capacitors, so that the amount of current flowing through the transistor Tr<b>1</b> varies. For example, a larger amount of current (an absolute value) is detected in the order of the points P, Q and S in FIG. 10. That is to say, a multilevel FeRAM is implementable.

P-0176[0176] This structure also achieves a stable multilevel operation with excellent separation of stored information, as in the multilevel memory of the first embodiment.

P-0177[0177] Embodiment 4

P-0178[0178]FIG. 21 is an equivalent circuit diagram showing a multilevel memory according a fourth embodiment of the present invention. The multilevel memory of this embodiment has a structure in which a capacitor <b>40</b> is interposed between the gate electrode <b>9</b> of the multilevel memory and the capacitor MFM<b>2</b> of the first embodiment. Specifically, the multilevel memory of this embodiment includes: an MIS transistor; capacitors MFM<b>1</b> and MFM<b>2</b> arranged in parallel, connected to the gate electrode <b>9</b> of the MIS transistor and each including a ferroelectric; and the capacitor <b>40</b> interposed between the gate electrode <b>9</b> and the capacitor MFM<b>2</b>. In FIG. 21, components also shown in FIG. 5 are identified by the same reference numerals. The areas of the capacitors MFM<b>1</b> and MFM<b>2</b> and the thicknesses of the ferroelectric layers are the same as those in the first embodiment. The capacitor <b>40</b> is a capacitor including a paraelectric but may be a ferroelectric capacitor.

P-0179[0179] When a voltage is applied to the multilevel memory of the first embodiment, voltages applied to the capacitors MFM<b>1</b> and MFM<b>2</b> are equal to each other. On the other hand, in the multilevel memory of this embodiment, the sum of the voltages distributed to the capacitor MFM<b>2</b> and the capacitor <b>40</b> is equal to the voltage distributed to the capacitor MFM<b>1</b>.

P-0180[0180] Therefore, in this embodiment, the voltage distributed to the capacitor MFM<b>2</b> is smaller than the voltage distributed to the capacitor MFM<b>2</b> in the first embodiment, upon the application of the same voltage to the multilevel memories. As a result, an apparent coercive voltage is higher than that in the first embodiment. In the multilevel memory of this embodiment, the capacitors MFM<b>1</b> and MFM<b>2</b> have mutually different coercive voltages, and a metastable point is created on the hysteresis loop of these capacitors. Accordingly, multilevel information can be stored in the multilevel memory of this embodiment with stability.

P-0181[0181] In addition, interposing at least one capacitor between a ferroelectric capacitor and the gate electrode of an MIS transistor allows an apparent coercive voltage to be adjusted to an arbitrary value, so that flexibility in design improves. In this embodiment, the capacitors MFM<b>1</b> and MFM<b>2</b> have mutually different coercive voltages. However, even if the coercive voltages of the two capacitors are equal to each other, a multilevel memory in which multilevel information is stored with stability is implementable because an apparent coercive voltage of the capacitor MFM<b>2</b> is varied by interposing the capacitor <b>40</b>. The multilevel memory of this embodiment is advantageous in that the ferroelectric layers of the capacitors MFM<b>1</b> and MFM<b>2</b> can be formed at a time.

P-0182[0182] In this embodiment, one capacitor is interposed between the capacitor MFM<b>2</b> and the gate electrode <b>9</b> of the MIS transistor. Alternatively, two or more capacitors may be interposed therebetween.

P-0183[0183] Embodiment 5

P-0184[0184] Hereinafter, a semiconductor device according to a fifth embodiment of the present invention will be described with reference to the drawings.

P-0185[0185]FIG. 22 is an equivalent circuit diagram showing the semiconductor device of this embodiment. As shown in FIG. 22, the semiconductor device of this embodiment is characterized by including: a control-voltage supply unit <b>110</b>; a field-effect transistor (which will be hereinafter referred to as an MOS transistor); a dielectric capacitor <b>104</b>; and a resistor <b>106</b>. The dielectric capacitor <b>104</b> and the resistor <b>106</b> are disposed in parallel and interposed between a gate electrode <b>109</b> of the MOS transistor and the control-voltage supply unit <b>110</b>.

P-0186[0186]FIG. 23 shows a top plan view of the semiconductor device of this embodiment. FIG. 24 shows a cross-sectional view taken along the line XXIV-XXIV in FIG. 23. FIG. 25 shows a cross-sectional view taken along the line XXV-XXV in FIG. 23. In FIG. 23, hatch patterns are omitted and only components on the uppermost surface are indicated by solid lines for better viewability. Some of the components also shown in FIGS. 24 and 25 are also omitted for better viewability. In FIGS. 24 and 25, components behind the cross section are omitted in part.

P-0187[0187] As shown in FIGS. 23, 24 and <b>25</b>, the semiconductor device of this embodiment includes: a p-type Si substrate <b>101</b> including an active region, for example; a substrate electrode <b>108</b> (shown only in FIG. 22) formed on a plane facing the active region of the Si substrate <b>101</b>; an isolation oxide film <b>105</b> formed in the Si substrate <b>101</b> to surround the active region; a gate insulating film <b>107</b> of SiO₂having a thickness of 5 nm and formed on the Si substrate <b>101</b>; a gate electrode <b>109</b> formed on the gate insulating film <b>107</b> and made of polysilicon containing phosphorus; drain and source regions <b>103</b><i>a </i>and <b>103</b><i>b </i>formed in the Si substrate <b>101</b> to the sides of the gate electrode <b>109</b> and containing an n-type impurity; a first interlevel dielectric film <b>111</b> formed on the Si substrate <b>101</b> and made of an insulator such as SiO₂; pads <b>115</b><i>a </i>and <b>115</b><i>b </i>and an intermediate electrode <b>114</b> that are formed on the first interlevel dielectric film <b>111</b> and made of a titanium nitride (TiN) film having a thickness of 20 nm and a Pt film having a thickness of 50 nm; a plug interconnect <b>113</b><i>a </i>of polysilicon connecting the gate electrode <b>109</b> to the intermediate electrode <b>114</b> through the first interlevel dielectric film <b>111</b>; plug interconnects <b>113</b><i>b </i>and <b>113</b><i>c </i>of polysilicon connecting the drain region <b>103</b><i>a </i>to the pad <b>115</b><i>a </i>and connecting the source region <b>103</b><i>b </i>to the pad <b>115</b><i>b</i>, respectively, through the first interlevel dielectric film <b>111</b>; a dielectric layer <b>116</b> of barium strontium titanate (hereinafter referred to as BST) formed on the first interlevel dielectric film <b>111</b> and having a thickness of 100 nm; an upper electrode <b>119</b> of Pt formed on the dielectric layer <b>116</b> and having a thickness of 50 nm; a second interlevel dielectric film <b>121</b> formed on the dielectric layer <b>116</b>; an interconnect <b>125</b><i>a </i>made of a conductor such as an AlSiCu alloy and penetrating through the second interlevel dielectric film <b>121</b> to connect with the upper electrode <b>119</b>; and interconnects <b>125</b><i>b </i>and <b>125</b><i>c </i>made of a conductor such as an AlSiCu alloy and penetrating through the second interlevel dielectric film <b>121</b> and the dielectric layer <b>116</b> to connect with the pads <b>115</b><i>a </i>and <b>115</b><i>b</i>, respectively.

P-0188[0188] Each of the intermediate electrode <b>114</b> and the upper electrode <b>119</b> has a size of 2.5 μm×4 μm, which is the same as the size of the MOS transistor including the gate electrode <b>109</b>.

P-0189[0189] In the semiconductor device of this embodiment, the dielectric layer <b>116</b> and the intermediate and upper electrodes <b>114</b> and <b>119</b>, between which the dielectric layer <b>116</b> is sandwiched, together form a capacitor. In addition, the dielectric layer <b>116</b> also constitutes the resistor <b>106</b> (see FIG. 22). Operation of the semiconductor device in consideration of this structure will be described later.

P-0190[0190] Next, a method for fabricating the semiconductor device of this embodiment will be hereinafter described with reference to FIGS. 26A through 26D.

P-0191[0191]FIGS. 26A through 26D are cross-sectional views taken along the line XXV-XXV in FIG. 23 and showing respective process steps for fabricating the semiconductor device of this embodiment. Components not appeared in the XXV-XXV cross-sections in FIGS. 26A through 26D and components omitted therein will be described using the reference numerals used in the descriptions for FIGS. 23 through 25.

P-0192[0192] First, in a process step shown in FIG. 26A, a p-type Si substrate <b>101</b> is subjected to oxidation using a silicon nitride film (not shown) formed thereon as a mask, thereby forming an isolation oxide film <b>105</b> (a LOCOS process). Thereafter, the silicon nitride film is removed by heated phosphoric acid, for example, and then the substrate is subjected to a pyrogenic oxidation at 900° C., thereby forming a SiO₂film with a thickness of 5 nm on the Si substrate <b>101</b>. Then, polysilicon doped with an n-type impurity such as phosphorus is deposited by a LPCVD process, for example, over the SiO₂film and then is patterned by dry etching, thereby forming a gate insulating film <b>107</b> and a gate electrode <b>109</b>. Subsequently, a p-type impurity such as boron is implanted using the gate electrode <b>109</b> as a mask, and then heat treatment is performed at 900° C. for 30 minutes, thereby forming drain and source regions <b>103</b><i>a </i>and <b>103</b><i>b </i>in the Si substrate <b>101</b> to the sides of the gate electrode <b>109</b>. The MOS transistor fabricated in this process step has a gate length of 1 μm and a gate width of 10 μm.

P-0193[0193] Next, in a process step shown in FIG. 26B, SiO₂is deposited by an LPCVD process, for example, over the substrate, thereby forming a first interlevel dielectric film <b>111</b>. Then, after a resist pattern (not shown) has been formed on the first interlevel dielectric film <b>111</b>, the first interlevel dielectric film <b>111</b> is dry-etched, thereby forming contact holes reaching the gate electrode <b>109</b> and the drain and source regions <b>103</b><i>a </i>and <b>103</b><i>b</i>, respectively. Thereafter, polysilicon is deposited by an LPCVD process, for example, over the substrate, and then the substrate surface is planarized by a CMP process, thereby forming plug interconnects <b>113</b><i>a</i>, <b>113</b><i>b </i>and <b>113</b><i>c </i>filling in the respective contact holes. Then, after TiN has been deposited by a sputtering process to a thickness of 20 nm over the first interlevel dielectric film <b>111</b>, Pt is deposited by a sputtering process to a thickness of 50 nm. Subsequently, a SiO₂film that has been deposited by a sputtering process is patterned to form a hard mask (not shown). The Pt/TiN layer is then patterned by Ar milling using the hard mask, thereby forming an intermediate electrode <b>114</b> and pads <b>115</b><i>a </i>and <b>115</b><i>b </i>on the plug interconnects <b>113</b><i>a</i>, <b>113</b><i>b </i>and <b>113</b><i>c</i>, respectively. Thereafter, the hard mask is removed by diluted hydrofluoric acid or the like.

P-0194[0194] In this case, the TiN layer is formed so as to prevent Pt and polycrystalline silicon from forming silicide which increases the resistance.

P-0195[0195] Then, in a process step shown in FIG. 26C, BST is deposited by a sputtering process, for example, over the first interlevel dielectric film <b>111</b> under conditions that the substrate temperature is 550° C., the partial pressure of oxygen is 20% and the RF power is 100 W, thereby forming a dielectric layer <b>116</b> with a thickness of 100 nm. Then, Pt is deposited by a sputtering process on the dielectric layer <b>116</b> and then is patterned by Ar milling using a hard mask of SiO₂(not shown), thereby forming an upper electrode <b>119</b> facing the intermediate electrode <b>114</b> with the dielectric layer <b>116</b> interposed therebetween. Thereafter, the hard mask is removed by diluted hydrofluoric acid or the like.

P-0196[0196] In this embodiment, each of the intermediate electrode <b>114</b> and the upper electrode <b>119</b> has a size of 2.5 μm×4 μm, which is the same as the size of the MOS transistor.

P-0197[0197] Then, in a process step shown in FIG. 26D, SiO₂is deposited by plasma CVD using TEOS (tetraethylorthosilicate) and then is planarized by a CMP process, thereby forming a second interlevel dielectric film <b>121</b>. Then, the second interlevel dielectric film <b>121</b> and the dielectric layer <b>116</b> are dry-etched using a resist mask, thereby forming contact holes. Subsequently, an AlSiCu alloy is deposited by a sputtering process over the substrate and then is dry-etched using a resist mask, thereby forming interconnects <b>125</b><i>a</i>, <b>125</b><i>b </i>and <b>125</b><i>c </i>on the second interlevel dielectric film <b>121</b> to connect with the upper electrode <b>119</b>, the pad <b>115</b><i>a</i>, and the pad <b>115</b><i>b</i>, respectively. The interconnect <b>125</b><i>a </i>is connected to a control-voltage supply unit <b>110</b> (not shown).

P-0198[0198] In this manner, the semiconductor device shown in FIG. 22 is fabricated.

P-0199[0199] The semiconductor device of this embodiment has a structure shown in the equivalent circuit in FIG. 22. However, in reality, as shown in FIGS. 23 through 26, the dielectric capacitor <b>104</b> having a structure in which the dielectric layer <b>116</b> is interposed between the intermediate electrode <b>114</b> and the upper electrode <b>119</b> operates also as an electric resistor shown in FIG. 22. That is to say, the dielectric capacitor <b>104</b> and the resistor <b>106</b> shown in FIG. 22 are one and the same, and electric resistance is a resistance component of the dielectric capacitor. Therefore, in the semiconductor device of this embodiment, the structure shown in the equivalent circuit in FIG. 22 is made simple, as compared to the case where the dielectric capacitor <b>104</b> and the resistor <b>106</b> are disposed separately.

P-0200[0200] Hereinafter, a driving method for and operation of the semiconductor device of this embodiment will be described.

P-0201[0201]FIG. 27 is a graph showing a characteristic of a pass current flowing between the intermediate electrode <b>114</b> and the upper electrode <b>119</b> through the dielectric layer <b>116</b> upon the application of a voltage to both electrodes of the dielectric capacitor <b>104</b> including the dielectric layer <b>116</b> of BST. As shown in FIG. 27, the material BST has a characteristic that the resistance value is almost constant while the electric field intensity is low, so that a pass current value varies in proportion to the voltage. In FIG. 27, since the abscissa uses a log scale, the characteristic in the graph is represented by axisymmetric curves with respect to 0V in the negative- and positive-voltage ranges.

P-0202[0202] A method for driving the semiconductor device of this embodiment including the dielectric layer <b>116</b> having such a characteristic and operation of the device will be hereinafter described.

P-0203[0203]FIG. 28 is a graph showing a drain current-applied voltage characteristic for describing a driving method for and operation of the semiconductor device of this embodiment. In FIG. 28, the abscissa represents a voltage applied between the Si substrate <b>101</b> and the interconnect <b>125</b><i>a </i>(hereinafter simply referred to as an applied voltage), while the ordinate represents a drain current flowing between the drain and source regions <b>103</b><i>a </i>and <b>103</b><i>b</i>. In evaluating the drain current-applied voltage characteristic for each of the semiconductor devices according to this embodiment and the following embodiments, a voltage of 1V is applied between the drain and source regions <b>103</b><i>a </i>and <b>103</b><i>b. </i>

P-0204[0204] The semiconductor device of this embodiment has a structure in which the MOS capacitor, in which the gate insulating film <b>107</b> is sandwiched between the Si substrate <b>101</b> and the gate electrode <b>109</b>, and the dielectric capacitor <b>104</b>, in which the dielectric layer <b>116</b> is sandwiched between the intermediate electrode <b>114</b> and the upper electrode <b>119</b>, are connected in series. Thus, in the semiconductor device, the applied voltage is applied, being distributed to the respective capacitors.

P-0205[0205] For example, in an measurement of the semiconductor device of this embodiment shown in FIG. 28 where the applied voltage is set in the range of −3 V to +3 V, when the maximum voltage of +3 V is applied, voltages of 2.2 V and 0.8 V are respectively distributed to the MOS capacitor and the dielectric capacitor. As shown in FIG. 27, in the dielectric capacitor, a leakage current is very small in the voltage range of −0.8 V to 0.8 V, both inclusive, in this measurement.

P-0206[0206] As shown in FIG. 28, when the semiconductor device of this embodiment in an initial state operates at high speed and at a pulse voltage with a frequency of about 1 MHz, for example, the semiconductor device exhibits a characteristic represented by a characteristic curve including points A and O (hereinafter referred to as an A-O curve).

P-0207[0207] In the range not higher than about 0 V, though the A-O curve is not shown therein, the drain current is at a noise level, i.e., at a level sufficiently smaller than 10⁻⁸(A). Therefore, when the applied voltage is 3 V, for example, a drain current of about 1×10⁻³(A) flows (the point A in FIG. 28). When the applied voltage is then decreased to 0 V, the drain current is at a noise level (the point O in FIG. 28). That is to say, when the semiconductor device of this embodiment operates at a high speed of about 1 MHz, the drain current increases according to the applied voltage, so that the device operates as the MOS transistor.

P-0208[0208] Next, if the state represented by the point A in FIG. 28, i.e., the state in which a voltage of +3 V is applied to the upper electrode <b>119</b>, is maintained, a charge is gradually accumulated in the intermediate electrode <b>114</b> by the pass current flowing through the dielectric layer <b>116</b>. In this state, a charge is also accumulated in the gate electrode <b>109</b> of the MOS transistor connected to the intermediate electrode, thus changing the threshold value of the MOS transistor. Accordingly, the applied voltage-drain current characteristic of the semiconductor device also changes.

P-0209[0209] For example, if an applied voltage of +3 V is held for 100 seconds and then a voltage is applied to the upper electrode <b>119</b> at about 1 MHz, the characteristic changes, drawing a curve including points B and C in FIG. 28. That is to say, the applied voltage-drain current characteristic (hereinafter referred to as a VG-ID characteristic) of the MOS transistor can be changed using the product of the magnitude of the applied voltage and the holding time thereof.

P-0210[0210] The difference in drain current between the initial state and the state with an applied voltage of +3 V held for 100 seconds is one or more orders of magnitude upon the application of a voltage of +2 V, while being five or more orders of magnitude upon the application of a voltage of 0 V. Thus, if the semiconductor device of this embodiment is used as a memory, for example, multilevel information can be read out by detecting the drain current.

P-0211[0211] In this manner, in the semiconductor device of this embodiment, a long application of a voltage to the upper electrode <b>119</b> in a voltage range in which the resistance value of the dielectric capacitor <b>104</b> can be considered almost constant is used as write information, thereby allowing modulation of the characteristics of the MOS transistor such that the drain current increases with the applied voltage as compared to the initial state. On the other hand, though not shown, if the state is held at a negative voltage of −3 V, for example, the characteristics of the MOS transistor can be modulated such that a smaller amount of drain current flows upon the applied voltage than that in the initial state.

P-0212[0212] As described above, the semiconductor device of this embodiment can perform a storing operation by a driving method completely different from that for the known semiconductor device functioning as a multilevel memory.

P-0213[0213] In addition, the semiconductor device of this embodiment has its characteristics changed, reflecting the history of earlier written information. Therefore, the semiconductor device is applicable not only as a multilevel memory but also as a neuron element.

P-0214[0214] In the application as a neuron element, a plurality of semiconductor devices according to this embodiment are connected to each other so that a load signal is applied to each interconnect <b>125</b><i>a </i>and an output signal from a previous-stage neuron element is added to each drain region <b>103</b><i>a</i>. At this time, if a voltage applied to the interconnect <b>125</b><i>a </i>is high and the pulse width thereof is long, current easily flows from the semiconductor devices. Such an application to a neuron element will be described in detail in a later embodiment.

P-0215[0215] In the semiconductor device of this embodiment, if an applied voltage of +3 V is hold for 100 seconds to create a state represented by the B-C curve shown in FIG. 28, and then the interconnect <b>125</b><i>a</i>, for example, is grounded, the characteristic curve of this semiconductor device gradually moves from the B-C curve toward the A-O curve and then returns to the A-O curve in approximately 100 seconds. This procedure shows a reverse operation of the storing operation for written information and also shows that the device has a function of “forgetting” information once written with the passage of time. In a practical operation, since the device operates at high speed of 100 MHz, for example, such a “forgetting” function is effective in the case where no signal is input for a long period. Specifically, the forgetting function makes an effective change in a portion which is seldom used upon the input of a next leaning operation, thus improving a leaning function of the element.

P-0216[0216] In the semiconductor device of this embodiment, the amount of a charge accumulated in the intermediate electrode <b>114</b> and the gate electrode <b>109</b> is adjusted depending on the time period over which the applied voltage is held, thereby controlling flowability of the drain current. As in the case of the speed of writing information, the speed of forgetting can also be adjusted by controlling the magnitude of the pass current in a voltage range in which the pass current varies in proportion to the voltage.

P-0217[0217]FIG. 29 shows a correlation between a pass current flowing through the dielectric capacitor <b>104</b> of the semiconductor device of this embodiment and a recovery time. In FIG. 29, the recovery time is a time period over which the semiconductor device returns to the initial state after the application of a write voltage (i.e., time period required for forgetting information).

P-0218[0218]FIG. 29 shows that the recovery time tends to be shorter as the pass current increases in a voltage range in which the resistance value of the dielectric layer <b>116</b> can be considered constant. From this tendency, it is shown that the charge accumulated in the intermediate electrode <b>114</b> and the gate electrode <b>109</b> by the write voltage is leaking as a pass current.

P-0219[0219] In FIG. 29, in view of holding stored information, the pass current flowing upon the application of a voltage of 1 V to both ends of the capacitor <b>104</b> is set at 100 (mA/cm²) or less and the recovery time has a holding time of 10 μsec. or more, such that a modulation memory of the transistor is held for a sufficiently long period relative to a computation time. The pass current needs only to be sufficiently small with respect to a period over which data is to be held.

P-0220[0220] For example, in the semiconductor device of this embodiment, the pass current is about 10⁻⁸(mA/cm²) upon the application of 1V as shown in the graph of FIG. 27. Therefore, the holding time is about 100 seconds as shown in FIG. 29.

P-0221[0221] As described above, the semiconductor device of this embodiment has a structure in which a dielectric capacitor and an electric resistor are disposed in parallel and connected to the gate electrode of a normal MOS transistor, thereby allowing the history of a signal to be stored as the change in an applied voltage-drain current characteristic of the MOS transistor.

P-0222[0222] In addition, in the semiconductor device of this embodiment, the dielectric capacitor <b>104</b> and the resistor <b>106</b> are one and the same, thus simplifying the structure of the device. Thus, if the semiconductor device of this embodiment is used as a memory cell by connecting the drain region <b>103</b><i>a </i>to a bit line and connecting the interconnect <b>125</b><i>a </i>to a word line, for example, a multilevel memory having a small size can be fabricated. Even if the semiconductor device of this embodiment is used as a neuron element, an advantage of allowing higher degree of integration is also obtained.

P-0223[0223] However, the information once stored is lost after a lapse of the recovery time. In view of this, the dielectric capacitor <b>104</b> and the resistor <b>106</b> may be fabricated separately and the resistor may be made of a material through which a smaller amount of pass current flows. Then, information can be stored for a longer time.

P-0224[0224] In the semiconductor device of this embodiment, BST is used as a dielectric material. Alternatively, the dielectric material may be any other material so long as current flows through the film. As such materials, strontium titanate, titanium oxide, tantalum oxide, aluminum oxide, zirconium oxide, cerium oxide, gadolinium oxide, lanthanum oxide, for example; are especially effective.

P-0225[0225] The distribution ratio of the voltage applied to the upper electrode <b>119</b> between the dielectric capacitor and the MOS transistor varies in inverse proportion to the capacitance of the capacitor. Thus, voltages distributed to the respective devices can be adjusted as required by changing the dielectric material, the area of the electrode, the thickness of the dielectric layer <b>116</b> or the gate insulating film, for example.

P-0226[0226] The gate insulating film of the MOS transistor is made of SiO₂in this embodiment. Alternatively, another insulator or dielectric such as silicon nitride may be used. Any type of field-effect transistor as well as the MOS transistor may be used for the semiconductor device of this embodiment. This is also applicable to the following embodiments.

P-0227[0227] In the semiconductor device of this embodiment, the write time is 100 seconds under a condition that the applied voltage is +3 V. This is only an example of a write time and does not mean that the amount of the charge accumulated in the intermediate electrode is saturated. The time period over which the charge is saturated is a little longer than 100 seconds and will vary by changing the design of the device as described above. The write voltage is not limited to +3 V so long as the resistance value of the dielectric layer <b>116</b> is in a certain range. If the write voltage is low, the time period required for writing becomes longer.

P-0228[0228] In the semiconductor device of this embodiment, the resistance component of the dielectric layer <b>116</b> in the dielectric capacitor <b>104</b> also functions as the resistor <b>106</b>. Alternatively, the dielectric capacitor <b>104</b> and the resistor <b>106</b> may be provided separately from each other. In such a case, although the area increases, design conditions can be adjusted as required. For example, a leakage current from the resistor <b>106</b> is reduced or the time period required for writing is shortened, with the dielectric layer <b>116</b> and the resistor <b>106</b> made of different materials.

P-0229[0229] In the semiconductor device of this embodiment, a charge is accumulated in the intermediate electrode <b>114</b> in proportion to the product of the applied voltage and the application time. Thus, if the device is applied to a neuron element, application time of a maximum voltage is varied, thereby allowing weighting. In addition, a signal once input is “forgotten” after the lapse of the recovery time unless another signal is input thereafter. As a result, for example, neuron elements used for computation are separated from unused neuron elements. That is to say, more effective computation is achieved over the long term as compared to the known neuron element.

P-0230[0230] Embodiment 6

P-0231[0231] Next, a sixth embodiment of the present invention will be described with reference to the drawings.

P-0232[0232] In this embodiment, a method that is for driving the same semiconductor device as in the fifth embodiment but is different from the method described in the fifth embodiment will be described. For this reason, only a driving method for and operation of the semiconductor device will be hereinafter described.

P-0233[0233]FIG. 30 is a graph showing a characteristic of a pass current flowing between the intermediate electrode <b>114</b> and the upper electrode <b>119</b> through the dielectric layer <b>116</b> when a voltage is applied between both electrodes of the dielectric capacitor <b>140</b> including the dielectric layer <b>116</b> of BST in the same semiconductor device as in the fifth embodiment shown in FIGS. 23 through 25.

P-0234[0234] In general, a perovskite oxide such as BST has a characteristic that the resistance value is almost constant in a range in which the electric field intensity is low, but when a voltage is further increased, the pass current increases exponentially with a voltage higher than about 1.3 V, as indicated by the characteristic curve shown in FIG. 30. Even in the negative range of the applied voltage, an applied voltage-pass current characteristic is represented by substantially symmetric curves with respect to the axis of 0V.

P-0235[0235] This abrupt increase in the pass current can be explained as a Schottky current. Specifically, a barrier is present at the interface between the intermediate or upper electrode <b>114</b> or <b>119</b> and the dielectric layer <b>116</b> so that current hardly flows while the electric field intensity is below a certain degree. However, when the electric field intensity exceeds the certain degree, current begins to flow over the barrier. This current is called a Schottky current.

P-0236[0236] Hereinafter, a method for driving the semiconductor device of this embodiment utilizing such a characteristic of the dielectric capacitor will be described.

P-0237[0237]FIG. 31 is a graph showing a drain current-applied voltage characteristic for explaining a driving method for and operation of the semiconductor device of this embodiment. In FIG. 31, the applied voltage is a voltage applied between the interconnect <b>125</b><i>a </i>(or the upper electrode <b>119</b>) and the substrate electrode <b>108</b>.

P-0238[0238] The semiconductor device of this embodiment has a structure in which the MOS capacitor, in which the gate insulating film <b>107</b> is sandwiched between the Si substrate <b>101</b> and the gate electrode <b>109</b>, and the dielectric capacitor, in which the dielectric layer <b>116</b> is sandwiched between the intermediate electrode <b>114</b> and the upper electrode <b>119</b>, are connected in series. Thus, the applied voltage is distributed to the respective capacitors. For example, when the applied voltage is +2 V, the applied voltage is distributed to 1.5 V and 0.5 V, which are applied to the MOS capacitor and the dielectric capacitor, respectively. When the applied voltage is +8 V, the applied voltage is distributed to 6.0 V and 2.0 V, which are applied to the MOS capacitor and the dielectric capacitor <b>104</b>, respectively. As shown in FIG. 30, the dielectric capacitor <b>104</b> of this embodiment operates as a resistor having a substantially constant resistance value upon the application of a voltage of 0.5 V, while operating a resistor in which the resistor is a relatively small, i.e., current increases exponentially with the increase in voltage, upon the application of a voltage of 2.0 V.

P-0239[0239] In the method for driving the semiconductor device of this embodiment, a voltage at about 50 kHz, for example, is applied so as to operate the semiconductor device.

P-0240[0240] First, in the initial state, supposing the applied voltage is in the range of +2 V, the semiconductor device of this embodiment exhibits a characteristic moving along a characteristic curve including the points D and O′ (hereinafter referred to as a D-O′ curve) in FIG. 31. In the range not higher than about 0 V, though the D-O′ curve is not shown therein, a drain current is at a noise level, i.e., at a level sufficiently smaller than 10⁻⁸(A) In this state, when a voltage of 2 V is applied, for example, a drain current of about 6×10⁻⁴flows (the point D). Then, when a voltage of 0 V is applied, the drain current returns to the state indicated by the point O at which only current almost at a noise level flows. Even if a voltage of 2 V or less is applied and then a voltage of 0 V is applied, the drain current is substantially at a noise level. That is to say, the semiconductor device of this embodiment operates as the MOS transistor at the applied voltage in the range of −2 V to +2 V.

P-0241[0241] Then, when a high voltage of +8 V is applied, for example, the pass current flowing through the dielectric layer <b>116</b> increases exponentially, so that a charge is accumulated in the intermediate electrode <b>114</b> and the gate electrode <b>109</b> in a very short time. In this embodiment, the device operates with the frequency of a pulse voltage to be applied set at 50 kHz. Alternatively, if a pulse voltage of +8 V is applied for 20 μsec., it is possible to shift the characteristic to the curve including points E and F shown in FIG. 31. That is to say, if the applied voltage is increased, the VG-ID characteristic of the MOS transistor can be changed in a short time. The time period required for accumulating a charge is 100 seconds in the fifth embodiment. On the other hand, according to the driving method of this embodiment, the time period is greatly shortened, i.e., 20 μsec.

P-0242[0242] Hereinafter, the operation of the semiconductor device of this embodiment will be described in further detail. When a pulse voltage of +8 V is applied, the pass current flowing through the dielectric layer <b>116</b> increases exponentially, so that a charge is accumulated in the intermediate electrode <b>114</b> and the gate electrode <b>109</b> rapidly.

P-0243[0243] Thereafter, when the applied voltage is returned to 0V, the characteristic changes into the state represented by the point F in FIG. 31 so that the drain current varies. When a voltage of +2 V is further applied to the upper electrode <b>119</b>, the characteristic changes from the state at the point F to the state at the point E, so that the a drain current of about 3×10⁻³(A) flows. However, when the applied voltage is set at <b>0</b>V again, the characteristic returns to the state at the point F. That is to say, even if a low pulse voltage of about 0V to 2 V is applied after the input of a high pulse voltage, the drain current-applied voltage characteristic of the semiconductor device does not change. On the other hand, when a negative pulse voltage of −2 V is applied to the upper electrode <b>119</b> in the state indicated by the point F, the state of the semiconductor device moves to a point G, so that the drain current decreases by about one order of magnitude. When the applied voltage is then set at 0V again, the state moves to a point H, which is close to the point F and at which the drain current is slightly smaller than in the state at the point F but the drain current does not change largely.

P-0244[0244] Based on the same principle, a voltage of −8 V is applied, for example, the characteristic of the device naturally changes into the state in which the drain current varies very slightly with a scan of +2 V upon the application of the voltage of −8 V.

P-0245[0245] As described above, according to the method for driving the semiconductor device in this embodiment, information is written in a voltage range in which the pass current flowing through the dielectric capacitor <b>104</b> increases exponentially with the rise of the applied voltage. In reading out the information, for example, the MOS transistor is driven in a voltage range in which the pass current varies substantially in proportion to the applied voltage. With this method, the time period required for writing information can be greatly shorten, as compared to the method for driving the semiconductor device described in the fifth embodiment.

P-0246[0246] By the method for driving the semiconductor device in this embodiment, the history of earlier written information can be stored as variations in device characteristics. Therefore, the semiconductor device of this embodiment can be applied not only as a multilevel memory but also as a neuron element. If the device is used as a neuron element, the time period required for writing information can be greatly shortened as compared to the method in the fifth embodiment, thus improving the computation speed largely.

P-0247[0247] Unlike the method of the fifth embodiment, the method for driving the semiconductor device in this embodiment is characterized in that the VG-ID characteristic of the MOS transistor can be changed not using the length of an applied voltage pulse but using the magnitude of the absolute value of the applied voltage. That is to say, the VG-ID characteristic can be modulated by setting only the value of the pulse voltage to be applied with the pulse thereof set periodic.

P-0248[0248] In the method for driving the semiconductor device of this embodiment, the write voltage is 8 V. Alternatively, the writing operation may be performed at higher voltages. However even when the voltage applied to the interconnect <b>125</b><i>a </i>or the upper electrode <b>119</b> is less than 8 V, for example, the write time can be shortened by reducing the capacitance of the dielectric layer through the process of reducing the area of the dielectric capacitor, the process of increasing the thickness of the dielectric layer, or other suitable processes, and eventually increasing the voltage to be distributed to the dielectric capacitor.

P-0249[0249] In the method for driving the semiconductor device of this embodiment, the interconnect <b>125</b><i>a</i>, for example, is grounded, so that the state of the semiconductor device returns to the initial state represented by the D-O′ curve in FIG. 31 with a lapse of time. That is to say, the semiconductor device of this embodiment has a function of “forgetting”, as described in the fifth embodiment.

P-0250[0250] In the method for driving the semiconductor device of this embodiment, in view of holding stored information, the pass current flowing upon the application of a voltage of 1 V to both ends of the dielectric capacitor <b>104</b> is set at 100 (mA/cm²) or less and the recovery time has a holding time of 10 μsec. or more. This is distinguished from the case where a pulse voltage having a large absolute value is applied. The method is conducted under the same conditions as in the fifth embodiment, so that the time period required for recovery is about 100 seconds in this embodiment.

P-0251[0251] Embodiment 7

P-0252[0252] A semiconductor device according to a seventh embodiment of the present invention is the same as the semiconductor device of the sixth embodiment, except for part of the structure, a driving method for and operation of the device.

P-0253[0253]FIG. 32 is an equivalent circuit diagram showing the semiconductor device of this embodiment. As shown in FIG. 32, the semiconductor device of this embodiment is characterized by having a structure in which a dielectric capacitor <b>104</b><i>a </i>and a resistor <b>106</b> are disposed in parallel and connected to a gate electrode <b>109</b> of a field-effect transistor (hereinafter referred to an MOS transistor).

P-0254[0254] The semiconductor device of this embodiment has substantially the same structure as those of the devices in the fifth and sixth embodiments but is different from the devices in that a ferroelectric layer <b>131</b> of a ferroelectric material is used instead of the dielectric layer <b>116</b>.

P-0255[0255] Specifically, the semiconductor device of this embodiment includes: a controlvoltage supply unit <b>110</b>; an MOS transistor including the gate electrode <b>109</b>, drain and source regions <b>103</b><i>a </i>and <b>103</b><i>b </i>and a substrate electrode <b>108</b>; the ferroelectric capacitor <b>104</b><i>a</i>; and the resistor <b>106</b>. The ferroelectric capacitor <b>104</b><i>a </i>and the resistor <b>106</b> are disposed in parallel and interposed between the gate electrode <b>109</b> of the MOS transistor and the control-voltage supply unit <b>110</b>. The ferroelectric capacitor <b>104</b><i>a </i>includes: an upper electrode <b>119</b>; an intermediate electrode <b>114</b>; and a ferroelectric layer <b>131</b> of bismuth titanate (BIT) sandwiched between the upper electrode <b>119</b> and the intermediate electrode <b>114</b> and having a thickness of 300 nm. In the semiconductor device of this embodiment, the ferroelectric layer <b>131</b> also functions as the resistor <b>106</b>. The source region <b>103</b><i>b </i>and the substrate electrode <b>108</b> are connected to each other.

P-0256[0256]FIGS. 33A through 33D are cross-sectional views showing respective process steps for fabricating the semiconductor device of this embodiment. In FIGS. 33A through 33D, the same components as those shown in FIGS. 26A through 26D are identified by the same reference numerals.

P-0257[0257] First, in a process step shown in FIG. 33A, through the same procedure as in the fifth embodiment, an isolation oxide film <b>105</b> is formed in a Si substrate <b>101</b> by a LOCOS process. Thereafter, a SiO₂film having a thickness of 5 nm is formed by a pyrogenic oxidation performed on the substrate, and then polysilicon containing an n-type impurity is deposited over the SiO₂film. Then, the polysilicon layer and the SiO₂film are patterned, thereby forming a gate electrode <b>109</b> and a gate insulating film <b>107</b>, respectively, over the Si substrate <b>101</b>. Subsequently, a p-type impurity such as boron is implanted into the Si substrate <b>101</b>, thereby forming drain and source regions <b>103</b><i>a </i>and <b>103</b><i>b </i>to the sides of the gate electrode <b>109</b>. The MOS transistor fabricated in this process step has a gate length of 1 μm and a gate width of 10 μm.

P-0258[0258] Next, in a process step shown in FIG. 33B, through the same procedure as in the fifth embodiment, after a first interlevel dielectric film <b>111</b> of SiO₂has been formed over the substrate, contact holes are formed by dry etching using a resist mask and then are filled with polysilicon, thereby forming plug interconnects <b>113</b><i>a</i>, <b>113</b><i>b </i>and <b>113</b><i>c </i>of polysilicon, respectively. Thereafter, an intermediate electrode <b>114</b> connected to the gate electrode <b>109</b> via the plug interconnect <b>113</b><i>a</i>, a pad <b>115</b><i>a </i>connected to the drain region <b>103</b><i>a </i>via the plug interconnect <b>113</b><i>b</i>, and a plug interconnect <b>15</b><i>b </i>connected to the source region <b>103</b><i>b </i>via the plug interconnect <b>113</b><i>c</i>, are formed. The components are respectively made of the same materials as corresponding ones in the fifth embodiment. However, the intermediate electrode has a size of 1 μm×2 μm, which is one-fifth of the area of the MOS transistor.

P-0259[0259] Then, in a process step shown in FIG. 33C, BST is deposited by a sputtering process under conditions that the substrate temperature is 600° C., the partial pressure of oxygen is 20% and the RF power is 100 W, thereby forming a first ferroelectric layer <b>131</b> having a thickness of 300 nm over the substrate. Thereafter, through the same procedure as in the fifth embodiment, an upper electrode <b>119</b> is formed on part of the ferroelectric layer <b>131</b>, facing the intermediate electrode. The upper electrode <b>119</b> has a size of 1 μm×2 μm, which is the same as the size of the intermediate electrode <b>114</b> and one-fifth of the area of the MOS transistor.

P-0260[0260] Then, in a process step shown in FIG. 33D, through the same procedure as in the first embodiment, a second interlevel dielectric film <b>121</b> is formed on the ferroelectric layer <b>131</b>. Subsequently, an interconnects <b>125</b><i>a</i>, <b>125</b><i>b </i>and <b>125</b><i>c </i>are formed on the second interlevel dielectric film <b>121</b> to reach the upper electrode <b>119</b>, the pad <b>115</b><i>a </i>and the pad <b>115</b><i>b</i>, respectively.

P-0261[0261] In the semiconductor device of this embodiment fabricated by the method described above, the ferroelectric capacitor <b>104</b><i>a </i>and the resistor <b>106</b> are one the same, and the resistor <b>106</b> is a resistance component of the ferroelectric capacitor <b>104</b><i>a. </i>

P-0262[0262] Therefore, the structure shown in FIG. 32 can be achieved in a relatively small area. In addition, the number of fabrication process steps is smaller than in the case where the ferroelectric capacitor <b>104</b><i>a </i>and the resistor <b>106</b> are fabricated separately.

P-0263[0263] Hereinafter, a driving method for and operation of the semiconductor device of this embodiment will be described.

P-0264[0264]FIG. 34A shows an equivalent circuit in a coarse control in which stored information is changed largely in the semiconductor device of this embodiment. FIG. 34B shows an equivalent circuit in a fine control in which stored information is changed slightly in the semiconductor device of this embodiment. FIG. 35 is a graph showing a characteristic of a pass current when a voltage is applied to both ends of the ferroelectric capacitor <b>104</b><i>a</i>. In this embodiment, the pass current is a current flowing between the intermediate electrode <b>114</b> and the upper electrode <b>119</b> through the ferroelectric layer <b>131</b>.

P-0265[0265] In this embodiment, an oxide, e.g., BIT used as a ferroelectric material, whose elements have a composition represented as ABO₃and whose crystal structure has a perovskite structure, exhibits the following characteristic, as BST used in the first and sixth embodiments. Specifically, the resistance value thereof is so small that it may be ignored while an applied electric field intensity is small. When the voltage is further increased, the pass current increases exponentially. FIG. 35 shows that the pass current also increases exponentially upon the application of a voltage higher than about 1.8 V in the ferroelectric capacitor <b>104</b><i>a </i>of this embodiment. When a negative voltage is applied, the characteristic is represented by substantially symmetric curves with respect to the axis of 0V.

P-0266[0266] Therefore, as shown in FIG. 35, when a voltage distributed to the ferroelectric is in a coarse control, i.e., not higher than −2.3 V or not lower than +2.3 V, the ferroelectric also functions as the resistor <b>106</b>, so that a leakage current I flows. In this case, the equivalent circuit has a configuration in which the ferroelectric capacitor <b>104</b><i>a </i>and the resistor <b>106</b> are disposed in parallel and connected to the gate electrode <b>109</b> of the MOS transistor, as shown in FIG. 34A.

P-0267[0267] On the other hand, when a voltage distributed to the ferroelectric is in a fine control, i.e., in the range of −1.4 V to +1.4 V, both inclusive, current hardly flows in the ferroelectric so that the ferroelectric functions as an insulator. In this case, the equivalent circuit has a configuration in which only the ferroelectric capacitor <b>104</b><i>a </i>is connected to the gate electrode <b>109</b> of the MOS transistor, as shown in FIG. 34B.

P-0268[0268] The semiconductor device of this embodiment has a structure in which the MOS capacitor, in which the gate insulating film <b>107</b> is sandwiched between the Si substrate <b>101</b> and the gate electrode <b>109</b>, and the ferroelectric capacitor, in which the ferroelectric layer <b>131</b> is sandwiched between the intermediate electrode <b>114</b> and the upper electrode <b>119</b>, are connected in series. Thus, the applied voltage is distributed to the respective capacitors. For example, when a voltage of +2 V is applied to the entire device, the applied voltage is distributed to 1.2 V and 0.8 V, which are applied to the MOS transistor and the ferroelectric capacitor <b>104</b><i>a</i>, respectively. When the applied voltage is +6 V, the applied voltage is distributed to 3.6 V and 2.4 V, which are applied to the MOS transistor and the ferroelectric capacitor <b>104</b><i>a</i>, respectively.

P-0269[0269] In the semiconductor device of this embodiment, if the voltage to be distributed to the ferroelectric capacitor <b>104</b><i>a </i>is set in the coarse control range, the leakage current can be increased and the potential at the floating gate (i.e., the gate electrode <b>109</b>) can be changed largely. If the voltage to be distributed to the ferroelectric capacitor <b>104</b><i>a </i>is set in the fine control range, the leakage current can be reduced, information can be stored, and the potential at the floating gate can be finely adjusted by changing the polarization of the ferroelectric.

P-0270[0270]FIG. 36 is a graph showing an example of an actual method for applying a voltage based on the findings described above. In this example, a pulse voltage of 2.5 V is applied to the ferroelectric in an initial period of 1 μsec. This allows a charge to be accumulated in the floating gate through the ferroelectric at high speed. During this period, the ferroelectric is polarized in one direction.

P-0271[0271] Next, after 5 μsec., a small negative voltage is applied to the ferroelectric for 1 μsec. During this period, the leakage current from the ferroelectric is so small that it may be neglected, resulting in that the polarization of the ferroelectric is gradually inverted little by little. In this manner, the amount of the charge accumulated in the floating gate can be varied slightly.

P-0272[0272] In a general ferroelectric gate transistor, the amount of charge in the floating gate can be varied only by the polarization value of the ferroelectric. On the other hand, if the driving method of this embodiment is used, the amount of the charge can be varied in a very wide range. Specifically, an ON resistance value of the MOS transistor can be determined in a very wide range and in detail. This means that the device of this embodiment functions as an analog memory in which multilevel information can be continuously stored according to the amount of the charge accumulated in the floating electrode.

P-0273[0273]FIG. 37 is a characteristic graph for describing operation of the semiconductor device of this embodiment in the initial state. In FIG. 37, the abscissa represents an applied voltage, while the ordinate represents a drain current. In this graph, the applied voltage indicates a voltage applied between the interconnect <b>125</b><i>a </i>(or the upper electrode <b>119</b>) and the Si substrate <b>101</b>.

P-0274[0274] As shown in FIG. 37, when a voltage in the range of +2 V is applied to the semiconductor device of this embodiment in the initial state, the VG-ID characteristic of the MOS transistor in the device exhibits a hysteresis moving counterclockwise. That is to say, the semiconductor device of this embodiment operates as a so-called ferroelectric gate transistor.

P-0275[0275] Therefore, even when a voltage of +2 V is applied to the semiconductor device and then removed, for example, a charge is induced into the intermediate electrode <b>114</b> due to the polarization of the ferroelectric layer <b>131</b>, thus causing a potential. Thus, a drain current of about 2 μA flows even upon the application of a voltage of 0 V. On the other hand, when a voltage of −2 V is applied and then removed, the drain current becomes extremely small (i.e., 10⁻⁸A or less, not shown) conversely. In this case, the voltage between source and drain is also 1 V, as in the fifth embodiment.

P-0276[0276] If a voltage of +6 V is then applied to the semiconductor device of this embodiment, the drain current can be set at another value.

P-0277[0277]FIG. 38 is a graph showing a drain current when a pulse voltage of 2 V is repeatedly applied to the semiconductor device of this embodiment to which a write voltage of +6 V has been applied. The interval of the pulse voltage in this graph is 20 μsec.

P-0278[0278] As shown in FIG. 38, when a write voltage of +6 V is applied to the semiconductor device of this embodiment in the initial state, a voltage of 2.4 V is distributed to the ferroelectric capacitor, so that the pass current increases exponentially. Accordingly, a charge is accumulated in the intermediate electrode <b>114</b> and the gate electrode <b>109</b> so that the drain current increases by more than two orders of magnitude. Even if the same pulse voltage of +2 V is input thereafter, the device exhibits the characteristic that the drain current hardly varies and is about 1×10⁻³(A).

P-0279[0279] This graph shows that data can be stored in the semiconductor device of this embodiment with stability by applying a high write voltage thereto.

P-0280[0280]FIG. 39 is a graph showing an applied voltage-drain current characteristic of the semiconductor device of this embodiment when scanned in the applied-voltage range of ±2 V after the application of +6V.

P-0281[0281] First, when a voltage of +6 V is applied to the semiconductor device and then is removed, the drain current takes a value indicated by a point I in FIG. 39.

P-0282[0282] Next, when a voltage of 2 V is applied to the semiconductor device in the state indicated by the point I and then the voltage is removed, the drain current describes a trajectory from the point I to a point J shown in FIG. 39. After the removal of the voltage, the drain current returns to the point I. The state indicated by the point I corresponds to the state in which a pulse voltage is applied as shown in FIG. 38.

P-0283[0283] If a voltage of −2 V is applied to the semiconductor device in the state indicated by the point I, the drain current moves to the point K, i.e., decreases by about two orders of magnitude to be 1×10⁻⁵(A) or less. Subsequently, when the voltage is removed, the drain current moves to a point L, i.e., decreases by about one order of magnitude as compared to the state at the point I before the application of the voltage.

P-0284[0284] In the semiconductor device of the sixth embodiment, there is no substantial difference in the drain current between the point F and a point H in FIG. 31. This makes the semiconductor device of this embodiment differ largely from the semiconductor devices of the fifth and sixth embodiments.

P-0285[0285] In this manner, the semiconductor device of this embodiment can hold more data than the semiconductor devices of the fifth and sixth embodiments.

P-0286[0286] Then, when a voltage of +2 V is applied to the semiconductor device in the state indicated by the point L in FIG. 39, the drain current moves to a point M. When the voltage is then removed, the drain current moves to a point N. In this case, the drain current varies, as describing the trajectory indicated by the points L→M→N, so that the drain current at the point N is larger than that at the previous point L. Thus, by thus scanning using a small applied voltages of ±2 V after the application of a high voltage of +6 V, the drain current can be further modulated.

P-0287[0287] On the other hand, a high negative pulse voltage may be input as a write voltage.

P-0288[0288]FIG. 40 is a graph showing a drain current in the case where a voltage of −6 V is applied to the semiconductor device of this embodiment before a pulse voltage of +2 V is applied and then removed. The pulse interval of the pulse voltage is 20 μsec.

P-0289[0289] As shown in FIG. 40, by applying a voltage of −6 V to the semiconductor device of this embodiment in the initial state, the drain current at 0 V is four orders of magnitude smaller than that in the initial state. In this case, the variations in the drain current are small when a pulse voltage of +2 V is repeatedly applied and removed.

P-0290[0290]FIG. 41 is a graph showing an applied voltage-drain current characteristic of the semiconductor device of this embodiment when scanned in the applied voltage range of ±2 V after the input of a pulse voltage of −6 V. Though hysteresis is also observed in this state at an applied voltage of 0V, the drain current is extremely low even upon the application of a voltage with each polarity. By thus applying a negative voltage, a small drain current, which is distinguished from that in the case of application of a positive voltage, is obtained.

P-0291[0291] As described above, in the semiconductor device of this embodiment, operations of driving the MOS transistor in a voltage range in which a resistance component of the ferroelectric capacitor <b>104</b><i>a </i>has a substantially constant resistance value (a low voltage range), and of writing in a range in which a current flowing through the ferroelectric capacitor <b>104</b><i>a </i>increases exponentially, are properly used.

P-0292[0292] In the semiconductor device of this embodiment, the change in the applied voltage-drain current characteristic depends on the change in the VG-ID characteristic of the MOS transistor which is caused by accumulating a charge in the intermediate electrode <b>114</b> through the ferroelectric layer <b>131</b> and thereby accumulating a charge also in the gate electrode <b>109</b> of the MOS transistor. Especially, in the semiconductor device of this embodiment, the amount of the charge accumulated in the intermediate electrode and the gate electrode <b>109</b> can be changed depending on the direction of polarization of the ferroelectric <b>104</b><i>a</i>. Thus, the semiconductor device of this embodiment is usable as a multilevel memory which can take much more levels than the semiconductor devices of the fifth and sixth embodiments.

P-0293[0293] A large modulation of the drain current caused by a high pulse voltage and a small modulation of the drain current caused by a low pulse voltage can be respectively reflected as modulations of the drain current. Therefore, the semiconductor device of this embodiment is applicable as a neuron element with extremely high flexibility in weighting.

P-0294[0294] As the semiconductor devices of the fifth and sixth embodiments, the semiconductor device of this embodiment also has a function of “forgetting” by making the interconnect <b>125</b><i>a </i>to be grounded, for example, and thereby restoring the characteristic to the initial state.

P-0295[0295] In the semiconductor device of this embodiment, to hold stored information, the pass current flowing upon the application of a voltage of 1 V to both ends of the ferroelectric capacitor is set equal to or smaller than 100 (mA/cm²) and the recovery time is set equal to or longer than 10 μsec., thus making a clear difference between the modulation of the drain voltage caused by the polarization of the ferroelectric and the modulation in the device of this embodiment. This tendency is substantially the same as in the semiconductor device of the fifth embodiment shown in FIG. 29. The time period required for recovery is about 100 seconds.

P-0296[0296] In the semiconductor device of this embodiment, the ferroelectric layer <b>131</b> and the resistor <b>106</b> may be separately provided, as in the semiconductor device of the fifth embodiment. In such a case, to extend the time period required for holding information, for example, the semiconductor device can be designed properly to meet requirements by making the resistor <b>106</b> out of a ferroelectric material that is less conductive than a ferroelectric material constituting the ferroelectric layer <b>131</b>.

P-0297[0297] In the case where the ferroelectric layer <b>131</b> and the resistor <b>106</b> are provided separately, a dielectric may be used as a material for the resistor <b>106</b>.

P-0298[0298] In the method for driving the semiconductor device of this embodiment, a voltage range in which the ferroelectric layer has a substantially constant resistance value and a voltage range in which the pass current increases exponentially with the voltage are properly used. If the semiconductor device is driven only in a narrow voltage range in which the resistance value of the ferroelectric layer is so small that it may be neglected and the pulse width of the applied voltage is set sufficiently shorter than the recovery time, as in the fifth embodiment, the amount of the charge accumulated in the intermediate electrode <b>114</b> and the gate electrode <b>109</b> can be varied, as in the fifth embodiment.

P-0299[0299] In the semiconductor device of this embodiment, BIT is used as a material for the ferroelectric layer. Alternatively, other materials exhibiting similar ferroelectric properties such as lead titanate, lead zirconate titanate or strontium tantalite may be used as a material for the ferroelectric layer.

P-0300[0300] Embodiment 8

P-0301[0301] In a semiconductor device according to an eighth embodiment of the present invention, the resistor <b>106</b> of the seventh embodiment is replaced by a resistor <b>150</b>, which is a variable resistor (a varistor) and is made of zinc oxide (ZnO). The resistor <b>150</b> and a ferroelectric are provided separately.

P-0302[0302]FIG. 42A is a circuit diagram showing the semiconductor device of this embodiment. FIG. 42B is a graph showing a varistor characteristic of the resistor <b>150</b>. Components already shown in FIG. 32 are indicated by the same reference numerals.

P-0303[0303] As shown in FIG. 42B, some metal oxides such as ZnO have a characteristic that the resistance value changes largely with an applied voltage. Specifically, the resistor <b>150</b> of this embodiment having an electrode area of 10 μm²exhibits a resistance value of as much as about 180 GΩ in the voltage range of −1 V to +1 V, both inclusive, while the resistance value decreases drastically when the absolute value of the voltage exceeds 1.5 V.

P-0304[0304] Thus, if the voltage ranges not more than −2 V and not less than +2 V are taken as a coarse control voltage range and the range of −1 V to +1 V, both inclusive, is taken as a fine control voltage range, the semiconductor device can operate as the semiconductor device of the seventh embodiment.

P-0305[0305] In addition, in the semiconductor device of this embodiment, the resistor <b>150</b> may be made of any material, so that the range of an operating voltage can be set flexibly. For example, the voltage corresponding to the low resistance state of the resistor <b>150</b> is set slightly higher than the voltage at which the polarization of the ferroelectric is saturated, for example, a coarse control and a fine control can be performed at lower driving voltages.

P-0306[0306]FIG. 43 is a cross-sectional view showing a structure of the semiconductor device of this embodiment.

P-0307[0307] As shown in FIG. 43, a ferroelectric <b>131</b> and the resistor <b>150</b> of this embodiment may share upper and lower electrodes. Such a structure can be easily attained by using publicly known techniques. For example, a ferroelectric is deposited over the entire surface of a lower electrode and is selectively etched in part, and then, ZnO is deposited over part of the lower electrode where the ferroelectric has been removed. FIG. 43 shows an example in which the ferroelectric and the resistor are in contact with each other. Alternatively, the ferroelectric and the resistor may be apart from each other.

P-0308[0308] The resistor may be made of a perovskite oxide such as Ba_xSr_1−xTiO₃, a TiO₂-based oxide, a Fe₂O₃-based oxide, or a Cu₂O-based oxide as well as ZnO. Ba₂O₃or a rate-earth element may be added to the metal oxide described above so as to reduce the resistance of the metal oxide. Then, the resistivity and a rate of change in resistance of the metal oxide material can be controlled as required. A P-N junction of Si, an Al-added SiC semiconductor, Se, and the like may be used as a material for the resistor.

P-0309[0309] In the semiconductor device of this embodiment, a coarse control and a fine control are used properly so as to hold multilevel information excellently. An element connected in parallel with the ferroelectric is not limited to a resistor but may be any other element or circuit so long as a charge to be accumulated in a floating gate can be controlled by an applied voltage.

P-0310[0310] Embodiment 9

P-0311[0311] In a semiconductor device according to a ninth embodiment of the present invention, the resistor <b>106</b> of the seventh embodiment is replaced by two diodes connected in parallel with each other and disposed in opposite orientations.

P-0312[0312]FIG. 44 is a circuit diagram showing the semiconductor device of this embodiment. Components already shown in FIG. 32 are indicated by the same reference numerals.

P-0313[0313] As shown in FIG. 44, the semiconductor device of this embodiment includes: a control-voltage supply unit <b>110</b>; an MOS transistor; a ferroelectric capacitor <b>104</b><i>a</i>; a diode <b>152</b>; and a diode <b>154</b>. The ferroelectric <b>104</b> and the diodes <b>152</b> and <b>154</b> are connected to a gate electrode <b>109</b> of the MOS transistor and arranged in parallel. The diodes <b>152</b> and <b>154</b> are disposed in opposite orientations. That is to say, the respective input ports of the diodes <b>152</b> and <b>154</b> are connected to respective output ports.

P-0314[0314] In this embodiment, the diodes <b>152</b> and <b>154</b> are PN diodes, for example. When a forward voltage at a given level or higher is applied to these diodes, current flows, while current hardly flows upon the application of a voltage lower than the given level. Below a breakdown voltage, current hardly flows even upon the application of a reverse voltage.

P-0315[0315] As shown in FIG. 44, by connecting the two diodes in opposite orientations in parallel, current hardly flows in the voltage range of −t V to +t V, both inclusive, while current flows when the absolute value of the voltage is t V or higher, allowing a charge to be flown into the floating gate (where the threshold voltage of the diodes is t V).

P-0316[0316] Thus, as in the third and eighth embodiments, multilevel data can be stored, taking a range in which the absolute value of the distributed voltage is high as a coarse control, and a range in which the absolute value of the distributed voltage is small as a fine control.

P-0317[0317] In the semiconductor device of this embodiment, PN diodes are used as the diodes <b>152</b> and <b>154</b>. Alternatively, any other diode such as a Schottky diode may be used instead.

P-0318[0318] Embodiment 10

P-0319[0319] In a semiconductor device according to a tenth embodiment of the present invention the resistor <b>106</b> of the seventh embodiment is replaced by an MIS transistor which is turned ON or OFF by a control voltage Vr.

P-0320[0320]FIG. 45 is a circuit diagram showing the semiconductor device of this embodiment.

P-0321[0321] As shown in FIG. 45, the semiconductor device of this embodiment includes: a control-voltage supply unit <b>110</b>; an MOS transistor; a ferroelectric capacitor <b>104</b><i>a </i>connected to a gate electrode <b>109</b> of the MOS transistor; an MIS transistor <b>156</b> interposed between the control-voltage supply unit <b>110</b> and the gate electrode <b>109</b>. The MIS transistor <b>156</b> is controlled by a control voltage Vr.

P-0322[0322] In the semiconductor device of this embodiment, the MIS transistor <b>156</b> is appropriately turned ON or OFF by an external control circuit or the like, so that a coarse control or a fine control of the potential at the floating gate can be used properly as described in the third through fifth embodiments. For example, when the absolute value of the voltage applied to the MOS transistor is equal to or higher than a given value, the MIS transistor <b>156</b> is turned ON. When the absolute value of the voltage applied to the MOS transistor is lower than the given value, the MIS transistor <b>156</b> is turned OFF.

P-0323[0323] In the semiconductor device of this embodiment, a coarse control and a fine control can be switched by changing the control voltage Vr without depending on the structure of the MIS transistor. Thus, the device can be operated in an arbitrary voltage range.

P-0324[0324] In the semiconductor device of this embodiment, a bipolar transistor may be used instead of the MIS transistor <b>156</b>.

P-0325[0325] Embodiment 11

P-0326[0326] In a semiconductor device according to an eleventh embodiment of the present invention, the resistor <b>106</b> of the seventh embodiment is replaced by a variable resistance element <b>158</b> whose crystallinity is controlled by a resistance control signal Vw.

P-0327[0327]FIG. 46 is a circuit diagram showing the semiconductor device of this embodiment.

P-0328[0328] As shown in FIG. 46, the semiconductor device of this embodiment includes: a control-voltage supply unit <b>110</b>; an MOS transistor; a ferroelectric capacitor <b>104</b><i>a </i>interposed between the control-voltage supply unit <b>110</b> and a gate electrode <b>109</b> of the MOS transistor; and the variable resistance element <b>158</b> interposed between the control-voltage supply unit <b>110</b> and the gate electrode <b>109</b> of the MOS transistor and arranged in parallel with the ferroelectric <b>104</b><i>a</i>. The variable resistance element <b>158</b> is made of an alloy containing three elements of germanium (Ge), tellurium (Te) and antimony (Sb), for example, as main components. The crystallinity of the variable resistance element <b>158</b> is controlled by a resistance control signal Vw.

P-0329[0329] The variable resistance element <b>158</b> is in an amorphous state when the resistance control signal Vw has a high voltage pulse of a given value or higher, so that the resistance value is high. When the Vw pulse is then reduced, the resistance value decreases gradually to be adjusted to an arbitrary value. Thus, in accumulating a charge in the floating gate, a voltage is supplied from the control-voltage supply unit <b>110</b> with the Vw pulse set at a low voltage. In a fine control of the potential at the floating gate or in holding data, the Vw pulse is set at a high voltage, and a voltage in a fine control voltage range shown in FIG. 35 is applied to the ferroelectric capacitor <b>104</b><i>a</i>. Then, a leakage current from the ferroelectric as well as a leakage current from the variable resistance element can be reduced. By thus using the variable resistance element, a semiconductor device in which multilevel information can be stored excellently is implemented.

P-0330[0330] The variable resistance element <b>158</b> of this embodiment is preferably made of a chalcogenide material other than Ge, Te and Sb.

P-0331[0331] Embodiment 12

P-0332[0332] As a twelfth embodiment of the present invention, a neurocomputer in which the semiconductor device of the seventh embodiment is used as a neuron element according to will be described.

P-0333[0333]FIG. 48 is a diagram showing a model representing a simplified structure of a fundamental unit of the brain of an animal. As shown in FIG. 48, the brain of an animal includes: a previous-stage neuron <b>141</b><i>a </i>and subsequent-stage neurons <b>141</b><i>b </i>and <b>142</b><i>c </i>that are nerve cells having a computation function, nerve fibers <b>142</b><i>a</i>, <b>142</b><i>b </i>and <b>142</b><i>c </i>transmitting computation results from neurons; and synaptic connections <b>143</b><i>a</i>, <b>143</b><i>b </i>and <b>143</b><i>c </i>which add weights to signals transmitted through the nerve fibers and which input the signals to the neurons.

P-0334[0334] Specifically, a signal transmitted through a large number of nerve fibers including the nerve fiber <b>142</b><i>a </i>receives weights such as weights Wa, Wb and Wc at a large number of synaptic connections including the synaptic connection <b>143</b><i>a </i>and then is input to the neuron <b>141</b><i>a</i>. At the neuron <b>141</b><i>a</i>, a linear sum of the strengths of input signals is taken. When the sum exceeds a threshold value, the neuron <b>141</b><i>a </i>is activated to output a signal to the nerve fiber <b>142</b><i>b</i>. The action of outputting a signal upon the activation of a neuron is called “firing” of the neuron.

P-0335[0335] The output signal is divided into two, for example. Each of the divided signals receives a weight at a synaptic connection and then input to the subsequent-stage neuron <b>141</b><i>b </i>or <b>141</b><i>c</i>. At the subsequent-stage neuron <b>141</b><i>b </i>or <b>141</b><i>c</i>, a linear sum of input signals is also taken. When the sum exceeds a threshold value, the subsequent-stage neuron <b>141</b><i>b </i>or <b>141</b><i>c </i>is activated and outputs a signal. This operation is repeated at a plurality of stages, thereby outputting a computation result.

P-0336[0336] Loads added to the synaptic connections are gradually modified through leaning, so that an optimum computation result is finally obtained.

P-0337[0337] The neurocomputer is designed to use semiconductor devices for executing such a function of the brain.

P-0338[0338]FIG. 47 is a diagram schematically showing a fundamental structure of the neurocomputer of this embodiment. In FIG. 47, components already mentioned for the semiconductor device of the seventh embodiment are identified by the same reference numerals shown in FIG. 32.

P-0339[0339] As described above, the semiconductor device of the seventh embodiment for use in the neurocomputer of this embodiment includes: a control-voltage supply <b>110</b>; an MOS transistor Tr<b>11</b> including a gate electrode <b>109</b>, drain and source regions <b>103</b><i>a </i>and <b>103</b><i>b </i>and a substrate electrode <b>108</b>; a ferroelectric capacitor <b>104</b><i>a</i>; and the resistor <b>106</b>. The ferroelectric capacitor <b>104</b><i>a </i>and the resistor <b>106</b> are disposed in parallel and interposed between the gate electrode <b>109</b> of the MOS transistor Tr<b>11</b> and the control-voltage supply unit <b>110</b>.

P-0340[0340] As shown in FIG. 47, the neurocomputer of this embodiment includes: the semiconductor device of the seventh embodiment; an electric resistance <b>133</b> interposed between the earth and a source electrode of the MOS transistor Tr<b>11</b>; a node N<b>1</b> disposed between the source electrode of the MOS transistor Tr<b>11</b> and the electric resistance <b>133</b>; a transistor Tr<b>12</b> including a floating gate, a large number of input gates arranged on the floating gate and source and drain electrodes; and an electric resistance <b>132</b> interposed between the source electrode of the transistor Tr<b>12</b> and a voltage supply line Vdd. The source electrode of the transistor Tr<b>12</b> is grounded to the earth. The node N<b>1</b> is connected to one of the input gates.

P-0341[0341] The semiconductor device of the seventh embodiment, the node N<b>1</b> and the electric resistance <b>133</b> correspond to synapse units (connections between nerve fibers and synapses) of the brain of an animal that transmit signals and add weights. A large number of synapse units are connected to a neuron unit (a neuron MOS) constituted by the transistor Tr<b>12</b> and the electric resistance <b>132</b>. The neurocomputer of this embodiment mimics the behavior of the brain and has a structure formed by stacking almost four layers, each of which is made of a synapse unit and a neuron unit connected to each other.

P-0342[0342] Hereinafter, a signal-flow path will be described. First, an output signal Ss<b>1</b> from a previous-stage neuron unit is input to a drain electrode of the MOS transistor Tr<b>11</b>, and a load signal S₁is input to the control-voltage supply unit <b>110</b>. Then, the value of a drain current flowing from the MOS transistor Tr<b>11</b> varies according to the load signal S₁.

P-0343[0343] Then, a current signal output from the MOS transistor Tr<b>11</b> is converted into a voltage signal by the electric resistance <b>133</b>, and is input to one of the input gates of the transistor Tr<b>12</b>. Signals from a large number of other synapse units are also input to the input gates of the transistor Tr<b>12</b>. When the sum of the voltages of these input signals exceeds the threshold value of the transistor Tr<b>12</b>, the neuron unit “fires” to output a signal therefrom. Subsequently, the output signal is transmitted to a subsequent-stage synapse unit.

P-0344[0344] On the other hand, if the sum of the voltages of the input signals from the synapse units is smaller than the threshold value of the transistor Tr<b>12</b>, no signal is output.

P-0345[0345] Since the semiconductor device of the seventh embodiment in which multilevel information can be stored at a synapse unit with a simple structure is used for a synapse unit in the neurocomputer of this embodiment, various weights can be added to signals within a small area. As a result, the neurocomputer in which synapse units and neuron units are integrated and which has a leaning function can be downsized.

P-0346[0346] In the semiconductor device of the seventh embodiment, as described above, the applied voltage-drain current characteristic is changed at a voltage of about 6V, and then a low voltage of about +2 V is applied, thus varying the drain current in the MOS transistor Tr<b>11</b> finely,. Therefore, in the neurocomputer of this embodiment, even if the load signal S₁is at a relatively low voltage, it is possible to add weights at various levels corresponding to the voltage.

P-0347[0347] The synapse units of the neurocomputer of this embodiment has a function of storing the history of the load signal S₁as well as a function of forgetting the history when not used for a long time.

P-0348[0348] The semiconductor device of the seventh embodiment including the ferroelectric capacitor is used for the synapse unit in the neurocomputer of this embodiment. Alternatively, the semiconductor device of the fifth embodiment including the dielectric capacitor or the semiconductor devices of the eighth through eleventh embodiments may be used.

P-0349[0349] A semiconductor device according to the present invention is used as a multilevel memory and is applicable to a neurocomputer including a multilevel memory.