Switched capacitor filter circuit and method of fabricating the same

CROSS REFERENCE TO RELATED APPLICATION

[0001] This application is based on and incorporates herein by reference Japanese patent application No. 2002-117603 filed on Apr. 19, 2002.

FIELD OF THE INVENTION

[0002] The present invention relates to a switched capacitor filter circuit and a method of fabricating the circuit. Specifically it relates to the switched capacitor filter circuit that can reduce feedthrough noise and the method of fabricating the circuit.

BACKGROUND OF THE INVENTION

[0003] Various switched capacitor circuits are proposed.

[0004] A switched capacitor integration circuit shown in FIG. 10A is configured with an operational amplifier <b>403</b>, an input capacitor <b>404</b>, switching circuits <b>405</b>, <b>406</b>, and an integration capacitor <b>407</b>. An input voltage Vin is inputted to an inverting input terminal of the operational amplifier <b>403</b> via the input capacitor <b>404</b> and the switching circuit <b>406</b>, and an output terminal of the operational amplifier <b>403</b> is connected to the inverting input terminal via the integration capacitor <b>407</b>.

[0005] The switching circuits <b>405</b>, <b>406</b> simultaneously switch the ground potential and the signal path side with a switching control signal (not shown). The signal path side is the path extended to the inverting input terminal of the operational amplifier <b>403</b> via the input capacitor <b>404</b> from the input terminal to which the input voltage Vin is impressed. First, when the switches <b>405</b>, <b>406</b> are connected to the ground, the input capacitor <b>404</b> is discharged. Next, the switching circuits <b>405</b>, <b>406</b> are connected to the signal path side, the input voltage Vin is impressed to the switching circuit <b>405</b> of the input capacitor <b>404</b>, and the input capacitor <b>404</b> is charged. When the switching circuits <b>405</b>, <b>406</b> are switched to the ground, the input capacitor <b>404</b> is discharged.

[0006] Assuming that capacitance of the input capacitor <b>404</b> is C<b>1</b> and an amount of charge stored in the input capacitor <b>404</b> is Q, the amount is expressed as Q=C<b>1</b>·Vin. Also assuming that a current flowing into the input capacitor <b>404</b> is i′, a switching frequency of a switching control signal (sampling frequency) is fs, and a switching period of the switching control signal is T=1 /fs. This current is expressed as i′=Q·fs=C<b>1</b>·Vin·fs=(C<b>1</b>·Vin)/T. As understood from this expression, due to the switching operations of the switching circuits <b>405</b>, <b>406</b>, the current i′ flows during a period of the switching control signal (not shown). Therefore this circuit may be considered as a resistor for the input signal of sufficiently lower frequency to the frequency fs of the switching control signal.

[0007] Assuming the switching circuit <b>405</b>, capacitor <b>404</b>, and switching circuit <b>406</b> in FIG. 10A are assumed to be equivalent to a resistor <b>401</b> of an analog integration circuit composed of an operational amplifier <b>400</b> and an integration capacitor <b>402</b> shown in FIG. 10B, that is, i=i′, the relationship of R=T/C<b>1</b>=1/(fs·C<b>1</b>) is obtained. Also, assuming that capacitance of the integration capacitor <b>407</b> in FIG. 10B is C<b>2</b>, cut-off frequency f<b>0</b> is expressed as f<b>0</b>=1/(2πR·C<b>2</b>) =(fs·C<b>1</b>)/(2πC<b>2</b>). As described above, the switched capacitor filter circuit is capable of controlling the cut-off frequency f<b>0</b> with a capacitance ratio of the sampling frequency fs to the input capacitor <b>404</b> and integration capacitor <b>407</b>. Therefore, unlike a large capacitor and an RC filter which are required to have a large scale capacitor or higher accuracy of capacitance, the switched capacitor filter circuit is suitable for integration.

[0008] The switched capacitor circuit is used for a first-order filter as shown in FIG. 11. This first-order filter is configured with switching transistors <b>100</b> to <b>107</b>, an input capacitor <b>110</b>, a limit capacitor <b>111</b>, an integration capacitor <b>112</b>, and an operational amplifier <b>113</b>.

[0009] One terminal of the input capacitor <b>110</b> is connected to an input terminal IN via the switching transistor <b>100</b> and also connected to an internal reference voltage terminal REF (indicated as an inverted triangle) via the switching transistor <b>104</b>, while the other terminal is connected to an inverting input terminal of the operational amplifier <b>113</b> via the second switching transistor <b>101</b> and also connected to the internal reference voltage terminal REF via the switching transistor <b>105</b>. One terminal of the limit capacitor <b>111</b> is connected to the inverting input terminal of the operational amplifier <b>113</b> via the switching transistor <b>102</b> and is also connected to the internal reference voltage terminal REF via the switching transistor <b>106</b>. The other terminal is connected to an output terminal OUT via the switching transistor <b>103</b> and also connected to the internal reference voltage terminal REF via the switching transistor <b>107</b>. One terminal of the integration capacitor <b>112</b> is connected to the inverting input terminal of the operational amplifier <b>113</b>. The other terminal is connected to an output terminal. It is assumed here that the voltage of input terminal IN is V<b>1</b>, the voltage of the inverting input terminal of the operational amplifier <b>113</b> is V<b>2</b>, and the output voltage of the operational amplifier <b>113</b> is V<b>3</b>.

[0010] With this configuration, the switching transistors <b>100</b> to <b>107</b> are turned on or off with switching control signals (control signals) φ<b>1</b>, φ<b>2</b> shown in FIG. 12. The switching transistors <b>100</b> to <b>103</b> turn on when the control signal φ<b>1</b> is high level, while the switching transistors <b>104</b> to <b>107</b> turn on when the control signal φ<b>2</b> is high level.

[0011] When the control signal φ<b>1</b> is low level and the control signal φ<b>2</b> is high level, the input capacitor <b>110</b> is grounded via the switching transistors <b>104</b>, <b>105</b>, while the limit capacitor <b>111</b> is grounded via the switching transistors <b>106</b>, <b>107</b> and are then discharged. Under this condition, when both control signals φ<b>1</b>, φ<b>2</b> are in the low level state, the switching transistors <b>100</b> to <b>107</b> are all turned off, and thus no currents flow into the input capacitor <b>110</b> and the limit capacitor <b>111</b>.

[0012] When the control signal φ<b>1</b> becomes high level and the control signal φ<b>2</b> becomes low level, the switching transistors <b>100</b> to <b>103</b> are turned on, so that a charging current flows into the input capacitor <b>110</b> depending on a voltage difference (V<b>1</b>−V<b>2</b>) applied across both terminals, and thereby the input capacitor <b>110</b> is charged up to the voltage depending on the voltage difference (V<b>1</b>−V<b>2</b>). Charging current flows into the integration capacitor <b>112</b> depending on a voltage difference (V<b>2</b>−V<b>3</b>) applied across both terminals and thereby the integration capacitor <b>112</b> is charged up to the voltage depending on the voltage difference (V<b>2</b>−V<b>3</b>).

[0013] When both control signals φ<b>1</b>, φ<b>2</b> become low level, the switching transistors <b>100</b> to <b>103</b> are turned off, so that no currents flow into the input capacitor <b>110</b> and the limit capacitor <b>111</b>.

[0014] As described above, the input capacitor <b>110</b> and the limit capacitor <b>111</b> become the circuit where predetermined current flows during a period of the control signals φ<b>1</b>, φ<b>2</b>. Therefore it may be considered to be equivalent respectively to resistors. The integration capacitor <b>112</b> is charged depending on the voltage difference (V<b>2</b>−V<b>3</b>) applied across both terminals thereof regardless of switching operations in the switching transistors <b>100</b> to <b>107</b>.

[0015] The switched capacitor filter circuit in FIG. 11 can be thought, for an input signal of sufficiently lower frequency to the sampling frequency, to be equivalent to a first-order low pass filter as shown in FIG. 13. In this filter, the input capacitor <b>110</b> and its associated transistors <b>100</b>, <b>101</b>, <b>104</b> and <b>105</b> are represented as a resistor <b>120</b>, while the limit capacitor <b>111</b> and its associated transistors <b>102</b>, <b>103</b>, <b>106</b> and <b>107</b> are represented as a resistor <b>130</b>.

[0016] As a switched capacitor filter circuit of this type, a“switched capacitor filter” is described in JP-A No. 11-205113.

[0017] In this switched capacitor filter circuit, feedthrough noise due to feedthrough capacitance sometimes give adverse effect on its filter characteristics. These feedthrough capacitance and feedthrough noise will be described below.

[0018] As illustrated in FIG. 14, a switching transistor has an overlapping area between the gate and drain or the gate and source. Small capacitances are formed in these overlapping areas, and are charged due to the change of a gate signal. These small capacitances are referred to as feedthrough capacitance. These feedthrough capacitances bring about feedthrough noise at the switching transistor in the switched capacitor filter circuit. Specifically, in the switching transistor in FIG. 15A, when a control signal φ in FIG. 15B is inputted under the condition that the input voltage Vin is low level, a voltage change is generated at an output voltage Vout due to the feedthrough capacitance of the switching transistor depending on the change of the control signal φ. Noise appearing in such voltage change is referred to as the feedthrough noise.

[0019] Influence of this feedthrough noise will be described using an equivalent circuit of the switched capacitor filter in FIG. 16. This circuit is configured with a switching transistor <b>600</b>, an input capacitor <b>601</b>, an integration capacitor <b>602</b>, and an operational amplifier <b>603</b>. When the switching transistor <b>600</b> is switched with the control signal φ to be inputted to the gate of the switching transistor <b>600</b>, feedthrough noise is generated due to the feedthrough capacitance of the switching transistor <b>600</b> at the inverting input terminal of the operational amplifier <b>603</b>, so that this feedthrough noise is outputted as an offset voltage to an output voltage Vout at the output terminal via the integration capacitor <b>602</b>.

[0020] Assuming that the feedthrough capacitance of the switching transistor <b>600</b> is Ce, capacitance of the integration capacitor <b>602</b> is Cf, voltage impressed to the gate of the switching transistor <b>600</b> is V; feedthrough noise Vnoise is expressed as follows.

<i>V</i>noise=(<i>Ce·V</i>)/<i>Cf</i>

[0021] From this expression, it can be understood that feedthrough noise Vnoise is proportional to a ratio Ce/Cf of the feedthrough capacitance Ce to capacitance Cf. The feedthrough noise is as small as to be negligible when capacitance Cf of integration capacitor is sufficiently larger than feedthrough capacitance Ce. However, when capacitance Cf of the integration capacitor is not sufficiently larger than the feedthrough capacitance Ce, the feedthrough noise becomes larger and the offset voltage due to the feedthrough noise increases, causing the filter characteristic to be deteriorated.

[0022] Assuming that unit capacitance to form a switched capacitor filter is C, sampling frequency is f, and capacitance of a capacitor is Cf, the cutoff frequency fc is expressed as follows.

<i>fc</i>=(<i>C·f</i>)/(2<i>π·Cf</i>)

[0023] From the above expressions, feedthrough noise Vnoise is expressed as follows.

<i>V</i>noise=(2<i>π·fc·Ce·V</i>)/(<i>C·f</i>)

[0024] From this expression, it can be understood that feedthrough noise Vnoise depends on the capacitance Cf of capacitor, cutoff frequency fc, and ampling frequency f.

[0025]FIG. 17 illustrates simulation result for cutoff frequency in the amount of feedthrough noise. This figure illustrates both characteristics of second-order filters when the sampling frequency f is 60 kHz and 120 kHz, and characteristics of a first-order filter when the sampling frequency f is 60 kHz. When the second-order filters in the figure are compared with each other for the sampling frequency f of 120 kHz and cutoff frequency fc of 400 Hz, and the sampling frequency f of 60 kHz, and cutoff frequency fc of 400 Hz, it can be understood that the feedthrough noise of the latter becomes two times the feedthrough noise of the former. If the second-order filters are compared with each other for the frequencies of f=120 kHz and fc =400 Hz, and the frequencies of f=60 kHz and fc=200 Hz, it can also be understood that the feedthrough noise is identical for both filters. However, the cutoff frequency fc of the former filter becomes two times the cutoff frequency of the latter filter.

[0026] The feedthrough noise of the first-order filter, whose sampling frequency f is 60 kHz, is different from the characteristics of the second-order filter, whose sampling frequency f is 60 kHz. This is because two switching transistors which generate feedthrough noise are provided. In the first-order filter of FIG. 11, feedthrough noise is generated by the switching operations of two switching transistors <b>101</b>, <b>102</b>, and it is then outputted as an offset voltage to the output terminal OUT via the integration capacitor <b>112</b>.

SUMMARY OF THE INVENTION

[0027] It is an object of the present invention to reduce feedthrough noise in a switched capacitor filter circuit.

[0028] In order to achieve the object, according to one aspect of the present invention, in a switched capacitor filter circuit, a first noise compensation transistor is provided in series to a second transistor located at an input terminal side of an operational amplifier for a first and a second transistors allocated at both sides of an input capacitor. This first noise compensation transistor receives, at its gate, a signal in the inverse polarity of the switching control signals inputted to the first and second switching transistors, and cancels feedthrough noise generated in the second switching transistor. Accordingly, this feedthrough noise can be reduced.

[0029] According to another aspect of the present invention, a switched capacitor filter circuit is configured as a high-order (higher than the second-order) switched capacitor filter circuit. In this case, feedthrough noise generated by the second switching transistor can be cancelled by providing the first noise compensation transistor in series to the second transistor located at the input terminal side of the operational amplifier for the first and second transistors provided in both sides of the input capacitor in the circuit of the final stage.

[0030] According to a further aspect of the invention, a method of fabricating the switched capacitor filter circuit is configured such that, when a ratio of feedthrough capacitance of switching transistor to capacitance of integration capacitor is larger than the predetermined value, wirings to the noise compensation transistor are formed, while when such capacitance ratio is not larger than the predetermined value, such wirings are not formed.

[0031] According to the invention, connection or non-connection of noise compensation transistor may be determined only by changing wiring patterns through application of the wiring forming process.

BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description made with reference to the accompanying drawings. In the drawings:

[0033]FIG. 1 is a circuit diagram of a switched capacitor filter circuit forming a first-order filter according to the first embodiment of the present invention;

[0034]FIGS. 2A and 2B are schematic diagrams showing a combination of a switching transistor and a noise compensation transistor, and a process of fabricating the switched capacitor filter circuit;

[0035]FIG. 3 is a signal diagram of control signals φ<b>1</b>, /φ<b>1</b>, and φ<b>2</b>;

[0036]FIG. 4 is a circuit diagram of the switched capacitor filter circuit forming a second-order filter according to the second embodiment of the present invention;

[0037]FIGS. 5A and 5B are schematic diagrams illustrating another example of switching transistor and noise compensation transistor;

[0038]FIG. 6 is a circuit diagram of a switched capacitor filter circuit forming a third-order filter according to the third embodiment of the present invention;

[0039]FIG. 7 is a circuit diagram of a switched capacitor filter circuit forming a fourth-order filter according to the fourth embodiment of the present invention;

[0040]FIGS. 8A and 8B are signal diagrams illustrating waveforms of feedthrough noise when the noise compensation transistor is provided or not provided in the fourth-order filter;

[0041]FIG. 9 is a graph illustrating frequency characteristic of filter attenuation coefficient;

[0042]FIGS. 10A and 10B are diagrams illustrating circuit examples of a switched capacitor integration circuit and an analog integration circuit;

[0043]FIG. 11 is a circuit diagram illustrating a first-order filter of switched capacitor according to a related art;

[0044]FIG. 12 is a signal diagram of control signals φ<b>1</b>, φ<b>2</b>;

[0045]FIG. 13 is a circuit diagram illustrating an equivalent circuit of the switched capacitor filter circuit;

[0046]FIG. 14 is a schematic diagram illustrating a switching transistor;

[0047]FIGS. 15A and 15B are signal diagrams showing feedthrough noise;

[0048]FIG. 16 is a schematic diagram illustrating an equivalent circuit of the switched capacitor filter circuit according to the related art; and

[0049]FIG. 17 is a graph illustrating characteristics of feedthrough noise amount for cutoff frequency.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0050] (First Embodiment)

[0051] Referring first to FIG. 1, a switched capacitor filter circuit is formed as a first-order filter. It is provided with first and second noise compensation transistors <b>108</b>, <b>109</b> in addition to the switched capacitor filter circuit shown in FIG. 11. Drains and sources of the first and second noise compensation transistors <b>108</b>, <b>109</b> are respectively connected between the switching transistors <b>101</b>, <b>102</b> and the inverting input terminal of the operational amplifier <b>113</b>. When a control signal /φ inverted from the control signal φ inputted to the gates of switching transistors <b>101</b>, <b>102</b> is inputted to the gates, these noise compensation transistors <b>108</b>, <b>109</b> cancel feedthrough noise generated by the switching transistors <b>101</b>, <b>102</b>.

[0052] Cancellation of this feedthrough noise will be described below. FIG. 2A illustrates a circuit where the switching transistor <b>101</b> and the first noise compensation transistor <b>108</b> are connected in series. The switching transistor <b>101</b> generates feedthrough noise between the gate and source thereof when the control signal φ changes. Since the first compensation transistor <b>108</b> performs switching operation when a control signal /φ inverted from the control signal φ is inputted to the gate thereof, this transistor <b>108</b> generates both feedthrough noise and feedthrough noise of inverted polarity generated by the switching transistor <b>101</b>.

[0053] Here, when the first noise compensation transistor <b>108</b> and the switching transistor <b>101</b> have equal characteristics, since the first noise compensation transistor <b>108</b> generates feedthrough noise between the gate and the drain and between the gate and the source, the amount of this feedthrough noise is equal to two times the feedthrough noise of the switching transistor <b>101</b>. In this case, the amount of the feedthrough noise of switching transistors becomes equal with each other by setting the gate length of switching transistors <b>101</b> and <b>108</b> to constant value and then setting the gate width of switching transistor <b>101</b> to two times the gate width of the first noise compensation transistor <b>108</b>. Accordingly, feedthrough noise can be cancelled.

[0054] The second noise compensation transistor <b>109</b> also operates in the same manner as the first switching transistor <b>108</b>. It is capable of canceling feedthrough noise generated by the switching transistor <b>102</b>. Therefore, the circuit in the first embodiment can operate as the switched capacitor filter circuit when the control signals of φ<b>1</b>, /φ<b>1</b>, and φ<b>2</b> in the timings of FIG. 3 are used and is also capable of reducing feedthrough noise appearing at the output terminal OUT.

[0055] The switched capacitor filter circuit of this embodiment is formed as a semiconductor integrated circuit as shown in FIG. 2B. In a wafer process in the fabrication process of this semiconductor integrated circuit, switching transistor group, capacitor group, and a plurality of operational amplifiers are formed on a semiconductor substrate at step S<b>1</b>; and various elements are connected by the aluminum wiring process to form the aluminum wirings prepared in the latter half processes of the wafer process in an optional manner at step S<b>2</b>. The capacitor group is formed of a plurality of capacitors having the constant unit capacitance. The capacitance can be varied by the number of capacitors connected. Therefore, various switched capacitor filter circuits of various cutoff frequencies and various number of orders can be formed by varying capacitance and filter configuration through modifications of wiring patterns in the aluminum wiring process.

[0056] In addition, in this embodiment, whether wiring should be formed or not to connect in series the first and second compensation transistors <b>108</b>, <b>109</b> to the switching transistors <b>101</b>, <b>102</b> between the switching transistors <b>101</b>, <b>102</b> and the inverting input terminal of the operational amplifier <b>113</b> can also be set with the wiring pattern in the aluminum wiring process.

[0057] Namely, in the case of forming a filter where a ratio of the feedthrough capacitance of the switching transistors <b>101</b>, <b>102</b> to the integration capacitance thereof is larger than the predetermined value (for example, Ce/Cf&lt;0.00002), the wiring pattern is introduced to form the wiring between the first and second noise compensation transistors <b>108</b>, <b>109</b> and switching transistors <b>101</b>, <b>102</b>. Moreover, in the case of forming a filter where the ratio of feedthrough capacitance of the switching transistors <b>101</b>, <b>102</b> to integration capacitance thereof is smaller than the predetermined value (for example, Ce/Cf≧0.00002), the wiring pattern is introduced not to form the wiring between the first and second noise compensation transistors <b>108</b>, <b>109</b> and switching transistors <b>101</b>, <b>102</b>.

[0058] This method does not require a new wiring process and can set connection and non-connection of the first and second noise compensation transistors <b>108</b>, <b>109</b> only by varying the wiring pattern in the aluminum wiring process. Accordingly, feedthrough noise can be reduced depending on various cutoff frequencies and the number of orders of filter.

[0059] Selection for connection and non-connection of the noise compensation transistor with such aluminum wiring process is also possible even in the embodiments described below.

[0060] (Second Embodiment)

[0061]FIG. 4 illustrates a switched capacitor filter circuit of the second embodiment of the present invention. This switched capacitor filter circuit is formed as a second-order filter and is configured with switching transistors <b>200</b> to <b>209</b>, a noise compensation transistor <b>210</b>, input capacitors <b>211</b>, <b>212</b>, integration capacitors <b>213</b> to <b>216</b> and operational amplifiers <b>217</b>, <b>218</b>.

[0062] One terminal of the input capacitor <b>211</b> is connected to the input terminal IN via the switching transistor <b>200</b> and is also connected to the internal reference voltage terminal REF via the switching transistor <b>205</b>, while the other terminal is connected to the inverting input terminal of the operational amplifier <b>217</b> via the switching transistor <b>201</b> and is also connected to the internal reference voltage terminal REF via the switching transistor <b>206</b>. Moreover,one terminal of the integration capacitor <b>216</b> is connected to the inverting input terminal of the operational amplifier <b>217</b> and the other terminal thereof to an output terminal.

[0063] In addition, one terminal of the input capacitor <b>212</b> is connected to an output terminal of the operational amplifier <b>217</b> via the switching transistor <b>207</b> and is also connected to the internal reference voltage terminal REF via the switching transistor <b>202</b>, while the other terminal thereof is connected to the inverting input terminal REF of the operational amplifier <b>218</b> via the switching transistor <b>203</b> and is also connected to the internal reference terminal REF of the switching transistor <b>208</b>.

[0064] Moreover, one terminal of the switching transistor <b>204</b> is connected to the inverting input terminal of the operational amplifier <b>218</b> via the integration capacitor <b>213</b> and is also connected to the output terminal of the operational amplifier <b>218</b>, while the other terminal is connected to a connecting point of the input capacitor <b>212</b> and switching transistor <b>203</b> via the integration capacitor <b>214</b> and is also connected to a connecting point of the input capacitor <b>211</b> and switching transistor <b>201</b> via the integration capacitor <b>215</b> and moreover to the internal reference voltage terminal via the switching transistor <b>209</b>. Moreover, the noise compensation transistor <b>210</b> connects a source terminal and a drain terminal thereof and is connected to the inverting input terminal of the operational amplifier <b>218</b>.

[0065] In the above configuration, the switching transistors <b>200</b> to <b>209</b> are turned on and off with the control signals φ<b>1</b>, /φ<b>1</b>, and φ<b>2</b> illustrated in FIG. 3. The switching transistors <b>200</b> to <b>204</b> turn on when the control signal φ<b>1</b> is high level, while the noise compensation transistor <b>210</b> turns on when the control signal /φ<b>1</b> is high level and the switching transistors <b>205</b> to <b>209</b> turn on when the control signal φ<b>2</b> is high level.

[0066] In the second-order filter configured as above, an offset voltage due to feedthrough noise is generated when the switching transistor <b>203</b> performs the switching operation with the control signal φ<b>1</b>. The noise compensation transistor <b>210</b> is switched with the control signal /φ<b>1</b> which is inverted from the control signal of the switching transistor <b>203</b> to generate feedthrough noise in the polarity inverted from that generated by the switching transistor <b>203</b>. Thereby, the feedthrough noise can be cancelled.

[0067] In the first-order filter illustrated in FIG. 1, feedthrough noise is generated by the switching operations of the two switching transistors <b>101</b>, <b>102</b> and it is outputted as an offset voltage to the output terminal OUT via the integration capacitor <b>112</b>. Meanwhile, in the second-order filter illustrated in FIG. 4, feedthrough noise is generated by switching operation of the switching transistor <b>203</b> and it is outputted as an offset voltage to the output terminal OUT via the integration capacitor <b>213</b>. Accordingly, the offset voltage due to feedthrough noise of the second-order filter becomes equal to ½ of the offset voltage due to feedthrough noise of the first-order filter.

[0068] In these first and second embodiments, as the switching transistors <b>100</b> to <b>107</b> and <b>200</b> to <b>209</b>, the transistor of the configuration illustrated in FIG. 5A may be used. Namely, as illustrated in FIG. 5A, an N-channel type transistor <b>301</b> and a P-channel type transistor <b>302</b> are connected in parallel. The control signal φ<b>1</b> or φ<b>2</b> is inputted to the gate of N-channel type transistor <b>301</b>, while a signal inverted from the control signal φ<b>1</b> or φ<b>2</b> by an inverter <b>303</b> is inputted to the gate of the P-channel type transistor <b>302</b>.

[0069] In this case, the noise compensation transistors <b>108</b>, <b>109</b>, and <b>210</b> are configured as illustrated in FIG. 5B. The circuit of FIG. 5B connects in parallel an N-channel type transistor <b>304</b> and a P-channel type transistor <b>305</b>. The control signal /φ<b>1</b> or /φ<b>2</b> is inputted to the gate of N-channel type transistor <b>304</b>, while a signal inverted from the control signal /φ<b>1</b> or /φ<b>2</b> by an inverter <b>306</b> is inputted to the gate of P-channel type transistor <b>305</b>. Moreover, the source terminals and drain terminals of the N-channel type transistor <b>304</b> and P-channel type transistor <b>305</b> are connected respectively.

[0070] (Third Embodiment)

[0071] Next, a switched capacitor filter circuit will be described as a third embodiment of high-order (three-order or more) filter. A high-order filter is configured with combination of the first-order filter and the second-order filter of the first and the second embodiments.

[0072]FIG. 6 and FIG. 7 illustrate the switched capacitor filter circuits formed as the third-order filter and fourth-order filter. Circuits <b>100</b> to <b>107</b>, <b>200</b> to <b>209</b>, <b>300</b> to <b>309</b> illustrated as the blocks are switching transistors illustrated in FIG. 1 and FIG. 4 or switching transistors illustrated in the configuration of FIG. 5A and perform the switching operations with a control signal illustrated in the block. Moreover, circuits <b>108</b>, <b>109</b>, and <b>210</b> illustrated in the block are also noise compensation transistors illustrated in FIG. 1 and FIG. 4 or noise compensation transistor in the configuration of FIG. 5B and perform the switching operations with a control signal illustrated in the block.

[0073] The third-order filter illustrated in FIG. 6 is formed of serial connection of the second-order filter <b>20</b> and first-order filter <b>10</b>. In this third-order filter, offset voltage due to feedthrough noise is generated by the switching transistors <b>101</b>, <b>102</b> of the first-order filter in the subsequent stage. Therefore, like the first embodiment, feedthrough noise can be cancelled by connecting in series the noise compensation transistors <b>108</b> and <b>109</b>.

[0074] A fourth-order filter illustrated in FIG. 7 is formed by serial connection of two second-order filters <b>20</b>. In this fourth-order filter, offset voltage due to feedthrough noise is generated by the switching transistor <b>203</b> of the second-order filter <b>20</b> in the subsequent stage. Therefore, like the second-order filter, feedthrough noise can be cancelled by connecting in series the noise compensation transistor <b>210</b> to the switching transistor <b>203</b>.

[0075] Waveforms of feedthrough noise when a noise compensation transistor is provided or not provided in this fourth-order filter are respectively illustrated in FIGS. 8A and 8B. When the noise compensation transistor is provided, as illustrated in FIG. 8B, feedthrough noise is reduced to a large extent in comparison with the waveforms illustrated in FIG. 8A that shows the case in which the noise compensation transistor is not provided.

[0076] As can be understood from the above description, a much higher order filter may be configured by combining the first-order filter and second-order filter and then connecting these filters in series in multiple stages. In this case, offset voltage of feedthrough noise in a high-order filter connected in multiple stages is given adverse effect by capacitance of the final stage. Therefore, it is recommended to provide a noise compensation transistor in the filter of final stage as described above.

[0077]FIG. 9 illustrates frequency characteristics of filter attenuation coefficient of a switched capacitor filter circuit. As illustrated in this figure, the higher the number of orders of filter is, the sharper the frequency characteristics of filter attenuation coefficient becomes like the characteristics of the ideal filter.

[0078] (Other Embodiments)

[0079] In the first embodiment to third embodiment, cancellation of feedthrough noise in a low-pass filter has been described. However, feedthrough noise can also be cancelled with a noise compensation transistor even in the switched capacitor filter forming a high-pass filter, band-pass filter and band-cut filter, in addition to such low-pass filter.