Semiconductor logical operation circuit

CROSS REFERENCE TO RELATED APPLICATION

[0001] This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-116664, filed on Apr. 18, 2002; the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

[0002] The present invention relates generally to a semiconductor logical operation circuit, and more particularly to a circuit suited for reducing a consumption of electric power.

[0003] A semiconductor integrated circuit is, with downsizing and a decrease in weight of devices using the semiconductor integrated circuit, highly required to reduce its electric power consumption. One of effective schemes of reducing the electric power consumption is to decrease the power consumption when the circuit is in a non-operation state.

[0004] For instance, one example of a conventional dynamic logical operation circuit is that a selection signal and a clock signal are ANDed. If a selection signal SEL assumes a high-level, a logical output node is set in a precharge state when a clock input CLK is at a low-level and set in an operation state when the clock input CLK is at a high-level, and, if the selection signal SEL assumes the low-level, the logical output node keeps its level high, i.e., the precharge state irrespective of the input of the logical operation circuit. This scheme reduces the power consumption by stopping a futile operation as on standby, i.e., during a non-operation.

[0005] This type of logical operation circuit often, however, involves the use of an N-channel MOS (NMOS) transistor, and a leak current is easy to flow even in an OFF-state in this type of transistor, and a quantity of this leak current can not be ignored especially when using a transistor of a submicron generation.

[0006] A method of raising a threshold value Vth of the transistor may be given as a method of reducing the leak current. In the case of a circuit taking this method, it follows that the threshold value Vth of the NMOS transistor increases, resulting in a problem of lowering an operation speed.

[0007] Furthermore, the leak current can be reduced also by downsizing the transistor, i.e., decreasing a gate width (W), however, there still exists a problem in which the operation speed is similarly decreased.

[0008] Moreover, a circuit using a CMOS transistor is often used as a circuit provided downstream of the output node, however, the size of the PMOS transistor is increased rather than downsizing in order to increase the operation speed thereof. In this case, however, a problem is that the leak current flows to the PMOS transistor having the large size when in the non-operation and the threshold value Vth can not be raised because of the PMOS transistor effecting the operation speed.

[0009] As explained above, the problem inherent in the conventional logical operation circuit is that it is difficult to reduce a consumption of electric power without decreasing the operation speed and that there is a large consumption of the electric power especially on standby state.

SUMMARY OF THE INVENTION

[0010] According to one embodiment of the present invention, there is provided a semiconductor logical operation circuit comprising: a logical operation part to output a result of a predetermined logical operation with respect to a plurality of input signals to an output node; a precharger to precharge said output node at a constant-potential before an operation of said logical operation part; and a setting part to forcibly set said output node at a reference potential when said logical operation part is in a non-operation state.

[0011] According to another embodiment of the present invention, there is provided a semiconductor logical operation circuit comprising: a first logical operation unit including a first logical operation part to output a result of a first logical operation to a first output node with respect to a plurality of input signals, a first precharger to precharge said first output node at a high electric potential before an operation of said first logical operation part, and a first setting part forcibly pulling said first output node down to a ground potential when said first logical operation part is in a non-operation state; and a second logical operation unit including a second logical operation part to output a result of a second logical operation to a second output node with respect to the plurality of input signals, a second precharger to precharge said second output node at a high electric potential before an operation of said second logical operation part, and a second setting part forcibly pulling said second output node down to the ground potential when said second logical operation part is in the non-operation state.

BRIEF DESCRIPTION OF THE DRAWINGS

[0012]FIG. 1 is a circuit diagram showing a first embodiment of the present invention;

[0013]FIG. 2 is a circuit diagram showing a modified example of the embodiment shown in FIG. 1; and

[0014]FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0015] Embodiments of the present invention will hereinafter be described with reference to the accompanying drawings.

[0016]FIG. 1 is a diagram showing a circuit in a first embodiment of the present invention.

[0017] This circuit is defined as an AND circuit, wherein NMOS transistors Q<b>1</b>, Q<b>2</b>, of which gates receive an input A and an input B respectively, are connected in series, this AND circuit outputting a logical product thereof. The transistor Q<b>1</b> is connected to a power supply via a PMOS transistor Q<b>3</b> for precharge, which is connected in series to the transistor Q<b>1</b>. Further, the transistor Q<b>2</b> is grounded via an NMOS transistor Q<b>4</b> connected in series to the transistor Q<b>2</b>.

[0018] Gates of these transistors Q<b>3</b>, Q<b>4</b> are each supplied with an output of a NAND gate X<b>1</b> to which an invert signal /CLK (the symbol “/” represents an inversion) of a clock signal and a selection signal SEL are inputted. Note that the gate of the transistor Q<b>3</b> is depicted as an inverted input terminal.

[0019] A connection node between the transistors Q<b>1</b> and Q<b>3</b> is a node P defined as a logical output node. An output from this node P is, though outputted via an inverter X<b>2</b>, given to a gate of a PMOS transistor Q<b>5</b> provided between an input side of the inverter X<b>2</b> and the power supply, thereby keeping the output with stability.

[0020] Furthermore, a transistor Q<b>6</b>, of which a gate receives an input of an invert selection signal /SEL, is connected between the node P and the ground.

[0021] Next, an operation of this circuit will be explained.

[0022] The discussion is at first focused on a case where the selection signal SEL assumes a high-level, i.e., a selecting state. In this case, when a clock input CLK is at a low-level, the transistor Q<b>3</b> is in ON state, while the transistor Q<b>4</b> is in OFF state. Therefore, the node P comes to a precharge state. When the clock input CLK is at the high-level, however, the transistor Q<b>3</b> becomes OFF state and the transistor Q<b>4</b> becomes ON state, the node P comes to an operating state. Further, the transistor Q<b>6</b> remains OFF state at all times, and hence an inverted AND (NAND) signal of the input signals A, B is outputted in response to the high-level of the clock input CLK.

[0023] By contrast, when the selection signal SEL assumes the low-level, the transistor Q<b>6</b> for discharge is always in ON state irrespective of how the inputs A, B are, and hence the node P is always pulled down to the ground potential and keeps the low-level as a discharge state.

[0024] In the case of adopting the circuit arrangement described above, when not operated, i.e., when the selection signal SEL is at the low-level, a leak current flows to the PMOS transistor such as the transistor for precharge and a transistor for keeping an output stability. The PMOS transistor does not, however, affect an operation speed. It is therefore possible to reduce the leak current when in operation without affecting the operation speed by downsizing these transistors to their minimums required or by raising a threshold value Vth.

[0025] Thus, according to this circuit, when the logical operation part does not execute the logical operation, the setting part forcibly sets the output node at the reference potential, whereby it is feasible to decrease both the current leak and the consumption of the electric power.

[0026] Moreover, in a CMOS circuit existing at downstream of the node P, the leak current flows to an NMOS transistor when in the non-operation. This NMOS transistor does not, however, affect the operation speed and is therefore downsized, and the leak current can be made smaller by increasing the threshold value Vth than in a case where the architecture of the present application is not adopted. Hence, the consumption of the electric power when in the non-operation can be restrained.

[0027]FIG. 2 shows a variation of the embodiment illustrated in FIG. 1. In this variation, two pieces of transistors Q<b>1</b>, Q<b>2</b> connected in series in FIG. 1 are connected in parallel, whereby a logical addition (NOR) signal is obtained.

[0028] Other configurations and operations are absolutely the same as those shown in FIG. 1, and therefore the repetitive explanations are omitted.

[0029] According to this circuit arrangement, any types of logical operation circuits can be applied to the part for performing the logical operation. For example, the arrangement is not limited to what includes the two inputs as illustrated in the embodiment but may include three or more inputs. Further, a variety of logical operations other than OR and AND can be carried out.

[0030] Moreover, according to the present embodiment, the logical circuit part is basically constructed of the NMOS, wherein the precharge voltage is set to the power supply voltage, and the on-standby electric potential of the output node is set to the ground potential. The present invention is not, however, confined to this mode but may include such a mode that the operation occurs with an absolutely reverse logic. Namely, the logical circuit part is basically constructed of the PMOS, wherein the precharge voltage can be set to the ground potential, and the on-standby electric potential of the output node can be set to the power supply potential.

[0031]FIG. 3 is a circuit diagram showing a semiconductor logical operation circuit according to an another embodiment of the present invention.

[0032] The circuit in this embodiment is a so-called dual rail circuit capable of fetching an output from a different output terminal depending on a content of the input signal.

[0033] To begin with, the arrangement of this circuit will be described. A first output OUT is obtained based on such a configuration that a transistor Q<b>11</b> of which a gate receives an input A, a transistor Q<b>12</b> of which a gate receives an input B and a transistor Q<b>13</b> of which a gate receives a clock signal, are connected in series between a node S and the ground. On the other hand, a second output /OUT is obtained based on such a configuration that a transistor Q<b>21</b> of which a gate receives an input /A, a transistor Q<b>22</b> of which a gate receives an input /B and a transistor Q<b>23</b> of which a gate receives the clock signal, are connected in series between a node T and the ground.

[0034] Further, the clock signals are inputted respectively to PMOS transistors Q<b>14</b>, Q<b>24</b> each controlled by the clock signals, and the nodes S and T are precharged through a conduction of these transistors. Moreover, NMOS transistors Q<b>15</b>, Q<b>25</b> of which gates receives inputs of invert selection signals, are connected to those nodes. These transistors have functions of pulling the nodes S, T down to the ground potential when in the non-operation.

[0035] Further, a PMOS transistor Q<b>16</b> of which a gate receives an input of an invert selection signal and a transistor Q<b>17</b> to which the electric potential of the node T is inputted, are connected in series between the node S and the power supply. A PMOS transistor Q<b>26</b> of which a gate receives an input of the invert selection signal and a transistor Q<b>27</b> to which the electric potential of the node T is inputted, are connected in series between the node T and the power supply. This part schemes to charge, if an output occurs at any one of the two outputs nodes when in selection, the other node.

[0036] Note that FIG. 3 does not show the output part drawn as what is constructed of the inverter X<b>2</b> and the transistor Q<b>5</b> in FIGS. 1 and 2, however, an output part constructed the same or having a different construction can be provided.

[0037] According to this embodiment, the two logical operation outputs can be obtained in a way that reduces both the leak current and the consumption of the electric power as in the embodiment illustrated in FIGS. 1 and 2.

[0038] In this embodiment also, a variety of logical operation circuits to be used and multiple conductivity types of transistors can be used as in the first embodiment.