Pipelined memory controller and method of controlling access to memory devices in a memory system

[0001] This application is a continuation of U.S. patent application Ser. No. 09/401,977, filed Sep. 23, 1999, now U.S. Pat. No. 6,571,325, which is hereby incorporated by reference.

[0002] This invention pertains to the field of memory controllers, and more particularly, to a memory controller having a pipelined architecture for controlling access to memory devices in a memory system using an open-page policy, wherein memory pages within a memory device are not closed after each memory access.

BACKGROUND OF THE INVENTION

[0003] Typically, a semiconductor memory system comprises one or more memory devices connected by means of a bus to a memory controller which manages data flow to and from the memory devices. The memory devices may be dynamic random access memory (DRAM) devices, static random access memory (SRAM), etc.

[0004]FIG. 1 illustrates the organization of an exemplary memory device <b>100</b>. The memory device <b>100</b> comprises a plurality of memory banks <b>110</b>. Each memory bank <b>110</b> in turn comprises a plurality of memory pages <b>120</b> and each memory page <b>120</b> comprises a plurality of memory cells <b>130</b>. The memory pages <b>120</b> within each memory bank <b>110</b> share a common pair of sense amplifier arrays <b>140</b> which are used to sense data stored within the memory cells <b>130</b> in the memory bank <b>110</b>. The total number of memory cells <b>130</b> within a memory page <b>120</b> is referred to as the “page size.”

[0005] The memory cells <b>130</b> within each memory page <b>120</b> are connected to each other by a word line which has a unique row address within a memory bank <b>110</b>. Each memory cell <b>130</b> in a memory page <b>120</b> is connected to a separate bit line, each of which has a unique column address within the memory bank <b>110</b>. Also, each memory cell <b>130</b> in a memory page <b>120</b> shares its bit line with corresponding memory cells <b>130</b> in all of the other memory pages <b>120</b> in the memory bank <b>110</b>. Thus the memory cells <b>130</b> within a memory bank <b>110</b> are arranged in a matrix structure of rows and columns. Each memory cell <b>130</b> within a memory bank <b>110</b> is uniquely addressable by its word line position, or row address, and its bit line position, or column address. Accordingly, each memory cell <b>130</b> within a memory device <b>100</b> has a unique (memory bank+row+column) address.

[0006] Each memory cell <b>130</b> stores one bit of data. To access data stored in one or more “target” memory cells <b>130</b> within the memory device <b>100</b>, the target memory page <b>120</b> wherein the target memory cells <b>130</b> are located is first “opened” by activating the corresponding word line for the target memory page <b>120</b>. When the word line is activated, the data stored within all of the memory cells <b>130</b> connected to the activated word line are transferred via the bit lines to the sense amplifier array <b>140</b>. From the sense amplifier array <b>140</b>, the data from one or more target memory cells may be read from memory device <b>100</b> and communicated via the memory bus. After the memory access request is completed, each sense amplifier within the open target memory page <b>120</b> is then “precharged” to prepare the sense amplifier for a subsequent operation. This operation is said to “close” the target memory page <b>120</b>.

[0007] As processor speeds increase, there exists a need for memory systems having faster and faster memory access speeds and data throughputs. Therefore high performance memory systems with new architectures are being implemented. One such architecture is the Direct Rambus™ memory architecture. A memory system according to the Direct Rambus™ memory architecture uses a narrow memory bus comprising a few signal channels (e.g., 30) connected device-to-device and operating at a very high clock rate to communicate memory access requests and data between a memory controller and one or more memory devices.

[0008]FIG. 2 shows such a memory system <b>200</b> wherein a plurality of memory devices <b>210</b> are connected to a memory controller <b>230</b> via a narrow, high-speed memory bus <b>220</b>. The memory bus <b>220</b> comprises a small number of very high speed signal channels which carry address, data and memory access control information between the memory controller <b>230</b> and the memory devices <b>210</b>. The memory system <b>200</b> uses a packetized signaling technology for the signal channels in the memory bus <b>220</b>. The memory system <b>200</b> provides several advantages over traditional memory architectures, including a substantially reduced number of pins on the memory controller <b>230</b> and memory devices <b>210</b>, and a higher sustained bandwidth for the memory bus <b>220</b>.

[0009] A processor connected to the memory system <b>200</b> may access data stored in a target memory device <b>210</b> by communicating a memory access request to the memory controller <b>230</b>. Within the memory system <b>200</b>, memory access is effectuated by means of control packets communicated from the memory controller <b>230</b> to the target memory device <b>210</b>, via one or more control signal channels in the emory bus <b>220</b>. Data is communicated from the target memory device <b>210</b> by means of separate data packets communicated from the target memory device <b>210</b> via a separate data signal channel in the memory bus <b>220</b>.

[0010] Within the memory system <b>200</b>, control packets communicate control commands, including memory access commands (e.g., Activate, Precharge, Read, and Write commands) and memory maintenance commands (e.g. Refresh, and Power Down commands), from the memory controller <b>230</b> to a memory device <b>210</b>. The control packets have predefined fields for control command type, memory address, and the like and are divided into row control packets and column control packets. Row control packets are communicated via a row control signal channel in the memory bus <b>220</b>. Among other things, row control packets are used: to issue Activate commands to activate a word line and thereby to open a memory page within a memory device <b>210</b>; to issue Precharge commands to precharge memory cells in an open memory page, and thereby close the open memory page, within a memory device <b>210</b>; and to issue Refresh commands to refresh the data contents stored in memory cells within a memory device <b>210</b>. Column control packets are communicated via a column control signal channel in the memory bus <b>220</b>. Among other things, column control packets are used to issue Read commands and Write commands to one or more memory cells within the memory device <b>210</b>.

[0011] The operations of opening and closing a memory page to access data stored within a memory device <b>210</b> require time for the associated control commands to be communicated via the memory bus <b>220</b>, and require some time to be performed by the memory device <b>210</b>. While a memory page is being opened or closed, the memory device <b>210</b> cannot provide data from memory cells in that memory page, or any other memory page, within its memory bank. Accordingly, the opening and closing operations consume bandwidth and can reduce the data throughput of the memory system <b>200</b>.

[0012] In general, a memory system can implement either a “close-age” policy, where after each memory access request to memory cells in a memory page in a memory device, the corresponding random memory page is closed, or an “open-page” policy, where the memory page is left open after a memory access request, until some other event necessitates closing it (e.g., a memory access request to another memory page within the memory bank).

[0013] “Locality” refers to the degree to which consecutive memory access requests are addressed to a same memory page within a memory system. The application(s) being performed by a processor issuing memory access requests to a memory system typically determine the degree of locality in memory access requests. In turn, the degree of locality in memory access requests in the memory system determines whether it is better to implement an open-page policy or a close-page policy.

[0014] If the pattern of memory access requests tends to be (i.e., has a low degree of locality) then it is preferable to use a close-page policy. In that case, every memory access ends with all memory pages and memory banks closed and there is no need to check whether a memory page or memory bank is open or closed before executing the next memory access request.

[0015] However, for certain other applications, where there is a high degree of locality in memory access patterns, it is preferable to use a memory system having an open-page policy, which leaves a memory page open after a memory access, and only closes it later when some subsequent event necessitates it. In that case, if a memory access request is addressed to the same common sense amplifier array <b>320</b>. This allows the memory device memory page as the previous memory access request, the precharge operation for the first memory access request, and the activation operation for the second memory access request, can each be avoided. This increases the data throughput in the memory system.

[0016] The memory system described herein operates according to an open-page policy. As such, the memory system imposes a number of constraints which must be adhered to by the memory controller in generating and issuing control commands in response to memory access requests received from a processor. These constraints include logical constraints, timing constraints, and physical constraints which are each discussed in detail below.

Logical Constraints

[0017] As discussed above, a memory device may be partitioned into a number of memory banks. FIG. 3 shows an arrangement of memory banks <b>310</b> in a memory device <b>210</b> which may be used in the memory system.

[0018] In the memory device <b>210</b>, adjacent memory banks <b>310</b> share a <b>210</b> to have more memory banks <b>310</b> within the same or similar die area. Since only one memory page within a memory bank <b>310</b> may be open at any given time, increasing the number of memory banks <b>310</b>, reduces the number of memory page conflicts within the memory device, leading to higher performance, and also reducing the power consumed by the memory device.

[0019] At any time, a memory bank can have one of three logical memory bank states: closed, open, or locked.

[0020] A memory bank is closed when neither of its associated sense amplifier arrays contain the data from either the memory bank itself, or an adjacent memory bank sharing a sense amplifier array. Before data may be accessed from a closed memory bank, it must first be opened, together with a desired memory page, by an Activate command from the memory controller.

[0021] A memory bank is opened when data from memory cells in an open memory page have been transferred to one of its sense amplifier arrays by a previous Activate command. When a memory bank is open, the memory controller can access data from the memory cells in the open memory page. However, if the memory controller wants to access data from another (closed) memory page within the open memory bank, the open memory bank must first be closed. The open memory bank is closed by the memory controller issuing a Precharge command addressed to the open memory page. Then, the memory bank is “reopened” to the desired memory page by a subsequent Activate command from the memory controller.

[0022] When a memory bank is open, its adjacent memory banks are unavailable because their common sense amplifier array is being used by the open memory bank <b>310</b>. FIG. 3 illustrates one example of memory banks <b>310</b> (indicated by a •) which can simultaneously be open within the memory device <b>210</b>. Memory banks which are unavailable due to their common sense amplifier array being used by one or both adjacent open memory bank are said to be in a “locked” state. When it is desired to access data from a locked memory bank, the adjacent open memory bank(s) must first be closed to free up the shared sense amplifier array(s). This action places the locked memory bank in a closed state. Once closed, the memory bank may be opened, together with a desired memory page to access data.

[0023] From the above description, it can be seen that a memory system comprising one or more memory devices with memory banks sharing common sense amplifier arrays impose a number of logical constraints upon a memory controller issuing control commands to the memory device(s). That is, when issuing a control command to one or more target memory cells in a target memory bank, the memory controller must insure that the target memory bank has a memory bank state suitable to receive the control command. For example, a closed or locked target memory bank cannot properly receive and process a read command. The target memory bank must first be opened. Also, a read command may be issued to a target memory bank only after the target memory bank has been activated by an Activate command. As another ready example, the memory controller should issue a Precharge command to a memory bank only if the memory bank has been previously activated. Many such logical constraints exist.

Timing Constraints

[0024] As noted above, each control command requires some amount of time to be communicated via the memory bus, and the memory device requires some amount of time to execute each received control command. FIGS. 4A through 4F illustrate certain timing constraints or requirements for the memory system which must be satisfied by control commands issued by a memory controller.

[0025]FIG. 4A shows a “transaction pipeline” for control packets and data packets communicated via the memory bus to effectuate a memory access request in the memory system. The transaction pipeline comprises: row control packets communicated via a row control signal channel; column control packets communicated via a column control signal channel; and data packets communicated via a data signal channel, all separated in time.

[0026]FIG. 4B shows the transaction pipeline for a read transaction which effectuates a read memory access request received by the memory controller from a processor, for example. In this particular case, the memory controller issues a row control packet comprising an Activate command, followed by one or more column control packets comprising a Read memory access request. Data then appears on the data signal channel in the memory bus some y cycles (e.g., eight cycles) later. Wherever possible, the memory controller uses unoccupied time on the control signal channels to issue further control commands to effectuate other memory access requests and operations, thereby increasing data throughput.

[0027]FIG. 4C shows the transaction pipeline for a write transaction effectuating a Write memory access request. The write transaction is similar to the read transaction shown in FIG. 4B, except that in the case of a write transaction, the data packet(s) appears on the data signal channel in the memory bus z cycles (e.g., six cycles) after the column control packet, rather than y cycles as in the read transaction.

[0028]FIG. 4D shows the transaction pipeline for read transactions. The control packets should be pipelined as tightly as possible to increase data throughput on the data signal channel of the memory bus. Write-write transactions differ from read-read transactions only in the time interval between when the control packets are communicated and when the data packets appear on the data signal channel in the memory bus. The data packets appear on the data signal channel z cycles after the write control packet in a write-write transaction, versus y cycles in the case of a read-read operation.

[0029]FIG. 4E shows the transaction pipeline for back to back read-write transactions. Due to timing differences on the memory bus between read and write transactions, a gap of |z−y| packets must be provided by the memory controller between the column control packets in order for the two transactions to produce full utilization of the data signal channel in the memory bus.

[0030]FIG. 4F shows the transaction pipeline for back to back write-read transactions. In this case, the column control packets can be tightly packed, however this results in a gap appearing between data packets on the data signal channel due to timing differences between the write and read transactions.

[0031] Inspection of FIGS. <b>4</b>A-<b>4</b>F shows that the memory system imposes timing constraints upon control packets issued by a memory controller. Each control command requires a certain amount of time to be communicated to and executed by a target memory device. For proper operation, a control command should only be issued when the target memory device is known to be in a state suitable to receive this control command, and only after the memory device has completed all previous control commands which may affect the proper execution of the present control command.

[0032] For example, when a memory device receives an Activate command for a particular memory page in a memory bank, the memory device requires a minimum time period (e.g., 20 nsec.) to activate the memory bank before the memory device can properly process a subsequent Read control command directed to the same memory bank. Similarly, when a memory device receives a Precharge command to precharge a memory page in a memory bank, it requires a minimum period of time to perform the precharge operation before it can properly receive and process another precharge operation for a different memory page in the same memory device. Therefore, the memory controller must insure that it coordinates the timing of all control commands which it issues to insure that they can be properly processed by the target memory device.

Physical Constraints

[0033] As discussed above, the memory system operates according to a packetized protocol with control packets and data packets. The memory bus thus comprises a column control signal channel for communicating column control packets, a row control signal channel for communicating row control packets, and a data signal channel for communicating data packets. These signal channels each have an associated set of physical pins on the memory controller and memory devices. Other pins on these devices are used for clock signals, initialization signals, and power/ground. Each control command occupies a set of signal channels and associated physical pins for a certain period of time. The memory controller may not issue another control command which would use the same signal channel and physical pins during the same time period.

[0034] The control and data signal channels also have interdependencies wherein when a control command is issued on a control signal channel, physical pins associated with the data signal channel are then occupied for a specified period of time. For example, after a Read command is issued by a memory controller to a target memory device, the target memory device drives the data signal channel, and occupies the associated physical pins, for a specified period of time.

[0035] This is but one example of many physical constraints that are imposed on memory controller operation by the memory bus and related resources.

[0036] Accordingly, it would be advantageous to provide a memory controller for use in a high performance memory system which issues control commands satisfying logical constraints, timing constraints, and physical constraints for the memory system. It would also be advantageous to provide a memory controller well suited to processing applications with a high degree of locality in memory access patterns.

SUMMARY

[0037] The present invention comprises a pipelined memory controller for a high performance memory system.

[0038] In one aspect of the invention, a pipelined memory controller checks and resolves all logical, timing and physical constraints on a memory access command before issuing the command. The pipelined memory controller isolates and resolves logical, timing, and physical constraint checks separately in two pipelined stages.

[0039] In another aspect of the invention, a pipelined memory controller controls memory access to memory devices in a memory system with a parallelized memory bus having a small number of very high speed signal channels which carry address, data and control information between the pipelined memory controller and the memory devices. Preferably, the memory system uses a packetized signaling technology for the signal channels in the memory bus.

[0040] In yet another aspect of the invention, a pipelined memory controller implements an open-page policy which improves memory access efficiency for applications with a high degree of memory access locality.

BRIEF DESCRIPTION OF THE DRAWINGS

[0041]FIG. 1 shows an arrangement of memory cells within a memory device.

[0042]FIG. 2 is a block diagram of a memory system wherein a pipelined memory controller according to one or more aspects of the present invention may operate.

[0043]FIG. 3 shows an arrangement of memory banks in a memory device which may be used in a memory system with a pipelined memory controller according to one or more aspects of the present, invention.

[0044] FIGS. <b>4</b>A-<b>4</b>F shows a transaction pipeline in a memory system wherein a pipelined memory controller according to one or more aspects of the present invention may operate.

[0045]FIG. 5 is a functional block diagram illustrating an architecture for a pipelined memory controller according to one or more aspects of the present invention.

[0046]FIG. 6 illustrates a preferred embodiment of a bank state cache for a pipelined memory controller.

[0047]FIG. 7 shows a high level functional block diagram of a preferred embodiment of a timing coordinator for a pipelined memory controller.

DESCRIPTION OF EMBODIMENTS

[0048] The present invention provides a pipelined memory controller which addresses the logical, timing, and physical constraints discussed above. In one aspect, the present invention is well adapted for incorporation in emerging high speed memory systems. The assignee of the present invention has pioneered the development of next generation memory systems having a relatively narrow, high speed bus(es) and associated memory devices, along with the interface technology required to provide high data throughput. See, U.S. Pat. Nos. 5,319,755; 5,243,703; and 5,254,883, the disclosures of which are incorporated herein by reference.

[0049] In addition to the referenced U.S. patents, information describing the assignee's memory systems and memory devices may be had at Rambus™ Inc., Mountain View, Calif. See, for example, the Direct RDRAM™ 64/72-Mbit Data Sheet, the Direct RAC Data Sheet, the Direct RMC.dl Data Sheet, A Logical View of the Direct Rambus Architecture, Direct Rambus Technology Overview, Direct Rambus Clock Generator Source Sheet, Direct Rambus RIMM™ Module Data Sheet, the Direct Rambus Memory controller Summary, all 1998 documents and all incorporated herein by reference.

[0050] Turning specifically to the present invention, FIG. 5 is a functional block diagram illustrating an architecture for a pipelined memory controller <b>500</b> which generates and issues control commands to memory devices. The pipelined memory controller <b>500</b> may operate as the memory controller <b>230</b> shown in the memory system <b>200</b> of FIG. 2. In this case, the pipelined memory controller <b>500</b> receives memory access requests from one or more processors, and generates control commands which it issues to target memory devices <b>210</b> in the memory system <b>200</b> to satisfy the memory access requests.

[0051] The pipelined memory controller <b>500</b> comprises two pipeline stages <b>505</b> and <b>555</b> for insuring that each control command issued by the pipelined memory controller <b>500</b> satisfies all logical, timing, and physical constraints for the memory system <b>200</b>.

[0052] The first pipeline stage <b>505</b> comprises an upstream interface <b>510</b>, an address extractor <b>520</b>, a bank state cache lookup <b>530</b>, and a hazard detector <b>540</b>. The first pipeline stage <b>505</b> generates and supplies control command information to the second pipeline stage <b>555</b> which comprises a command sequencer <b>560</b>, a timing coordinator <b>570</b>, and a physical constraint checker <b>580</b>. The first pipeline stage <b>505</b> insures that each control command issued by the pipelined memory controller <b>500</b> satisfies all logical constraints for the memory system <b>200</b>. The second pipeline stage <b>555</b> generates the control commands, insuring first that each control command satisfies all timing constraints for the memory system <b>200</b>. The second pipeline stage <b>555</b> then frames the control commands into control packets, and performs checks to insure that the physical constraints for the control signal channels and data signal channel in the memory bus are satisfied before communicating the control packet via the memory bus. Each functional block in the pipelined memory controller <b>500</b> will be discussed more fully below.

Upstream Interface

[0053] The upstream interface <b>510</b> interfaces with and receives memory access requests from one or more processors which access the memory system through the pipelined memory controller <b>500</b>.

[0054] The pipelined memory controller <b>500</b> may be implemented as one component in a larger logic integrated circuit (IC), in which case the pipelined memory controller <b>500</b> will typically communicate with the rest of the IC through some kind of internal bus through the upstream interface <b>510</b>. In that case, the upstream interface <b>510</b> will preferably include logic to implement a regular bus protocol involving start/stop, acknowledge type signals, which may include bus arbitration logic circuitry and chip select logic circuitry. The upstream interface <b>510</b> passes received memory access requests to the address extractor <b>520</b> to be processed by the pipelined memory controller <b>500</b>.

Address Extractor

[0055] A memory access request received by the pipelined memory controller <b>500</b> specifies a full n-bit wide memory address (e.g., n=32) for target memory cells to which the memory access request is addressed. However, within the memory system <b>200</b>, each memory cell is addressed using a partitioned (memory device+memory bank+row+column) address, comprising a memory device address, a memory bank address, a row address and a column address. Accordingly, the address extractor <b>520</b> decodes the n-bit wide memory address into a partitioned (memory device+memory bank+row+column) address which may be used by the memory controller <b>500</b> to address the target memory cell(s). After the n-bit wide memory address is decoded into the (memory device+memory bank+row+column) address, the memory device address, a memory bank address, row address, and column address can all be separately provided to various component within the memory controller <b>500</b> which require them.

Bank State Cache Lookup

[0056] The pipelined memory controller <b>500</b> contains a bank state cache which tracks memory bank states for memory banks <b>310</b> within the memory devices <b>210</b> in the memory system <b>200</b>.

[0057]FIG. 6 illustrates a preferred embodiment of a bank state cache <b>600</b>. The bank state cache <b>600</b> has “N” entries <b>610</b> (e.g., N=32). In one embodiment, N may be equal to the number of memory banks <b>310</b> in the memory system <b>200</b>, such that the bank state cache has an entry <b>610</b> for every memory bank <b>310</b> in the memory system <b>200</b>.

[0058] Alternatively, for larger memory systems, multiple memory banks in the memory system may be mapped to each entry <b>610</b> in the back state cache <b>600</b>. Preferably, each memory device in the memory system has a same number of memory banks, “M” (e.g., M=16), and each memory bank within the memory devices has a different memory bank number i, where i 0(1, M).

[0059] Then, in a preferred embodiment, each entry <b>610</b> i memory device having the memory bank number i, where i 0(1, M). The memory banks from two or more memory devices, having the same memory bank number i, all map to a same entry <b>610</b> i.

[0060] Alternatively, the number of entries <b>610</b> in the bank state cache <b>600</b> may be greater than M, in which case the bank state cache <b>600</b> may have two or more entries <b>610</b> i1, <b>610</b> i2, etc, each corresponding to a same memory bank number i. In that case, the memory banks having the memory bank number i from one set of memory devices map to one entry <b>610</b> i1, and the memory banks having the memory bank number i from another set of memory devices map to another entry <b>610</b> i2.

[0061] An entry <b>610</b> i in the bank state cache <b>600</b> has three fields: a device field <b>612</b> identifying a memory device in the memory system to which the entry <b>610</b> i pertains; a memory bank state field <b>614</b> which comprises a single bit indicating whether the memory bank having the memory bank number i in the memory device is open or closed/locked; and a row address field <b>616</b> identifying a memory page which is open within the memory bank having the memory bank number i (if the memory bank number i within the memory device is open).

[0062] In the embodiment wherein multiple memory banks in the memory system are mapped to a same entry <b>610</b>, all open memory banks in the memory system are identified in the bank state cache <b>600</b>. However, an entry <b>610</b> i identifying an open memory bank is “retired” from the bank state cache <b>600</b> when another memory bank which maps to the same entry <b>610</b> i is activated. At that point, the memory cells in the open memory page in the open memory bank <b>310</b> identified by the entry <b>610</b> i are precharged, and the open memory bank is thereby closed.

[0063] Any memory bank which is not tracked by an entry in the bank state cache must be closed or locked. All memory banks are closed when they are retired from the bank state cache, but the memory bank may become locked due to a neighboring adjacent memory bank becoming open.

[0064] When the pipelined memory controller <b>500</b> receives a memory access request containing an n-bit wide memory address for one or more target memory cells, the address extractor <b>520</b> decodes the n-bit wide memory address and produces the memory device address for a target memory device, memory bank address for a target memory bank, and a row address for the target memory page. The address extractor provides these addresses to the bank state cache lookup <b>530</b>.

[0065] The bank state cache lookup <b>530</b> looks up in the bank state cache <b>600</b> the memory bank state for the target memory bank in the target memory device, to determine whether the target memory bank is in an open or closed/locked state. If the target memory bank is open, then there is an entry <b>610</b> in the bank state cache corresponding to the target memory bank. In that case, the bank state cache reads the row address field <b>616</b> for the entry <b>610</b> corresponding to the target memory bank, identifying an open memory page in the target memory bank, and determines if the open memory page matches the target memory page for the memory access request.

[0066] If the target memory bank is closed/locked, the bank state cache lookup <b>530</b> also looks up in the bank state cache <b>600</b> the memory bank state for the memory banks which are adjacent to the target memory bank, to ascertain whether either of them is open. If either neighboring adjacent memory bank is open, then the target memory bank is locked; otherwise the target memory bank is closed.

[0067] Thus the bank state cache lookup <b>530</b> determines and outputs a memory bank state for a target memory bank to which a memory access request is directed.

Hazard Detector

[0068] When the pipelined memory controller <b>500</b> receives a memory access request for one or more target memory cells in a target memory device, the target memory cell(s) may be located in a target memory page which is open or closed. The target memory page may be located in a target memory bank which is open, closed, or locked. However, the target memory cell(s) cannot be accessed until the target memory bank and target memory page are both opened. A “hazard condition” is said to exist when there is a memory access request received for one or more target memory cells in a target memory bank with a memory bank state such that the target memory cells cannot currently be accessed. Several such hazard conditions exist, where a current memory access request needs to be stalled until a prior memory access request is completed.

[0069] For example, the pipelined memory controller <b>500</b> may receive a Read request for memory cells in a target memory bank which was locked by a previous memory access request. The hazard detector <b>540</b> will receive from the bank state cache lookup <b>530</b> the memory bank state (i.e., “locked”) for the target memory bank. The hazard detector <b>540</b> detects this as a hazard condition for the Read request, and in response thereto issues a Stall command to the command sequencer <b>560</b> to stall generation of control commands for effectuating the Read request until the previous memory access request which locked the target memory bank is completed, and the target memory bank is closed. Preferably, at the same time, the hazard detector stalls any further memory access requests for the same target memory cells which are received from a memory accessing device, such as a processor, connected to the pipelined memory controller <b>500</b>, until all logical constraints for the control commands for the Read request are resolved. Thus, command conflicts ripple up the pipeline to the top. This insures that all control commands satisfy all logical constraints for the memory system before they are issued by the pipelined memory controller <b>500</b>.

[0070] The hazard detector <b>540</b> checks all such logical constraints for the memory system and issues Stall commands when necessary to insure that the pipelined memory controller <b>500</b> does not issue a control command which violates these logical constraints.

Command Sequencer

[0071] Memory access requests received by the memory system from a memory accessing device, such as a processor, arrive at the pipelined memory controller <b>500</b> in the form of Read/Write requests addressed to a group of one or more target memory cells. The command sequencer <b>560</b> receives these memory access requests, as well as any Stall commands from the hazard detector <b>540</b>, and in response thereto generates and sequences control commands which effectuate the memory access requests.

[0072] In a preferred embodiment, the pipelined memory controller <b>500</b> issues control commands generated by the command sequencer <b>560</b> as row control packets, communicated from the pipelined memory controller <b>500</b> via the row control signal channel in the memory bus, and column control packets, communicated via the column control signal channel in the memory bus. Row control packets are used to communicate row control commands, such as Activate and Precharge commands. Column control packets are used to communicate column control commands, such as Read commands and Write commands. For every memory access request, the command sequencer <b>560</b> will generate one or more row control commands followed by a one or more column control commands, depending upon the number of target memory cells addressed in the memory access request.

[0073] In a preferred embodiment, in response to every Read command issued by the memory controller <b>500</b>, a target memory page in a target memory bank in a target memory device <b>210</b> transfers up to 16 contiguous bytes of data onto the data signal channel of the memory bus. Accordingly, if a Read request is received by the memory controller <b>500</b>, to read 64 contiguous bytes of data from a target memory page in a target memory bank in a target memory device, the command sequencer <b>560</b> will generate in response thereto an Activate command, including a (memory device+memory bank+row) address, for activating the target memory page, followed by four Read commands.

[0074] Several logical constraints must be satisfied before the command sequencer can issue a control command for a target memory bank. Each control command can only be issued if the target memory bank to which it is addressed has a memory bank state which is acceptable for properly receiving and processing the control command.

[0075] For example, when the command sequencer <b>560</b> receive a Stall command from the Hazard Detector <b>540</b> in connection with Read request to a target memory bank, the command sequencer <b>560</b> will generate a Precharge command to close any open memory pages in the target memory bank and its neighboring adjacent memory banks left open by a previous memory access request, before generating the Activate command to the target memory bank. After activating the memory cells in the target memory page, the command sequencer <b>560</b> generates four Read commands, each Read command instructing the target memory device to transfer 16 contiguous bytes of data from the target memory page. The command sequencer <b>560</b> sequences all control commands to insure that they satisfy all such logical constraints for the memory system.

[0076] Thus, based on memory access requests received by the pipelined memory controller <b>500</b>, and information from the bank cache lookup <b>530</b> and the hazard detector <b>540</b>, the command sequencer <b>560</b> generates and sequences control commands to effectuate the memory access requests such that they satisfy all logical constraints for the memory system.

Timing Coordinator

[0077] A control command issued by the pipelined memory controller <b>500</b> may impose timing constraints upon subsequent control commands, depending upon the memory device and/or the memory bank to which the control commands are addressed. The timing coordinator <b>570</b> receives sequenced control commands from the command sequencer <b>560</b> and times the communication of each sequenced control command by the pipelined memory controller <b>500</b> via the memory bus to satisfy the timing requirements for the memory system.

[0078] Table 1 shows some exemplary timing requirements for an exemplary memory system into which the present invention may be readily adapted. <tables id="TABLE-US-00001" num="1"><table frame="none" colsep="0" rowsep="0" pgwide="1"><tgroup align="left" colsep="0" rowsep="0" cols="3"><colspec colname="1" colwidth="42PT" align="left" /><colspec colname="2" colwidth="49PT" align="center" /><colspec colname="3" colwidth="175PT" align="left" /><thead><row><entry namest="1" nameend="3" align="center">TABLE 1</entry></row><row><entry /></row><row><entry namest="1" nameend="3" align="center" rowsep="1" /></row><row><entry>Constraint</entry><entry>Typical Value</entry><entry>Comments</entry></row><row><entry namest="1" nameend="3" align="center" rowsep="1" /></row></thead><tbody valign="top"><row><entry>T_rcd</entry><entry>20 ns</entry><entry>Minimum time between an Activate command and a</entry></row><row><entry /><entry /><entry>Read/Write command to the same memory page within a</entry></row><row><entry /><entry /><entry>memory page within a memory device.</entry></row><row><entry>T_rasmin</entry><entry>60 ns</entry><entry>Minimum time between an Activate command and a</entry></row><row><entry /><entry /><entry>Precharge Command to the same memory page within a</entry></row><row><entry /><entry /><entry>memory device.</entry></row><row><entry>T_ss</entry><entry>20 ns</entry><entry>Minimum time between an Activate command to one</entry></row><row><entry /><entry /><entry>memory bank and a subsequent Activate command to</entry></row><row><entry /><entry /><entry>a different memory bank within the same memory device.</entry></row><row><entry>T_pp</entry><entry>20 ns</entry><entry>Minimum time between a Precharge command to one</entry></row><row><entry /><entry /><entry>memory bank and a subsequent Precharge command to a</entry></row><row><entry /><entry /><entry>different memory bank within the same memory device.</entry></row><row><entry>T_rp</entry><entry>20 ns</entry><entry>Minimum time between a Precharge command and an</entry></row><row><entry /><entry /><entry>Activate command to the same memory bank within a</entry></row><row><entry /><entry /><entry>memory device.</entry></row><row><entry>T_cas+ T_cps</entry><entry>20 ns</entry><entry>Minimum time between a Read/Write command and a</entry></row><row><entry /><entry /><entry>Precharge command to the same memory bank within a</entry></row><row><entry /><entry /><entry>memory device.</entry></row><row><entry namest="1" nameend="3" align="center" rowsep="1" /></row></tbody></tgroup></table></tables>

[0079]FIG. 7 shows a high level functional block diagram of a preferred embodiment of the timing coordinator <b>570</b>. The timing coordinator <b>570</b> includes finite state machines <b>710</b> with timers <b>720</b> and combinatorial logic <b>730</b> to simultaneously track timing requirements for a number of control commands which may simultaneously be in process by memory devices in the memory to issue six Activate commands during the time period T_rasmin. In that case, six finite state machines <b>710</b> would be necessary to simultaneously track the timing requirements for each of the six Activate commands.

[0080] An example will now be described to help explain the operation of the timing coordinator <b>570</b>. When the command sequencer <b>560</b> issues an Activate command to a memory page within a memory bank in a memory device, the timing coordinator <b>570</b> assigns a finite state machine <b>710</b> A to track timing requirements pertaining to the Activate command. The Activate command will include a (memory device+memory bank+row) address, “D+B+R. ” The finite state machine <b>710</b> A in turn starts one or more timers <b>720</b> to track timing requirements for any control commands which follow the Activate command. For the exemplary set of timing requirements shown in Table 1, in response to the Activate command, the finite state machine <b>710</b> A starts a T_redtimer <b>720</b>, a T_rasmintimer <b>720</b>, and a T_sstimer <b>720</b>. Each of the timers <b>720</b> runs for a period of time matching its corresponding timing requirement, as shown for example in Table 1. When the period of time has elapsed, the timer <b>720</b> clears or “times-out.” When the command sequencer <b>560</b> issues a subsequent control command, the timing coordinator <b>570</b> checks whether the subsequent control command is addressed to the memory device “D” and the memory bank and the memory bank <b>310</b> “B” and if so, whether the appropriate timer <b>720</b> pertaining to the subsequent control command has cleared.

[0081] For example, if the subsequent control command is a Precharge command addressed to the memory device “D” and memory bank <b>310</b> “B,”, then the timing coordinator <b>570</b> will check its finite state machines <b>710</b> to see if any of them are currently assigned to track timing requirements pertaining to the memory device “D” and memory bank “B.” The timing coordinator <b>570</b> will determine that finite state machine <b>710</b> A was assigned to track timing requirements for the previous Activate command addressed to the memory device “D” and memory bank “B.” Then, the timing coordinator <b>570</b> will determine that the T_rasmintimer <b>720</b> pertains to the Precharge command. If the T_rasmintimer <b>720</b> has not yet timed out, indicating that the timing requirement for the Precharge command has not yet been satisfied, then the timing coordinator <b>570</b> will hold the Precharge command. Once the T_rasmintimer <b>720</b> does time out, indicating that the timing requirement has been satisfied, the timing coordinator will pass the timed and sequenced Precharge command to the physical layer manager <b>580</b>.

[0082] Accordingly, the timing coordinator <b>570</b> times the communication of sequenced control commands via control signal channels in the memory bus and insures that all timing requirements for the memory system are satisfied before a control command is issued by the pipelined memory controller <b>500</b>.

Physical Layer Manager

[0083] Once a control command has been checked to satisfy all logical constraints and timing constraints by the hazard detector <b>540</b>, the command sequencer <b>560</b> and the timing coordinator <b>570</b>, the timed and sequenced control command is ready to be issued in the form of one or more control packets communicated via the memory bus. The physical layer manager <b>580</b> receives timed and sequenced control commands, and frames the timed and sequenced control commands into row control packets and column control packets for communication via the memory bus.

[0084] In a preferred embodiment, the memory bus is comprised of three signal channels—a row control signal channel, a column control signal channel and a data signal channel, each having a dedicated set of physical pins on a circuit device incorporating the pipelined memory controller <b>500</b>, and on each memory device <b>210</b>. The physical layer manager <b>580</b> includes framing logic to frame each timed and sequenced control command into one or more control packets, using the (memory device+memory bank+row+column) address generated by the address extractor <b>520</b>. For example, the physical layer manager <b>580</b> frames a timed and sequenced Activate command into an Activate control packet, a timed and sequenced Precharge command into a Precharge control packet, etc.

[0085] Each control packet occupies a control signal channel in the memory bus for a predetermined number of clock cycles (e.g., four clock cycles). Moreover, there are interdependencies between the control signal channels and the data signal channel in the memory bus which introduce physical constraints on the availability of signal channels, and associated physical pins, in the memory bus. These physical constraints must be resolved by the pipelined memory controller <b>500</b>. For example, after the pipelined memory controller <b>500</b> issues a read control packet on the column control signal channel, the target memory device will drive the data signal channel for “X” clock cycles. The physical layer manager <b>580</b> checks all physical constraints for the communication of each control packet, and insures the availability of the appropriate signal channel and associated physical pins, before communicating the control packet to a target memory device via the memory bus.

[0086] The physical layer manager <b>580</b> also includes arbitration logic which arbitrates between control packets which are pending and ready for communication via the control signal channels.

[0087] In a preferred embodiment, the physical layer manager <b>580</b> prioritizes the communication of control packets via the control signal channels so as to increase the data throughput of the memory bus. For example, at some point in time there may be a of pending Activate control packet and a pending Precharge control packet, each properly timed and sequenced, each addressed to a different memory device, and each waiting for the availability a control signal channel for communication via the memory bus. In that case, the physical layer manager <b>580</b> may prioritize the Activate control packet and communicate it before communicating the Precharge control packet on the row control signal channel so as to increase the data throughput on the memory bus.

[0088] Thus, a pipelined memory controller according to the present invention uses a minimum number of pipelines stages to satisfy all logical, timing, and physical constraints for control commands in the memory system. Each of these constraints is eliminated in a successive pipelined stage of logic. A pipelined memory controller thus produced can implement an open-page policy in a memory system having memory devices with a large number of memory banks.

[0089] While preferred embodiments are disclosed herein, many variations are possible which remain within the concept and scope of the invention. For example, the number and type of control commands may vary from memory system to memory system. Also, the number and type of timing constraints which the pipelined memory controller must satisfy may vary from memory system to memory system. Such variations would become clear to one of ordinary skill in the art after inspection of the specification, drawings and claims herein. The invention therefore is not to be restricted except within the concept and scope of the appended claims.