Memory system for supporting multiple parallel accesses at very high frequencies

FIELD OF THE INVENTION

[0001] This invention relates to computer memory systems and, more particularly, to pipelined memory systems that support multiple accesses at very high frequencies. The memory systems are particularly useful in digital signal processing systems, but are not limited to such applications.

BACKGROUND OF THE INVENTION

[0002] A digital signal computer, or digital signal processor (DSP), is a special purpose computer that is designed to optimize performance for digital signal processing applications, such as, for example, fast Fourier transforms, digital filters, image processing, signal processing in wireless systems and speech recognition. Digital signal processor applications are typically characterized by real-time operation, high interrupt rates and intensive numeric computations. In addition, digital signal processor applications tend to be intensive in memory access operations and require the input and output of large quantities of data. Digital signal processor architectures are typically optimized for performing such computations efficiently.

[0003] Microcontrollers, by contrast, involve the handling of data but typically do not require extensive computation. Architectures that are optimized for DSP computations typically do not operate efficiently as microcontrollers, and microcontrollers typically do not perform well as digital signal processors. Nonetheless, applications frequently require both digital signal processor and microcontroller functionality.

[0004] The characteristics of microcontroller data access patterns include temporal and spatial locality, which is ideally found in a cache. Specifically, the latency of memory operations is important, and common instruction sequences, such as load-compare-branch, need to be executed with a short latency. Otherwise, the branch misprediction penalty is large. Pointer chasing, where a load is performed to a register and the load is subsequently used to form an address for another load (commonly referred to as load-to-load interlock or pointer chasing), also needs to be executed with a short latency. This is because the second load, whose address is dependent on the first load, stalls for a longer time. In an in-order processor, a stall stops the entire machine without any useful work being done. Therefore, a microcontroller demands a short pipeline memory architecture.

[0005] Digital signal processors perform repetitive computations on large data sets. These large data sets may be accessed only once in the form of a load-compute-store sequence where the load and store are executed many times and are to different addresses. Temporal locality doesn't apply to these data sets, since data is not being re-accessed. Spatial locality applies in a limited sense in that data access patterns tend to be non-sequential stride based. These features make caches non-optimal for DSP applications, since caches have the undesirable overhead of cache fills and copybacks. In a cache fill, the memory operation which produced a cache miss stalls the entire processor, waits for the data to come from memory and then the fill data is written to memory. In a typical example, four cycles may be required to write back 32 bytes of data, during which time that particular bank of memory is not available to the processor. A similar situation applies to copybacks. If data is rarely reused, i.e., poor temporal locality, then there is no advantage in bringing a line of memory into the cache in view of sparse spatial locality.

[0006] In one prior art approach, the cache is provided with SRAM capability. If the cache is programmed as SRAM, then there is no refill and copyback overhead. However, the SRAM size is very small compared to the large data set typically used in DSP computations. The burden of managing overlays, the swapping in and out of data from a larger SRAM using DMA, must be done by software. Getting to this work correctly in performance sensitive applications may be very difficult.

[0007] Digital signal processor designs may be optimized with respect to different operating parameters, such as computation speed, power consumption and ease of programming, depending on intended applications. Furthermore, digital signal processors may be designed for 16-bit words, 32-bit words, or other word sizes. A 32-bit architecture that uses a long instruction word and wide data buses and which achieves high operating speed is disclosed in U.S. Pat. No 5,954,811, issued Sep. 21, 1999 to Garde. The disclosed digital signal processor includes three memory banks, each having a capacity of 2 megabits, connected by respective data buses to dual computation blocks. Notwithstanding very high performance, the disclosed processor does not provide an optimum solution for all applications.

[0008] Memory latency is frequently a limiting factor in achieving enhanced processor performance. Because digital signal processor computations tend to be intensive in memory access operations, memory systems are critical components of high performance digital signal processors. Accordingly, there is a need for further innovations in memory systems for digital signal processors.

SUMMARY OF THE INVENTION

[0009] According to a first aspect of the invention, a memory system is provided for operation with a processor. The memory system comprises a high speed pipelined memory, a store buffer for holding store access requests from the processor, a load buffer for holding load access requests from the processor, prioritization logic for selecting access requests in accordance with a priority scheme, and bank conflict logic for detecting and handling conflicts between access requests.

[0010] The pipelined memory may comprise at least two independently accessible megabanks, each comprising at least two independently-accessible superbanks. In one embodiment, the pipelined memory comprises two independently-accessible megabanks, each comprising five independently-accessible superbanks. The pipelined memory is preferably configured to output two load results per clock cycle and more preferably is configured to output two load results and one DMA result per clock cycle.

[0011] The prioritization logic may be configured for receiving load access requests from the load buffer, load access requests from the processor and instruction access requests from the processor. The prioritization logic may be configured for receiving access requests from two or more processors.

[0012] The bank conflict logic may be configured for receiving selected access requests from the prioritization logic, store access requests from the store buffer and DMA access requests from a DMA requestor. The bank conflict logic may detect conflicts among the access requests and generate a stall signal in response to the conflicts.

[0013] According to a second aspect of the invention, a memory system is provided for operation with a processor. The memory system comprises a high speed memory, a load buffer for holding load access requests from the processor, and a memory control unit for processing access requests from the processor. The memory control unit places load access requests from the processor in the load buffer in response to a stall condition and processes the load access requests held in the load buffer in response to removal of the stall condition.

[0014] According to a third aspect of the invention, a memory system is provided for operation with a processor. The memory system comprises a high speed memory, a store buffer for holding store access requests from the processor, and a memory control unit. The memory control unit places the store access requests in the store buffer, detects conflicts between the store access requests and other types of access requests, and processes each store access request held in the store buffer in the absence of a conflict with another type of access request.

[0015] According to a fourth aspect of the invention, a memory system is provided for operation with first and second processors. The memory system comprises a high speed memory, first and second store buffers for holding store access requests from the first and second processors, respectively, first and second load buffers for holding load access requests from the first and second processors, respectively, and a memory control unit for processing access requests from the first and second processors, from the first and second store buffers and from the first and second load buffers.

[0016] The memory control unit may comprise prioritization logic for selecting access requests in accordance with a priority scheme, and bank conflict logic for detecting and handling conflicts between access requests. The memory control unit may be configured for placing load access requests from each of the processors in the respective load buffers in response to a stall condition and for processing the load access requests held in the respective load buffers in response to removal of the stall condition. The memory control unit may further be configured for placing the store access requests from the first and second processors in the first and second store buffers, respectively, and for processing each store access request held in the first and second store buffers in the absence of a conflict with another type of access request.

[0017] According to a fifth aspect of the invention, a method is provided for operating a high speed memory with a processor. The method comprises the steps of processing access requests from the processor and generating a stall signal in response to a specified stall condition, sending the stall signal to the processor, and placing load access requests from the processor in a load buffer in response to the stall signal. The method may further comprise the step of processing the load access request held in the load buffer in response to removal of the stall condition.

[0018] According to a sixth aspect of the invention, a method is provided for operating a high speed memory with a processor. The method comprises the steps of placing store access requests from the processor in a store buffer, detecting a conflict between a store access request and another type of access request, and processing each store access request held in the store buffer in the absence of a conflict with another type of access request.

BRIEF DESCRIPTION OF THE DRAWINGS

[0019] For a better understanding of the present invention, reference is made to the accompanying drawings, which are incorporated herein by reference and in which:

[0020]FIG. 1 is a block diagram of an embodiment of a digital signal processor suitable for incorporation of the invention;

[0021]FIG. 2 is a block diagram of the digital signal processor of FIG. 1, showing major components of each pipeline unit;

[0022]FIG. 3 is a schematic block diagram of a memory system in accordance with an embodiment of the invention;

[0023]FIG. 4 is a schematic block diagram of an embodiment of a megabank shown in FIG. 3;

[0024]FIG. 5 is a schematic block diagram of an embodiment of a super-bank shown in FIG. 4;

[0025]FIG. 6 is a schematic block diagram of an embodiment of a mini-bank shown in FIG. 5; and

[0026]FIG. 7 is a schematic diagram that illustrates a pipeline configuration of the memory system in accordance with an embodiment of the invention.

DETAILED DESCRIPTION

[0027] A block diagram of an embodiment of a digital signal processor suitable for incorporation of the invention is shown in FIGS. 1 and 2. The digital signal processor includes a computation core <b>10</b> and a memory <b>12</b>. The computation core <b>10</b> is the central processor of the DSP. Both the core <b>10</b> and the memory <b>12</b> are pipelined, as described below. Core <b>10</b> includes an instruction fetch unit <b>20</b>, a data address generator <b>22</b>, a load/store unit <b>24</b>, a data cache <b>26</b>, a register file <b>28</b>, a microcontroller execution unit <b>30</b>, a DSP execution unit <b>32</b> and a data cache controller <b>34</b>.

[0028] Instruction fetch unit <b>20</b> may include a 32 k byte instruction cache <b>50</b>, branch prediction circuitry <b>52</b>, a TLB (translation look-aside buffer) <b>54</b>, an instruction alignment unit <b>56</b> and an instruction decoder <b>58</b>. In instruction fetch unit <b>20</b>, program instructions are fetched from the instruction cache <b>50</b> and are decoded by the instruction decoder <b>58</b>. In the event of an instruction cache miss, the requested instruction is accessed in memory <b>12</b>. Instructions may be placed in an instruction queue and subsequently decoded by the instruction decoder <b>58</b>.

[0029] The data address generator <b>22</b> may include loop buffers <b>70</b> and adders <b>72</b> for data address generation in program loops. Virtual addresses are translated to physical addresses in data address generator <b>22</b>. Data address generator <b>22</b> may also include a P register file <b>74</b>, a future file <b>76</b>, hazard detection circuitry <b>78</b> and a TLB <b>80</b>.

[0030] Load/store unit <b>24</b> controls access to data cache <b>26</b> and memory <b>12</b>. Load/store unit <b>24</b> may include a load buffer <b>90</b>, a store buffer <b>92</b>, a fill buffer <b>94</b> and a copyback buffer <b>96</b>. The operations of the load/store unit <b>24</b> depend on instruction type, as described below. In the case of a microcontroller instruction or other instruction which requires access to data cache <b>26</b>, the physical address is routed to data cache <b>26</b>, the tag arrays of data cache <b>26</b> are accessed and the accessed data is output, as required by the instruction. Data cache controller <b>34</b> controls transfer of data between data cache <b>26</b> and memory <b>12</b>. Instructions which do not require memory access may obtain operands from register file <b>28</b>. In the case of a DSP instruction with memory access, the DSP instruction is placed in a skid buffer, and two memory accesses to memory <b>12</b> are initiated. Multiple DSP instructions can be placed in the skid buffer, and two memory accesses can be initiated on each cycle. The data from memory <b>12</b> is output to register file <b>28</b> for instruction execution. In a preferred embodiment, register file <b>28</b> has sixteen entries of 64 bits each and has four write ports and four read ports.

[0031] Microcontroller execution unit <b>30</b> may include an adder/subtractor <b>100</b>, a shifter <b>102</b>, circuitry <b>104</b> for logical operations and branch resolution circuitry <b>106</b>. DSP execution unit <b>32</b> may include quad 32/64-bit multiplier/accumulators <b>110</b>, a 32/64-bit ALU <b>112</b>, a 32/64-bit shifter <b>114</b>, an accelerator <b>116</b> for high speed execution of specific instructions and result formatting circuitry. The results of the microcontroller execution unit <b>30</b> and the DSP execution unit <b>32</b> are written back to register file <b>28</b>. The final results may be written from register file <b>28</b> to memory <b>12</b>.

[0032] The computation core <b>10</b> preferably has a pipelined architecture. The pipelined architecture is a well-known architecture wherein the core includes series-connected stages that operate synchronously, and instruction execution is divided into a series of operations performed in successive pipeline stages in successive clock cycles. Thus, for example, a first stage may perform instruction fetch, a second stage may perform instruction decoding, a third stage may perform data address generation, a fourth stage may perform data memory access and a fifth stage may perform the specified computation. An advantage of the pipelined architecture is increased operating speed, since multiple instructions may be in process simultaneously, with different instructions being in different states of completion.

[0033] An embodiment of a pipeline architecture is described with reference to FIGS. 1 and 2. With respect to pipeline operation, data cache <b>26</b> may be considered as part of the load/store function. Similarly, register file <b>28</b> may be considered as part of the execution function. In one embodiment, instruction fetch unit <b>20</b> has seven stages IF1-IF7, data address generator <b>22</b> has three stages AC1-AC3, and the combination of load/store unit <b>24</b> and data cache <b>26</b> has three stages LS1-LS3. The combination of register file <b>28</b> and microcontroller execution unit <b>30</b> has three stages UC1-WB, and the combination of register file <b>28</b> and DSP execution unit <b>32</b> has eight stages UC1-EP0. In addition, memory <b>12</b> is pipelined and has 11 stages SR1-SR11 in this embodiment. The number of stages defines the number of clock cycles required for an instruction to be completed in a particular unit. However, as noted above, multiple instructions may be in various stages of completion simultaneously.

[0034] The memory of the digital signal processor may have a hierarchical organization. The instruction cache <b>50</b> and the data cache <b>26</b> are level 1 memories, and memory <b>12</b> is a level 2 memory. The level 1 memories are characterized by low latency and relatively small capacities. By contrast, level 2 memory <b>12</b> is characterized by high capacity and relatively high latency. In the event of a cache miss, the level 2 memory is accessed.

[0035] Memory <b>12</b> is functionally connected to load/store unit <b>24</b> for processing load and store requests in connection with program execution. Memory <b>12</b> is also connected via data cache controller <b>34</b> to data cache <b>26</b> for transferring data to and from data cache <b>26</b> and is connected via an instruction cache controller to instruction cache <b>50</b> for transferring data to and from instruction cache <b>50</b>. Accessed data is loaded from memory <b>12</b> to register file <b>28</b>, and results are written back from register file <b>28</b> to memory <b>12</b>. Memory <b>12</b> may further include a DMA port for DMA transfers to and from an external source. Memory <b>12</b> is preferably pipelined for high speed operation and, in one example, has a capacity of 10 megabits.

[0036] As described below, DSP performance may be enhanced by controlling operation such that certain instruction types access data cache <b>26</b>, whereas other instruction types directly access level 2 memory <b>12</b> without first accessing data cache <b>26</b>. Instruction types that access data cache <b>26</b> are typically used in program segments where data access is characterized by temporal and/or spatial locality. Such program segments are likely to benefit from the use of a data cache. Microcontroller instructions typically fall into this category. Instruction types that directly access level 2 memory <b>12</b> are typically used in program segments where data access is not characterized by temporal or spatial locality. Such program segments are unlikely to benefit from the use of a data cache. DSP instructions typically fall into this category. To achieve the desired performance, level 2 memory <b>12</b> is preferably capable of high speed operation and may be pipelined. Further, level 2 memory <b>12</b> may be configured to provide two or more data words per cycle, since DSP instructions may require two or more operands. In one embodiment, data cache <b>26</b> has a capacity of 16 k bytes, and level 2 memory <b>12</b> has a capacity of 10 megabits.

[0037] As indicated above, a memory hierarchy is utilized. In particular, data cache <b>26</b> serves as a level 1 memory, and memory <b>12</b> serves as a level <b>2</b> data memory. As known in the art, higher levels in the memory hierarchy typically are characterized by low latency and low capacity. In the embodiment of FIG. 1, data cache <b>26</b> accesses level 2 memory <b>12</b> in the case of a cache miss. However, DSP instructions requiring memory access do not access the data cache <b>26</b> and thus do not incur the overhead associated with a cache miss. Instead, DSP instructions requiring memory access directly access level 2 memory <b>12</b>. The latency otherwise associated with lower level memories is avoided by configuring level 2 memory <b>12</b> as a highly pipelined memory that is capable of providing two data items per cycle. In particular, on every cycle two memory accesses can be started and two data items can be provided to DSP execution unit <b>32</b>. So far as the programmer is concerned, two 64-bit data items are being received by DSP execution unit <b>32</b> on every cycle.

[0038] A block diagram of an embodiment of level 2 memory <b>12</b> is shown in FIG. 3. In the embodiment of FIG. 3, memory <b>12</b> may be accessed by DSP core <b>10</b> and a second DSP core <b>14</b>. However, it will be understood that memory <b>12</b> may operate with a single DSP core, such as DSP core <b>10</b>. Furthermore, memory <b>12</b> may operate with processors other than DSP core <b>10</b> and with other DSP core configurations. For example, the DSP does not necessarily include separate DSP and microcontroller execution units.

[0039] DSP core <b>10</b> communicates with memory <b>12</b> via load buses L<b>00</b> and L<b>01</b>, a store bus S<b>0</b> and an instruction bus <b>10</b>. Memory <b>12</b> includes a store buffer <b>300</b>, a load skid buffer <b>302</b>, prioritization logic <b>310</b>, bank conflict detection and handling logic <b>312</b>, control logic <b>314</b>, SRAM megabanks <b>320</b> and <b>322</b> and a data crossbar <b>330</b>. Prioritization logic <b>310</b>, bank conflict detection and handling logic <b>312</b> and control logic <b>314</b> constitute a memory control unit <b>316</b>. In the case where the memory <b>12</b> operates with DSP core <b>14</b>, memory <b>12</b> further includes a store buffer <b>340</b> and a load skid buffer <b>342</b>.

[0040] Load buses L<b>00</b> and L<b>01</b> are coupled to prioritization logic <b>310</b> and to load skid buffer <b>302</b>. Load skid buffer <b>302</b> provides buffering of load requests in the event that the pipeline is stalled. The store bus S<b>0</b> is coupled through store buffer <b>300</b> to bank conflict detection and handling logic <b>312</b>. Instruction bus <b>10</b> is coupled to prioritization logic <b>310</b>.

[0041] Prioritization logic <b>310</b> prioritizes memory access requests according to priorities that are predetermined or are programmable. In one embodiment, a DMA request has highest priority, a load from skid buffer <b>302</b> has second priority, a load from DSP core <b>10</b> has third priority, an instruction request from DSP core <b>10</b> has fourth priority and a store request has lowest priority. It will be understood that different priorities may be utilized to achieve a desired result.

[0042] As shown in FIG. 3, prioritization logic <b>310</b> includes muxes <b>350</b>, <b>352</b>, <b>354</b> and <b>356</b>. Mux <b>350</b> selects two buses from load buses L<b>00</b> and L<b>01</b>, instruction bus I<b>0</b> and the two output buses of load skid buffer <b>302</b>. Mux <b>352</b> selects two buses from load buses L<b>10</b> and L<b>11</b>, instruction bus I<b>1</b> and the two output buses of load skid buffer <b>342</b>. Mux <b>354</b> selects the two output buses of mux <b>350</b> or the two output buses of mux <b>352</b>. Similarly, mux <b>356</b> selects the two output buses of mux <b>350</b> or the two output buses of mux <b>352</b>.

[0043] The bank conflict detection and handling logic <b>312</b> determines conflicts among memory access requests. In one embodiment, each of megabanks <b>320</b> and <b>322</b> includes five superbanks and can handle two load requests, one store request and one DMA request in parallel, provided that the access requests are addressed to different superbanks. In the event of a bank conflict, i.e. two access requests to the same superbank, the conflicting requests are pipelined one behind the other in the memory and a stall condition is generated. A stall signal is forwarded to the DSP core <b>10</b>, whereby the DSP core <b>10</b> is notified to expect the result later.

[0044] In one embodiment, each of megabanks <b>320</b> and <b>322</b> has a size of 5 megabits, for a total memory size of 10 megabits, and can run at a clock frequency greater than 1 gigahertz. Each megabank includes five superbanks, each having a size of 1 megabits, so that multiple access requests can be serviced simultaneously by different superbanks. This permits two load requests to be started on each cycle and two load results to be provided to register file <b>28</b> on each cycle. Thus, two 64-bit load results can be obtained on each cycle. Data crossbar <b>330</b> routes data from megabanks <b>320</b> and <b>322</b> to DSP core <b>10</b>, DSP core <b>14</b> and a DMA requestor in accordance with control signals derived from the instruction being executed.

[0045] A block diagram of an embodiment of megabank <b>320</b> is shown in FIG. 4. Megabank <b>322</b> (FIG. 3) may have the same configuration. In the embodiment of FIG. 4, megabank <b>320</b> includes five super-banks <b>400</b>, <b>402</b>, <b>404</b>, <b>406</b> and <b>408</b>. Each super-bank preferably has a capacity of 128 k bytes, or 1 megabit. The megabank can service multiple accesses simultaneously, provided that the accesses are to different super-banks. The granularity of the parallel accesses is limited to the super-bank level in the embodiment of FIG. 4. As shown in FIG. 4, each super-bank is coupled to four address buses, including load address bus 1d0, load address bus 1d1, store address bus st and DMA address bus dma. Each super-bank is also coupled to two input data buses, including a store data bus st and a DMA data bus dma. The data outputs of super-banks <b>400</b>, <b>402</b>, <b>404</b>, <b>406</b> and <b>408</b> are coupled through gated buffers <b>410</b>, <b>412</b>, <b>414</b>, <b>416</b> and <b>418</b>, respectively, to a load result bus 1dresult0 and are coupled through gated buffers <b>420</b>, <b>422</b>, <b>424</b>, <b>426</b> and <b>428</b>, respectively, to a load result bus 1dresult1. In addition, the outputs of super-banks <b>400</b>, <b>402</b>, <b>404</b>, <b>406</b> and <b>408</b> are coupled through gated buffers <b>430</b>, <b>432</b>, <b>434</b>, <b>436</b> and <b>438</b>, respectively, to a DMA bus dma_out. Gated buffers <b>410</b>, <b>412</b>, <b>414</b>, <b>416</b> and <b>418</b> constitute a first 5:1 mux <b>440</b>, gated buffers <b>420</b>, <b>422</b>, <b>424</b>, <b>426</b> and <b>428</b> constitute a second 5:1 mux <b>442</b>, and gated buffers <b>430</b>, <b>432</b>, <b>434</b>, <b>436</b> and <b>438</b> constitute a third 5:1 mux <b>444</b>. The muxes <b>440</b>, <b>442</b> and <b>444</b> are controlled by appropriate address bits to provide two load results and one DMA read result per clock cycle. The output data buses in the embodiment of FIG. 4 are 64 bits wide.

[0046] The megabank can support up to four simultaneous accesses, including two DSP core reads, one DSP core store and one DMA read/write. The two DSP core reads can be either two data memory accesses or one instruction memory access and one data memory access.

[0047] A block diagram of an embodiment of super-bank <b>400</b> is shown in FIG. 5. Super-banks <b>402</b>, <b>404</b>, <b>406</b> and <b>408</b> (FIG. 4) may have the same configuration. Super-bank <b>400</b> may include mini-banks <b>500</b>, <b>502</b>, <b>504</b> and <b>506</b>, each having a capacity of 32 k bytes. A mux <b>510</b> selects one of the address buses 1d0, 1d1, st or dma. The selected address bus is coupled to mini-banks <b>500</b>, <b>502</b>, <b>504</b> and <b>506</b>. In a store operation or a DMA write operation, a mux <b>520</b> selects one of the input data buses st or dma, and the selected input data bus is coupled to mini-banks <b>500</b>, <b>502</b>, <b>504</b> and <b>506</b>. The data outputs of mini-banks <b>500</b>, <b>502</b>, <b>504</b> and <b>506</b> are supplied through gated buffers <b>530</b>, <b>532</b>, <b>534</b> and <b>536</b>, respectively, to a data bus <b>540</b>. Gated buffers <b>530</b>, <b>532</b>, <b>534</b> and <b>536</b> constitute a 4:1 mux <b>550</b>, which is controlled by appropriate address bits. Bus <b>540</b> is coupled to a register <b>542</b>.

[0048] A block diagram of an embodiment of mini-bank <b>500</b> is shown in FIG. 6. Mini-banks <b>502</b>, <b>504</b> and <b>506</b> (FIG. 5) may have the same configuration. As shown in FIG. 6, each mini-bank may have four quadrants, each of which includes an SRAM memory array. Thus, mini-bank <b>500</b> includes SRAM memory arrays <b>600</b>, <b>602</b>, <b>604</b> and <b>606</b>, each of which is 128 bits by 512 bits in this embodiment. The bank address is supplied to address decoders <b>610</b> and <b>612</b>. Outputs of address decoder <b>610</b> are supplied to memory arrays <b>600</b> and <b>602</b>, and outputs of address decoder <b>612</b> are supplied to memory arrays <b>604</b> and <b>606</b>. The outputs of memory arrays <b>600</b>, <b>602</b>, <b>604</b> and <b>606</b> are supplied to 8:1 muxes <b>620</b>, <b>622</b>, <b>624</b> and <b>626</b>, respectively. Muxes <b>620</b> and <b>622</b> are controlled by outputs of address decoder <b>610</b>, and muxes <b>624</b> and <b>626</b> are controlled by outputs of address decoder <b>612</b>. Muxes <b>620</b>, <b>622</b>, <b>624</b> and <b>626</b> perform read column select of the respective memory arrays. The outputs of muxes <b>620</b>, <b>622</b>, <b>624</b> and <b>626</b> are supplied to registers <b>630</b>, <b>632</b>, <b>634</b> and <b>636</b>, respectively. The outputs of registers <b>630</b>, <b>632</b>, <b>634</b> and <b>636</b> are coupled through gated buffers <b>640</b>, <b>642</b>, <b>644</b> and <b>646</b>, respectively, to data bus <b>650</b>. Gated buffers <b>640</b> and <b>642</b> are controlled by outputs of address decoder <b>610</b>, and gated buffers <b>644</b> and <b>646</b> are controlled by outputs of address decoder <b>612</b>. Gated buffers <b>640</b>, <b>642</b>, <b>644</b> and <b>646</b> constitute a 4:1 mux <b>660</b> for selection of a 64-bit result.

[0049] As noted above, level 2 memory <b>12</b> preferably has a pipeline configuration. A schematic diagram of an embodiment of a pipeline configuration of memory <b>12</b> is shown in FIG. 7. Like elements in FIGS. <b>3</b>-<b>7</b> have the same reference numerals. In the embodiment of FIG. 7, memory <b>12</b> has eleven stages and thus requires eleven cycles to service a load request. However, the eleven stage pipeline may process eleven access requests simultaneously and may supply two load results per clock cycle to register file <b>28</b> (FIG. 1).

[0050] The memory access is initiated in the LS1 stage of load/store unit <b>24</b> (FIG. 2). Memory <b>12</b> includes stages SR1 through SR11. Stage SR1 involves routing delay to the edge of memory <b>12</b> and SRAM base address compare <b>700</b> (FIG. 7). Stage SR2 involves prioritization of requests and bank address decode. Stage SR3 involves bank conflict detection, bank select generation and address and control signals present in registers <b>710</b> at the edge of the megabank. Stage SR4 involves address routing to all the superbanks.

[0051] Stage SR5 involves delay through the 4:1 address mux <b>510</b> at the edge of the superbank for selection of 1d0, 1d1, st or dma address buses and address routing to minibanks within the superbanks. Stage SR6 involves row address decoding by address decoders <b>610</b> and <b>612</b> (FIG. 6) and generation of quadrant enable. Stage SR7 involves reading memory arrays <b>600</b>-<b>606</b>, read column multiplexing by muxes <b>620</b>-<b>626</b> and data present in registers <b>630</b>-<b>636</b> at the edge of the quadrant. Stage SR8 involves quadrant multiplexing by mux <b>660</b>, minibank multiplexing by mux <b>550</b> and routing data across minibanks. Data is present in register <b>542</b> at the edge of the superbank. Stage SR9 involves routing across the five superbanks, superbank multiplexing by muxes <b>440</b>, <b>442</b> and <b>444</b>, and data present in register <b>750</b> at the edge of the megabank. Stage SR10 involves routing across the two minibanks and megabank multiplexing by data crossbar <b>330</b> (FIG. 3). Stage SR11 involves transport to the edge of the DSP core <b>10</b>.

[0052] Data is multiplexed to the register file <b>28</b> in stage UC1. The corresponding instruction is read out of a skid buffer, which may be located in load/store unit <b>24</b>, during stage SR8 and is advanced through stages LS1, LS2 and LS3 of load/store unit <b>24</b> simultaneously with the load request being advanced through stages SR9, SR10 and SR11, respectively, of memory <b>12</b>. Thus, the corresponding instruction reaches the DSP execution unit <b>32</b> when the accessed data is present in register file <b>28</b>.

[0053] When a stall condition is detected in systems that run at high frequencies, several clock cycles may be required for different pipeline units to react to the stall condition. The DSP core continues to initiate memory accesses every clock cycle. If a stall condition, such as a bank conflict condition, occurs in the memory, the DSP core continues to send access requests down the pipeline until the stall signal reaches the DSP core and the DSP core has reacted to the stall signal. The access requests following the stall condition are placed in the respective load skid buffers <b>302</b> and <b>342</b> (FIG. 3). After the stall condition is no longer present, the access requests that were placed in the skid buffers <b>302</b> and <b>342</b> are output from the skid buffers to prioritization logic <b>310</b> and are processed. Thus, the skid buffers <b>302</b> and <b>342</b> permit the system to run at high clock frequencies.

[0054] All of the store requests by the DSP cores <b>10</b> and <b>14</b> are placed in store buffers <b>300</b> and <b>340</b>, respectively. The outputs of store buffers <b>300</b> and <b>340</b> are supplied to bank conflict detection and handling logic <b>312</b>. Bank conflict detection and handling logic <b>312</b> identifies conflicts between load access requests, DMA access requests and store access requests, and gives priority to load access requests and DMA access requests.

[0055] The store access requests are output from store buffers <b>300</b> and <b>340</b> when there is no conflict with other load or DMA access requests. Stalls due to conflicts with stores are eliminated by providing the store buffer. Store to load forwarding support out of the store buffers is also provided. This eliminates stalls on loads that are dependent on stores.

[0056] The memory <b>12</b> is deeply pipelined and thus has relatively high latency. However, when the DSP is performing a series of computations, the high latency does not degrade performance. The memory <b>12</b> operates at very high speed and completes two load requests per clock cycle. The deeply pipelined memory permits clock frequencies greater than one gigahertz to be utilized.

[0057] While there have been shown and described what are at present considered the preferred embodiments of the present invention, it will be obvious to those skilled in the art that various changes and modifications may be made therein without departing from the scope of the invention as defined by the appended claims.