Cache-line reuse-buffer

FIELD OF THE INVENTION

P-0001[0001] This invention generally relates to cache memories. More particularly, an aspect of this invention relates to a cache-line reuse-buffer.

BACKGROUND OF THE INVENTION

P-0002[0002] A cache is generally a small fast memory holding recently accessed data, designed to speed up subsequent access to the same data. Instructions and data are transferred from main memory to the cache in blocks, using a look-ahead algorithm. The cache stores this information in one or more cache lines. Typically, sequential lines of instructions are stored in the cache lines. A fetch engine system speculatively stores consecutive sequential lines of instructions in anticipation of their future use.

P-0003[0003]FIG. 1 illustrates a prior art fetch engine system fetching a new cache line from the instruction cache every fetch cycle. The fetch engine system consists of a BTB engine, a branch predictor (BP), a return address stack (RAS), logic to determine the next address, and an instruction cache. The fetch engine fetches one full block of instructions from the instruction cache per cycle by accessing the instruction cache. The BTB engine and branch predictor (BP) provide instruction information of the current fetch cycle. The logic to determine the next address provides the next fetch address. The instruction cache consists of multiple cache lines. Note, the at sign “@” means “address.

P-0004[0004] In general, a cache line is a unit of information, such as multiple bytes, words, etc. In most Reduced Instruction Set Codes (RISC) systems, the cache lines are 32 bytes or 64 bytes wide. Typically, instructions are 4 bytes wide and fetch engines are designed to fetch 3-5 instructions (12-20 bytes) per clock cycle. Rather than reading a single word or byte from main memory at a time, each cache entry is usually holds a certain number of words, known as a “cache line” and a whole line is read and cached at once. However, it is very frequent that the same cache line is fetched in several consecutive cycles. This is especially true for long cache lines.

P-0005[0005] Typically, fetch performance is a very important factor because it effectively limits the overall processor performance. However, traditional thinking is usually that there is little performance advantage in increasing front-end performance beyond what the back-end can consume. For each processor design, typically the target is to build the best possible fetch engine for the required performance level. Thus, a fetch engine can fetch a certain number (width) of instructions per clock cycle. The fetch width of fetch operation preformed by the fetch engine is cooperated with the number of instructions that the processor can consume.

P-0006[0006] The prior art fetch engine reads a cache line from the instruction cache every cycle and then extracts the requested instructions from that cache line, as instructed by the fetch request. The fetch engine first tries to obtain these instructions from the instruction cache and then from main memory. The longer in width a cache line is the more area on the chip that a cache line occupies. If a fetch engine can only fetch X number of instructions, then traditional thinking has been why build a cache line that store 8× of instructions because the actual execution of those instructions by the processor will not occur any faster than if the cache line is 2×. Fetching a cache line wider than the actual fetch width of the processor represents a wasted number of instructions transferred, because not all the instructions in the cache line will be actually used/fetched for actual execution.

P-0007[0007] However, a fetch engine will be better if it provides better performance, but also if it takes fewer resources, requires less chip area, or consumes less power. Power consumption is becoming an important design factor in high performance microarchitectures. A design that consumes as little energy and dissipate as little power as possible is also advantageous.

P-0008[0008] Also, the increasing clock frequencies employed in current and future generation processors limits the size of cache memories, or else increases their access time. The use of line buffers has been implemented in main memory chips to reduce access time, providing a level of cache within the memory chip itself. However, some traditional thinking has been not to use line buffers for on-chip cache memories because it does not offer any speed performance advantage as long as the access time is one cycle.

BRIEF DESCRIPTION OF THE DRAWINGS

P-0009[0009] The drawings refer to the invention in which:

P-0010[0010]FIG. 1 illustrates a prior art fetch engine system fetching a new cache line from the instruction cache every fetch cycle;

P-0011[0011]FIG. 2 illustrates a block diagram of an embodiment of the cache-line reuse-buffer to store a cache line from an instruction cache;

P-0012[0012]FIG. 3 illustrates a block diagram of an embodiment of the control logic cooperating with the cache-line reuse-buffer and a first address buffer and a second address buffer;

P-0013[0013]FIG. 4 illustrates an exemplary comparison of the current cache line stored in the cache-line reuse-buffer to the starting address of the next request to determine if all or some of the content in the cache-line reuse-buffer will be used to fulfill the next fetch cycle;

P-0014[0014]FIG. 5 illustrates a block diagram of an embodiment of a cache-line reuse-buffer having a length matched to a cache line that has a byte length equal to or greater than two times the fetch width of an instruction fetch operation performed by a fetch engine in order to reduce instruction misalignment;

P-0015[0015]FIG. 6 illustrates a block diagram of an embodiment of a cache-line reuse-buffer loaded with content that partially fulfills a fetch request;

P-0016[0016]FIG. 7 illustrates a block diagram of an embodiment of cache-line reuse-buffer loaded with content that completely fulfills a fetch request;

P-0017[0017]FIG. 8 illustrates an exemplary graph showing the fraction of instruction cache accesses that can be avoided using embodiments of the cache-line reuse-buffer having different lengths greater than the fetch width; and

P-0018[0018]FIG. 9 illustrates a block diagram of an exemplary computer system that may use an embodiment of the cache-line reuse-buffer.

P-0019[0019] While the invention is subject to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and will herein be described in detail. The invention should be understood to not be limited to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

DETAILED DISCUSSION

P-0020[0020] In the following description, numerous specific details are set forth, such as examples of specific data signals, named components, connections, number of bytes in a cache line, etc., in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well known components or methods have not been described in detail but rather in a block diagram in order to avoid unnecessarily obscuring the present invention. Further specific numeric references such as first starting address, may be made. However, the specific numeric reference should not be interpreted as a literal sequential order but rather interpreted that the first starting address is different than a second starting address. Thus, the specific details set forth are merely exemplary. The specific details may be varied from and still be contemplated to be within the spirit and scope of the present invention. The term coupled is defined as meaning connected either directly or indirectly.

P-0021[0021] In general, various methods, apparatuses, and systems are described that compare a current fetch request having a first start address and length associated with the current fetch request to a second start address of the next fetch request, determine whether the content already loaded in a buffer will be used to at least partially fulfill the next fetch request based upon the comparison, and inhibit access to an instruction cache based upon the comparison.

P-0022[0022]FIG. 2 illustrates a block diagram of an embodiment of the cache-line reuse-buffer to store a cache line from an instruction cache. Fetch engine system <b>200</b> may include components such as request predictor <b>202</b>, a fetch target queue (FTQ) <b>204</b>, an instruction cache <b>206</b>, a cache-line reuse-buffer <b>208</b>, control logic <b>210</b>, rotate and select logic <b>212</b>, and other similar components. In general, the fetch engine system <b>200</b> retrieves instructions from the instruction cache <b>206</b> and stores instructions in the instruction cache <b>206</b>. The request predictor <b>202</b> receives the current fetch request <b>214</b>. A fetch request <b>214</b> contains an indication of the starting address of the fetch request. The request predictor <b>202</b> speculates on the length associated to the current fetch request <b>214</b> and the fetch request for the next cycle. The request predictor <b>202</b> sends the starting address of the current fetch request, length of the current request, and the anticipated starting address of the fetch request for the next cycle to the fetch target queue <b>204</b>. The fetch target queue <b>204</b> stores fetch requests (address and length) <b>214</b>. The cache-line reuse-buffer <b>208</b> stores one or more cache lines of the instruction cache <b>206</b> corresponding to the current fetch request <b>214</b>. In an embodiment, the length of the cache-line reuse-buffer <b>208</b>, such as, for example, one hundred and twenty-eight bytes, matches the length of a single cache line, such as, for example, one hundred and twenty-eight bytes.

P-0023[0023] The control logic <b>210</b> determines if the content in the cache-line reuse-buffer <b>208</b> will be reused the next cycle or if a new cache line will be required. The control logic <b>210</b>, such as a comparator, compares the starting address of the next request to the range of address stored in the cache-line reuse-buffer <b>208</b>. If the starting address of the next fetch request falls within the range of address in the cache line already loaded in the cache-line reuse-buffer <b>208</b>, then control logic <b>210</b> inhibits the signal to trigger accessing the instruction cache <b>206</b> to load another cache line into the cache-line reuse-buffer <b>208</b>.

P-0024[0024] When a cache line from the instruction cache <b>206</b> is not loaded to provide the next set of instructions desired in the next fetch cycle, then power that would have been consumed to load that cache line is now saved. For example, consumed power may be saved from not energizing sense amplifiers associated with the instruction cache <b>206</b>, reading word lines storing the desired instructions, energizing control circuitry associated with the instruction cache <b>206</b>, and reloading the content of the cache line into the cache-line reuse-buffer <b>208</b>. Some prior art systems access the instruction cache and load a cache line for each fetch request even if some or all of the content loaded in a cache line will be used to fulfill the next fetch cycle. The rotate and select logic <b>212</b> sends the instructions loaded in the cache-line reuse-buffer <b>208</b> to the pipeline for use by the processor.

P-0025[0025] In an embodiment, the fetch target queue (FTQ) <b>204</b> stores the starting address of the current fetch request <b>214</b>, the length of the current fetch request <b>214</b> and the starting address of the next request. In an embodiment, the request predictor <b>202</b> may be a branch predictor, a stream predictor, a fetch request predictor or some other mechanism predicting the next needed instruction address. In an embodiment, the request predictor <b>202</b> may calculate the starting address of the next fetch request by adding the starting address of the current fetch request <b>214</b> and the length of the current request <b>214</b>. In an embodiment, the request predictor <b>202</b> may determine the starting address of the next fetch request by identifying and decoding a branch instruction. In an embodiment, the control logic <b>206</b> may directly or indirectly inhibit accessing the instruction cache <b>206</b> to load another cache line for eventual processor use. In an embodiment, the request for instructions <b>214</b> may be a fetch request, an instruction stream request, or some other similar request for instructions that communicates the current start address of the request and length of the current request.

P-0026[0026]FIG. 3 illustrates a block diagram of an embodiment of the control logic cooperating with the cache-line reuse-buffer and a first address buffer and a second address buffer. The fetch engine system <b>300</b> has similar components as described above as well as a first address buffer <b>316</b> and a second address buffer <b>318</b>. The first address buffer stores <b>316</b> the start address and request length for the current fetch cycle. The second address buffer <b>318</b> stores the starting address for the next fetch cycle. The control logic <b>310</b> decodes the current fetch request in the first address buffer <b>316</b> to determine the cache line required for the current fetch cycle, the starting address of the current fetch request, and the length of the current request. Similarly, the control logic <b>310</b> decodes the next fetch request to determine the start address of the next fetch cycle. In an embodiment, the control logic <b>310</b> may be programmed with fetch engine specifications such as fetch width of the fetch engine, cache line width, as well as other similar information. The control logic <b>310</b> compares the starting address of the next fetch request stored in the second address buffer <b>318</b> to the range of address loaded in the cache-line reuse-buffer <b>308</b> as identified by content in the first address buffer <b>316</b> in order to determine if all or some of the content in the cache-line reuse-buffer <b>308</b> will be used to fulfill the next fetch cycle.

P-0027[0027]FIG. 4 illustrates an exemplary comparison of the current cache line stored in the cache-line reuse-buffer to the starting address of the next request to determine if all or some of the content in the cache-line reuse-buffer will be used to fulfill the next fetch cycle. The cache-line reuse-buffer <b>408</b> stores the content of the first cache line <b>420</b>. The current fetch request correlates to the content of the first cache line <b>420</b>. The control logic compares the starting address of the next request to the range of addresses stored in the cache-line reuse-buffer <b>408</b>. In an Embodiment, the first cache line <b>420</b> is 128 bytes wide and so is the second cache line <b>422</b>; the starting address of the current fetch starts on byte number <b>52</b>; and the request length of the current fetch request is 64 bytes. Therefore, the 128 bytes in the stored cache-line reuse-buffer <b>408</b> will satisfy the current fetch request because the start address (byte <b>52</b>) plus the length of the request (64 bytes) equals byte <b>116</b> which is equal to or less than the 128 byte width of the instructions stored in the first cache line <b>420</b>. No necessity exists to load another cache line to satisfy the current fetch request. If the starting address of the next fetch request is either be the next sequential byte, byte <b>117</b>, or branches to starting address in this same cache line, such byte <b>20</b>, then the cache-line reuse-buffer <b>408</b> retains this same cache line, the first cache line <b>420</b>, without loading in a new cache in from the instruction cache. Some exemplary cache-line reuse-buffer <b>408</b> scenarios will be further described later.

P-0028[0028] Note, the request length may be determined from various combinations of bytes per instruction and instructions fetched per clock cycle. For example, the 64 byte request length of the current fetch request may be four bytes per instruction and sixteen instructions fetched per clock cycle (64 bytes) or thirty-two bytes per instruction and two instructions fetched per clock cycle (64 bytes).

P-0029[0029] Referring to FIG. 3, the instruction cache <b>306</b> may be a direct mapped cache, fully associative cache, set associative cache, or other similar cache. The instruction cache <b>306</b> contains two or more cache lines to store instructions that the fetch engine system <b>300</b> speculates the processor will be using in the near future. In an embodiment, the fetch engine system <b>300</b> loads an instruction stream, composed of sequential instructions, into multiple consecutive cache lines anticipating the use of these instructions in a sequential order.

P-0030[0030] The instruction cache <b>306</b> is driven by the fetch requests stored in the fetch target queue <b>304</b>. Not all instructions provided by the instruction cache <b>306</b> need to be fetched in a single cycle. If the single cache line contains the whole fetch request, then the control logic <b>310</b> communicates to the fetch target queue <b>304</b> to advance to the next request. If the single cache line does not contain the whole fetch request, the control logic <b>310</b> communicates to the fetch target queue <b>304</b> to update and reflect the remaining part of the stream to be fetched.

P-0031[0031]FIG. 5 illustrates a block diagram of an embodiment of a cache-line reuse-buffer having a length matched to a cache hue that has a byte length equal to or greater than two times the fetch width of an instruction fetch operation performed by a fetch engine in order to reduce instruction misalignment. Instruction misalignment occurs when a single fetch request for consecutive instructions requires accessing two or more cache lines to fulfill that request. If instruction misalignment occurs the control logic communicates to the fetch target queue to update and reflect the remaining part of the stream to be fetched. A fetch engine having a four-wide fetch width <b>526</b> may fetch an exemplary fetch request consisting of three consecutive instructions <b>528</b>. In an embodiment, the cache-line reuse-buffer <b>508</b> has a length matched to the exemplary eight-wide cache line <b>530</b>. In an embodiment, the cache-line reuse-buffer <b>308</b> has a length matched to the exemplary sixteen-wide cache line <b>532</b>.

P-0032[0032] In an embodiment, a fetch request consisting of three consecutive instructions <b>528</b> are be fetched in a single cycle by a fetch engine having a four-wide fetch width <b>526</b>, but such is not always the case. A three-instruction stream request <b>528</b> may take more than one cycle to fetch on a fetch engine having a four-wide fetch width <b>526</b> if the instructions cross the cache line boundary <b>534</b>. It is possible that the three instruction stream request <b>528</b> is split across two separate cache lines, a first four-wide cache-line <b>536</b> and a second four-wide cache-line <b>538</b>. The starting address of the fetch request may be the third word line <b>540</b> of the first four-wide cache line <b>536</b> and continue in length to the first word line <b>542</b> of the second four-wide cache line <b>538</b>. The fetch engine requires two clock cycles to fetch the entire fetch request. The second four-wide cache line <b>538</b> needs to be accessed and loaded to complete the single fetch request. Performance of the system may be impacted if it takes two clock cycles to complete a single fetch request.

P-0033[0033] The use of instruction cache lines having a greater byte width reduces the possibilities of the fetch request crossing the cache line boundary <b>534</b>. In an embodiment, use of cache lines that posses width's twice that of the fetch width, eight-width <b>530</b> in this example, reduces the chances that the three-wide instruction stream fetch request <b>528</b> is split across a cache line boundary <b>534</b>. In an embodiment, use cache lines that posses width's four times that of the fetch width, sixteen-width <b>532</b> in this example, significantly reduces the chances that the three-wide instruction stream fetch request <b>528</b> is split across a cache line boundary <b>534</b>.

P-0034[0034] In an embodiment, the cache-line reuse-buffer <b>508</b> cooperates with layout optimized codes to benefit from denser packing of useful instructions to cache lines.

P-0035[0035] Referring to FIG. 3, the cache-line reuse-buffer <b>308</b> differs from the instruction cache <b>306</b> because the cache-line reuse-buffer <b>308</b> does not store its contents in a speculative manner expecting the loaded instructions to be used in future fetch cycles in order to be useful. The control logic <b>310</b> determines with certainty whether the some or all of the content in the cache-line reuse-buffer <b>308</b> will be reused or not in the next fetch cycle. The advanced certain knowledge of the necessities of the next fetch cycle allows the control logic <b>310</b> to determine whether to inhibit accessing the instruction cache <b>306</b> to save power, decide whether a cache line misalignment will occur in the current fetch cycle, as well as other similar decisions.

P-0036[0036] The cache-line reuse-buffer <b>308</b> may improve power dissipation by reducing instruction cache <b>306</b> accessing, potential latency performance and cache line misalignment. The cache-line reuse-buffer <b>308</b> reduces the activity of the instruction cache <b>306</b> by fully exploiting cache lines before fetching a new cache line. The cache-line reuse-buffer <b>308</b> has a defined length from which the control logic <b>310</b> can make advanced decisions with certainty about the instruction necessities of the current fetch cycle as well as the next fetch cycle with certainty. As noted in an embodiment, the defined length of the cache-line reuse-buffer <b>308</b> is matched to a single cache line. However, in another embodiment, the defined length of the cache-line reuse-buffer <b>308</b> may be matched to the combined width of two or more consecutive cache-lines. The defined length of the cache-line reuse-buffer <b>308</b> may be equal to or greater than four times the fetch width. The defined length of the cache-line reuse-buffer <b>308</b> may be equal to or greater than eighty bytes.

P-0037[0037] The actual instruction fetch proceeds from the contents of the cache-line reuse-buffer <b>308</b>. The instructions are aligned using the starting address, and valid instructions are selected up to the maximum fetch width of the fetch engine or the remaining instructions in the cache-line reuse-buffer <b>308</b>. Once all the valid instructions in the cache-line reuse-buffer <b>308</b> have been passed to the processor, new instructions are fetched from the instruction cache <b>306</b>. The actual number of instructions fetched is then used to update the fetch target queue <b>304</b> entry, or to advance the fetch target queue <b>304</b> if the request was completely fetched.

P-0038[0038]FIG. 6 illustrates a block diagram of an embodiment of a cache-line reuse-buffer loaded with content that partially fulfills a fetch request. If the start address of the fetch request plus the length of the fetch request is less than the content remaining in the cache-line reuse-buffer <b>608</b>, then the that content completely fulfills the fetch request. However, the fetch request may also span across a first cache line <b>620</b> and a second cache line <b>622</b> and the defined length of the cache-line reuse-buffer <b>608</b> has loaded the content stored in the first cache line <b>620</b>. The fetch request for the current cycle has a start address <b>650</b> that correlates to content within the first cache line <b>620</b>. However, the length of the current request <b>652</b> is such that instructions desired by the current fetch request also are stored in the second cache line <b>622</b>. The control logic determines the content already loaded in a cache-line reuse-buffer <b>608</b> will be used to at least partially fulfill the next fetch request and initially inhibits instruction cache access. The instruction fetch proceeds from the contents of the cache-line reuse-buffer <b>608</b>. The instructions are aligned using the starting address of the current fetch request <b>650</b>. The remaining valid instructions in the cache-line reuse-buffer <b>608</b> are selected to be sent to the processor. The actual number of instructions fetched is then used to update the fetch target queue entry. Once all the valid instructions in the cache-line reuse-buffer <b>608</b> have been passed to the processor, the control logic directs the cache-line reuse-buffer <b>608</b> to load new instructions from the second cache line. The instruction cache is accessed to load the content of the second cache line <b>622</b>. The cache-line reuse-buffer <b>608</b> saved the power consumption approximately equal to one instruction cache access.

P-0039[0039]FIG. 7 illustrates a block diagram of an embodiment of cache-line reuse-buffer loaded with content that completely fulfills a fetch request. The start address <b>750</b> and length <b>752</b> of the current fetch request falls within the range of address stored in the cache-line reuse-buffer <b>708</b>. The request predictor identifies that the branch instruction of the next request also has a starting address <b>758</b> within the cache-line reuse-buffer <b>708</b>. The fetch width <b>760</b> of the engine is approximately one third the length of the cache-line reuse-buffer <b>708</b>. Three fetch cycles are required to complete the current fetch request. Thus, the cache-line reuse-buffer <b>708</b> reduces instruction cache activity when a cache line will be used several times to read a long instruction stream request. Also, the cache-line reuse-buffer <b>708</b> reduces instruction cache activity for a whole loop body, i.e. all the loop iterations occur within the content of the cache-line reuse-buffer <b>708</b>. Being able to read instructions from the cache-line reuse-buffer <b>708</b> for several consecutive cycles means that there is no need to fetch a new cache line from the instruction cache. Therefore, it is not necessary to power up the instruction cache to read a new cache line.

P-0040[0040] Also, it is not necessary to wait for the cache line to be read if the instruction cache has a non-unit latency (that is, if reading from it takes several cycles). The increasing clock frequencies employed in current and future generation processors may limit the size of cache memories or else increase cache access time. In an environment with non-unit latency in the instruction cache, the cache-line reuse-buffer <b>708</b> could also be used to improve performance. If the instruction cache has a latency greater than one cycle, the cache-line reuse-buffer <b>708</b> provides a single cycle access time.

P-0041[0041]FIG. 8 illustrates an exemplary graph showing the fraction of instruction cache accesses that can be avoided using embodiments of the cache-line reuse-buffer having different lengths greater than the fetch width. The X axis <b>762</b> shows different cache-line reuse-buffer lengths, relative to the fetch width of the processor: a single cache line as wide as the fetch width, a single cache line twice as wide as the fetch width, and a cache line four times as wide as the fetch width.

P-0042[0042] If the increased cache line width scaled perfectly, a cache-line reuse-buffer twice as wide as the fetch width would reduce 50% of all accesses, and a cache line 4 times wider than the fetch width would save 75% of all accesses.

P-0043[0043] In an embodiment, due to instruction misalignment problems, the reduction obtained may not be perfect. For example, the reduction obtained may be 45% for 2× width and 65% for 4× widths.

P-0044[0044] In an embodiment, any of the logic described above consists of electronic circuits that follow the rules of Boolean Logic, software that contain patterns of instructions, or any combination of both. The software can be embodied onto a machine-readable medium A machine-readable medium includes any mechanism that provides (e.g., stores and/or transmits) information in a form readable by a machine (e.g., a computer). For example, a machine-readable medium includes read only memory (ROM); random access memory (RAM); magnetic disk storage media; optical storage media; flash memory devices; DVD's, electrical, optical, acoustical or other form of propagated signals (e.g., carrier waves, infrared signals, digital signals, EPROMs, EEPROMs, FLASH, magnetic or optical cards, or any type of media suitable for storing electronic instructions. Slower mediums could be cached to a faster, more practical, medium.

P-0045[0045]FIG. 9 illustrates a block diagram of an exemplary computer system that may use an embodiment of the cache-line reuse-buffer. In one embodiment, computer system <b>900</b> comprises a communication mechanism or bus <b>911</b> for communicating information, and an integrated circuit component such as a processor <b>912</b> coupled with bus <b>911</b> for processing information. One or more of the components or devices in the computer system <b>900</b> such as the processor <b>912</b> may contain a cache and use the cache line buffer.

P-0046[0046] Computer system <b>900</b> further comprises a random access memory (RAM), or other dynamic storage device <b>904</b> (referred to as main memory) coupled to bus <b>911</b> for storing information and instructions to be executed by processor <b>912</b>. Main memory <b>904</b> also may be used for storing temporary variables or other intermediate information during execution of instructions by processor <b>912</b>. In an embodiment, the Processor <b>912</b> may include a microprocessor, but is not limited to a microprocessor, such as a Pentium, PowerPC, etc.

P-0047[0047] Computer system <b>900</b> also comprises a read only memory (ROM) and/or other static storage device <b>906</b> coupled to bus <b>911</b> for storing static information and instructions for processor <b>912</b>, and a mass storage memory <b>907</b>, such as a magnetic disk or optical disk and its corresponding disk drive. Mass storage memory <b>907</b> is coupled to bus <b>911</b> for storing information and instructions.

P-0048[0048] Computer system <b>900</b> may further be coupled to a display device <b>921</b>, such as a cathode ray tube (CRT) or liquid crystal display (LCD), coupled to bus <b>911</b> for displaying information to a computer user. An alphanumeric input device (keyboard) <b>922</b>, including alphanumeric and other keys, may also be coupled to bus <b>911</b> for communicating information and command selections to processor <b>912</b>. An additional user input device is cursor control device <b>923</b>, such as a mouse, trackball, trackpad, stylus, or cursor direction keys, coupled to bus <b>911</b> for communicating direction information and command selections to processor <b>912</b>, and for controlling cursor movement on a display device <b>912</b>.

P-0049[0049] Another device that may be coupled to bus <b>911</b> is a hard copy device <b>924</b>, which may be used for printing instructions, data, or other information on a medium such as paper, film, or similar types of media. Furthermore, a sound recording and playback device, such as a speaker and/or microphone (not shown) may optionally be coupled to bus <b>911</b> for audio interfacing with computer system <b>900</b>. Another device that may be coupled to bus <b>911</b> is a wired/wireless communication capability <b>925</b> to communication to a phone.

P-0050[0050] Some portions of the detailed descriptions above are presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of steps leading to a desired result. The steps are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

P-0051[0051] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise as apparent from the above discussions, it is appreciated that throughout the description, discussions utilizing terms such as “processing” or “computing” or “calculating” or “determining” or “displaying” or the like, refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers, or other such information storage, transmission or display devices.

P-0052[0052] While some specific embodiments of the invention have been shown the invention is not to be limited to these embodiments. For example, most functions performed by electronic hardware components may be duplicated by software emulation. Thus, a software program written to accomplish those same functions may emulate the functionality of the hardware components in input-output circuitry. In an embodiment, if some or all of the content in same cache line will be used in two consecutive cycles, the control logic may send a signal to the cache-line reuse-buffer or some other component to ensure that the instruction cache is not accessed. The invention is to be understood as not limited by the specific embodiments described herein, but only by scope of the appended claims.