Calibration of memory circuits

BACKGROUND OF THE INVENTION

P-0001[0001] This invention relates to the calibration of memory circuits in a computer system. More particularly, this invention relates to the calibration of memory circuits to reduce spurious data during memory circuit accesses.

P-0002[0002] Computer systems that incorporate memory circuits are generally designed to ensure high accuracy of the memory circuits because faulty memory circuits lead to malfunctioning computer systems. A common obstacle to proper functioning of memory circuits is lengthy transitional delay between ones and zeroes, as well as clock skew in the case of clocked memories. Spurious data occurs when ones are read as zeroes, and vice-versa.

P-0003[0003] Memory circuits increasingly incorporate variable drive buffers to drive data onto external busses. These buffers may be programmed to drive different levels of current and voltage in order to, for example, accommodate varying environmental conditions such as bus loading and ambient temperature. The adjustability of memory circuit output parameters can be used to reduce the probability of spurious data. One metric of memory circuit data quality is based on the measured data eye pattern of the memory circuit. Thus, it may be desirable to calibrate memory circuit output parameters based on measurements of the observed data eye patterns of memory circuit outputs.

SUMMARY OF THE INVENTION

P-0004[0004] It is an object of this invention to provide a method to calibrate memory circuit output parameters based on measurements of the observed data eye patterns of memory circuit outputs. Memory circuits that include outputs with adjustable parameters (e.g., output voltage levels, output current levels, and signal strength levels) are coupled to a memory controller that can write and read data into the memory circuits. Data is written into memory circuits by the memory controller, which then reads back the same data. When the data is read back, the dimensions of the resultant data eye pattern are measured by the memory controller with circuits such as capture registers.

P-0005[0005] The memory controller measures the data eye pattern of the memory circuit outputs with the parameters of the memory circuit adjusted to different settings. Various approaches are then taken to selecting appropriate settings for these parameters based on the observed data eye patterns. For example, a memory circuit output parameter may be adjusted to the setting that corresponds to the widest measured data eye pattern.

BRIEF DESCRIPTION OF THE DRAWINGS

P-0006[0006] The above and other objects and advantages of the invention will be apparent upon consideration of the following detailed description, taken in conjunction with the accompanying drawings, in which like reference characters refer to like parts throughout, and in which:

P-0007[0007]FIG. 1 is a diagram of a typical data eye observed on an oscilloscope;

P-0008[0008]FIG. 2 is a block diagram of a typical computer system;

P-0009[0009]FIG. 3 is a flow chart of a preferred embodiment of a computer system initialization process according to the present invention; and

P-0010[0010]FIG. 4 is a flow chart of a preferred embodiment of process for selection of V_OH/V_OLlevels in accordance with the present invention.

DETAILED DESCRIPTION OF THE INVENTION

P-0011[0011] The present invention provides a method for calibrating memory circuits that include adjustable output parameters. Examples of typical memory circuit output parameters include output voltage levels, output current level, and signal strength levels. By measuring the data eye width patterns at each setting of memory circuit output parameters, and selecting settings for these parameters that correspond to desirable data eye width patterns, the incidence of spurious data output from memory circuits can be reduced.

P-0012[0012] Calibration may be performed when memory circuits are first initialized and before they are put into operation. For example, in typical PC (Personal Computer) applications, calibration of memory circuits may take place when the computer system initializes. For PC applications, initialization routines are generally stored in its BIOS (Basic Input/Output System). The BIOS can be stored in a boot ROM (Read Only Memory) such as flash memory, which is not part of the memory circuits that are to be tested. Self-test and calibration routines are often performed on dynamic memory circuits such as DRAMs (Dynamic Random Access Memories) during execution of the BIOS so that memory circuits can be programmed to operate with their optimal operating parameters before they are used.

P-0013[0013] The quality of synchronous digital signals output by memory circuits can be monitored by observing the “data eye” patterns formed by the digital signals. When the outputs of any digital synchronous circuit transition between ones and zeroes and these transitions are captured on an oscilloscope, each trace can be overlapped over a previous trace. The resulting overlapping traces resemble a series of eyes, hence “data eye” patterns.

P-0014[0014] An illustrative data eye pattern is shown in FIG. 1. Diagram <b>100</b> shows an oscilloscope diagram with four waveforms <b>102</b>, <b>104</b>, <b>106</b>, and <b>108</b>. The oscilloscope can be set to observe the voltage of an input signal to the oscilloscope and to “trigger”, i.e., to start capturing the waveform of the input signal on the oscilloscope once the input signal is at a specific voltage, V_TRIGGER. The input signal is displayed as a waveform on the oscilloscope such that the point at which the input signal crosses the voltage V_TRIGGERis aligned against a specific time, t_TRIGGER, on the time axis of the oscilloscope. As shown in diagram <b>100</b>, waveforms <b>102</b>, <b>104</b>, <b>106</b>, and <b>108</b> are aligned to t_TRIGGERon the time axis when each waveform crosses the V_TRIGGERvoltage level.

P-0015[0015] As shown in FIG. 1, a data eye pattern is formed by the contours of waveforms <b>102</b>, <b>104</b>, <b>106</b>, and <b>108</b>. The size of the perceived data eye depends on the selection of waveforms that form the contours of the data eye. For example, a first data eye can be perceived by selecting waveforms <b>104</b> and <b>106</b> to be its contours. A second data eye can be perceived by selecting waveforms <b>102</b> and <b>108</b> to be its contours. The first data eye is narrower in width than the second data eye.

P-0016[0016] When a digital circuit outputs a logical one signal, the signal is conventionally perceived to be a logical one if it is above a first threshold voltage (V_IH). When a digital circuit outputs a logical zero signal, the signal is conventionally perceived to be a logical zero if it is below a second threshold voltage (V_IL). One metric of synchronous digital signal quality is based on the amount of time required for a synchronous digital signal to reach these threshold levels and the amount of time that the signal stays above (or below) these threshold levels when the signal is meant to be at that level for a clock cycle. This metric is represented by the width of the data eye formed by the signal under observation.

P-0017[0017] Another metric of signal quality is based on the margin by which a digital circuit output exceeds threshold voltage V_IHwhen outputting a logical zero signal. This metric may also include an observation of the margin by which a digital circuit output remains below threshold voltage V_IL. This metric of synchronous digital signal quality is represented by the height of the data eye formed by the signal under observation.

P-0018[0018] As illustrated in FIG. 1, waveform <b>102</b> reaches V_IHbefore waveform <b>104</b> and waveform <b>108</b> reaches V_ILbefore waveform <b>106</b>. Moreover, waveform <b>102</b> and waveform <b>108</b> stay above and below the V_IHand V_ILlevels respectively for a longer period of time than waveforms <b>104</b> and <b>106</b>. Therefore, waveforms <b>102</b> and <b>108</b> are of better quality than waveforms <b>104</b> and <b>106</b>. Coincidentally, the eye formed by waveforms <b>102</b> and <b>108</b> is wider than that formed by waveforms <b>104</b> and <b>106</b>. Therefore, the quality of a digital signal can be measured through observation of the data eyes formed by the observed waveforms of the digital signal.

P-0019[0019] Memory circuits with adjustable output parameters are calibrated in accordance with the present invention by adjusting the parameters based on the widths of the observed data eye patterns formed by the output signals of the memory circuit. For example, the width and height of the data eye are measured for different signal strength settings of the memory circuit outputs under calibration and the memory circuit is then set to the signal strength setting corresponding to the largest data eye observed. Alternatively, the memory circuit outputs are observed over a period of time for each signal strength setting, and the average data eye width and height are computed over the same period of time. The memory circuit is then set to the signal strength setting corresponding to the widest average data eye width or highest average data eye height. For clarity, calibration of memory circuits based on observed data eye patterns according to the invention is described in the following discussion primarily in the context of observing data eye widths instead of data eye heights. One skilled in the art will appreciate that the present invention includes calibration of memory circuits based on observed data eye heights and data eye widths.

P-0020[0020] If the signal strength of each memory circuit output can be individually adjusted, the signal strength setting may be selected that corresponds to the widest data eye or widest average data eye measured for each memory circuit output. Otherwise, data eye width measurements may be taken for all memory circuit outputs or any suitable subset thereof and the average of the data eye widths over all measured circuit outputs computed for each signal strength setting. The signal strength setting corresponding to the widest of the average data eye widths over all measured circuit outputs may then be selected.

P-0021[0021] Data vectors can be stored in the boot ROM and accessed by the memory controller, which then writes and reads back the data vectors to and from the memory circuits at different signal strength settings. Alternatively, data vectors can be pre-stored in the memory circuits, and can be read back by the memory controller. In yet another approach, the memory controller may generate the data vectors that are to be written to the memory circuits. The memory circuit then observes the data eye at each signal strength setting. Depending on the nature of the memory circuit under calibration, the signal strength may be a function of a specific programmable setting or a function of any combination of memory circuit output voltage or current level settings. If the signal strength is directly programmable through a specific programmable setting, the memory controller can measure the width of the data eye at different settings for signal strength. If the signal strength is a function of output voltage or current level settings, the memory controller can observe the data eye for different settings of output voltage or current level or any combination thereof. Calibration may be performed by hardware or software that writes and reads back data vectors to and from the memory circuits for different settings of various memory circuit parameters.

P-0022[0022] FIGS. <b>2</b>-<b>4</b> relate to calibration of a particular type of memory circuits with configurable memory circuit parameters such as V_OH(Voltage Output High) levels and V_OL(Voltage Output Low) levels. One type of memory circuit with configurable memory circuit parameters that can be calibrated according to the present invention is DDRII SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory). For convenience, adjustment of memory circuit output parameters will be discussed in connection with adjustment of V_OHand V_OLlevels. Adjustment of other memory circuit parameters (e.g., signal strength settings, output current settings, and data timing settings) can be performed based on data eye width measurements in accordance with the present invention.

P-0023[0023] During initialization of the memory controller, the memory controller can fetch data vectors, for example, pseudo-random data vectors, from the boot ROM, and write data based on these vectors into the memory circuits. The data is then read back from the memory circuits while the memory controller monitors the width of the resulting data eye patterns. In one approach, the memory controller first steps through all possible V_OHlevels while keeping the V_OLlevel fixed and monitoring the width of the resulting data eye pattern for each V_OHlevel. The memory controller can store the widest data eye width for a particular V_OHlevel and V_OLlevel, or compute and store the average data eye width for a particular V_OHlevel and V_OLlevel. The memory controller then changes the V_OLlevel and steps through all possible V_OHlevels while keeping the V_OLlevel fixed and monitoring the width of the resulting data eye pattern for each V_OHlevel. The following table illustrates the tabulation of data eye widths obtained using this approach. For every combination of V_OHand V_OLlevels tested by the memory controller, the memory controller stores either the widest data eye width or widest average data eye width associated with each combination. The memory controller can then set the V_OHand V_OLlevels that correspond to the widest data eye width. <tables id="TABLE-US-00001" num="1"><table frame="none" colsep="0" rowsep="0"><tgroup align="left" colsep="0" rowsep="0" cols="2"><colspec colname="OFFSET" colwidth="28PT" align="left" /><colspec colname="1" colwidth="189PT" align="center" /><tbody valign="top"><row><entry /><entry /></row><row><entry /><entry namest="OFFSET" nameend="1" align="center" rowsep="1" /></row><row><entry /><entry>V_OH</entry></row></tbody></tgroup><tgroup align="left" colsep="0" rowsep="0" cols="5"><colspec colname="1" colwidth="28PT" align="center" /><colspec colname="2" colwidth="42PT" align="center" /><colspec colname="3" colwidth="56PT" align="center" /><colspec colname="4" colwidth="42PT" align="center" /><colspec colname="5" colwidth="49PT" align="center" /><tbody valign="top"><row><entry>V_OL</entry><entry>V_OH1</entry><entry>V_OH2</entry><entry>V_OH3</entry><entry>V_OH4</entry></row><row><entry namest="1" nameend="5" align="center" rowsep="1" /></row><row><entry>V_OL1</entry><entry>Eye width₁₁</entry><entry>Eye width₂₁</entry><entry>Eye width₃₁</entry><entry>Eye width₄₁</entry></row><row><entry>V_OL2</entry><entry>Eye width₁₂</entry><entry>Eye width₂₂</entry><entry>Eye width₃₂</entry><entry>Eye width₄₂</entry></row><row><entry>V_OL3</entry><entry>Eye-width₁₃</entry><entry>Eye width₂₃</entry><entry>Eye width₃₃</entry><entry>Eye width₄₃</entry></row><row><entry>V_OL4</entry><entry>Eye width₁₄</entry><entry>Eye width₂₄</entry><entry>Eye width₃₄</entry><entry>Eye width₄₄</entry></row><row><entry namest="1" nameend="5" align="center" rowsep="1" /></row></tbody></tgroup></table></tables>

P-0024[0024]FIG. 2 shows a typical computer system <b>200</b>.

P-0025[0025] Microprocessor <b>202</b> is preferably coupled to memory controller <b>204</b> with system bus <b>212</b>. In some computer systems, memory controller <b>204</b> is part of microprocessor <b>202</b>. Memory controller <b>204</b> is preferably coupled to boot ROM <b>214</b> as well as memory circuits <b>206</b>, <b>208</b>, and <b>210</b>. BIOS instructions and data can be stored on boot ROM <b>214</b> and can be accessed by microprocessor <b>202</b> through memory controller <b>204</b> for initialization purposes. Memory circuits <b>206</b>, <b>208</b>, and <b>210</b> are preferably coupled to memory controller <b>204</b> with unidirectional command bus <b>216</b> and bidirectional data bus <b>218</b>.

P-0026[0026]FIG. 3 shows illustrative process <b>300</b> that may be used to measure the data eye at different V_OHand V_OLlevels. At step <b>302</b>, microprocessor <b>202</b> powers up and initializes. At step <b>304</b>, BIOS instructions can be accessed from boot ROM <b>214</b> by memory controller <b>204</b>. At step <b>306</b>, pseudo-random data vectors can be read from boot ROM <b>214</b>. These data vectors can be written into memory circuits <b>206</b>, <b>208</b>, and <b>210</b> by memory controller <b>204</b> at step <b>308</b>. At step <b>310</b>, the same data vectors are read back from memory circuits <b>206</b>, <b>208</b>, and <b>210</b>, and the data eye widths are obtained by memory controller <b>204</b> based on values of data vectors that are read back. During a first pass through this process, memory controller <b>204</b> can be initialized with default settings for V_OHand V_OLlevels.

P-0027[0027] At step <b>310</b>, the data eye width measurements are made at a specific V_OHand V_OLlevels. At step <b>314</b>, memory controller <b>204</b> can change the V_OHor V_OLlevel or both levels. The settings can be changed automatically by memory controller <b>204</b>. Alternatively, the settings can be changed based on data read from the boot ROM or any other suitable source by memory controller <b>204</b>.

P-0028[0028] Process <b>300</b> can be repeated from step <b>306</b> with different settings for V_OHand V_OLlevels. When it is determined that data eye width measurements have been obtained for all suitable combinations of V_OHor V_OLlevels at step <b>312</b>, the V_OHand V_OLlevels can be set to the settings that correspond to the widest data eye or widest average eye pattern at step <b>316</b>. By setting V_OHand V_OLlevels to those that correspond to the widest data eye pattern (or widest average eye pattern), the probability that the memory circuit thus calibrated will provide spurious data may be reduced under operating conditions.

P-0029[0029] In one embodiment, the width of the data eye can be measured by providing a clock signal to the memory circuit for read accesses (“read clock”) and observing the data that is read from the memory circuit with an observation circuit that is clocked by a phase-adjustable clock signal. The phase-adjustable clock is phase adjusted in small increments. It has a range of adjustment greater than or equal to the read data clock width. It is then capable of sweeping the entire read data eye. The phase-adjustable clock can be initially set to be in phase with the read clock. The memory controller then initiates read accesses from the memory circuit under calibration. The observation circuit records a “pass” (i.e., when the data read from a particular memory circuit location matches the data written to that location) and a “failure” (i.e., when the data read from a particular memory location does not match the data written to that location). The phase difference between the phase-adjustable clock and the read clock can be incrementally increased, while the memory controller continues to initiate read accesses from the memory circuit under calibration. At each increment of the phase difference, the observation circuit records the numbers of passes and failures. As the phase difference between the two clocks increases, the observation circuit will eventually observe a failure. As the phase difference between the two clocks approaches 360 degrees, the observation circuit will start to record passes again. In this embodiment, the data eye width is equal to the length of time (in phase difference increments) that the observation circuit records passes.

P-0030[0030] Data eye width measurements relevant to the invention can be taken when the memory circuit outputs transition from: (i) a logic-0 to a logic-1 and from a logic-1 to a logic-0; or (ii) a logic-1 to a logic-0 and from a logic-0 to a logic-1, during a single clock period. For the first type of transition, only the “top” half of the data eye is measured. For the second type of transition, only the “bottom” half of the data eye is measured. Alternatively, both the “top” and “bottom” of the data eye can be measured, and the average of the two types of measurements may be used to calibrate memory circuits in accordance with invention. This last approach to measuring data eye widths is illustrated in FIG. 4.

P-0031[0031]FIG. 4 shows illustrative process <b>400</b> for measuring and computing average data eye widths. At step <b>402</b>, memory controller <b>204</b> first obtains data eye widths based on logic-1 to logic-0 followed by logic-0 to logic-1 transitions (within a clock period). These widths can be averaged to obtain an average data eye width for this pattern of transitions at step <b>404</b>. Memory controller <b>204</b> can obtain data eye widths for logic-0 to logic-1 followed by logic-1 to logic-0 transitions (within a clock period) at step <b>406</b>. These widths can also be averaged to obtain an average data eye width for this pattern of transitions at step <b>408</b>. Steps <b>402</b> to <b>404</b> and steps <b>406</b> to <b>408</b> can be repeated for all suitable combinations of V_OHand V_OLlevels and can be performed in parallel or sequentially. When average data eye widths for all suitable combinations of V_OHand V_OLlevels are known, memory controller <b>204</b> can find the particular combination of V_OHand V_OLlevels that corresponds to the highest average data eye width at step <b>410</b>.

P-0032[0032] Alternatively, V_OHand V_OLlevels may be adjusted based on the narrowest data eye width observed as opposed to average data eye width. It may be desirable to find the poorest quality data eye (i.e., narrowest data eye width) observed for each combination of V_OHand V_OLlevels because the narrowest data eye width may represent worst case timing for each combination of V_OHand V_OLlevels. The memory circuit can thus be calibrated with the combination of V_OHand V_OLlevels that corresponds to the widest of the narrowest data eye widths observed for each combination of V_OHand V_OLlevels.

P-0033[0033] Thus it is seen that memory circuits can be calibrated based on measuring data eye patterns. One skilled in the art will appreciate that the present invention can be practiced by other than the described embodiments, which are presented for purposes of illustration and not of limitation, and the present invention is limited only by the claims which follow.