Wireless data communications using FIFO for synchronization memory

CROSS-REFERENCE TO RELATED APPLICATIONS

0001[0001] This application is a divisional of patent application Ser. No. 09/593,583, filed Jun. 12, 2000, the content of which is incorporated herein by reference.

BACKGROUND

[0002] 1. Field of the Invention

[0003] This invention relates to wireless communication and more particularly to an apparatus that receives transmission of data synchronized to a clock that is out of phase with the clock of the apparatus.

[0004] This invention also relates to microprocessor system architecture, and more particularly to a microprocessor architecture that allows read-only memory (ROM) microcode to be effectively altered or enhanced without the need to reprogram or replace the ROM.

[0005] 2. Description of Related Art

[0006] Bluetooth is the name of a well known and open technical specification for wireless communication of data and voice. Bluetooth allows the replacement of very short range cables (wires) now used to connect one device to another with one universal short-range radio link; for example, a computer can thereby communicate with its printer via a radio link instead of a cable. Bluetooth is characterized by operation in the 2.4 GHz and at variable transmission power depending on the distance between devices. For example, for a power class 2 Bluetooth device, the transmission power ranges from 1 mW to 2.5 mW. Bluetooth also allows computing devices to connect to a communicating device via a radio link. For example, a computer can communicate with a nearby cell phone via a radio link to access the Internet. Bluetooth units (radios) connect to each other in “piconets”, which are formed by a master unit connecting up to seven slave units. In a piconet, the slave units are synchronized to the master unit's clock and hopping sequence. See “Specification of the Bluetooth System-Core v l.Ob” available from the Bluetooth Special Interest Group at its web site.

[0007] A typical Bluetooth conforming radio includes an RF (radio frequency) circuit and a baseband circuit. The RF circuit receives a frequency modulated electromagnetic signal (i.e., FM signal) carrying data synchronized to the clock signal (“external clock”) of another Bluetooth radio. The baseband circuit includes a demodulator circuit that extracts the data and the external clock signal from the FM signal (symbol timing recovery). The baseband circuit also includes a PLL (phase lock loop) circuit that synchronizes the phase of the internal clock of the baseband circuit to the phase of the external clock to allow data processing circuits of the baseband to process the extracted data. The PLL circuit is necessary because even if the internal clock and the external clock may have substantially the same frequency, they may not have the same phase. Furthermore, interference to the FM signal as it travels through the air may also distort the representation of the frequency of the external clock in the FM signal.

[0008] A microprocessor is a central processing unit (CPU) enclosed in one integrated circuit (IC) package. Because of their small size and low cost, microprocessors have revolutionized digital system design technology, giving the designer the capability to create structures that were previously uneconomical. Microprocessors are used in a wide variety of applications. They can function as a CPU in a general purpose computer or as a processor unit in a special purpose, automated system.

[0009] Microprocessor systems usually incorporate several different types of memory devices to hold data for processing and instructions for system control. Memory devices come in a wide variety of forms. Two of the more common forms are generally referred to as “read-only memory” (ROM) and “random access memory” (RAM). In its simplest form, sometimes called “mask-programmed”, a ROM memory device is manufactured with fixed contents. The binary information stored in the ROM is made permanent during the hardware production of the unit and cannot subsequently be altered. Such a ROM memory unit performs the read operation only; it does not have a write capability. ROM is most often used to hold microcode, the lowest level instructions that directly control a microprocessor.

[0010] By contrast, a RAM is a data storage device that can perform both the read and write function. A system CPU uses its RAM as a storage area for data, calculation results, and program instructions, drawing on this storage as necessary to perform the tasks required by programs. Its binary contents can easily be changed during operation and its stored data is typically erased or lost when the device incorporating it is powered off. Part of the initial “power-up” or boot routine for microprocessor systems includes the loading of desired or necessary code into RAM according to the system design.

[0011] Microprocessor systems may also incorporate some type of “non-volatile” memory, such as a hard-disk. Like RAM, such memory can usually be read or written to, but unlike RAM its content is preserved until over-written, even without system power.

[0012] More recent varieties of ROM provide for some limited programming capability after manufacture. PROM (“programmable read-only memory”) devices can be programmed by the end user, but only once. EPROM (“erasable programmable read-only memory”) can be erased and then reprogrammed, but must be removed from the system to do so. EEPROM (“electronic erasable read-only memory”) can be erased and programmed electrically some limited number of times with standard supply voltages while in the circuit. However, such devices come with increased cost and limitations of their own. For example, EPROM must be removed from the system to be reprogrammed, and EEPROM must be erased and reprogrammed in its entirety, not selectively. For many processing systems, especially those used to perform set, repetitive tasks, it is desirable to use the cheapest and simplest (mask-programmed) ROM, with minimal reliance on more expensive RAM or other types of memory devices.

[0013] However, in even the simplest microprocessor system it may be desirable to alter the execution of the ROM microcode to, for example, correct errors in the code or add new capabilities to it. The disclosed invention allows for alterations in the processing of ROM microcode without incurring the added expense and complexity of integrating some form of programmable ROM into the system.

SUMMARY

[0014] In accordance with one aspect of the invention, a wireless device (e.g. radio) includes a receiver coupled to a first-in first-out memory device (FIFO). The, e.g. RF receiver includes a RF circuit that receives RF signals via an antenna, and a demodulator circuit that decodes the RF signals to data signals and recovered clock signals. The RF receiver stores the data signals into the FIFO using the recovered clock signals as write signals. In one implementation, a host device reads the data out from the FIFO with read signals synchronized to the system clock of the host device. In one variation, the write signals and the read signals are of similar frequencies. Thus, the host device can read the data received as RF signals without synchronizing its system clock to the recovered clock signals.

[0015] In another embodiment, a data processing circuit reads the data out from the FIFO with read signals synchronized to the system clock of the data processing circuit. In one implementation, the write signals and the read signals are of similar frequencies. Thus, the data processing circuit can process the data received as RF signals without synchronizing its system clock to the recovered clock signals. In one variation, the host device is coupled to the data processing circuit to receive the processed data.

[0016] Accordingly, the function performed in the prior and by PLL circuits are performed by FIFOs so that data received as RF signals may be processed by circuits without synchronizing their system clock to the recovered clock signals.

[0017] In accordance with another aspect of the invention, a microprocessor system architecture allows for the selective execution of programmed ROM microcode or, alternatively, RAM microcode if there has been a correction or update made to the ROM microcode originally programmed into the system. Patched or updated RAM microcode is utilized or executed only to the extent of changes to the ROM microcode, otherwise the ROM microcode is executed in its normal fashion.

[0018] When a patch is received, it is loaded into system RAM along with instructions or other appropriate signals to direct the execution of the patched or updated microcode from RAM instead of the existing ROM microcode. Those skilled in the art will appreciate and understand that a variety of techniques can be utilized to direct the execution of patched or updated RAM microcode rather than corresponding ROM microcode, only a few of which are discussed in some detail below.

BRIEF DESCRIPTION OF THE DRAWINGS

0019[0019]FIG. 1 illustrates, in a block diagram, a wireless network involving wireless devices.

0020[0020]FIG. 2A illustrates, in a block diagram, a wireless device of FIG. 1 in accordance with one embodiment of the invention.

0021[0021]FIG. 2B illustrates, in a block diagram, a radio frequency (RF) receiver of FIG. 2A.

0022[0022]FIG. 2C illustrates, in a block diagram, a first-in first-out memory device (FIFO) of FIG. 2A.

0023[0023]FIG. 2D illustrates, in a timing diagram, the input and output signals from the FIFO of FIG. 2C in accordance with one embodiment of the invention.

0024[0024]FIG. 3A illustrates, in a block diagram, a wireless device of FIG. 1 in accordance with another embodiment of the invention.

0025[0025]FIG. 3B illustrates, in a block diagram, a data processing circuit of FIG. 3A.

0026[0026]FIG. 3C illustrates, in a timing diagram, the input and output signals from a host interface of FIG. 3B in accordance with one embodiment of the invention.

0027[0027]FIGS. 4 and 4A illustrate alternative embodiments of a memory architecture in which main microcode ROM and main microcode RAM share a common memory address area, along with a “select” RAM bit used to control the selection of main microcode ROM or main microcode RAM for execution. In FIG. 4A, all microcode ROM is associated with an area of microcode RAM. In FIG. 4B, all microcode ROM shares a common address with microcode RAM, but additional address areas for microcode RAM are allocated to accept new microcode.

0028[0028]FIG. 5 illustrates a memory architecture in which main microcode ROM is mapped to a common memory address area shared by microcode ROM routines and corresponding microcode RAM routines, along with a “select” RAM bit used to control the selection of microcode ROM routines or microcode RAM routines.

0029[0029]FIGS. 6A, 6B, and <b>6</b>C illustrate a memory architecture in which the ROM is divided into main portion and a “routine” portion consisting of more detailed and lengthy instruction. A specified RAM bit is used to control the selection of main microcode ROM or main microcode RAM, and associated “routine” ROM or patches loaded into RAM. FIG. 6A illustrates the selection of microcode ROM in the absence of any patches. FIG. 6B illustrates the selection of patch microcode RAM when present, and FIG. 6C illustrates the selection of patch microcode RAM when new routines are available.

0030[0030]FIGS. 7A, 7B, and <b>7</b>C illustrate a memory architecture in which a specified RAM bit is used to control the selection of main microcode ROM or patch microcode RAM. FIG. 7A illustrates the selection of main microcode ROM in the absence of any changes. FIG. 7B illustrates the selection of patch microcode RAM when changes are present, and FIG. 7C illustrates the selection of patch microcode RAM when new instructions are present.

0031[0031]FIGS. 8A, 8B, and <b>8</b>C illustrate a memory architecture in which an “index” method is used to select the execution of ROM or RAM microcode as desired. FIG. 8A shows how ROM routines are mapped into RAM for execution in the absence of any patches or updates. FIG. 8B illustrates how RAM-mapped ROM routines are directed to patch microcode RAM for execution when existing RAM microcode is modified. FIG. 8C illustrates how new microcode routines are executed.

0032[0032]FIG. 9 is a block diagram showing the functional implementation of the memory architecture illustrated in FIG. 4.

0033[0033]FIG. 10 is a block diagram showing the functional implementation of the memory architecture illustrated in FIG. 5.

0034[0034]FIG. 11 is a block diagram showing the functional implementation of the memory architecture illustrated in FIGS. 6A, 6B, and <b>6</b>C.

0035[0035]FIG. 12 is a block diagram showing the functional implementation of the memory architecture illustrated in FIGS. 7A, 7B, and <b>7</b>C.

0036[0036]FIG. 13 is a block diagram showing the functional implementation of the memory architecture illustrated in FIGS. 8A, 8B, and <b>8</b>C.

0037[0037]FIG. 14 is a programming flow chart showing a microcode patch initialization routine.

DETAILED DESCRIPTION

0038[0038] A wireless network <b>100</b> (FIG. 1) includes a plurality of wireless devices <b>102</b>-<b>1</b>, <b>102</b>-<b>2</b> . . . <b>102</b>-<i>i </i>. . . <b>102</b>-<i>n </i>(<b>2</b>≦i≦n). Wireless network <b>100</b> includes radio frequency (RF) networks, optical networks, and infrared networks. Wireless network <b>100</b> is, for example, a Bluetooth piconet where wireless device <b>102</b>-<b>1</b> is a master Bluetooth radio and wireless devices <b>102</b>-<b>2</b> to <b>102</b>-<i>n </i>are slave Bluetooth radios. As one skilled in the art understands, a Bluetooth piconet can form part of a larger Bluetooth scatternet.

0039[0039] In accordance with one aspect of the invention hereafter referred to as “thin baseband/host-based”, wireless device <b>102</b>-<i>i </i>(FIG. 2A) performs radio and baseband modulation functions in circuitry. A host <b>220</b> performs all other baseband, link management, and protocol stack functions through software. Host <b>220</b> includes a high performance and low latency host processor (e.g., reduced instruction-set computing processors) capable of handling time-critical link management functions. Such processors are available from ARM Ltd. of Cambridge, England, MIPS Technologies, Inc. of Mountain View, ARC Cores, Inc. of San Jose, and Tensillica of Santa Clara.

0040[0040] Wireless device <b>102</b>-<i>i </i>includes in one embodiment a conventional radio frequency (RF) receiver <b>202</b> (FIG. 2A) that receives RF signals from another Bluetooth radio via an antenna <b>204</b>. The RF signals carry data synchronized to the clock (“external clock”) of the another Bluetooth radio. RF receiver <b>202</b> decodes the RF signals to recover the data signals and the external clock signals (symbol timing recovery). RF receiver <b>202</b> respectively outputs the data signals and the external clock signals via respective lines <b>206</b> and <b>208</b>.

0041[0041] Lines <b>206</b> and <b>208</b> are respectively coupled to input terminals <b>210</b> and <b>212</b> of a conventional first-in first-out memory device (FIFO) <b>214</b>. FIFO <b>214</b> receives the external clock signals (“recovered clock signals”) as write signals from RF receiver <b>202</b>. When FIFO <b>214</b> receives an active recovered clock signal on terminal <b>212</b>, FIFO <b>214</b> writes the data signal received on terminal <b>210</b> from RF receiver <b>202</b> into one of its empty memory locations indicated by a write pointer. Thus, the input data to FIFO <b>214</b> is in response to the recovered clock signals.

0042[0042] When FIFO <b>214</b> is full, it outputs an active full signal via a line <b>216</b> coupled to a terminal <b>218</b> of host <b>220</b>. Conversely, when FIFO <b>214</b> is empty, it outputs an active empty signal via a line <b>222</b> coupled to a terminal <b>224</b> of host <b>220</b>. Host <b>220</b> reads the data stored in FIFO <b>214</b> by driving an active read signal via a line <b>226</b> coupled to input terminal <b>228</b> of FIFO <b>214</b>. In response to the active read signal on its terminal <b>228</b>, FIFO <b>214</b> outputs the data in the memory location pointed to by a read pointer via a line <b>230</b> coupled to an input terminal <b>232</b> of host <b>220</b>. Since the read signal from host <b>220</b> is synchronized with a clock <b>233</b> of host <b>220</b>, the data read out of FIFO <b>214</b> is synchronized with clock <b>233</b>.

0043[0043] In one embodiment, RF receiver <b>202</b> comprises a suitable RF circuit <b>234</b> (FIG. 2B) that receives the FM signals transmitted by other Bluetooth radio(s). For a description of one embodiment of RF circuit <b>234</b>, see U.S. patent application Ser. No. 09/591,925, filed Jun. 12, 2000, and U.S. patent application Ser. No. 09/592,016, filed Jun. 12, 2000, the contents of which are incorporated by reference herein in their entirety. Another suitable embodiment of RF circuit <b>234</b> is Radio Module PBA31 301 from Ericsson.

0044[0044] RF circuit <b>234</b> outputs the RF signals via a line <b>236</b> coupled to a terminal <b>238</b> of a suitable demodulator circuit <b>240</b>. Demodulator circuit <b>240</b> extracts the data signals and the recovered clock signals from the RF signals. Demodulator circuit <b>240</b> outputs the data signals and the recovered clock signals via respective lines <b>206</b> and <b>208</b>. Demodulator circuit <b>240</b> is, for example in one embodiment, implemented by Verilog source code listed in Appendix A. Another example of a suitable demodulator is modeled by C source code listed in Appendix B. One skilled in the art can translate the C source code to Verilog source code to synthesize a suitable demodulator.

0045[0045] In one embodiment, FIFO <b>214</b> includes a random access memory (RAM) <b>242</b> (FIG. 2C) that receives data on a terminal <b>243</b> coupled to line <b>206</b>, write signals (i.e., recovered clock signals) on a terminal <b>244</b> coupled to line <b>208</b>, and write addresses on a terminal <b>245</b> coupled to a line <b>246</b> of a counter (write pointer) <b>248</b>. RAM <b>242</b> stores the data (e.g., data <b>267</b> in FIG. 2D) received on a terminal <b>243</b> in the write address (e.g., address <b>268</b> in FIG. 2D) indicated by counter <b>248</b> each time RAM <b>242</b> receives an active write signal (e.g., signal <b>266</b> in FIG. 2D) on terminal <b>243</b>. Counter <b>248</b> increments the write address each time counter <b>248</b> receives an active write signal (e.g., signal <b>266</b> in FIG. 2D) on a terminal <b>250</b> coupled to line <b>208</b>. Counter <b>248</b> wraps around once it reaches the total number of memory locations in RAM <b>242</b> (e.g., the transition from address <b>269</b> to <b>270</b>).

0046[0046] RAM <b>242</b> further receives a read signal on a terminal <b>252</b> coupled to line <b>226</b>, and a read address on a terminal <b>253</b> coupled to a line <b>254</b> of a counter (read pointer) <b>255</b>. RAM <b>242</b> outputs the data (e.g., data <b>273</b> in FIG. 2D) in the memory address (e.g., address <b>271</b> in FIG. 2D) indicated by counter <b>255</b> each time RAM <b>242</b> receives an active read signal (e.g., signal <b>272</b> in FIG. 2D) on a terminal <b>252</b>. Similar to counter <b>248</b>, counter <b>255</b> increments the read address each time counter <b>255</b> receives an active read signal (e.g., signal <b>272</b> in FIG. 2D) on a terminal <b>258</b> coupled to line <b>226</b>. Counter <b>255</b> wraps around once it reaches the total number of memory locations in RAM <b>242</b> (e.g., transition from address <b>274</b> to <b>275</b> in FIG. 2D).

0047[0047] A counter <b>260</b> stores a numitem that indicates whether RAM <b>242</b> is full or empty. Counter <b>260</b> increments the numitem each time it receives an active write signal on a terminal <b>262</b> coupled to line <b>208</b>. Conversely, counter <b>260</b> decrements the numitem each time it receives an active read signal on a terminal <b>264</b> coupled to line <b>226</b>. For example, when two data signals (e.g., data <b>276</b> and <b>277</b> in FIG. 2D) are written into RAM <b>242</b> while only one data signal (e.g., data <b>278</b> that corresponds to data <b>276</b> in FIG. 2D) is read out of RAM <b>242</b>, numitem (e.g., numitem <b>279</b> in FIG. 2D) has a value of one. Counter <b>260</b> outputs an active full signal via line <b>216</b> when the numitem is equal to the total number of memory locations in RAM <b>242</b>. Conversely, counter <b>260</b> outputs an active empty signal (e.g., signal <b>280</b> in FIG. 2D) via line <b>222</b> when the numitem (e.g., numitem <b>281</b> in FIG. 2D) is equal to zero.

0048[0048] In one embodiment, host <b>220</b> read data out from FIFO <b>214</b> at relatively the same rate as data is being written into FIFO <b>214</b> (i.e., the frequency of the recovered clock). If data is being read out from FIFO <b>214</b> at substantially the same rate as data is being written into FIFO <b>214</b>, the size of FIFO <b>214</b> can be minimized (e.g., 2 bits). However, the write rate may not be as constant as the read rate because the write signal is synchronized to the recovered clock. Thus, the size of FIFO <b>214</b> is equal to the product of the (1) variation between the write rate and the read rate (e.g., frequency variation between the recovered clock and the system clock) and (2) the length of the data to be transmitted. Specifically, the minimum required size of the FIFO <b>214</b> between any two times (e.g., t₁and a t₂) may be defined as: <maths id="MATH-US-00001" num="1"><math overflow="scroll"><mrow><msubsup><mo>∫</mo><msub><mi>t</mi><mn>1</mn></msub><msub><mi>t</mi><mn>2</mn></msub></msubsup><mo></mo><mrow><mrow><mo>[</mo><mrow><mrow><msub><mi>F</mi><mi>in</mi></msub><mo></mo><mrow><mo>(</mo><mi>t</mi><mo>)</mo></mrow></mrow><mo>-</mo><mrow><msub><mi>F</mi><mi>out</mi></msub><mo></mo><mrow><mo>(</mo><mi>t</mi><mo>)</mo></mrow></mrow></mrow><mo>]</mo></mrow><mo></mo><mstyle><mtext> </mtext></mstyle><mo></mo><mrow><mo></mo><mi>t</mi></mrow></mrow></mrow></math><img file="US20030194982A1-20031016-M00001.TIF" id="EMI-M00001" he="21.12075" wi="216.027" img-format="tif" img-content="mf" /><attachments><attachment idref="MATHEMATICA-00001" attachment-type="nb" file="US20030194982A1-20031016-M00001.NB" /></attachments></maths>

0049[0049] where F_in(t) is the data rate into FIFO <b>214</b> as a function of time, and F_out(t) is the data rate out from FIFO <b>214</b> as a function of time. In one implementation, FIFO <b>214</b> is a four bit FIFO.

0050[0050] In another embodiment, host <b>220</b> reads the data from FIFO <b>214</b> in bursts because host <b>220</b> operates at a higher clock speed than the recovered clock. Host <b>220</b> can allow the bits to be stored in FIFO <b>214</b> and read the data out in a burst before FIFO <b>214</b> overflows.

0051[0051] FIFO <b>214</b> is, for example in one embodiment, implemented by Verilog source code listed in Appendix C. As one skilled in the art understands, FIFOs can be implemented in a variety of ways by flip-flops, registers, memory arrays, random access memory (RAM), and other similar components.

0052[0052] As described above, FIFO <b>214</b> allows host <b>220</b> to read data signals transmitted from another Bluetooth radio without retiming its clock to the external clock of the other Bluetooth radio. Thus, the prior art PLL circuit is replaced here with one embodiment by a FIFO <b>214</b> that is both simple and inexpensive to implement. Accordingly, a Bluetooth radio utilizing FIFO <b>214</b> offers a more efficient design than other Bluetooth radios that utilize PLL circuits to retime their clocks.

0053[0053] In accordance with another aspect of the invention hereafter referred to as “host-based”, wireless device <b>102</b>-<i>i </i>performs all radio, baseband, and time-critical link management functions in circuitry rather than in the host. Host <b>220</b> performs all non-time critical link management and protocol stack functions (in software). Host <b>220</b> includes a host processor such as an X<b>86</b> or <b>8051</b> based processor.

0054[0054] Wireless device <b>102</b>-<i>i </i>includes a data processing circuit <b>302</b> (FIG. 3A) that reads and processes the data from FIFO <b>214</b>. Data processing circuit <b>302</b> has terminals <b>318</b>, <b>324</b>, and <b>332</b> respectively coupled to lines <b>216</b>, <b>222</b>, and <b>230</b> of FIFO <b>214</b>. To read data from FIFO <b>214</b>, data processing circuit <b>302</b> drives an active read signal via a line <b>326</b> coupled to terminal <b>228</b> of FIFO <b>214</b>.

0055[0055] In one embodiment, data processing circuit <b>302</b> includes a conventional forward error correction (FEC) decoding circuit <b>336</b> (FIG. 3B) having input terminal <b>338</b> coupled to line <b>230</b>. FEC decoding circuit <b>336</b> uses correction bits embedded in the data to repair any error in the transmitted data received at terminal <b>338</b>. If there is no error, FEC circuit <b>336</b> removes the correction bits from the data stream. This is as set forth in the Bluetooth specifications. FEC circuit <b>336</b> outputs the data stream via a line <b>340</b> to input terminal <b>342</b> of a de-whitening circuit <b>344</b>.

0056[0056] Conventional de-whitening circuit <b>344</b> descrambles the data with a “whitening” word used to randomize the data from highly redundant patterns and to minimize DC bias in the packet. This is as set forth in the Bluetooth specifications. De-whitening circuit <b>344</b> outputs the data stream via a line <b>346</b> to input terminal <b>348</b> of a conventional cyclical redundancy check (CRC) circuit <b>350</b>. CRC circuit <b>350</b> detects data transmission error by performing CRC checking. CRC circuit <b>350</b> outputs the data stream via a line <b>352</b> to input terminal <b>354</b> of a suitable FIFO <b>356</b>.

0057[0057] FIFO <b>356</b> stores the data received from CRC circuit <b>350</b>. FIFO <b>356</b> outputs the data via a line <b>349</b> coupled to input terminal <b>357</b> of a host interface <b>359</b>. Host interface <b>359</b> reads data out from FIFO <b>356</b> (e.g., bits <b>370</b> to <b>377</b> in FIG. 3C) to an output line <b>330</b> coupled to terminal <b>232</b> of host <b>220</b> when host <b>220</b> outputs an inactive ready-to-receive signal (e.g., signal <b>378</b> in FIG. 3C) on a line <b>329</b> coupled to a terminal <b>361</b> of host interface <b>359</b>. Host interface <b>359</b> includes a start bit and an end bit (e.g., bits <b>379</b> and <b>380</b>, respectively, in FIG. 3C) at the start and the end of the data transmission to host <b>220</b>. Host interface <b>359</b> is, for example, coupled to a XR<b>16</b>C<b>850</b> UART (universal asynchronous receiver and transmitter) made by EXAR Corporation of Fremont, Calif., that forms part of host <b>220</b>.

0058[0058] A microcontroller <b>358</b> controls the data flow through FIFO <b>214</b>, FEC circuit <b>336</b>, de-whitening circuit <b>344</b>, CRC circuit <b>350</b>, FIFO <b>356</b>, and host interface <b>359</b>. (Microcontroller is not the host, which as in FIG. 3A is external to date processing circuit <b>302</b>.) To read data from FIFO <b>214</b> to FEC circuit <b>336</b>, microcontroller <b>358</b> drives an active read signal via a line <b>326</b> coupled to terminal <b>228</b> of FIFO <b>214</b>. Microcontroller <b>358</b> has terminals <b>360</b> and <b>362</b> respectively coupled to lines <b>216</b> and <b>224</b> of FIFO <b>214</b> to determine if FIFO <b>214</b> is full or empty. Microcontroller <b>358</b> may read data out from FIFO <b>214</b> at a constant rate or in bursts depending on the embodiment.

0059[0059] Microcontroller <b>358</b> also enables FEC circuit <b>336</b>, de-whitening circuit <b>344</b>, and/or CRC circuit <b>350</b> depending on the type of data received. Microcontroller <b>358</b> instructs FIFO <b>356</b> whether to accept or reject the data received from CRC <b>350</b> depending if FEC <b>336</b> or CRC <b>350</b> detects an error in the data. Microcontroller <b>358</b>, for example, executes microcode listed in Appendix D.

0060[0060] A clock source <b>364</b> provides clock signals to FEC circuit <b>336</b>, de-whitening circuit <b>344</b>, CRC circuit <b>350</b>, FIFO <b>356</b>, microcontroller <b>358</b>, and host interface <b>359</b>. Data processing circuit <b>302</b> is, for example, implemented by Verilog source code listed in Appendix F.

0061[0061] In accordance with yet another aspect of the invention hereafter referred as “stand alone”, wireless device <b>102</b>-<i>i </i>performs the radio, the base, and the link management functions in circuitry. Host <b>220</b> is not necessary in this aspect because data processing circuit <b>302</b> includes application specific circuitry that allows wireless device <b>102</b>-<i>i </i>to operate independently of a host. For example, wireless device <b>102</b>-<i>i </i>may be a wireless headset that allows a user to receive signals from another Bluetooth radio enabled device.

0062[0062] Although one aspect of the invention has been described with reference to particular embodiments, the description is only of examples and should not be taken as a limitation. For example, although the above disclosure refers to the Bluetooth specifications, the present method and apparatus may be used in other wireless applications where the data received is synchronized to a clock of similar frequency but out of phase with the internal clock. This is not limited to RF, but includes optical and infrared communications. Furthermore, radio <b>102</b>-<i>i </i>can be implemented as an integrated circuit (on a single chip) or as separate chips that can be coupled. Various other adaptations and combinations of features of the embodiments disclosed are within the scope of the invention as defined by the following claims.

0063[0063] As used herein, the term “patch” is intended to mean any correction, change, or alteration to the original microcode stored in a microprocessor system's read-only memory (ROM). The terms “patch” or “update” may also be used herein to refer to microcode developed after the original programming of system ROM microcode for the implementation of new instructions or routines.

0064[0064] As used herein, the term “microcode” is intended to mean the lowest level instructions that directly control a microprocessor.

0065[0065] There are several reasons why it might be desirable or even necessary to make changes in the programmed ROM of a microprocessor, corrections to existing code or the addition of new code being chief among them. For systems utilizing mask-produced (unalterable) ROM, such changes are not possible with existing memory and system architectures. Thus, to correct errors in the microcode, or to implement new capabilities, it is necessary to completely replace the defective or outmoded ROM devices if not the entire unit incorporating them, an expensive and inconvenient process.

0066[0066] The invention disclosed herein effectively allows for changes in otherwise unalterable ROM microcode, by loading microcode changes into allocated RAM and then providing for the selective execution of the existing ROM microcode or the changed RAM microcode. The disclosed techniques can be applied to any microprocessor system, but will be most beneficial for those systems that for economic or other reasons primarily rely on ROM memory devices that are programmed at system manufacture and incapable of alteration once programmed.

0067[0067] Depending upon the particular embodiment, as more fully discussed below, each address of at least one portion of the designated RAM address area(s) will contain one or more control or “select” bits to signal a change to existing ROM microcode. During program execution, when the select bit is detected, the system is directed to execute the changed RAM microcode rather than existing ROM microcode.

0068[0068] The RAM is organized into storage units that are larger than the ROM storage units, and logically divided into two sections. The first section of each RAM storage unit is of the same fixed size as each ROM storage unit, and is used to store the changed or new (patched) microcode. The second section of each RAM storage unit is used to control the ultimate selection of either original ROM or RAM microcode for system execution. For those skilled in the art, it is well understood how to implement a memory system design of the type described for the RAM.

0069[0069] A multiplexer has its inputs coupled, respectively, to the ROM and to that section of the patch RAM containing the patch microcode, if any. The select input terminal of the multiplexer is coupled to the second section of patch RAM, containing the signal telling the system whether it is to execute the ROM or the patched RAM microcode. This input select signal is used by the multiplexer to select either a ROM or a patch RAM routine for output. The output of the multiplexer, whether ROM or patch RAM, is then processed for further execution.

0070[0070] Patch microcode can be introduced into the system in a variety of ways. It can be received and taken into the system in the same manner as other forms of data by, for example, modem, wireless data link, disk, or CD. Once received, the patch may be stored in any non-volatile memory device accessible by the system, where it will be available for subsequent loading into the patch RAM. Alternatively, when initially received from an external source, the patch microcode may be simultaneously loaded into patch RAM (for immediate use) and into nonvolatile memory for more permanent storage and future access.

0071[0071] There are a variety of methods for initiating the use of patch RAM microcode instead of or in addition to original ROM microcode, as discussed in the following embodiments.

0072[0072]FIGS. 4 and 4A illustrates an architecture in which ROM (<b>1101</b> or <b>1101</b><i>a</i>), RAM (<b>1103</b>) and a RAM select bit share a common address. The select bit is used to determine whether the associated RAM or ROM instructions are to be executed.

0073[0073]FIGS. 8A through 8C illustrate one embodiment in which a portion of system RAM is used to store the address location for each ROM microcode routine or instruction. The addresses are loaded into RAM when the system is initialized on startup, or when a patch to system ROM microcode is received. FIG. 14 is a logic flowchart for a software routine to load the subject addresses into RAM. When a microcode routine or instruction is to be executed, the system is directed to obtain the microcode address from RAM. As shown in FIG. 8A, if there has been no change or addition to the microcode, the system will be directed to a ROM address, whereupon it will execute the routine or instruction stored in ROM. As illustrated in FIG. 8B, if a patch has been received and loaded in the patch RAM, the applicable RAM address will be substituted for the corresponding ROM instruction address and the routine executed in order from the patch RAM.

0074[0074]FIG. 9 illustrates a system for implementing the memory architecture shown in FIG. 4. To execute a microcode instruction, the program counter (<b>1601</b>) simultaneously addresses main ROM (<b>1101</b>), main RAM (<b>1103</b>), and a RAM select bit (<b>1102</b>). The ROM (<b>1101</b>) microcode and RAM (<b>1103</b>) microcode held in the selected address are input to a multiplexer (<b>1602</b>). The RAM select bit (<b>1102</b>) is used by the multiplexer to control the selection of ROM microcode or RAM microcode as the output of the multiplexer. Depending upon the status of the select bit, the multiplexer selects either the ROM microcode or the RAM microcode for output and further processing. The microcode selected for output from the multiplexer is then executed and the program counter incremented or branched as necessary to initiate the next microcode instruction routine.

0075[0075]FIG. 10 illustrates a system for implementing the memory architecture shown in FIG. 5. Here, the program counter (<b>1601</b>) simultaneously addresses main ROM (<b>1201</b>), routine ROM (<b>1202</b>), routine RAM (<b>1204</b>), and the RAM select bit (<b>1203</b>). The routine ROM (<b>1202</b>) and routine RAM (<b>1204</b>) microcode are input to a multiplexer (<b>1701</b>). The RAM select bit (<b>1203</b>) is used by the multiplexer to control the selection of routine ROM microcode or routine RAM microcode as the output of the multiplexer. Depending upon the status of the select bit, the multiplexer selects either the routine ROM microcode or the routine RAM microcode for output and further processing. The selected output from multiplexer <b>1701</b> is input to another multiplexer (<b>1702</b>). Main ROM microcode (<b>1201</b>) is also input to multiplexer <b>1702</b>. The most significant bit (MSB) or other control bit from the program counter is used to select the output of multiplexer <b>1702</b>. Depending upon the status of the MSB or other control bit, main ROM microcode or the output of multiplexer <b>1701</b> (routine ROM or routine RAM microcode) is selected for output and further processing. The microcode selected for output from multiplexer <b>1702</b> is then executed and the program counter incremented or branched as required to initiate the next microcode instruction.

0076[0076]FIG. 11 illustrates a system for implementing the memory architecture shown in FIGS. 6A, 6B, and <b>6</b>C. In this case, the program counter (<b>1601</b>) simultaneously addresses main ROM (<b>1301</b>), main RAM (<b>1303</b>), routine ROM (<b>1304</b>), routine RAM (<b>1305</b>), and the RAM select bit (<b>1302</b>). The addressed main ROM microcode and main RAM microcode are used as inputs to multiplexer <b>1802</b>. The RAM select bit (<b>1302</b>) is used to control the output of multiplexer <b>1802</b>, either main ROM microcode or main RAM microcode. This output is then directed to multiplexer <b>1801</b>. Routine ROM microcode (<b>1304</b>) and routine RAM microcode (<b>1305</b>) are also input to multiplexer <b>1801</b>. The most significant bits (MSB) or other control bits from the program counter are used to select the output of multiplexer <b>1801</b>. Depending upon the status of the MSBs or other control bits, routine ROM microcode, routine RAM microcode, or the output of multiplexer <b>1802</b> (main ROM or main RAM microcode) is selected for output and further processing. The microcode selected for output from multiplexer <b>1801</b> is then executed and the program counter incremented or branched as required to initiate the next microcode instruction.

0077[0077]FIG. 12 illustrates a system for implementing the memory architecture shown in FIGS. 7A, 7B, and <b>7</b>C. The program counter (<b>1601</b>) simultaneously addresses ROM (<b>1401</b>), RAM (<b>1403</b>), and the RAM select bit (<b>1402</b>). The ROM instruction is re-mapped by a logic circuit and then input to a multiplexer (<b>1901</b>) along with the available RAM patch routines. The routine to be selected is controlled by 1 or more RAM select bits (the number of bits determined by the number of potential patch routines). The selected routine is input to another multiplexer (<b>1902</b>), along with the re-mapped address of RAM instructions (<b>1403</b>). The selection from multiplexer <b>1902</b> is controlled by the most significant bit (MSB) of the program counter. The output instruction from multiplexer <b>1902</b> is executed and the address for the next instruction determined and forwarded to the program counter.

0078[0078]FIG. 13 illustrates a system for implementing the memory architecture shown in FIGS. 8A, 8B, and <b>8</b>C. Program counter <b>1601</b> simultaneously addresses routine ROM (<b>1503</b>), main ROM (<b>1501</b>), main RAM (<b>1505</b>), and routine RAM (<b>1504</b>). The main RAM and main ROM microcode are used as inputs to multiplexer <b>2001</b>. The most significant bits (MSB) or other control bits from the program counter are used to select the output of multiplexer <b>2001</b>. Depending upon the status of the MSBs or other control bits, main ROM microcode or main RAM microcode is selected for output from multiplexer <b>2001</b>. The selected address is then referenced to the index RAM (<b>1502</b>), remapped as necessary and input to multiplexer <b>2002</b>. Routine ROM microcode and routine RAM microcode are input to multiplexer <b>2002</b>. Again, the most significant bit (MSB) or other control bit from the program counter is used to select the output of multiplexer <b>2002</b>. Depending upon the status of the MSB or other control bit, routine ROM microcode, routine RAM microcode, remapped main RAM or remapped main ROM is selected for output and further processing.

0079[0079]FIG. 14 is a programming flow chart showing a microcode patch initialization routine for the memory architecture depicted in FIGS. 8A, 8B, and <b>8</b>C. After program initialization, all index RAM locations are set to the unused pattern (such as all “is”). An index is read from ROM and written to RAM, and pointer incremented to show the next index location. The process is repeated until all indexes are initialized in order. Once the indexes are initialized, the presence of a microcode patch is queried from non-volatile memory by, for example, sampling the status of a designated “patch” bit. If a patch is detected, its index is read from non-volatile memory and written to the corresponding RAM index location. The patch routine is then read from non-volatile memory and written to the designated patch RAM area of memory. The process is repeated until all patches have been indexed and written to RAM. Those skilled in the art will understand that this is only one of many possible programs for loading patched microcode into RAM and indexing its location(s) As one skilled in the art understands, data processing circuit <b>302</b> described above may further comprise a context switching circuit as described in U.S. patent application Ser. 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