Copper interconnect with sidewall copper-copper contact between metal and via

BACKGROUND OF THE INVENTION

P-0001[0001] 1. Field of the Invention

P-0002[0002] Embodiments of the present invention generally relate to semiconductor substrate processing and integrated circuits. More particularly, the invention relates to a method of forming a semiconductor substrate having an area of contact between an underlying metal feature and an interconnect opening filled with metal.

P-0003[0003] 2. Description of the Related Art

P-0004[0004] Modern semiconductor integrated circuits usually involve multiple conductive metal layers separated by dielectric (insulating) layers, such as silicon oxide or silica, often referred to simply as an oxide layer, although other materials are being considered for use as the dielectric. The metal layers are electrically interconnected by holes penetrating the intervening oxide layers that contact some underlying conductive feature. After the holes are etched, they are filled with a metal, such as aluminum or copper, to electrically connect the bottom layer with the top layer. The generic structure is referred to as a plug.

P-0005[0005] Plugs have presented an increasingly difficult problem as integrated circuits are formed with an increasing density of circuit elements because the feature sizes have continued to shrink. For logic applications, the thickness of the oxide layer seems to be constrained to the neighborhood of 1 μm, while the diameter of the plug is being reduced from the neighborhood of 0.35 μm or 0.25 μm to 0.18 μm and below. As a result, the aspect ratios (the ratio of the depth to the minimum lateral dimension) of the plugs are being pushed to 5:1 and above. As sizes continue to decrease, the characteristics of the material forming the plugs become increasingly important. The smaller the plug, the less resistive the material forming the plug should be for speed performance. Copper is a material which is becoming more important as a result. Copper has a resistivity of 1.7 μΩ.cm. Copper has a small RC time constant thereby increasing the speed of a device formed thereof. In addition, copper exhibits improved reliability over aluminum in that copper has excellent electromigration resistance and can drive more current in the lines.

P-0006[0006] One problem with the use of copper is that copper diffuses into silicon dioxide, silicon and other dielectric materials. Therefore, barrier layers become increasingly important to prevent copper from diffusing into the dielectric and compromising the integrity of the device. Unfortunately, barrier layers become incorporated into the fabricated structure and remain between two conductive features at their interface.

P-0007[0007] An example of a prior art dual damascene structure <b>10</b> which includes a barrier layer is shown in FIG. 1. The structure <b>10</b> includes a substrate <b>12</b> with an underlying metal feature <b>14</b>. The structure further includes a first dielectric layer <b>16</b> and a second dielectric layer <b>18</b> which can be deposited and patterned by conventional dual damascene processes. The first dielectric layer <b>16</b> has a vertical interconnect opening <b>20</b> and the second dielectric layer <b>18</b> has a horizontal interconnect opening <b>22</b>. A barrier layer <b>24</b> is deposited on the structure. By covering the sidewalls <b>26</b>, <b>28</b> of the vertical interconnect opening and the horizontal interconnect opening, the barrier layer <b>24</b> helps prevent the diffusion of the metal <b>30</b> deposited in the vertical interconnect opening and the horizontal interconnect opening into the first dielectric layer <b>16</b> and the second dielectric layer <b>18</b>. However, barrier layers deposited by currently used methods also typically cover the bottom <b>32</b> of the vertical interconnect opening, and thus separate the metal <b>30</b> deposited in the vertical interconnect opening from the underlying metal feature <b>14</b>. The barrier layer at the bottom <b>32</b> of the vertical interconnect opening increases the resistance of the structure and detracts from the performance of the structure. The barrier layer at the bottom <b>32</b> of the via also prevents the formation of continuous metal grains between the underlying metal feature <b>14</b> and the metal <b>30</b> deposited in the vertical and horizontal interconnecting openings <b>20</b> and <b>22</b>.

P-0008[0008] Therefore, there remains a need for a method of forming a semiconductor device that minimizes the detrimental effects that can be caused by barrier layers.

SUMMARY OF THE INVENTION

P-0009[0009] The present invention generally provides a method for forming a conductive feature in a dual damascene structure formed over an underlying metal feature, comprising etching the metal feature, wherein etching the metal feature creates an undercut in the metal feature, depositing a barrier layer on the dual damascene structure by a line of sight process, and depositing a conductive metal and filling the dual damascene structure and the etched metal feature with the conductive metal.

P-0010[0010] In one embodiment, a method for forming a conductive feature on a substrate comprises providing a substrate including a metal feature, depositing an intermediate layer on the substrate, depositing a dielectric layer on the substrate, etching the dielectric layer to form an interconnect opening in the dielectric layer, etching the intermediate layer at the bottom of the interconnect opening to connect the interconnect opening and the metal feature, etching the metal feature, wherein etching the metal feature creates an undercut in the metal feature, depositing a barrier layer on the substrate by a line of sight process, and depositing a conductive metal and filling the interconnect opening and the etched metal feature with the conductive metal.

P-0011[0011] In one embodiment, the line of sight process comprises physical vapor deposition (PVD). Preferably, the barrier layer is deposited by physical vapor deposition of a material selected from the group consisting of Ta, TaN, W, WN, Ti, TiN, Co, and combinations thereof. In at least one embodiment, the metal feature comprises copper and the conductive metal comprises copper.

P-0012[0012] In at least one embodiment, the conductive metal is deposited by at least one of chemical vapor deposition, electroless deposition, PVD, electroplating.

P-0013[0013] In one embodiment, the method for forming a conductive feature on a substrate may further comprise annealing the deposited conductive material. In another embodiment, the method for forming a conductive feature on a substrate may further comprise chemical mechanical polishing or electropolishing the substrate.

P-0014[0014] A further embodiment comprises a method for forming a dual damascene structure, comprising providing a substrate including a metal feature, depositing a intermediate layer on the substrate, depositing a first dielectric layer on the substrate, depositing a second dielectric layer on the substrate, etching the first and second dielectric layers to form a vertical interconnect opening in the first dielectric layer and a horizontal interconnect opening in the second dielectric layer, etching the intermediate layer at the bottom of the vertical interconnect opening to connect the vertical interconnect opening and the metal feature, etching the metal feature, wherein etching the metal feature creates an undercut in the metal feature, depositing a barrier layer on the substrate by a line of sight process, and depositing a conductive metal and filling the horizontal interconnect opening, the vertical interconnect opening, and the etched metal feature with the conductive metal.

P-0015[0015] In another aspect, substrates such as semiconductor structures and dual damascene structures are provided.

BRIEF DESCRIPTION OF THE DRAWINGS

P-0016[0016] So that the manner in which the above recited features of the present invention are attained and can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to the embodiments thereof which are illustrated in the appended drawings.

P-0017[0017] It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.

P-0018[0018]FIG. 1 is a prior art dual damascene structure.

P-0019[0019] FIGS. <b>2</b>-<b>11</b> are structures prepared in accordance with embodiments of the invention.

P-0020[0020]FIG. 12 is a cross sectional view of a structure prepared in accordance with embodiments of the present invention.

P-0021[0021]FIG. 13 illustrates another structure prepared in accordance with embodiments of the present invention.

P-0022[0022]FIG. 14 is a prior art structure.

P-0023[0023]FIG. 15 is a structure prepared in accordance with an embodiment of the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

P-0024[0024] The present invention generally provides a method for forming a device having an area of contact between an underlying metal feature and an interconnect opening filled with metal. Generally, an interface is opened between an underlying metal feature and an interconnect opening such that a barrier layer can be formed on portions of the device, such as portions of the dielectric layer, while a barrier layer is not formed on at least a portion of the interface between the underlying metal feature and the interconnect opening. In any or all of the embodiments described below, a barrier layer which separates the metal deposited in the interconnect opening(s) from the dielectric layers but does not completely separate the metal deposited in the interconnect opening(s) and the metal deposited in the etched metal feature is deposited by a line of sight process.

P-0025[0025] In one embodiment, a substrate <b>50</b> having an underlying metal feature <b>52</b> is provided, as shown in FIG. 2. While the metal feature <b>52</b> can include a variety of metals, the metal feature <b>52</b> preferably is or includes copper. As shown in FIGS. <b>3</b>-<b>5</b>, an intermediate layer <b>54</b>, such as a barrier layer and/or an etch stop, e.g., SiN, between the metal feature <b>52</b> and the vertical interconnect opening <b>62</b> is deposited on the substrate before first and second dielectric layers <b>56</b>, <b>58</b> are deposited on the substrate. The dielectric layers may comprise oxides, carbon-doped oxides, low dielectric constant polymers, parylene-based materials, or combinations thereof. The dielectric layers may comprise porous oxides, carbon-doped oxides, low dielectric constant polymers, parylene-based materials, or combinations thereof. The etch stop may comprise silicon nitrides, silicon carbides, porous silicon nitrides or silicon carbides, or combinations thereof. A photoresist (not shown) or other conventional material may be used to pattern the first and second dielectric layers <b>56</b>, <b>58</b>.

P-0026[0026] The second dielectric layer <b>58</b> and the first dielectric layer <b>56</b> are then etched, as shown in FIG. 5, such as by a dual damascene process. The etching of the second dielectric layer <b>58</b> creates a horizontal interconnect opening <b>60</b>, and the etching of the first dielectric layer <b>56</b> creates a vertical interconnect opening <b>62</b> having sidewalls <b>65</b>. The intermediate layer <b>54</b> is then etched using an etching material that does not significantly etch the dielectric layers <b>56</b>, <b>58</b> and removed from the vertical interconnect opening <b>62</b>. The vertical interconnect opening <b>62</b> is then connected to the horizontal interconnect opening <b>60</b> and the underlying metal feature <b>52</b>, as shown in FIG. 6.

P-0027[0027] The underlying metal feature <b>52</b> is then etched such that a portion of the underlying metal feature is removed, as shown in FIG. 7. Removal of the portion of the underlying metal feature <b>52</b> results in undercuts <b>64</b> in the metal feature <b>52</b>. While two undercuts <b>64</b> are shown, etching the underlying metal feature may create one or more undercuts in the metal feature. Furthermore, while two undercuts <b>64</b> are shown, the two undercuts <b>64</b> may be considered to be part of one annular undercut that is shown in cross section in the metal feature. While the undercuts <b>64</b> are shown as having a rounded shape, the undercuts may have other shapes depending on the etch characteristics of the material and the chemistry being used. The undercuts may extend laterally from between about 50 Å to about 1000 Å from the sidewalls <b>65</b> of the vertical interconnect opening <b>62</b> and away from the vertical interconnect opening <b>62</b>. Preferably, the undercuts extend laterally from between about 200 Å to about 500 Å from the sidewalls <b>65</b> of the vertical interconnect opening <b>62</b> and away from the vertical interconnect opening <b>62</b>. The undercuts may extend vertically down from between about 100 Å to about 2500 Å from the bottom of the etched vertical interconnect opening <b>62</b>. Preferably, the undercuts extend vertically from between about 500 Å to about 1000 Å from the bottom of the etched vertical interconnect opening <b>62</b>. While examples of undercut dimensions are described above, undercuts that have other dimensions may be used. Generally, a metal feature is etched such that the undercuts extend laterally away from the vertical interconnect opening, and thus, the undercuts can not be completely covered by a layer deposited by a line of sight process.

P-0028[0028] Several known types of processes may be used to etch the underlying metal feature. For example, a wet or a dry etch process may be used.

P-0029[0029] The etching chemistry used to etch the underlying metal feature should be one that will etch the metal feature but preferably will not etch the intermediate layer and will not etch the dielectric layers. Examples of materials, such as solutions, that can be used to perform a wet etch include nitric acid, sulfuric acid, hydrogen peroxide, and ammonium hydroxide. Solvents, such as EKD 265, NE 14, and ACT 970, may be used as etching solutions. Combinations of the etching solutions listed above may also be used. A wet etch can be performed in any sink or spray tool. The etching chemistry is applied for a period of time necessary to form an undercut. The etching period typically depends on the concentration of the etching chemistry used and/or the rate at which the etching chemistry etches the underlying metal feature. Generally, a wet etch is performed for between about 30 seconds to about one hour, e.g., between about 30 seconds to about 30 minutes, to achieve the desired amount of etching of the underlying metal feature. However, the etch process time is preferably minimized to increase throughput of substrates during processing. Examples of etching chemistries and etching periods that may be used include the following: EKC 265 for about 2 minutes, NE 14 for about 20 minutes, or ACT 970 for about 20 minutes.

P-0030[0030] An example of a material that can be used to perform a dry etch is a combination of a fluorine containing-gas, such as CHF₃or C₂F₆, and O₂. Other gases that may be used to perform a dry etch include C_xH_yF_zgases, nitrogen, NF₃and combinations thereof. A dry etch can be performed in any conventional etching or plasma chamber. An inductive plasma may be used in the chamber. The substrate is typically biased at between −1000 volts and 0 volts. The magnetic field of the chamber may be about 10 Gauss. The biasing of the substrate and the length of time of the etch may be varied as necessary to achieve the desired amount of etching in the underlying metal feature. Generally, a dry etch is performed for between about 10 seconds to about 2 minutes.

P-0031[0031] One example of a dry etch process to form undercuts in a metal feature includes biasing a substrate at between −1000 volts and 0 volts in a plasma chamber. The power applied to the chamber is about 1600 watts, and the magnetic field is about 10 Gauss. CF₄is flowed into the chamber at about 20 sccm (standard cubic centimeters per minute). C₄F₆is flowed into the chamber at about 25 sccm. O₂is flowed into the chamber at about 20 sccm. Argon is flowed into the chamber at about 300 sccm. The substrate is plasma treated for about 30 seconds to form undercuts.

P-0032[0032] Alternatively, the underlying metal feature <b>52</b> may be etched by a sputter etch process such as a sputtering process used to pre-clean substrates before depositing layers of material on substrates. For example, the underlying metal feature <b>52</b> may be etched by bombarding the feature with sputtered argon, helium, hydrogen, other gases or ions, or combinations thereof for between about 10 seconds to about 2 minutes. One such process can be performed in a Pre-Clean II chamber available from Applied Materials, Inc., located in Santa Clara, Calif. An example of a pre-cleaning process that can be used to create undercuts includes flowing argon, such as at about 20 sccm into a chamber and creating a plasma in the chamber. The plasma activates the argon, and the argon bombards the substrate. The substrate is biased at between −1000 volts and 0 volts. The power applied to the chamber is about 300 watts. The substrate is plasma treated for about 30 seconds to form undercuts.

P-0033[0033] After the underlying metal feature <b>52</b> is etched, a barrier layer <b>66</b> is then deposited on the substrate, as shown in FIG. 8. Preferably, the barrier layer <b>66</b> is deposited by a line of sight process, i.e., a process in which the material that is deposited on the substrate is primarily deposited on the portions of the substrate that are visible from the processing area that is above the substrate and through which the source of the material to be deposited is provided. Line of sight processes that may be used include PVD, ionized PVD, or self-ionized PVD according to methods known in the art. However, other line of sight processes may also be used. The barrier layer <b>66</b> that is deposited by any of these processes is preferably selected from the group of Ta, TaN, W, WN, Ti, TiN, Co, and combinations thereof. The barrier layer <b>66</b> deposited by a line of sight process will not cover the sides of the undercuts <b>64</b> in the metal feature <b>52</b> because the undercuts are underneath the first dielectric layer <b>56</b>, rather than underneath the vertical interconnect opening and thus, not in the line of sight of the material being directionally deposited. Thus, while a portion <b>68</b> of the barrier layer <b>66</b> may cover a portion of the underlying metal feature <b>52</b>, as shown in FIG. 8, the barrier layer does not completely separate the vertical interconnect opening <b>62</b> and the underlying metal feature <b>52</b> because of the gaps in the barrier layer around the undercuts <b>64</b> and the portion <b>68</b> of the barrier layer <b>66</b> on the underlying metal feature <b>52</b>.

P-0034[0034] After the barrier layer is deposited, a conductive metal <b>70</b> is deposited in and fills the etched metal feature, the vertical interconnect opening, and the horizontal interconnect opening, as shown in FIG. 9. Preferably, the underlying metal feature <b>52</b> is or includes copper and the metal <b>70</b> deposited is or includes copper. In at least one embodiment, the metal <b>70</b> can be deposited by chemical vapor deposition (CVD). In another embodiment, the metal <b>70</b> can be deposited by electroless deposition. In another embodiment, the metal <b>70</b> can be deposited by forming a seed layer using PVD or CVD followed by bulk fill using electroplating techniques. In each of these embodiments, the method of metal deposition can be used to fill non-line of site structures, such as the undercuts <b>64</b>. While examples of undercut dimensions are discussed above, the undercuts in any of the embodiments described herein may have other dimensions that may be filled with the metal <b>70</b> using the processes described herein.

P-0035[0035] After the metal <b>70</b> is deposited, the metal can be annealed to optimize the size and uniformity of the metal grains. Annealing may also enhance the flow and distribution of the metal <b>70</b> into the undercuts <b>64</b>. The substrate can also undergo chemical mechanical polishing (CMP) or electropolishing to remove any excess metal on the substrate and to provide a substrate with a uniform surface, as shown in FIG. 9.

P-0036[0036] In another embodiment, a dual damascene structure formed over a metal feature is provided. The dual damascene structure includes a vertical interconnect opening <b>62</b> connected to horizontal interconnect opening <b>60</b> and underlying metal feature <b>52</b>, as shown in FIG. 6. As shown and described above with respect to FIGS. <b>7</b>-<b>9</b>, the underlying metal feature <b>52</b> is etched such that undercuts are created in the metal feature. A barrier layer <b>66</b> is deposited on the dual damascene structure by a line of sight process. A conductive metal <b>70</b> is deposited on and fills the dual damascene structure and the etched metal feature with the conductive metal.

P-0037[0037] In yet another embodiment, shown in FIG. 10, a substrate <b>80</b> has an underlying metal feature <b>82</b> and an intermediate layer <b>84</b>, such as a barrier layer and/or an etch stop, e.g., SiN, deposited on the substrate. A dielectric layer <b>86</b> is then deposited on the substrate. The dielectric layer is etched to form an interconnect opening <b>88</b>. The intermediate layer <b>84</b> is then etched using an etching material that does not significantly etch the dielectric layer and removed from the bottom of the interconnect opening <b>88</b> such that the underlying metal feature <b>82</b> and the interconnect opening <b>88</b> are connected. The underlying metal feature is then etched such that only a portion of the underlying metal feature is removed, and undercuts <b>90</b> are created in the underlying metal feature. While two undercuts <b>90</b> are shown, etching the underlying metal feature may create one or more undercuts in the metal feature. Furthermore, while two undercuts <b>90</b> are shown, the two undercuts <b>90</b> may be considered to be part of one annular undercut that is shown in cross section in the metal feature. After the underlying metal feature <b>82</b> is etched, a barrier layer <b>94</b> is then deposited on the substrate. Preferably, the barrier layer <b>94</b> is deposited by a line of sight process, i.e., a process in which the material that is deposited on the substrate is primarily deposited on the portions of the substrate that are visible from the processing area that is above the substrate and provides the source of the material to be directionally deposited. Line of sight processes that may be used include PVD, ionized PVD, or self-ionized PVD according to methods known in the art. However, other line of sight processes may also be used. The barrier layer <b>94</b> that is deposited by any of these processes is preferably selected from the group of Ta, TaN, W, WN, Ti, TiN, Co, and combinations thereof. The barrier layer <b>94</b> deposited by a line of sight process will not cover the sides of the undercuts <b>90</b> in the metal feature <b>82</b> because the undercuts are underneath the dielectric layer <b>86</b> and extend away from the sidewalls <b>91</b> of the interconnect opening <b>88</b>, and thus, are not in the line of sight of the material being directionally deposited. Thus, while a portion <b>96</b> of the barrier layer <b>94</b> may cover a portion of the underlying metal feature <b>82</b>, as shown in FIG. 10, the barrier layer does not completely separate the interconnect opening <b>88</b> and the underlying metal feature <b>82</b> because of the gaps in the barrier layer around the undercuts <b>90</b> and the portion <b>96</b> of the barrier layer <b>94</b> on the underlying metal feature <b>82</b>.

P-0038[0038] The deposition and etching steps described herein for the substrate <b>80</b> are performed according to processes similar or identical to those described with respect to dual damascene structures, and further processing steps similar or identical to the processes described above with respect to dual damascene structures may be performed on the substrate. For example, in one embodiment, a conductive metal (not shown) is deposited in and fills the etched metal feature and the interconnect opening. Preferably, the underlying metal feature comprises copper and the metal deposited comprises copper. CVD, electroless deposition, PVD followed by electroplating, and electroplating are methods that may be used to deposit the conductive metal. In each of these embodiments, the method of metal deposition can be used to fill non-line of sight structures, such as the undercuts <b>90</b>. After the metal is deposited, the metal may be annealed. The substrate may also be treated with CMP or an electropolish etch to remove any excess metal on the substrate and to provide a substrate with a uniform surface.

P-0039[0039] While the embodiments described above are shown with respect to figures in which the underlying metal feature has a greater width than the vertical interconnect opening, the processes described herein may also be performed on substrates having an underlying metal feature with the same width as the vertical interconnect opening in one plane or on substrates having unlanded vertical interconnect openings such as substrates having an underlying metal feature that extends on one side horizontally beyond the area underneath the vertical interconnect opening.

P-0040[0040] An example of a substrate having an underlying metal feature having the same width as a vertical interconnect opening in one plane is shown in FIG. 11. The substrate <b>110</b> includes an underlying metal feature <b>102</b>, an intermediate layer <b>112</b> deposited on the substrate, a first dielectric layer <b>114</b>, a second dielectric layer <b>116</b>, a vertical interconnect opening <b>118</b> having sidewalls <b>119</b>, and a horizontal interconnect opening <b>120</b>. The underlying metal feature <b>102</b> is the same or approximately the same width as the vertical interconnect opening <b>118</b> in the plane and cross section shown in FIG. 11. However, in a view of the plane and cross section taken along <b>12</b>-<b>12</b>, shown in FIG. 12, the underlying metal feature <b>102</b> and the vertical interconnect opening <b>118</b> do not have the same width. The underlying metal feature <b>102</b> is wider than the vertical interconnect opening <b>104</b>, and thus, one or more undercuts <b>106</b> can be created in the underlying metal feature by the processes described above.

P-0041[0041] An example of a substrate having an unlanded vertical interconnect opening, e.g., a substrate having an underlying metal feature that extends on one side horizontally beyond the area underneath the vertical interconnect opening, is shown in FIG. 13. The substrate <b>120</b> includes an underlying metal feature <b>122</b>, an intermediate layer <b>123</b> deposited on the substrate, a first dielectric layer <b>124</b>, a second dielectric layer <b>126</b>, a vertical interconnect opening <b>128</b> having sidewalls <b>129</b>, and a horizontal interconnect opening <b>130</b>. The underlying metal feature <b>122</b> is partially underneath the vertical interconnect opening <b>128</b> and partially underneath a first dielectric layer <b>124</b> and the intermediate layer <b>123</b> on the substrate on one side of the vertical interconnect opening. The portion of the underlying metal feature <b>122</b> underneath the first dielectric layer <b>124</b> can be etched to form an undercut <b>132</b> using the processes described above.

P-0042[0042] The processes described herein can be used to prepare devices, i.e., structures, having a more continuous grain formation than devices prepared according to traditional techniques in which the underlying metal feature of a device is completely separated from the metal deposited in the device interconnects by a barrier layer. The barrier layers deposited by the processes described herein do not completely separate the underlying metal feature and the metal deposited in the interconnects, and thus, continuous metal grains may be formed between the underlying metal feature and the metal deposited in the interconnects. The connection and continuous grain between the underlying metal feature and the metal deposited in the interconnects may also enhance electromigration within the metal of the device and may improve the thermal stress reliability of the device. Furthermore, the undercuts created by the processes described herein result in a large surface area between the underlying metal feature and the metal deposited in the interconnects. The large surface area between the underlying metal feature and the metal deposited in the interconnects typically decreases the resistance of the device.

P-0043[0043] The processes described herein also provide devices which are less likely to lose their metal plugs because of the direct connection between the metal plugs in the interconnect openings and the underlying metal feature. Thus, the metal plugs are more deeply anchored in the substrate than metal plugs formed according to conventional processes. Furthermore, the metal which is deposited in the undercut(s) of the underlying metal feature helps anchor the metal deposited in the interconnect openings and the underlying metal feature by creating a deposited metal structure which is bigger, i.e., wider that the vertical interconnect opening.

P-0044[0044] While attempts have been made to provide a continuous connection between an underlying metal feature and the metal deposited in an unlanded vertical interconnect opening by selectively etching the barrier layer <b>134</b> from the bottom of the vertical interconnect opening, these processes can result in the removal of barrier layer from the substrate so that there is no barrier layer <b>134</b> between the metal deposited in the unlanded vertical interconnect opening and the substrate, as shown in region <b>140</b> of FIG. 14. A structure having an unlanded vertical interconnect opening and produced by the processes described herein and shown in FIG. 15 does not have the exposed region. The barrier layer <b>134</b> does not completely separate the metal <b>142</b> deposited in the horizontal interconnect opening <b>130</b>, the vertical interconnect opening <b>128</b>, and the underlying metal feature <b>122</b> from the metal already present in the underlying metal feature <b>122</b> because the undercut <b>132</b> in the underlying metal feature is not covered by the barrier layer <b>134</b>.

P-0045[0045] While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.