Method for forming a via in a damascene process

FIELD OF THE INVENTION

P-0001[0001] The present claimed invention relates to the field of semiconductor processing. More particularly, the present claimed invention relates to a method for forming a via in a damascene process.

BACKGROUND ART

P-0002[0002] As semiconductor geometries continue to become smaller and smaller, new difficulties arise in the fabrication of the correspondingly smaller features. As one example, when device sizes decrease in size (in order to form more devices on each wafer), features such as vias have critical dimensions (CDs) which become considerably smaller. The reduced CD of, for example, a via has certain drawbacks associated therewith. Referring now to Prior Art FIG. 1A, a side sectional view of a via formed in a damascene process wherein the via has a reduced CD is shown. In Prior Art FIG. 1A, a substrate <b>100</b> has a via <b>102</b> formed therein using a damascene process. In the structure of Prior Art FIG. 1A, the critical dimension (CD) is shown as the width, W, at the top of via <b>102</b>. Furthermore, via <b>102</b> has a depth, D.

P-0003[0003] Referring still to Prior Art FIG. 1A, as the CD of via <b>102</b> decreases, significant manufacturing difficulties arise. For example, in a damascene process, such a via is typically formed using a plurality (e.g. two major etches for the formation of via <b>102</b>) of anisotropic etches in order to etch a sufficient depth into substrate <b>100</b> while still maintaining the desired CD for via <b>102</b>. As a result, sharp corners, typically shown as <b>104</b><i>a </i>and <b>104</b><i>b </i>and <b>106</b><i>a </i>and <b>106</b><i>b</i>, are formed at the top edges present within via <b>102</b>. Sharp corners <b>104</b><i>a </i>and <b>104</b><i>b </i>induce stress in subsequently deposited overlying layers and reduce adherence of the overlying layer to underlying substrate <b>100</b>.

P-0004[0004] With reference now to Prior Art FIG. 1B, a side sectional view of via <b>102</b> of Prior Art FIG. 1A is shown having an overlying layer of material disposed thereon. As shown in Prior Art FIG. 1B, due to the presence of sharp corners (e.g. corners <b>104</b><i>a</i>, <b>104</b><i>b</i>, <b>106</b><i>a</i>, and <b>106</b><i>b</i>) and the profile of via <b>102</b>, voids (typically shown as <b>108</b>) are formed in the overlying layer of material. These voids deleteriously affect the integrity of the device, and may ultimately lead to failure of the device in which the void-containing via is used.

P-0005[0005] As critical dimensions of vias formed using the damascene process continue to decrease in size, it is expected that the above-described problems will be further exacerbated. Additionally, any attempts to eliminate or reduce the problems associated with damascene process-formed vias should be compatible with existing semiconductor fabrication processes such that a complete retooling of conventional semiconductor fabrication facilities is not required.

P-0006[0006] Thus, a need exists for a method for forming a via in a damascene process wherein the via does not suffer from poor adherence to a subsequently deposited overlying layer. Still another need exists for a method for forming a via in a damascene process which enables the formation of a metallized interconnect wherein the method meets the above need and wherein the metallized interconnect does not suffer from void/seam formation. Yet another need exists for a method for forming a via in a damascene process wherein the method meets all of the above-listed needs and wherein the method is compatible with existing semiconductor fabrication processes.

SUMMARY OF INVENTION

P-0007[0007] The present invention provides a method for forming a via in a damascene process wherein the via does not suffer from poor adherence to a subsequently deposited overlying layer. The present invention further provides a method for forming a via in a damascene process which enables the formation of a metallized interconnect wherein the method achieves the above accomplishment and wherein the metallized interconnect does not suffer from void/seam formation. The present invention also provides a method for forming a via in a damascene process wherein the method achieves all of the above-listed accomplishments and wherein the method is compatible with existing semiconductor fabrication processes.

P-0008[0008] In one embodiment of the present invention, the present method comprises depositing a material into a via formed using a damascene process. More particularly, in one embodiment, the material which is comprised of a substantially conformal material which has an etch selectivity with respect to the substrate into which the via is formed. Furthermore, in this embodiment, the material is deposited along the sidewalls and the base of the via. Next, the present embodiment etches material such that the via is formed having a profile conducive to the adherence of overlying material thereto. In this embodiment, the etching of the material is performed without substantially etching the substrate into which the via is formed. In so doing, the present embodiment creates a via in a damascene process which allows for the formation of a metallized interconnect which is substantially free of voids.

P-0009[0009] In another embodiment, the present invention includes the steps of the above-described embodiment, and further includes the step of depositing a layer of a conductive material into the via having the profile conducive to the adherence of overlying material thereto. After the deposition of the conductive material, the present embodiment performs a planarization step such that the conductive material remains primarily within the via. As a result, the present embodiment provides a metallized interconnect within a via formed in a damascene process, wherein the metallized interconnect is substantially free of voids.

P-0010[0010] These and other objects and advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments which are illustrated in the various drawing figures.

BRIEF DESCRIPTION OF THE DRAWINGS

P-0011[0011] The accompanying drawings, which are incorporated in and form a part of this specification, illustrates embodiments of the invention and, together with the description, serve to explain the principles of the invention:

P-0012[0012] PRIOR ART FIG. 1A is a side sectional view of a via formed into a substrate wherein the via has a small critical dimension.

P-0013[0013] PRIOR ART FIG. 1B is a side sectional view of the structure of PRIOR ART FIG. 1A having a layer of material disposed thereover.

P-0014[0014]FIG. 2A is a side sectional view of a starting step in a method to form a void-free via in accordance with one embodiment of the present claimed invention.

P-0015[0015]FIG. 2B is a side sectional view of the structure of FIG. 2A having a first etch stop layer disposed thereover in accordance with one embodiment of the present claimed invention.

P-0016[0016]FIG. 2C is a side sectional view of the structure of FIG. 2B having a first material deposited above the first etch stop layer in accordance with one embodiment of the present claimed invention.

P-0017[0017]FIG. 2D is a side sectional view of the structure of FIG. 20 having a second etch stop layer disposed thereover in accordance with one embodiment of the present claimed invention.

P-0018[0018]FIG. 2E is a side sectional view of the structure of FIG. 2D having a second material disposed thereover in accordance with one embodiment of the present claimed invention.

P-0019[0019]FIG. 2F is a side sectional view of the structure of FIG. 2E having an opening formed through the second material in accordance with one embodiment of the present claimed invention.

P-0020[0020]FIG. 2G is a side sectional view of the structure of FIG. 2F having an opening formed through the first material in accordance with one embodiment of the present claimed invention.

P-0021[0021]FIG. 2H is a side sectional view of the structure of FIG. 2G having a third material disposed thereover in accordance with one embodiment of the present claimed invention.

P-0022[0022]FIG. 2I is a side sectional view of the structure of FIG. 2H after the structure has been subjected to an etching operation in accordance with one embodiment of the present claimed invention.

P-0023[0023]FIG. 2J is a side sectional view of the structure of FIG. 2H after material has been deposited into the via and over the remaining portion of the structure in accordance with one embodiment of the present claimed invention.

P-0024[0024]FIG. 2K is a side sectional view of the structure of FIG. 2J after a planarizing step has been performed in accordance with one embodiment of the present claimed invention.

P-0025[0025]FIG. 3 is a flow chart of steps performed in accordance with one embodiment of the present claimed invention.

P-0026[0026]FIG. 4 is a flow chart of steps performed in accordance with another embodiment of the present claimed invention.

P-0027[0027] The drawings referred to in this description should be understood as not being drawn to scale except if specifically noted.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

P-0028[0028] Reference will now be made in detail to the preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. While the invention will be described in conjunction with the preferred embodiments, it will be understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be obvious to one of ordinary skill in the art that the present invention may be practiced without these specific details. In other instances, well known methods, procedures, components, and circuits have not been described in detail as not to unnecessarily obscure aspects of the present invention.

P-0029[0029] FIGS. <b>2</b>A-<b>2</b>K provide side sectional views of the structure created according to embodiments of the method of the present invention as set forth in the flow charts of FIGS. 3 and 4. For purposes of clarity, the following discussion will utilize the side sectional views of FIGS. <b>2</b>A-<b>2</b>K in conjunction with the flow charts of FIGS. 3 and 4 to clearly describe the embodiments of the present invention. Flow chart <b>300</b> of FIG. 3 begins with step <b>302</b>. At step <b>302</b>, the present embodiment deposits a first etch stop layer above a material <b>202</b> in which a target <b>203</b> is present. As will be described in detail below, the damascene process formed via to be created in accordance with the present embodiment is a via which, unlike conventional damascene process formed vias, will not induce the formation of voids and/or seams in the material subsequently deposited therein.

P-0030[0030] Referring still to step <b>302</b> of FIG. 3, in the present embodiment, material <b>202</b> is any material in which a target can be located. As will be understood, conductively filled damascene process formed vias are often formed to electrically couple conductive features (e.g. target <b>203</b> and a subsequently deposited overlying conductive layer) which are separated by a dielectric material. In the present embodiment, material <b>202</b> as shown in FIG. 2A is comprised of an intermetal dielectric (IMD) material such as, for example, silicon dioxide. Although such an IMD material is recited in the present embodiment, the present embodiment is well suited to the use of any other material into which it is desired to form a via. Other materials which are well suited for use as the first material include, but are not limited to, tetraethylorthosilicate (TEOS), fluorine-doped TEOS, and the like.

P-0031[0031] With reference still to step <b>302</b> of FIG. 3, first etch stop layer <b>204</b> is shown in FIG. 2B overlying material <b>202</b> and target <b>203</b>. In the present embodiment first etch stop layer <b>204</b> is comprised of an oxy-nitride (ONO) layer. Although such a material is recited as comprising the first etch stop layer in the present embodiment, the present invention is also well suited to the use of various other types of materials for first etch stop layer <b>204</b>.

P-0032[0032] At step <b>304</b> of FIG. 3, the present embodiment recites depositing a layer <b>206</b>, shown in FIG. 2C, of a first material above first etch stop layer <b>204</b>. In the present embodiment, layer of first material <b>206</b> is comprised of a material which has an etch selectivity with respect to first etch stop layer <b>204</b>. That is, layer of first material <b>206</b> is comprised of a material that can be etched using an etching process wherein the etching process does not significantly etch first etch stop layer <b>204</b>. Similarly, first etch stop layer <b>204</b> is comprised of a material that can be etched using a different etching process wherein the different etching process does not significantly etch layer of first material <b>206</b>. In the present embodiment, layer of first material <b>206</b> is comprised of an intermetal dielectric (IMD) material such as, for example, silicon dioxide. Although such an IMD material is recited in the present embodiment, the present embodiment is well suited to the use of any other material into which it is desired to form a via. Other materials which are well suited for use as the first material include, but are not limited to, tetraethylorthosilicate (TEOS), fluorine-doped TEOS, and the like.

P-0033[0033] With reference now to step <b>306</b> of FIG. 3, the present embodiment recites depositing a second etch stop layer <b>208</b>. Second etch stop layer <b>208</b> is shown in FIG. 2D overlying material <b>206</b>. In the present embodiment, second etch stop layer <b>208</b> is comprised of an oxy-nitride (ONO) layer. Although such a material is recited as comprising second etch stop layer <b>208</b> in the present embodiment, the present invention is also well suited to the use of various other types of materials for second etch stop layer <b>208</b>.

P-0034[0034] At step <b>308</b> of FIG. 3, the present embodiment recites depositing a layer, shown in FIG. 2E, of a second material <b>210</b> above second etch stop layer <b>208</b>. In the present embodiment, layer of second material <b>210</b> is comprised of a material which has an etch selectivity with respect to second etch stop layer <b>208</b>. That is, layer of second material <b>210</b> is comprised of a material that can be etched using an etching process wherein the etching process does not significantly etch second etch stop layer <b>208</b>. Similarly, second etch stop layer <b>208</b> is comprised of a material that can be etched using a different etching process wherein the different etching process does not significantly etch layer of second material <b>210</b>. In the present embodiment, layer of second material <b>210</b> is comprised of an intermetal dielectric (IMD) material such as, for example, silicon dioxide. Although such an IMD material is recited in the present embodiment, the present embodiment is well suited to the use of any other material into which it is desired to form a via. Other materials which are well suited for use as the first material include, but are not limited to, tetraethylorthosilicate (TEOS), fluorine-doped TEOS, and the like. Additionally, in one embodiment of the present invention, layer of first material <b>206</b> and layer of second material <b>210</b> are comprised of the same material.

P-0035[0035] Referring still to step <b>308</b>, in the present embodiment both layer of first material <b>206</b> and layer of second material <b>210</b> have an etch selectivity with respect to a third material (which is discussed in detail below) such that the third material can be etched using an etching process wherein the etching process does not significantly etch layer of first material <b>206</b> or layer of second material <b>210</b>. Additionally, the deposition and of first etch stop layer <b>204</b>, layer of first material <b>206</b>, second etch stop layer <b>208</b>, and layer of second material <b>210</b> are consistent with existing damascene process flows.

P-0036[0036] At step <b>310</b>, the present embodiment recites forming a first opening, opening <b>212</b> of FIG. 2F, through layer of second material <b>212</b>. As shown in FIG. 2F, first opening <b>212</b> extends through layer of second material <b>212</b> and terminates at second etch stop layer <b>208</b>. In the present embodiment, etching of layer of second material <b>210</b> is accomplished using a dry etch such as, for example, a plasma etch. Although such an etching process is recited in the present embodiment, the present invention is also well suited to the use of various other etching processes.

P-0037[0037] At step <b>312</b>, the present embodiment recites forming a second opening, opening <b>214</b> of FIG. 2G, through layer of first material <b>206</b>. As shown in FIG. 2F, first opening <b>212</b> extends through second etch stop layer <b>208</b> and through layer of first material <b>206</b>. In the FIG. 2F, opening <b>214</b> is also shown extending through first etch stop layer <b>204</b> and terminating at the top surface of target <b>203</b>. As mentioned above, layer of first material <b>206</b> and layer of second material <b>210</b> are comprised of material which has an etch selectivity with respect to first and second etch stop layers <b>204</b> and <b>208</b>, respectively. That is, layer of second material <b>210</b> is comprised of a material that can be etched using an etching process wherein the etching process does not significantly etch second etch stop layer <b>208</b>. Similarly, layer of first material <b>206</b> is comprised of a material that can be etched using an etching process wherein the etching process does not significantly etch first etch stop layer <b>204</b>. It will be understood, therefore, that various breakthrough etches may be performed to etch through either first etch stop layer <b>208</b> or second etch stop layer <b>204</b> to allow for the completion of the present damascene process formed via (i.e. the via comprised of opening <b>212</b> and <b>214</b>).

P-0038[0038] Referring still to step <b>312</b> and to FIG. 2G, in the present embodiment, second opening <b>214</b> originates at the bottom of first opening <b>212</b>. Each of first opening <b>212</b> and second opening <b>214</b> have sidewalls and a base. Additionally, in the present embodiment second opening <b>214</b> has a smaller diameter than a diameter of first opening <b>212</b>. Although such opening dimensions are shown in the present embodiment, the present invention is also well suited to the formation of a greater of lesser number of damascene process formed openings having various other physical dimensions.

P-0039[0039] At step <b>314</b>, the present embodiment recites depositing a third material, material <b>216</b> of FIG. 2H, above layer of second material <b>210</b> and into openings <b>212</b> and <b>214</b>. In the present embodiment, third material <b>216</b> is disposed along the sidewalls and above the base of each of first opening <b>212</b> and second opening <b>214</b>. In one embodiment, third material <b>216</b> is comprised of an organic-based spin-on-glass material (e.g. HSQ, MSQ, and the like) which has an etch selectivity with respect to layer of first material <b>206</b> and layer of second material <b>210</b>. Although such a material is recited in the present embodiment, the present embodiment is well suited to the use of any other material for third material <b>216</b> as long as the material has an etch selectivity with respect to layer of first material <b>206</b> and layer of second material <b>210</b>. Hence, third material <b>216</b> may be etched without significantly etching first etch stop layer <b>204</b>, layer of first material <b>206</b>, second etch stop layer <b>208</b>, or layer of second material <b>210</b>.

P-0040[0040] Referring still to step <b>314</b> and FIG. 2H, as mentioned above, third material <b>216</b>, is comprised of a conformal material which has an etch selectivity with respect to layer of first material <b>206</b> and layer of second material <b>210</b>. Additionally, in the present embodiment, third material <b>216</b> is deposited to a depth which corresponds to the critical dimension, CD, of the via to be formed by the present damascene process. For example, in one embodiment, third material <b>216</b> is deposited to a depth of approximately 10-30 percent of the CD of the via to be formed (e.g. the diameter of opening <b>212</b>). As an example, where opening <b>212</b> is to have a width or CD of 0.5 microns, third material <b>216</b> will be deposited with a depth of approximately 0.05 to 0.15 microns (i.e. 500 to 1500 Angstroms). Although such a depth for third material <b>216</b> is recited in the present embodiment, the present embodiment is well suited to depositing third material <b>216</b> to various greater or lesser depths. More importantly, in the present embodiment, third material <b>216</b> should conformally cover the sidewalls and the base of each of first opening <b>212</b> and second opening <b>214</b>.

P-0041[0041] Referring now to step <b>316</b>, the present embodiment then etches third material <b>216</b> such that an opening extends to the top surface of target <b>203</b> as shown in FIG. 2I. Referring now to FIG. 2I, for purposes of clarity, in the structure remaining after step <b>316</b>, third material <b>216</b> is shown combined with layer of first material first layer <b>204</b> of the second material and second layer <b>204</b> of the second material are shown in combination as layer <b>214</b>. The etching process which etches third material <b>216</b> does not substantially etch layer of first material <b>206</b> or layer of second material <b>210</b>. Importantly, in the present embodiment, the remaining opening, opening <b>217</b>, has a profile conducive to the adherence of overlying material thereto. That is, unlike vias generated using prior art damascene processes, opening <b>217</b> of the present embodiment has a profile including rounded corners <b>218</b><i>a </i>and <b>218</b><i>b</i>, and <b>220</b><i>a </i>and <b>220</b><i>b</i>. By having rounded top edge corners <b>218</b><i>a </i>and <b>218</b><i>b</i>, and <b>220</b><i>a </i>and <b>220</b><i>b</i>, as opposed to the sharp corners associated with prior art vias, opening <b>217</b> does not induce stress in subsequently deposited overlying layers. Hence, opening <b>217</b> of the present embodiment does not deleteriously reduce adherence of overlying layers thereto. Additionally, in one embodiment of the present invention, unlike vias generated using prior damascene-process based via formation methods, opening <b>217</b> of the present embodiment has a profile including sloped sidewalls. By having sloped sidewalls, as opposed to the vertical sidewalls associated with prior damascene process-based vias, opening <b>217</b> readily accommodates the adherence of overlying materials thereto. Hence, opening <b>217</b> of the present embodiment does not deleteriously reduce adherence of overlying layers thereto.

P-0042[0042] Referring still to step <b>316</b> of FIG. 3, in this embodiment, the damascene-based via formation method of the present embodiment is readily manufactured using existing semiconductor fabrication processes. That is, the present damascene-based via formation method is compatible with existing semiconductor fabrication processes. Additionally, as will be discussed below in conjunction with another embodiment of the present embodiment, via <b>217</b> of the present embodiment enables the formation of a metallized interconnect which does not suffer from void/seam formation.

P-0043[0043] With reference now to FIG. 4, a flow chart <b>400</b> is shown of steps performed in accordance with another embodiment of the present claimed invention in which a metallized interconnect is formed. As shown in flow chart <b>400</b>, the method of the present embodiment includes the steps and features of the above-described embodiment (i.e. as recited in steps <b>302</b>-<b>316</b>, and shown in FIGS. <b>2</b>A-<b>2</b>I). For purposes of brevity and clarity, a discussion of these steps is not repeated here. The method of the present embodiment includes additional steps <b>402</b> and <b>404</b> which are described below in detail.

P-0044[0044] At step <b>402</b>, as illustrated in FIG. 2J, the present embodiment deposits a layer <b>222</b> of a fourth material above the structure of FIG. 2I and into via <b>217</b>. Moreover, due to the profile of opening <b>217</b> as described above in detail, layer <b>222</b> of the fourth material adheres strongly to the edges of opening <b>217</b>. That is, because opening <b>217</b> has rounded top edge corners <b>218</b><i>a </i>and <b>218</b><i>b</i>, and <b>220</b><i>a </i>and <b>220</b><i>b</i>, via <b>217</b>, facilitates adherence of thereto by a subsequently deposited overlying layer (e.g. layer <b>222</b> of fourth material). As a result, the present embodiment does not suffer from corner nucleation (caused in part by sharp opening edges), and subsequent void and/or seam formation in layer <b>222</b> of the fourth material. In one embodiment of the present invention, layer <b>222</b> of fourth material is comprised of a conductive metallic layer such as, for example, tungsten. Although such a conductive material is recited in the present embodiment, the present embodiment is well suited to the use of any other conductive material from which it is desired to form a metallized interconnect. Other materials which are well suited for use as the third material include, but are not limited to, aluminum, copper, various alloys, and the like.

P-0045[0045] At step <b>404</b>, and as illustrated in FIG. 2K, the present embodiment completes the formation of the metallized interconnect by performing a planarization step to remove fourth material <b>222</b> disposed above layer of second material <b>210</b> such that excess fourth material is removed and such that fourth material <b>222</b> remains only in opening <b>217</b>. As a result, the present embodiment provides a metallized interconnect which is substantially free of the voids and/or seams associated with metallized interconnects formed in conjunction with conventional damascene process-based vias.

P-0046[0046] Thus, the present invention provides a method for forming a via in a damascene process wherein the via does not suffer from poor adherence to a subsequently deposited overlying layer. The present invention further provides a method for forming a via in a damascene process which enables the formation of a metallized interconnect wherein the method achieves the above accomplishment and wherein the metallized interconnect does not suffer from void/seam formation. The present invention also provides a method for forming a via in a damascene process wherein the method achieves all of the above-listed accomplishments and wherein the method is compatible with existing semiconductor fabrication processes.

P-0047[0047] The foregoing descriptions of specific embodiments of the present invention have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed, and obviously many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims appended hereto and their equivalents.