Semiconductor device and method for the fabrication thereof

BACKGROUND OF THE INVENTION

P-0001[0001] The present invention relates to a semiconductor device provided with semiconductor elements and to a method for the fabrication of such a semiconductor device. The present invention relates more particularly to a semiconductor device protecting its semiconductor elements and securing establishment of electrical connections between the semiconductor elements and external equipment.

P-0002[0002] In recent years, since electronic equipment is becoming smaller and smaller in size and being highly improved in function, there have been strong demands for improvement in packaging density as well as the miniaturization and the high operation rate of the semiconductor device. In order to meet these demands, various forms of packaging have been developed. For example, the COC (Chip On Chip) module has been developed as a packaging form (Japanese Unexamined Patent Gazette No. H10-32307).

P-0003[0003] Hereinafter, a semiconductor device of a conventional COC module (hereinafter referred to as the “COC”) and a method for the fabrication of such a COC will be described with reference to FIG. 5.

P-0004[0004]FIG. 5 schematically shows a cross section of the conventional COC <b>100</b>. The COC <b>100</b> includes a first semiconductor chip <b>101</b> containing a first semiconductor integrated circuit part and a second semiconductor chip <b>102</b> containing a second semiconductor integrated circuit part. These first and second semiconductor chips <b>101</b> and <b>102</b> are electrically connected together by a face-down technique. Since the face-down technique is used, the major surface of the semiconductor chip <b>102</b> faces downward while the backside surface of the semiconductor chip <b>102</b> faces upward.

P-0005[0005] The first semiconductor chip <b>101</b> is mounted on a die pad <b>106</b><i>a </i>of a lead frame <b>106</b>, and the second semiconductor chip <b>102</b>, located above the first semiconductor chip <b>101</b>, is smaller in chip size than the first semiconductor chip <b>101</b>. Both the first semiconductor chip <b>101</b> and the second semiconductor chip <b>102</b> are encapsulated with an encapsulating resin <b>108</b>.

P-0006[0006] Formed on the major surface of the first semiconductor chip <b>101</b> are a plurality of first element electrodes <b>103</b> electrically connected to the first semiconductor integrated circuit part. On the other hand, formed on the major surface of the second semiconductor chip <b>102</b> are a plurality of second element electrodes <b>104</b> electrically connected to the second semiconductor integrated circuit part. The first semiconductor chip <b>101</b> and the second semiconductor chip <b>102</b> are placed such that their major surfaces face each other, and a portion <b>103</b><i>a </i>of the first element electrodes <b>103</b> of the first semiconductor chip <b>101</b> and the second element electrodes <b>104</b> of the second semiconductor chip <b>102</b> are connected together electrically by a connection member (for example, a bump) <b>105</b>. Further, a portion <b>103</b><i>b </i>of the first element electrodes <b>103</b> of the first semiconductor chip <b>101</b> is electrically connected to an external lead (an external electrode) <b>106</b><i>b </i>of the lead frame <b>106</b> by a boding wire (for example, a wire of Au).

P-0007[0007] Referring still to FIG. 5, a method for the fabrication of the conventional COC <b>100</b> will be described below.

P-0008[0008] First, the first semiconductor chip <b>101</b> and the second semiconductor chip <b>102</b> are prepared. Following this, the connection member <b>105</b>, made of solder or the like, is formed on each of the second element electrodes <b>104</b> of the second semiconductor chip <b>102</b>. Next, the second semiconductor chip <b>102</b> is mounted onto the first semiconductor chip <b>101</b> such that each of the second element electrodes <b>104</b> of the second semiconductor chip <b>102</b> is connected to each of the first element electrode portions <b>103</b><i>a </i>of the first semiconductor chip <b>101</b> through the connection member <b>105</b>. Then, the connection member <b>105</b> is melted, thereby electrically connecting together the second element electrodes <b>104</b> of the second semiconductor chip <b>102</b> and the first element electrode portions <b>103</b><i>a </i>of the first semiconductor chip <b>101</b>.

P-0009[0009] Next, the first semiconductor chip <b>101</b> is mounted onto the die pad <b>106</b><i>a </i>of the lead frame <b>106</b>. This is followed by wire bonding of electrically connecting together the first element electrode portion <b>103</b><i>b </i>of the first semiconductor chip <b>101</b> and the external lead <b>106</b><i>b </i>of the lead frame <b>106</b> by a bonding wire (for example, a wire of Au). Lastly, the fist semiconductor chip <b>101</b>, the second semiconductor chip <b>102</b>, the die pad <b>106</b><i>a </i>of the lead frame <b>106</b>, and a portion of the external lead <b>106</b><i>b </i>of the lead frame <b>106</b> are all encapsulated by the encapsulating resin <b>108</b>, and the COC <b>100</b> is obtained.

P-0010[0010] However, the conventional COC <b>100</b> has difficulties in being multipin-ized to a further extent. That is, in the COC <b>100</b>, external connection is established by the external lead <b>106</b><i>b </i>extracted from a lateral surface of the encapsulating resin (the package) <b>108</b>, which makes it difficult to further provide many external electrodes (external terminals). Furthermore, the external dimensions of the COC <b>100</b> are constrained by the package dimensions such as the size of the lead frame <b>106</b>. Therefore, it is difficult to reduce the size of the COC <b>100</b>.

P-0011[0011] Bearing in mind the above-described problems, the present invention was made. Accordingly, a major object of the present invention is to provide a semiconductor device capable of coping with multipin-ization and reducible in size and a method for the fabrication of such a semiconductor device.

SUMMARY OF THE INVENTION

P-0012[0012] The present invention provides, in order to achieve the aforesaid object, a semiconductor device which comprises (a) a first semiconductor element having a major surface on which a plurality of first element electrodes are disposed, (b) a second semiconductor element having a major surface on which a plurality of second element electrodes are disposed, the major surface of the second semiconductor element facing the major surface of the first semiconductor element, (c) a connection member electrically connecting together at least a portion of the plural first element electrodes of the first semiconductor element and at least a portion of the plural second element electrodes of the second semiconductor element, (d) an insulation layer coating the major surface of the first semiconductor element and a backside surface of the second semiconductor element, (e) an opening portion formed in the insulation layer and exposing at least a portion of the plural first element electrodes, (f) a wiring layer formed on the insulation layer and electrically connected to the first element electrode exposed in the opening portion, and (g) a plurality of external electrodes formed, as portions of the wiring layer, on the insulation layer and electrically connectable to external equipment.

P-0013[0013] In an embodiment of the present invention, the first semiconductor element and the second semiconductor element are a semiconductor chip, respectively, and the area of the major surface of the first semiconductor element is greater than the area of the major surface of the second semiconductor element. Further, in an embodiment of the present invention, the first semiconductor element is a semiconductor chip formed in a semiconductor wafer.

P-0014[0014] It is preferable that at least a portion of the plural external electrodes is formed on the insulation layer located over the backside surface of the second semiconductor element.

P-0015[0015] In an embodiment of the present invention, the second semiconductor element has on its backside surface at least one external electrode electrically connectable to external equipment.

P-0016[0016] The semiconductor device of the present invention may further comprise a passivation film formed on the major surface of the first semiconductor element and having opening portions exposing the plural first element electrodes, wherein the insulation layer is formed on the passivation film.

P-0017[0017] The semiconductor device of the present invention may further comprise metal balls provided on the external electrodes.

P-0018[0018] The present invention provides a method for the fabrication of a semiconductor device comprising the steps of (a) preparing a first semiconductor element having a major surface on which a plurality of first element electrodes are disposed and a second semiconductor element having a major surface on which a plurality of second element electrodes are disposed, (b) placing the first and second semiconductor elements such that their major surfaces face each other, and thereafter electrically connecting together at least a portion of the plural first element electrodes of the first semiconductor element and at least a portion of the plural second element electrodes of the second semiconductor element by a connection member, (c) forming an insulation layer coating a backside surface of the second semiconductor element and the major surface of the first semiconductor element, (d) forming in the insulation layer an opening portion exposing at least a portion of the plural first element electrodes, and (e) forming on the insulation layer a wiring layer which is electrically connected to the first element electrode exposed in the opening portion, a portion of the wiring layer functioning as an external electrode electrically connectable to external equipment.

P-0019[0019] It is preferable for the method of the present invention to comprise a step of grinding the backside surface of the second semiconductor element, wherein the step of grinding is performed after the step of electrically connecting together at least the aforesaid portion of the plural first element electrodes and at least the aforesaid portion of the plural second element electrodes.

P-0020[0020] It is preferable for the method of the present invention to comprise a step of filling an encapsulating resin between the major surfaces of the first and second semiconductor elements facing each other, wherein the step of filling is performed after the step of electrically connecting together at least the aforesaid portion of the plural first element electrodes and at least the aforesaid portion of the plural second element electrodes.

P-0021[0021] In an embodiment of the present invention, after the step of forming the opening portions in the insulation layer, a step of grinding both the insulation layer and the backside surface of the second semiconductor element and a step of forming another insulation layer on the ground insulation layer and on the ground backside surface of the second semiconductor element, are carried out.

P-0022[0022] It is preferable for the fabrication method of the present invention to further comprise a step of providing metal balls on the external electrode.

P-0023[0023] In an embodiment of the present invention, the step of preparing the first and second semiconductor elements is a step of preparing a semiconductor wafer in which a plurality of the first semiconductor elements are formed and preparing a plurality of the second semiconductor elements corresponding to the plural first semiconductor elements formed in the semiconductor wafer, respectively, and after the step of forming the wiring layer a step of dividing the semiconductor wafer is performed such that the plural first semiconductor elements are separated into individual units.

P-0024[0024] In an embodiment of the present invention, the step of preparing the first and second semiconductor elements is a step of preparing the first and second semiconductor elements which are semiconductor chips.

P-0025[0025] In the semiconductor device of the present invention, external electrodes are formed on the insulation layer with which the major surface of the first semiconductor element and the backside surface of the second semiconductor element are coated, whereby a two-dimensional arrangement of external electrodes becomes possible to make. This therefore provides a semiconductor device on which a much greater number of external electrodes can be formed, when compared with the conventional semiconductor device using, as an external electrode, an external lead extracted from a lateral surface of the conventional semiconductor device. Further, the semiconductor device of the present invention differs from the conventional semiconductor device in using no lead frame, and in the semiconductor device of the present invention the external electrodes are formed on the insulation layer located on the major surface of the first semiconductor element, whereby the semiconductor device of the present invention can be of the size of the first semiconductor element. The present invention therefore provides a further down-sized semiconductor device than the conventional semiconductor device which is dimensionally constrained by the size of lead frame or the like. If external electrodes are formed on the insulation layer located on the backside surface of the second semiconductor element, this makes it possible to use the entire top surface of the semiconductor device for the layout of external electrodes.

P-0026[0026] When external electrodes are formed on the backside surface of the second semiconductor element, this guides heat, generated in the second semiconductor element, directly to external equipment (e.g., a wiring substrate) where the heat is released. Therefore, the heat releasabiltiy of the semiconductor device can be improved.

P-0027[0027] When a passivation film is formed on the major surface of the first semiconductor element, the first semiconductor integrated circuit part, contained in the first semiconductor element, can be protected by the passivation film. When a metal ball is provided on the external electrode, this makes it possible to electrically connecting together the external electrode and the wiring substrate through the metal ball in a simple and quick process. Additionally, the provision of the metal ball on the external electrode makes it possible to widen the distance between the external electrode and the wiring substrate, thereby relaxing thermal stress caused by the difference in linear expansion coefficient between the semiconductor device and the wiring substrate and applied to a joint between the semiconductor device and the wiring substrate.

P-0028[0028] In the semiconductor device fabrication method of the present invention, the step of forming on the insulating layer the wiring layer, which is electrically connected to the first element electrode and portions of which function as external electrodes, is carried out. Thus, the first element electrode and the external electrode can be connected together electrically without using a wire bonding technique used in the conventional technology. Therefore, the present invention is able to provide formation of finer wiring in comparison with the prior art technology. Further, wiring collectively formable in a semiconductor wafer can be prepared and the length of wiring can be made shorter in comparison with the conventional technology, thereby enabling fabrication of a semiconductor device exhibiting improved electrical characteristics.

P-0029[0029] The thickness of the semiconductor device can be reduced by grinding of the backside surface of the second semiconductor element. When using a pre-thinned second semiconductor element, its handling is difficult because of possible chip breakage or the like. On the other hand, such handling difficulty can be reduced by subjecting to the backside surface of the second semiconductor element to grinding.

P-0030[0030] In the case that encapsulating resin is filled between the major surface of the first semiconductor element and the major surface of the second semiconductor element, the strength of joining together these semiconductor elements is enhanced. Moreover, such encapsulating-resin filling prevents formation of voids between the major surface of the first semiconductor element and the major surface of the second semiconductor element, thereby preventing the semiconductor device from undergoing cracking due to expansion of water vapor collected in a void. Therefore, semiconductor devices, which are advantageous in being subjected to testing on water absorption and reflow resistance, can be fabricated.

P-0031[0031] In the case that both the insulation layer and the backside surface of the second semiconductor chip are ground and another insulation layer is formed on the ground insulation layer and on the ground backside surface of the second semiconductor chip, the planarity of the insulation layer is secured and the planarity of the external electrode is made good. Preparation of a semiconductor wafer in which a plurality of the first semiconductor elements have been formed makes it possible to carry out each of the fabrication steps in the semiconductor wafer state, therefore considerably reducing manufacturing costs.

BRIEF DESCRIPTION OF THE DRAWINGS

P-0032[0032]FIG. 1A is a partial cutaway view schematically showing a semiconductor device <b>10</b> according to a first embodiment of the present invention and FIG. 1B is a cross-sectional view schematically showing the semiconductor device <b>10</b>.

P-0033[0033]FIG. 2A is a partial cutaway view schematically showing a semiconductor device <b>30</b> according to the first embodiment and FIG. 2B is a cross-sectional view schematically showing the semiconductor device <b>30</b>.

P-0034[0034] FIGS. <b>3</b>A-<b>3</b>G cross-sectionally show respective steps of a method for the fabrication of a semiconductor device according to a second embodiment of the present invention.

P-0035[0035] FIGS. <b>4</b>A-<b>4</b>G cross-sectionally show respective steps of the semiconductor device fabrication method of the second embodiment.

P-0036[0036]FIG. 5 is a cross-sectional view schematically showing a semiconductor device <b>100</b> as known in the prior art.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

P-0037[0037] Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. In the drawings, components having substantially the same function have been assigned the same reference numeral for the purpose of simplifying the description of the present invention. The present invention will not be limited to the following embodiments.

P-0038[0038] Embodiment 1

P-0039[0039] A first embodiment of the present invention will be described with reference to FIG. 1. FIG. 1A is a schematic of the top surface of the semiconductor device <b>10</b> according to the present embodiment. A portion of the semiconductor device <b>10</b> is cut away to provide an explanation of the internal structure of the semiconductor device <b>10</b>. FIG. 1B schematically shows a cross section of the semiconductor device <b>10</b>.

P-0040[0040] The semiconductor device <b>10</b> of the present embodiment includes a first semiconductor element (a first semiconductor chip) <b>11</b> having a major surface <b>11</b><i>a </i>on which a plurality of first element electrodes <b>12</b> are disposed, a second semiconductor element (a second semiconductor chip) <b>13</b> having a major surface <b>13</b><i>a </i>on which a plurality of second element electrodes <b>14</b> are disposed, an insulation layer <b>17</b> formed on the major surface <b>11</b><i>a </i>of the first semiconductor chip <b>11</b> so as to cover the second semiconductor chip <b>13</b>, and a wiring layer <b>22</b> formed on the insulation layer <b>17</b>. The wiring layer <b>22</b> is electrically connected to a portion <b>12</b><i>b </i>of the first element electrodes <b>12</b>, and a land <b>23</b>, which functions as an external electrode electrically connectable to external equipment (not shown), is formed in a portion of the wiring layer <b>12</b>. As shown in the figure, a metal ball <b>25</b> is provided on the land <b>23</b>, and it is preferable that a solder resist film <b>24</b> be formed on regions of the top surface of the semiconductor device other than where the metal balls <b>25</b> are located.

P-0041[0041] The first semiconductor chip <b>11</b> contains therein a first semiconductor integrated circuit part (not shown), and the first element electrode <b>12</b> of the first semiconductor chip <b>11</b> is electrically connected to the first semiconductor integrated circuit part. On the other hand, the second semiconductor chip <b>13</b> contains therein a second semiconductor integrated circuit part (not shown), and the second element electrode <b>14</b> of the second semiconductor chip <b>13</b> is electrically connected to the second semiconductor integrated circuit part. Preferably, a passivation film (not shown) having an opening portion exposing the first element electrode <b>12</b> is formed on the major surface <b>11</b><i>a </i>of the first semiconductor chip <b>11</b> for giving protection to the first semiconductor integrated circuit.

P-0042[0042] The first semiconductor chip <b>11</b> and the second semiconductor chip <b>13</b> are placed such that their major surfaces <b>11</b><i>a </i>and <b>13</b><i>a </i>face each other, and the major surface <b>13</b><i>a </i>of the second semiconductor chip <b>13</b> faces downward while on the other hand a backside surface <b>13</b><i>b </i>of the second semiconductor chip <b>13</b> faces upward. The second element electrodes <b>14</b> of the second semiconductor chip <b>13</b> are electrically connected, through a connection member <b>15</b>, to a portion <b>12</b><i>a </i>of the first element electrodes <b>12</b> of the first semiconductor chip <b>11</b>.

P-0043[0043] In the present embodiment, the first element electrode portions <b>12</b><i>a </i>electrically connected to the second element electrodes <b>14</b> of the second semiconductor chip <b>13</b> are placed at the middle of the major surface <b>11</b><i>a </i>of the semiconductor chip <b>11</b>. The first element electrodes <b>12</b> other than the first element electrode portions <b>12</b><i>a</i>, i.e., the first element electrode portions <b>12</b><i>b</i>, are placed at the outer periphery of the major surface <b>11</b><i>a </i>of the first semiconductor chip <b>11</b>. The size of the second semiconductor chip <b>13</b> is smaller than that of the first semiconductor chip <b>11</b>. In other words, the area of the major surface <b>13</b><i>a </i>of the second semiconductor chip <b>13</b> is smaller than the area of the major surface <b>11</b><i>a </i>of the first semiconductor chip <b>11</b>. In the present embodiment, for the purpose of reducing the thickness of the semiconductor device <b>10</b>, a semiconductor chip which is thinner than typical semiconductor chips is used as the second semiconductor chip <b>13</b>.

P-0044[0044] In the present embodiment, the first semiconductor element is a semiconductor chip. However, a semiconductor wafer prior to undergoing division into individual semiconductor chips may be used. That is to say, the first semiconductor chip <b>11</b> may be in the state of being formed in a semiconductor wafer. Further, the first element electrode portions <b>12</b><i>b </i>of the first semiconductor chip <b>11</b> are not necessarily provided around all the sides of the outer periphery of the major surface <b>11</b><i>a </i>of the first semiconductor chip <b>11</b>.

P-0045[0045] The connection member <b>15</b>, which provides electrical connection between the first element electrode portion <b>12</b><i>a </i>of the first semiconductor chip <b>11</b> and the second element electrode <b>14</b> of the second semiconductor chip <b>13</b>, is made of, for example, solder or conductive paste. The height of the connection member <b>15</b> is about from 5 to 150 μm and the width (or the diameter) is about from 5 to 150 μm.

P-0046[0046] In the present embodiment, the encapsulating resin <b>16</b> is filled in a space between the major surface <b>11</b><i>a </i>of the first semiconductor chip <b>11</b> and the major surface <b>13</b><i>a </i>of the second semiconductor chip <b>13</b>. Such filling by the encapsulating resin <b>16</b> provides improved reliability of connection of the first semiconductor chip <b>11</b> with the second semiconductor chip <b>13</b>. As the encapsulating resin <b>16</b>, epoxy resin can be used. Alternatively, the insulation layer <b>17</b> may be applied between the major surface <b>11</b><i>a </i>of the first semiconductor chip <b>11</b> and the major surface <b>13</b><i>a </i>of the second semiconductor chip <b>13</b>, without filling the encapsulating resin <b>16</b>.

P-0047[0047] In the case that the encapsulating resin <b>16</b> is filled, in addition to the advantage of improving the aforesaid connection reliability between the first semiconductor chip <b>11</b> and the second semiconductor chip <b>13</b>, there is produced another advantage that the gap between the major surface <b>11</b><i>a </i>of the semiconductor chip <b>11</b> and the major surface <b>13</b><i>a </i>of the semiconductor chip <b>13</b> is made free of voids. Such a measure against the creation of voids makes it possible to prevent the semiconductor device from undergoing cracking due to expansion of water vapor collected in a void. Therefore, semiconductor devices, which are advantageous in being subjected to testing on water absorption and reflow resistance, can be fabricated.

P-0048[0048] The insulation layer <b>17</b> is formed on the major surface <b>11</b><i>a </i>of the first semiconductor chip <b>11</b> and on a backside surface <b>13</b><i>b </i>of the second semiconductor chip <b>13</b>. Formed in the insulation layer <b>17</b> is an opening portion <b>21</b> exposing the first element electrode portion <b>12</b><i>b </i>of the first semiconductor chip <b>11</b>. In order to prevent disconnection of the wiring layer <b>22</b>, it is preferable to form the opening portion <b>21</b> of the insulation layer <b>17</b> in such a way that each of lateral surfaces defining the opening portion <b>21</b> and the top surface of the insulation layer <b>17</b> form an obtuse angle (for example, from about 100 to about 140 degrees).

P-0049[0049] The insulation layer <b>17</b> is made of material having insulative properties such as polymeric material (ester bonding type polyimide and acrylic epoxy). The insulation layer <b>17</b> is so thick as to cover the second semiconductor chip <b>13</b>. Preferably, the thickness of the insulation layer <b>17</b> is from about 50 to about 800 μm on the basis of the major surface <b>11</b><i>a </i>of the first semiconductor chip <b>11</b>, more preferably, about 400 μm from the viewpoint of stress absorption and semiconductor device packaging height.

P-0050[0050] It is preferable that the insulation layer <b>17</b> is made of elastic material having insulative properties, the reasons for which is as follows. If the insulation layer <b>17</b> is made of a material whose modulus of elasticity is low (for example, 2000 kg/mm²or below), thermal stress, caused by the difference in thermal expansion coefficient between the wiring substrate on which the semiconductor device <b>10</b> is mounted and the first semiconductor chip <b>11</b>, can be prevented and controlled effectively by the insulation layer <b>17</b>. Polymeric material, such as ester bonding type polyimide and acrylic epoxy, can be used as the low elasticity modulus material.

P-0051[0051] Formed on the insulation layer <b>17</b> is the wiring layer <b>22</b> as a wiring pattern electrically connected to the first element electrode portion <b>12</b><i>b </i>exposed in the opening portion <b>21</b>. The wiring layer <b>22</b> is made of copper, et cetera. Formed in a portion of the wiring layer <b>22</b> is the land <b>23</b> electrically connectable to external equipment (not shown). Since the land <b>23</b> is formed, in two dimensions, on the insulation layer <b>17</b> located over the major surface <b>11</b><i>a </i>of the semiconductor chip <b>11</b>, this allows the semiconductor device <b>10</b> of the present embodiment to cope with multipin-ization in comparison with the conventional COC <b>100</b>. Moreover, it is possible to form the lands <b>23</b> also on the insulation layer <b>17</b> located on the backside surface <b>13</b><i>b </i>of the second semiconductor chip <b>13</b>, therefore making it possible to form a great number of the lands <b>23</b> all over the top surface of the semiconductor device <b>10</b>. Further, in the semiconductor device <b>10</b> of the present embodiment, the land <b>23</b> functioning as an external electrode and the first element electrode portion <b>12</b><i>b </i>are connected together electrically by the wiring layer <b>22</b> capable of fine wiring. Therefore, when compared with the COC <b>100</b> in which a wire bonding technique is used to electrically connecting together the element electrode <b>103</b><i>b </i>and the external electrode (external lead) <b>106</b><i>b </i>by the bonding wire <b>107</b>, the size of the semiconductor device can be reduced to a further extent.

P-0052[0052] It is preferable that the metal ball <b>25</b> functioning as an external electrode terminal is joined to the land <b>23</b>. The metal ball <b>25</b> is made of, for example, solder, solder-plated copper, or nickel. The metal ball <b>25</b> is jointed to the land <b>23</b>, which makes it possible to electrically connect the land <b>23</b> and the wiring substrate through the metal ball <b>25</b> in an easy and quick process. Moreover, since the distance between the land <b>23</b> and the wiring substrate can be broadened by the metal ball <b>25</b>, this makes it possible to relax stress caused by the difference in linear expansion coefficient between the semiconductor device <b>10</b> and the wiring substrate and applied to a junction between the semiconductor device <b>10</b> and the wiring substrate.

P-0053[0053] It is preferable that the solder resist film <b>24</b> is formed in a region of the surface of the insulation layer <b>17</b> other than where the metal balls <b>25</b> are located, to cover the wiring layer <b>22</b>. That is to say, it is preferable to form the solder resist film <b>24</b> so as to cover the wiring layer <b>22</b> and expose a portion of the metal ball <b>25</b>. The solder resist film <b>24</b> prevents unwanted electrical short of the wiring layer <b>22</b> caused by the solder of the metal ball <b>25</b>. Furthermore, unwanted electrical contact of the wiring layer <b>22</b> with the wiring substrate can be prevented.

P-0054[0054] In accordance with the present embodiment, it is possible to form, in two dimensions, a plurality of the lands <b>23</b> functioning as external electrodes on the insulation layer <b>17</b>. As a result, a great number of the lands <b>23</b> can be formed all over the top surface of the semiconductor device <b>10</b>, therefore making it possible to cope with multipin-ization. Moreover, the land <b>23</b> formed over the major surface <b>11</b><i>a </i>of the first semiconductor chip <b>11</b> is made to function as an external electrode, therefore eliminating the need for using a lead frame (an external lead). Thus, it is possible to make the size of the semiconductor device <b>10</b> become the size of the first semiconductor chip <b>11</b>, as a result of which the size of the semiconductor device can be made smaller in comparison with the COC <b>100</b> that employs a lead frame. Further, since the element electrode <b>12</b> and the external electrode <b>23</b> are connected together electrically by the wiring layer <b>22</b> without using a wire bonding technique employed in the COC <b>100</b>, this makes it possible to provide formation of finer wiring when compared with the COC <b>100</b>. Furthermore, since the length of wiring can be made shorter in comparison with the COC <b>100</b>, this improves the electrical characteristics of the semiconductor device.

P-0055[0055] Additionally, as shown in FIGS. 2A and 2B, it is possible to provide a semiconductor device <b>30</b> having a structure in which a land (external electrode) <b>26</b> electrically connectable to external equipment is formed on the backside surface <b>13</b><i>b </i>of the second semiconductor chip <b>13</b> exposed from the insulation layer <b>17</b>. In the example of FIG. 2, a metal ball <b>27</b> is further formed on the land <b>26</b>. Because of such arrangement that the land <b>26</b> is formed on the backside surface <b>26</b> of the second semiconductor chip <b>13</b>, heat generated in the second semiconductor chip <b>13</b> travels to the land <b>26</b>, therefore providing a structure capable of direct heat release to external equipment (for example, a wiring substrate). As a result, the heat releasabiltiy of the semiconductor device can be improved. In the example of FIG. 2, the second semiconductor chip <b>13</b> has a common thickness. However, the second semiconductor chip <b>13</b>, which is thinner than usual, may be used.

P-0056[0056] Embodiment 2

P-0057[0057] Hereinafter, a method for the fabrication of a semiconductor device according to a second embodiment of the present invention will be described with reference to FIGS. <b>3</b>A-<b>3</b>G and FIGS. <b>4</b>A-<b>4</b>G. FIGS. <b>3</b>A-<b>3</b>G and FIGS. <b>4</b>A-<b>4</b>G illustrate in cross section respective steps of the semiconductor device fabrication method of the present embodiment.

P-0058[0058] First, as shown in FIG. 3A, a semiconductor wafer <b>50</b> is prepared. The semiconductor wafer <b>50</b> includes a plurality of the first semiconductor chips <b>11</b> on which the first element electrodes <b>12</b> are formed. Not the semiconductor wafer <b>50</b> but the first semiconductor chip <b>11</b> in the chip state may be prepared.

P-0059[0059] Next, as shown in FIG. 3B, the connection member <b>15</b>, made of, for example, solder or conductive paste, is formed on the second element electrode <b>14</b> of the second semiconductor chip <b>13</b>. Thereafter, the second element electrode <b>14</b> of the second semiconductor chip <b>13</b> is placed, through the connection member <b>15</b>, onto the first element electrode portion <b>12</b><i>a </i>of the first semiconductor chip <b>11</b> and these electrodes are jointed together.

P-0060[0060] Next, as shown in FIG. 3C, the backside surface <b>13</b><i>b </i>of the second semiconductor chip <b>13</b> is ground flat. For example, this plane grinding is carried out with a back grinder usually used in the semiconductor fabrication process, so as to reduce the thickness of a semiconductor device to be fabricated. When the backside surface <b>13</b><i>b </i>of the second semiconductor chip <b>13</b> is ground in the way described above, this contributes to reducing handling difficulty. On the other hand, the pre-thinned second semiconductor element is difficult to handle because it is likely to break.

P-0061[0061] Next, as shown in FIG. 3D, the encapsulating resin <b>16</b> is filled in a gap between the first semiconductor chip <b>11</b> and the second semiconductor chip <b>13</b>. The encapsulating resin <b>16</b> is filled to enhance the strength of joining together these semiconductor chips <b>11</b> and <b>13</b>. For example, like the conventional FC packaging step, the encapsulating resin <b>16</b> is filled by dispenser application. As the encapsulating resin, epoxy resin can be used. In order to improve the reliability, it is preferable to enhance the strength of joining together the first semiconductor chip <b>11</b> and the second semiconductor chip <b>13</b> before subjecting the backside surface <b>13</b><i>b </i>of the second semiconductor chip <b>13</b> to grinding. Therefore, there can be made switching between the step of FIG. 3C and the step of FIG. 3D in the order in which they are carried out.

P-0062[0062] It is possible to advance to the next step (FIG. 3E) without performing the filling step by the encapsulating resin <b>16</b>. However, the filling of the encapsulating resin <b>16</b> is able to avoid the possibility that voids are left between the major surface <b>11</b><i>a </i>of the first semiconductor chip <b>11</b> and the major surface <b>13</b><i>a </i>of the second semiconductor chip <b>13</b>. This prevents the semiconductor device from undergoing cracking caused by expansion of water vapor collected in a void, being advantageous in being subjected to testing on water absorption and reflow resistance.

P-0063[0063] Next, as shown in FIG. 3E, the insulation layer <b>17</b> is so formed as to coat the backside surface <b>13</b><i>b </i>of the second semiconductor chip <b>13</b> and the major surface <b>11</b><i>a </i>of the first semiconductor chip <b>11</b>. The insulation layer <b>17</b> is formed as follows. A photosensitive insulating material is applied by a spin coat technique to such an extent that the backside surface <b>13</b><i>b </i>of the second semiconductor chip <b>13</b> is coated with the photosensitive insulating material. Thereafter, the photosensitive insulating material is dried. The thickness of the insulation layer <b>17</b> is preferably from about 50 to about 800 μm, more preferably about 400 μm.

P-0064[0064] When forming the insulation layer <b>17</b> coating the backside surface <b>13</b><i>b </i>of the second semiconductor chip <b>13</b> and the major surface <b>11</b><i>a </i>of the first semiconductor chip <b>11</b>, there is the possibility that stepped portions are created in the insulation layer <b>17</b> depending on the thickness and dimensions of the second semiconductor chip <b>13</b>. In this case, after forming the insulation layer <b>17</b> or after performing the next step (the step of FIG. 3F), the following step may be carried out. Both the backside surface <b>13</b><i>b </i>of the second semiconductor chip <b>13</b> and the insulation layer <b>17</b> are ground, and then a further insulation layer is formed on the ground insulation layer <b>17</b> and on the ground backside surface <b>13</b><i>b </i>of the second semiconductor chip <b>13</b>. This secures the planarity of the insulation layer <b>17</b>, therefore making the planarity of external electrodes formed on the insulation layer <b>17</b> good. It is possible to perform grinding at only this stage without performing any grinding in the step of FIG. 3C.

P-0065[0065] Next, as shown in FIG. 3F, the dried insulation layer <b>17</b> is sequentially exposed to light and developed, whereby the insulation layer <b>17</b> located on the first element electrode portions <b>12</b><i>b </i>of the first semiconductor chip <b>11</b> is selectively removed. By this, the opening portions <b>21</b> exposing the first element electrode portions <b>12</b><i>b </i>of the first semiconductor chip <b>11</b> are formed in the insulation layer <b>17</b>. When forming the opening portion <b>21</b>, it is preferable that not parallel light but diffused light (including scattered light) be used in the exposure step. The use of scattered light makes it possible to form the opening portion <b>21</b> such that the lateral surface of the opening portion <b>21</b> and the top surface of the insulation layer <b>17</b> form an obtuse angle (for example, from about 100 to about 140 degrees).

P-0066[0066] As the photosensitive insulating material used to form the insulation layer <b>17</b>, polymeric material, such as ester bonding type polyimide and acrylic epoxy, can be used. The insulation layer <b>17</b> is not limited to a particular material (any material may be used as long as it has insulating properties). As the insulating layer <b>17</b> having photosensitive properties, a material pre-formed in the form of a film may be used. In this case, it is possible to form, after the film-like insulation layer <b>17</b> is affixed onto the major surface <b>11</b><i>a </i>of the first semiconductor chip <b>11</b>, the opening portions <b>21</b> in the insulation layer <b>17</b> by sequentially carrying out exposure and development steps. Furthermore, it is possible to form the opening portions <b>21</b> by mechanical processing making use of laser or plasma, or by chemical processing such as etching after the formation of the non-photosensitive insulation layer <b>17</b>.

P-0067[0067] Next, as shown in FIG. 3G, a thin metal layer <b>18</b> is formed on the insulation layer <b>17</b> and on the first element electrode portion <b>12</b><i>b </i>of the first semiconductor chip <b>11</b> exposed in the opening portion <b>21</b>. The thin metal layer <b>18</b> can be formed by thin film formation technologies such as sputtering, vacuum evaporation, CVD, and electroless plating. In the present embodiment, the thin metal layer <b>18</b> is made up of a film of Ti having a thickness of about 0.2 μm and a film of Cu formed on the Ti film and having a thickness of about 0.5 μm.

P-0068[0068] Next, as shown in FIG. 4A, either a positive photosensitive resist film or a negative photosensitive resist film is formed on the thin metal layer <b>18</b> by a spin coat technique. Thereafter, other than desired patterns for the finished product is hardened by exposure and development technology known in the art, to prepare a plating resist film <b>19</b>.

P-0069[0069] Next, as shown in FIG. 4B, a thick metal layer <b>20</b> is selectively formed, by thick film formation technologies such as electro-plating, on regions of the thin metal layer <b>18</b> other than where the plating resist film <b>19</b> has been formed. In the present embodiment, the thick metal layer <b>20</b> is made of a film of Cu (thickness: 10 μm).

P-0070[0070] Next, as shown in FIG. 4C, after the formation of the thick metal layer <b>20</b>, the plating resist film <b>19</b> is decomposed and removed. Following this, the thin film metal layer <b>18</b> and the thick film metal layer <b>20</b> are selectively removed to form the metal wiring layer <b>22</b> as a metal wiring pattern including the land <b>23</b> and a contact portion <b>22</b><i>a </i>contacting the first element electrode portion <b>12</b><i>b</i>. The metal wiring layer <b>22</b> is formed by application of an etching liquid capable of dissolution and removal of the thin metal layer <b>18</b>. For instance, when entire surface etching is carried out by using a solution of cupric chloride for the Cu film and a solution of EDTA for the Ti film, the thin metal layer <b>18</b>, which is thinner than the thick metal layer <b>20</b>, is removed preceding the thick metal layer <b>20</b>, to form the metal wiring layer <b>22</b>. An arrangement may be made in which after the plating resist film <b>19</b> is removed an etching resist film having a desirable pattern form is formed by a photolithography technique so that the thick metal layer <b>20</b> is protected by the etching resist film.

P-0071[0071] Next, as shown in FIG. 4D, the photosensitive solder resist film <b>24</b> is formed, by a spin coat technique, on the metal wiring layer <b>22</b> and the insulation film <b>17</b>. Thereafter, as shown in FIG. 4E, an opening portion <b>24</b><i>a </i>exposing the land <b>23</b> is formed in the solder resist film <b>24</b> by a photolithography technique known in the art. The formation of the solder resist film <b>24</b> makes it possible to protect portions of the metal wiring layer <b>22</b> other than the lands <b>23</b> from melted metal balls (solder).

P-0072[0072] Next, as shown in FIG. 4F, the metal ball <b>25</b> is placed on the land <b>23</b>, following which the metal ball <b>25</b> and the land <b>23</b> are jointed together by melting. Finally, as shown in FIG. 4G, the semiconductor wafer <b>50</b> is divided by a dicing saw to obtain the semiconductor devices <b>10</b>.

P-0073[0073] In the present embodiment, without employing any wire bonding technique used in the prior art, the metal wiring layer (metal wiring pattern) <b>22</b> is formed thereby to electrically connect together the first element electrode <b>12</b> and the land <b>23</b>. Accordingly, when compared with the conventional COC <b>100</b>, it is possible to form finer wiring as well as to make the length of wiring shorter. Furthermore, in the present embodiment, each fabrication step is carried out in the semiconductor wafer state, therefore making it possible to considerably reduce manufacturing costs in comparison with the fabrication method of the COC <b>100</b>.

P-0074[0074] Other Embodiments

P-0075[0075] In the foregoing embodiments, as the material for forming the thin metal layer <b>18</b> and the thick metal layer <b>20</b>, Cu is used. However, instead of Cu, for example, Cr, W, Ti/Cu, or Ni may be used. Further, an arrangement may be made in which the thin metal layer <b>18</b> and the thick metal layer <b>20</b> are made of different materials and in the final etching step an etchant, by which only the thin metal layer <b>18</b> is selectively etched, is used.

P-0076[0076] In the foregoing embodiments, the metal ball <b>25</b> is provided. However, instead of the metal ball <b>25</b>, a projected electrode may be provided. As the projected electrode, either a solder bump formed by printing and melting of solder cream on the land <b>23</b>, a solder bump formed by dipping in melted solder, or a nickel/gold bump formed by electro-less plating may be provided. Any type of projected electrode is adequate as long as it has conductive properties and projects from the solder resist film <b>24</b>. The provision of projected electrodes eliminates the need for sequential placement of the metal balls <b>25</b> which is a time-consuming step, thereby providing low-cost semiconductor devices.

P-0077[0077] Additionally, the land grid array (LGA) configuration, in which the land <b>23</b> functions as an external electrode terminal, may be employed. When mounting on a wiring substrate a semiconductor device employing an LGA configuration, solder cream is applied onto connection terminals of the wiring substrate. Thereafter, the land <b>23</b> and the wiring substrate can be easily brought into electrical connection with each other by, for example, reflowing.

P-0078[0078] According to the present invention, it is possible to provide a semiconductor device capable of coping with multipin-ization and reducible in dimensions, in comparison with the prior art techniques, for a plurality of external electrodes are formed on the insulation layer with which both the major surface of the first semiconductor element and the backside surface of the second semiconductor element are coated. Furthermore, with the semiconductor device fabrication method of the present invention, the wiring layer, which is electrically connected to the first element electrode and a portion of the wiring layer functions as an external electrode, is formed. Therefore, in comparison with a prior art technique using the wiring bonding technique, the present invention method provides formation of finer wiring.