Constant-phase, gain-controlled amplification circuit

TECHNICAL FIELD OF THE INVENTION

P-0001[0001] The present invention relates generally to automatic gain control (AGC) circuits. More specifically, the present invention relates to gain-controlled amplifiers that may be used in radio receivers and which may benefit from high fidelity while maintaining substantially constant phase shift regardless of gain.

BACKGROUND OF THE INVENTION

P-0002[0002] Front ends of radio receivers often include gain-controlled amplifiers and automatic gain control (AGC) circuits. An AGC circuit keeps the output signal from the gain-controlled amplifier in a desired amplitude range regardless of input signal level. The desired amplitude range is typically one that allows subsequent signal processing to take place in the most effective manner. For example, when subsequent processing includes digital conversion, the output signal of the gain-controlled amplifier is often managed to use the full range of an analog-to-digital (A/D) converter to minimize the effects of quantization noise, avoid the need for a costly high-resolution A/D converter, and otherwise extend the dynamic range of the radio receiver.

P-0003[0003] While gain-controlled amplifiers provide significant benefits for receiver designs, they also pose more serious distortion problems than constant-gain amplifiers. Often, communication signals use phase to convey information. Hence, phase distortion can lead to errors in recovering the conveyed information. Often, communication signals use carriers of sufficient bandwidth so that intermodulation falls in the bandwidth of interest, either directly or through aliasing. Intermodulation can also lead to errors in recovering the conveyed information. Gain-controlled amplifiers suffer from these types of distortions more than constant-gain amplifiers.

P-0004[0004] Conventional gain-controlled amplifiers are often associated with filtering or tuning networks. Often, gain-controlled amplifiers, perhaps in conjunction with such networks, can be devised to minimize phase distortion by causing the amplifier to impart roughly equal amounts of phase shift to signals being amplified at different gains. Unfortunately, such techniques tend to cause intermodulation distortion to become unacceptably prominent. Conversely, conventional gain-controlled amplifier circuits may be devised which minimize the intermodulation distortion. However, these circuits usually suffer from a great degree of phase variance between low gain and high gain, leading to unacceptable phase distortion.

P-0005[0005] Too often, a radio receiver designer must select components and design filtering and other networks which compromise one type of distortion against the other to find a solution that just manages to work for a given application. This is an undesirable and inflexible approach that often leads to a great reduction in the population of components from which selections can be made. In a typical application, the conventional approach often leads to the use of difficult-to-obtain and expensive components. In many applications, performance suffers because the receiver front end introduces an excessive amount of distortion.

SUMMARY OF THE INVENTION

P-0006[0006] It is an advantage of the present invention that an improved constant-phase, gain-controlled amplification circuit is provided.

P-0007[0007] Another advantage of the present invention is that phase constancy is controlled independently of fidelity parameters, such as intermodulation.

P-0008[0008] Another advantage of the present invention is that a gain-controlled amplifier circuit may be configured to minimize intermodulation and/or other fidelity parameters, then phase distortion is compensated downstream of the gain-control amplifier circuit.

P-0009[0009] Another advantage of the present invention is that a gain-controlled amplification circuit is used in a radio receiver having a front end which exhibits both low phase distortion and low intermodulation distortion.

P-0010[0010] Another advantage of the present invention is that a gain-controlled amplification circuit improves radio design flexibility, making a wider range of components available for use in a given application, improving performance, and/or reducing costs.

P-0011[0011] These and other advantages are realized in one form by a constant-phase, gain-controlled amplification circuit. The amplification circuit includes a gain-controlled amplifier which generates an amplified signal exhibiting a phase shift that varies in response to amplifier gain. An automatic gain control (AGC) circuit is configured to provide a gain-control signal to the gain-controlled amplifier. A phase-shift compensator couples to the AGC circuit and the gain-controlled amplifier. The phase-shift compensator imposes a variable delay on the amplified signal. The variable delay has a duration determined in response to the gain-control signal.

BRIEF DESCRIPTION OF THE DRAWINGS

P-0012[0012] A more complete understanding of the present invention may be derived by referring to the detailed description and claims when considered in connection with the Figures, wherein like reference numbers refer to similar items throughout the Figures, and:

P-0013[0013]FIG. 1 shows a block diagram of a constant-phase, gain-controlled amplification circuit configured in accordance with a preferred embodiment of the present invention;

P-0014[0014]FIG. 2 shows a graph depicting one representative example of the intermodulation exhibited by a gain-controlled amplifier usable in a preferred embodiment of the present invention;

P-0015[0015]FIG. 3 shows a graph depicting one representative example of the phase linearity exhibited by a gain-controlled amplifier usable in a preferred embodiment of the present invention; and

P-0016[0016]FIG. 4 shows a graph depicting one representative example of delay imposed by a gain-controlled amplifier usable in a preferred embodiment of the present invention as a function of a gain-control signal.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

P-0017[0017]FIG. 1 shows a block diagram of a constant-phase, gain-controlled amplification circuit <b>10</b> configured in accordance with a preferred embodiment of the present invention. Amplification circuit <b>10</b> is used in a radio receiver <b>12</b>. In this embodiment, an input signal <b>14</b> is received at an antenna <b>15</b>. In other embodiments of the present invention, input signal <b>14</b> may be conveyed in other ways, such as by cable, optical fiber, magnetic sensing head, and the like. Input signal <b>14</b> is routed to an input of a gain-controlled amplifier <b>16</b> in the preferred embodiment.

P-0018[0018] In the preferred embodiment, gain-controlled amplifier <b>16</b> is a radio frequency (RF) semiconductor integrated circuit of a conventional design. Filtering circuits typically associated with RF amplifiers in radio receivers are omitted in FIG. 1 for the sake of clarity. While this preferred embodiment uses gain-controlled amplifier <b>16</b> in an RF stage where the problems to which the present invention are directed may be more pronounced, other embodiments can nevertheless use gain-controlled amplifier <b>16</b> in an intermediate frequency (IF) stage.

P-0019[0019]FIG. 2 shows a graph depicting one representative example of the intermodulation exhibited by a gain-controlled amplifier usable in the preferred embodiment of the present invention, and FIG. 3 shows a graph depicting one representative example of the phase linearity exhibited by a gain-controlled amplifier usable in the preferred embodiment of the present invention. Those skilled in the art will appreciate that the graphs of FIGS. 2 and 3 are for exemplary purposes only, and that gain-controlled amplifier <b>16</b> may be characterized by graphs vastly different in appearance than those depicted in FIGS. 2 and 3 and/or other parameters that characterize distortion and/or fidelity. Together, FIGS. 2 and 3 partially characterize the fidelity and distortion of a gain-controlled amplifier, such as gain-controlled amplifier <b>16</b>.

P-0020[0020]FIG. 2 depicts various orders <b>18</b> of intermodulation as a function of a gain-control signal <b>20</b>. In FIG. 2, a greater gain results from a smaller gain-control signal and a lesser gain results from a greater gain-control signal. FIG. 2 depicts intermodulation <b>18</b> in a central region F_cof a frequency band of interest. In a typical gain-controlled amplifier <b>16</b>, intermodulation <b>18</b> would be even less at lower frequencies, but somewhat higher at higher frequencies. In an ideal response <b>22</b>, depicted as a dotted line, all orders of intermodulation would collapse together at 0 dBm and remain constant regardless of gain-control signal <b>20</b>. In other words, no intermodulation <b>18</b> would be introduced by gain-controlled amplifier <b>16</b>, regardless of gain or frequency. However, in a real-world gain-controlled amplifier, such as gain-controlled amplifier <b>16</b> (FIG. 1), ideal response <b>22</b> is not practical. On the other hand, gain-controlled amplifier <b>16</b> is desirably configured so that intermodulation <b>18</b> is optimized at a relatively low level, even at the expense of worsening the phase linearity depicted in FIG. 3. In other words, fidelity may be optimized at the expense of phase linearity.

P-0021[0021]FIG. 3 depicts a family of phase shift curves <b>24</b>. Each phase shift curve <b>24</b> generally proceeds from a somewhat greater phase shift at lower frequencies to a somewhat lesser phase shift at higher frequencies. Moreover, phase shift curves <b>24</b> are spread out so that, for any given frequency, more phase shift results from operating at a lower gain than from operating at a higher gain. In an ideal response <b>26</b>, all phase shift curves <b>24</b> would collapse onto a single line of constant phase shift. The precise value of that constant phase shift would typically be of little importance. The same phase shift would be imposed regardless of gain or frequency, indicating perfect phase linearity. However, in a real-world gain-controlled amplifier, such as gain-controlled amplifier <b>16</b> (FIG. 1), ideal response <b>26</b> is not practical. Thus, a certain amount of phase non-linearity is tolerated, as illustrated by the spread between phase shift curves <b>24</b> in FIG. 3. Moreover, in the preferred embodiment, phase linearity may be somewhat poor due to the optimization of controlled-gain amplifier <b>16</b> for good fidelity.

P-0022[0022]FIG. 4 shows a graph depicting one representative example of the variable delay imposed by a gain-controlled amplifier usable in a preferred embodiment of the present invention as a function of gain-control signal <b>20</b>. In FIG. 4, a greater gain results from a smaller gain-control signal, and a lesser gain results from a greater gain-control signal. FIG. 4 presents substantially the same information conveyed in phase shift curves <b>24</b> of FIG. 3, but in a different form. In particular, frequency and phase shift information have been combined into a single delay parameter <b>28</b> in a manner well understood to those skilled in the art, and gain is depicted continuously along one axis of the graph rather than in the discrete curves used in FIG. 3. As illustrated in FIG. 4, the phase non-linearity characteristic causes gain-controlled amplifier <b>16</b> to impose a variable delay <b>28</b>, where the duration of delay <b>28</b> changes in response to the gain, as defined by gain control signal <b>20</b>. Generally, more gain causes gain-controlled amplifier <b>16</b> to impose a smaller delay <b>28</b> than less gain, as indicated by a curve <b>30</b>.

P-0023[0023] The optimizing of gain-controlled amplifier <b>16</b> for fidelity at the expense of phase linearity is well within the abilities of those skilled in the art. However, while such an optimization is desirable in the preferred embodiment of the present invention, it is not a necessity. By optimizing fidelity, even at the expense of phase linearity, improved fidelity is exhibited by amplification circuit <b>10</b> (FIG. 1). The phase non-linearity introduced at gain-controlled amplifier <b>16</b> is substantially compensated for in subsequent processing, as discussed below.

P-0024[0024] Referring back to FIG. 1, gain-controlled amplifier <b>16</b> amplifies input signal <b>14</b>, imposing an unwanted phase non-linearity, and producing an amplified signal <b>32</b>. The unwanted phase non-linearity is characterized by a phase shift <b>24</b> (FIG. 3) or delay <b>28</b> (FIG. 4) that varies in response to gain.

P-0025[0025] Amplified signal <b>32</b> is routed to a downconverter <b>34</b> in the preferred embodiment. Downconverter <b>34</b> is configured in a conventional manner which causes amplification circuit <b>10</b> to be usable as radio receiver <b>12</b>. Downconverter <b>34</b> includes mixers, oscillators, and the like, as are typically associated with downconverters in radio receivers. In the preferred embodiment, amplified signal <b>32</b>, now converted to IF or baseband, passes from downconverter <b>34</b> to a digitizer <b>36</b>. In this embodiment, digitizer <b>36</b> is provided by an analog-to-digital (A/D) converter <b>38</b>.

P-0026[0026] Digitizer <b>36</b> digitizes amplified signal <b>32</b> and also imposes a variable delay on amplified signal <b>32</b>. The delay imposed at digitizer <b>36</b> is of a duration that compensates for the phase non-linearity introduced by gain-controlled amplifier <b>16</b>. Amplified signal <b>32</b>, now digitized into a digital form, passes from digitizer <b>36</b> to a demodulator <b>40</b> and to an automatic gain control (AGC) circuit <b>42</b> in the preferred embodiment.

P-0027[0027] Demodulator <b>40</b> extracts the information conveyed by input signal <b>14</b> and amplified into amplified signal <b>32</b>, desirably making as few errors as is practical. The more effectively distortions, such as intermodulation (FIG. 2) and phase non-linearity (FIG. 3) can be minimized, the fewer errors demodulator will make, all other conditions being equal. Demodulator <b>40</b> may take any form.

P-0028[0028] AGC circuit <b>42</b> may also take any form. In particular, AGC circuit <b>42</b> may be a relatively fast or slow AGC circuit, and AGC circuit <b>42</b> may be adapted to work with any of a wide variety of modulation formats. AGC circuit <b>42</b> may be primarily of a digital construction, as provided for the preferred embodiment, or AGC circuit <b>42</b> may alternatively be primarily of an analog construction. In an embodiment of the present invention where AGC circuit <b>42</b> is of an analog construction, amplified signal <b>32</b> from upstream of digitizer <b>36</b> may desirably be used to drive AGC circuit <b>42</b> rather than from downstream of digitizer <b>36</b> as shown in FIG. 1. Regardless of speed, modulation format, analog or digital construction, and the like, ACG circuit <b>42</b> generates gain-control signal <b>20</b> in a manner well understood to those skilled in the art. In the preferred embodiment, gain-control signal <b>20</b> is an analog signal, but in other embodiments gain-control signal <b>20</b> may be a digital signal.

P-0029[0029] Gain-control signal <b>20</b> passes through a synchronizer <b>44</b>, specifically provided by a sample and hold (S/H) circuit <b>46</b> in the preferred embodiment, to a gain-control input of gain-controlled amplifier <b>16</b>. Gain-control signal <b>20</b> also passes to a phase-shift compensator <b>48</b>. Gain-control signal <b>20</b> establishes the amount of gain that gain-controlled amplifier <b>16</b> should impart to input signal <b>14</b>. In addition, gain-control signal <b>20</b> also indirectly indicates the duration of delay that gain-controlled amplifier <b>16</b> will impose on amplified signal <b>32</b>. The relationship between gain-control signal <b>20</b> and delay is presented in the form of one representative example by curve <b>30</b> in FIG. 4.

P-0030[0030] A clock generator <b>50</b> generates a basic clock signal <b>52</b> that eventually drives digitizer <b>36</b>. However, an input of phase-shift compensator <b>48</b> is adapted to receive clock signal <b>52</b>, and phase-shift compensator <b>48</b> is configured to generate an adjusted clock signal <b>54</b>, which is routed to a clock input <b>56</b> of A/D <b>38</b> and to a clock input <b>58</b> of S/H <b>46</b> in the preferred embodiment. In generating adjusted clock signal <b>54</b>, phase-shift compensator <b>48</b> delays clock signal <b>52</b> by a duration which varies in response to gain-control signal <b>20</b>.

P-0031[0031] In the preferred embodiment, phase-shift compensator <b>48</b> includes an A/D <b>60</b>, a look-up table (LUT) <b>62</b>, and a programmable delay element <b>64</b>. A/D <b>60</b> receives gain-control signal <b>20</b>, which is in an analog form in the preferred embodiment, and converts signal <b>20</b> into a digital form. This digital form of signal <b>20</b> couples to address inputs of a memory device which serves as LUT <b>62</b>. Data outputs of LUT <b>62</b> provide a stream of delay values <b>66</b>, which are provided to control inputs <b>68</b> of programmable delay element <b>64</b>. A signal input <b>70</b> of programmable delay element <b>64</b> is adapted to receive clock signal <b>52</b>, and a signal output <b>72</b> of programmable delay element <b>64</b> generates adjusted clock signal <b>54</b>.

P-0032[0032] LUT <b>64</b> desirably implements a difference between a constant duration <b>74</b> and relationship <b>30</b>, as depicted by difference relationship <b>76</b> in FIG. 4. That constant duration is desirably greater than the greatest delay imposed by gain-controlled amplifier <b>16</b>. Desirably, the derivative of relationship <b>30</b> with respect to gain-control signal <b>20</b> substantially equals the negative of the derivative of relationship <b>76</b> with respect to gain-control signal <b>20</b>.

P-0033[0033] In the preferred embodiment, difference relationship <b>76</b> is determined in an empirical manner. For example, gain-controlled amplifiers <b>16</b>, being semiconductor integrated circuits, are desirably manufactured in relatively large batches. For each batch, one or more gain-controlled amplifiers <b>16</b> may be selected and tested to determine the delay imposed on the signal being amplified versus its gain-control signal. LUT <b>62</b> may then be programmed with the appropriate difference data, represented as a constant value minus the indicated delay, and formatted as needed so that programmable delay element <b>64</b> will implement the specified delays. Since semiconductor devices manufactured in a common batch tend to exhibit like characteristics, the same data may be used for all gain-controlled amplifiers <b>16</b> manufactured in a single batch.

P-0034[0034] Those skilled in the art will appreciate that difference relationship <b>76</b> may be implemented in different ways. For example, for some gain-controlled amplifiers <b>16</b> difference relationship <b>76</b> may approximate a linear or other curve that can be implemented using non-memory circuit design techniques. In the preferred embodiment, the programming of LUT <b>62</b> does not change over the life of amplification circuit <b>10</b>, but this is not a requirement. In other embodiments, circuits and processes located downstream of amplification circuit <b>10</b> may monitor amplified signal <b>32</b> and/or data produced by demodulator <b>40</b> and alter the programming of LUT <b>62</b> in a feedback loop that minimizes error in the data.

P-0035[0035] LUT <b>62</b> repetitively translates gain-control signal <b>20</b> into a value that specifies a duration. The specified duration changes in response to gain-control signal <b>20</b>. That duration is then imposed on amplified signal <b>32</b>. In particular, programmable delay element <b>64</b> is desirably a conventional delay chip of the type that is intended for clock de-skewing and timing adjustment. Delay values applied at control input <b>68</b> are used to indicate by how much to delay clock signal <b>52</b> in order to generate adjusted clock signal <b>54</b>. In the preferred embodiment, phase-shift compensator <b>48</b> merely delays clock signal <b>52</b> by a variable duration and does not alter the frequency of clock signal <b>52</b> in generating adjusted clock signal <b>54</b>.

P-0036[0036] Adjusted clock signal <b>54</b> is supplied to input <b>58</b> of synchronizer <b>44</b> so that amplification circuit <b>10</b> will synchronously update the delay imposed through phase-shift compensator <b>48</b> on amplified signal <b>32</b> with gain-control signal <b>20</b> applied to gain-controlled amplifier <b>16</b>. The next sampling instant defined by adjusted clock signal <b>54</b> after gain-control signal <b>20</b> changes at gain-controlled amplifier <b>16</b> will reflect a new delay responsive to the changed state of gain-control signal <b>20</b>.

P-0037[0037] Accordingly, gain-controlled amplifier <b>16</b> may introduce differing amounts of phase shift at different gain levels. However, the gain level, as expressed in gain-control signal <b>20</b>, is translated into delays of variable duration that compensate for the differing amounts of phase shift. As a result, amplified signal <b>32</b> output from digitizer <b>36</b> and input to demodulator <b>40</b> exhibits constant phase. Those skilled in the art will appreciate that constant phase is a relative, not an absolute term. Amplification circuit <b>10</b> need only demonstrate phase constancy within a predetermined phase shift tolerance. No absolute phase constancy requirement is imposed on the present invention. Within that context, the present invention provides a constant phase signal relative to the amplified signal <b>32</b> output from gain-controlled amplifier <b>16</b> that exhibits a phase shift that varies as a function of gain.

P-0038[0038] In summary, the present invention provides an improved constant-phase, gain-controlled amplification circuit <b>10</b>. Phase constancy is controlled independently of fidelity parameters, such as intermodulation. Gain-controlled amplifier <b>16</b> may be configured to minimize intermodulation and/or other fidelity parameters at the expense of unwanted phase distortion. However, phase distortion is compensated downstream of gain-control amplifier <b>16</b>. Accordingly, amplification circuit <b>10</b> is used in a radio receiver <b>12</b> having a front end which exhibits both low phase distortion and low intermodulation distortion. Amplification circuit <b>10</b> improves radio design flexibility, making a wider range of components available for use in a given application, improving performance, and/or reducing costs.

P-0039[0039] Although the preferred embodiments of the invention have been illustrated and described in detail, it will be readily apparent to those skilled in the art that various modifications may be made therein without departing from the spirit of the invention or from the scope of the appended claims. For example, digitizer <b>36</b> may be provided in alternate forms. In one example, an A/D may be clocked using a signal with timing determined independently from gain-control signal <b>20</b>, and a digital interpolator (not shown) may be inserted downstream of the A/D and used to impose the variable delay discussed herein. In another example, an A/D may be clocked using a signal with timing determined independently from gain-control signal <b>20</b>, and an analog delay element (not shown) may be inserted upstream of the A/D to impose the variable delay discussed herein. In these examples, the interpolator or upstream delay element is a part of digitizer <b>36</b> that both digitizes and delays amplified signal <b>32</b>. In other embodiments, synchronizer <b>44</b> may be formed as a part of AGC circuit <b>42</b> and/or AGC circuit <b>42</b> may provide digital addressing information directly to LUT <b>62</b>. These and other changes and modifications are intended to be included in the scope of the present invention.