US20030193936A1

Scalable switching fabric

Claim Score by NHIP

Abstract

A switch fabric includes a first plurality of data switches each having a plurality of input ports and a plurality of output ports the plurality of switches capable of switching any of its input ports to any of its output ports with the plurality of data switches having inputs coupled to a plurality of input buses so that a first byte of a first one of the input buses is coupled to a first one of the plurality of switches, and a succeeding byte of the first input bus is coupled to a succeeding one of the plurality of switches.

US20030193936A1, drawing sheet 1 — Sheet 1 of 8

Term

Term ended

Projected expiry passed 28 January 2024, 2.7 years ago.

20 claims: 4 independent, 16 dependent

1
Broadest claimClaim Score 87, broad(NHIP)A switch fabric comprises:a network switch having a plurality of inputs and outputs;and a distributed switching arrangement to provide a non-blocking switching fabric capability over a series of byte sliced buses.
5
A switch for coupling network devices to a network processor, comprises:a plurality of virtual queues;input segment logic coupled to at least one bus, said input segment logic to determine to which virtual queue incoming data should be sent to;and output segment logic to select which new Virtual Queue should be connected to an output port.
10
A switch fabric, comprises:a pair of data switches each having a plurality of input ports and a plurality of output ports the switches capable of switching any of its input ports to any of its output ports;said pair of data switches having inputs coupled to a plurality of input buses so that a first byte of a first one of the buses is coupled to the first switch, and a last byte of the first bus is coupled to the second switch.
15
A switch fabric, comprises:a first plurality of data switches each having a plurality of input ports and a plurality of output ports the plurality of switches capable of switching any of its input ports to any of its output ports;said plurality of data switches having inputs coupled to a plurality of input buses so that a first byte of a first one of the input buses is coupled to a first one of the plurality of switches, and a succeeding byte of the first input bus is coupled to a succeeding one of the plurality of switches.

Independent claims4

167 paragraphs in 4 sections, as filed

BACKGROUND

[0001] This invention relates to switching fabrics used to switch data in computer networks and other data moving applications.

[0002] Crossbars are one type of switching fabric used to switch data between pluralities of devices. They can be thought of as a switch that has a plurality of vertical paths interconnected by switching elements to a plurality of horizontal paths in a manner that the switch elements can interconnect any one of the vertical paths to any one of the horizontal paths. Generally such crossbars are implemented with custom application specific integrated circuits (ASIC's).

SUMMARY

[0003] According to an aspect of the present invention, a switch fabric includes a network switch having a plurality of inputs and outputs and a distributed switching arrangement to provide a non-blocking switching fabric capability over a series of byte sliced buses.

[0004] According to an additional aspect of the present invention, a switch for coupling network devices to a network processor, includes a plurality of virtual queues and input segment logic coupled to at least one bus, said input segment logic to determine to which virtual queue incoming data should be sent to and output segment logic to select which new virtual queue should be connected to an output port.

[0005] According to an additional aspect of the present invention, a switch fabric includes a first plurality of data switches each having a plurality of input ports and a plurality of output ports the plurality of switches capable of switching any of its input ports to any of its output ports with the plurality of data switches having inputs coupled to a plurality of input buses so that a first byte of a first one of the input buses is coupled to a first one of the plurality of switches, and a succeeding byte of the first input bus is coupled to a succeeding one of the plurality of switches.

[0006] One or more of the following advantages may be provided by one or more aspects of the invention.

[0007] A high performance, scalable switching fabric is provided for scaling a rotary switch for a multitude of ports. The rotary switch uses virtual queuing providing the rotary switch controller (RSC) full crossbar capability, such that any of its input queues can couple to any of its output queues without blocking. The RSC permits dynamic configuration of additional ports. The RSC is a modular concept allowing a switch to grow from e.g., 32 ports to 64 ports to 128 ports using a passive backplane.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008]FIG. 1 is a block diagram of a network system including a rotary switch.

[0009]FIG. 2 is block diagram showing an implementation of the rotary switch.

[0010]FIG. 3 is a block diagram of the rotary switch.

[0011]FIG. 4A is a block diagram of a rotary switch coupled in a byte sliced configuration.

[0012]FIG. 4B is a block diagram of two rotary switches coupled in a byte sliced configuration.

[0013]FIG. 5A is a chart diagram showing byte mapping for a single rotary switch of FIG. 4A.

[0014]FIG. 5B is a chart diagram showing byte mapping in the device of FIG. 4B.

[0015]FIG. 6 is a block diagram showing structures used in arbitration in the rotary switch.

DESCRIPTION

[0016] Referring to FIG. 1, a networked system 10 includes a rotary switch 12 transfering data from input ports to output ports in a non-blocking manner. For instance, the switch can be used for sending packet data at plurality of network processors 14 to network devices 16 coupled to separate 32 bit FIFO busses. The rotary switch 12 includes a data path that is sliced or partitioned on an 8 bit (i.e. byte) basis to allow system 10 to be expanded from e.g., a 2×2 FIFO bus system to an 8×8 FIFO bus system and so forth as described below. The rotary switch 12 includes a plurality of 8-bit wide Virtual Input Queues (“VIQ”) 18 that are distributed into input segments with each of 8 byte wide input segments coupled to 16 of the VIQ's 18. The rotary switch device 12 also includes a plurality of Output Segments 20.

[0017] The rotary switch 12 also includes a switching fabric network 24 which in combination with the Virtual Input Queues and output segment logic 20 can move byte wide data from any of the plurality of Input Virtual Queues 18 to an output FBUS byte without restricting the access of any other input segment to any of Input Virtual Queues 18. Data switching is controlled by a arbiter 22.

[0018] The internal fabric 24 of the RSC 12 provides full input to output connectivity that is, a full of any and all of the inputs to any and all of the outputs. In a exemplary rotary switch 12, there are 128 8-bit wide Virtual Input Queues (“VIQ”), distributed over 8 segments e.g., 16 VIQ's per segment and 8 output segments, thus providing a device 12 having 128 input ports to any of the 128 output ports. The fabric is an independently queued structure that does not require symmetric switching. The switching is a distributed function between a loose arrangement among processors 14 and the RSC fabric 24. The RSC arbiter 22 provides a fair round robin service for received packets. The processors 14 can provide packets either through a simple round robin or weighted fair queuing to the RSC 12. The output port switching is based on a PULL arbitration scheme.

[0019] Referring to FIG. 2, an implementation of the system 10 of FIG. 1, is shown. A rotary switch device 12 is shown coupled to a pair of network processors 14. The network processors are preferably parallel-based multithreaded processors. One example of such a processor is described in U.S. patent application entitled “PARALLEL PROCESSOR ARCHITECTURE”, filed on by and assigned to the assignee of the present invention and incorporated herein by reference. Each of the processors 14 communicate with data supplying devices 13 e.g., here Media Access Controllers (MAC'S) that are coupled to the physical layer of a network 30.

[0020] The system 10 also includes a passive backplane 30. The passive backplane 30 employs tri-state steering logic to enable dynamic reconfiguration of the system 10 based on the number of ports supported. This system 10 is a byte slice arrangement. As a byte sliced arrangement, when new ports are added, all ports stop transmitting to RSC devices 12. Depending on buffering and steering initialization time, input ports may or may not have to be paused. The passive backplane includes nine (9) main busses 30a-30b. The first bus 30a is a computer bus e.g., a Personal Computer Interconnect (PCI) bus. While this is bridged bus, and therefore strictly speaking the backplane is not passive, the bridge and microprocessor unit that is commonly associated with busses such as the PCI bus can be provided as a daughter card to maintain a passive backplane 30. The other 8 busses on the backplane are used to interconnect the RSC blades Blade—0-Blade—3. A RSC blade is an arrangement of RSC devices 12, network processors 14 and network devices 16.

[0021] Since the FBUS data (32 bit Unidirectional busses) is sectioned into up to four 8 bit segments. The segments can be sized based on the number of equivalent ports supported by the system 10. If a single blade is used i.e., a 32 port system, the backplane steering logic connects Bus 30b to Bus 30e and Bus 30i to Bus 30f to provide input data, i.e., two 24 bit FBUS data busses to the RSC 12. These two busses along with immediate feedback of 8 bits each from Bus 30b and Bus 30i form two 32 bit input busses to the RSC 12. Bus 30d is steered to Bus 30c for transmit to the MAC device 16. The 24 data bits of FBUS buses along with the 8 bits from the RSC 12 form 32 bits to the MAC. Similarly, Bus 30g is steered to Bus 30h and merged with 8 bits of immediate feedback data from the RSC 12 to form 32 bits to the MACs 16.

[0022] Each blade e.g., Blade—0 to Blade—3 is similar in construction and are scaled together via the passive backplane 32. Thus, if system 10 has 64 ports supported, the steering logic (not shown) selects the appropriate bytes from each of the busses and connects them to their respective destination busses in 16 bit sections. If 128 ports are instantiated, then the section size is 8 bits. It should be noted that a 64 port system can be configured into a 96 port system where the section size is 8 bits, and the three RSC blades are used, with only 6 input segments (instead of the possible 8). In this type of configuration, a fourth RSC is required to complete the 32 bit byte-slice. Therefore, 96 port systems require the use of a simple add-in board which is populated with only an RSC using bits (31:8) on both input sections.

[0023] Referring to FIG. 3, the RSC 12 includes input segment logic devices (ISL) 40a-40h that handles incoming FBUS data and distributes the incoming data to an appropriate virtual input queue in virtual queue logic (VQL) devices 42a-42p. The RSC 12 also includes output segment logic devices (OSL) 44a-44h. The OSL devices 44 pull data from the VQL logic devices 42 and deliver the data to the output side of the FBUS for distribution to appropriate MAC devices 14. The input virtual queues 420, to 42127 are coupled to the output segment logic 44 via a series of multiplexers 470 to 47127. Each of the multiplexers 420 to 42127 is coupled to each of the virtual input queues 42 in its row e.g., VIQ 420-42112 for multiplexer 420). There are sixteen of said multiplexers in each column. The output of the multiplexers 470 to 47127 for each of the columns (e.g., multiplexer 470-4715 for column 0) feed corresponding output multiplexers 490 to 497 which are coupled to the output segment logic 44a-44h.

[0024] The RSC 12 also includes Input Ready logic 46 that samples the virtual input queues in the virtual queue logic (VQL) devices 42a-42p to report back the status of the virtual input queues to mapped input segments, so that the devices 14 (FIG. 1) that supply data can track buffer fullness. The RSC 12 also includes output ready logic 48. The Output Ready Logic (ORL) 48 is analogous to the Input ready logic. However, the ORL 48 samples the network devices 16 e.g., MAC transmit ready bits to determine if the network devices 16 are ready to accept more transmit data. The RSC 12 also includes Output Segment Arbitration Logic 50. The Output Segment Arbitration Logic 50 as will be described in FIG. 6, is used to determine which virtual input queue should provide data to its output segment in an appropriate timeslot. One preferred scheme has the Output Segment Arbitration Logic 50 using a round robin time multiplexed arbitration algorithm.

[0025] The Input Segment Logic (ISL) 40 interfaces with the network processor 14 and determines which virtual queue an incoming mpkt (64 byte payload) should be sent to. The RSC 12 has a plurality of virtual queues. In one example, there are 16 virtual queues to which each input segment can direct incoming mpkts. The RSC 12 is arranged into segments e.g., 8 input segments. If fewer input segments are required (i.e., the RSC 12 is configured for fewer ports), then logically contiguous input segments are joined to form either a 32 bit datapath (32 ports), or a 16 bit datapath (64 ports).

[0026] The ISL 40 uses in-band information to control virtual queue loading and port arbitration. In-band information is used to minimize pin cost as would be associated with explicit out-of-band control. The in-band information includes a destination output port (8 bits), an SOP bit, a “Transmit As Is” control bit, a byte enable control bit, a CSR enable, and a Virtual Queue Identifier (4 bits). Since, there is only 8 bits of in-band data available per cycle, and there are 16 bits required, 2 in-band cycles are required. There is an optimization, in 64 or 32 port modes, 16 bits/32 bits of in-band information are possible, therefore only one in-band information cycle is required.

[0027] Input data to the crossbar includes two 32 bit header words containing control information followed by up to eight (8) 32 bit words of packet data. The 32 bit input word is connected to 4 input segments. The header is segmented into 2 bytes of control for each input segment, and specifies the VIQ to load, the output destination, byte count, end of packet, and byte enable for the last 32 bit word being transmitted. The 4 output segments specified receive the VIQ addresses of new packets being loaded in a “pending” output FIFO. All packets being sent to the same output port are loaded into a similar “pending” FIFO so that all four output byte segments begin to send data to the output FIFO bus on the same cycle. Byte data from the 4 output segments is combined to form the 32 bit output FIFO bus.

[0028] Two output segments per RSC are enabled to drive control signals (start of packet, end of packet, transmit as is, transmit error), while all segments drive byte enable signals. The output control logic samples the ready signals for all output destinations. All output segments update their ready bit status in lock step so that the 4 sliced bytes of the input FIFO bus can be switch at the same time.

[0029] The inputs to the input segment logic 42 include the FBUS data bits (7:0), and control signals, TxSel, EOP, and NewQHdr. The FBUS data bits are as above, the TxSel bits are used to frame the FBUS data bits as valid, whereas, EOP is used to explicitly identify the end of a packet. The NewQHdr bit indicates to the ISL 420 that a new set of Virtual Queue information is coming. An optimization may be that if EOP AND NewQhdr are asserted this would require only a single prepend cycle to indicate a target Virtual Queue. The implication in that case is that the transfer is not a new packet but rather continuation data from a currently transmitting packet. In this case an in-band EOP is required.

[0030] The Input Ready Logic (IRL) 46 samples the status of the 16 virtual queues in virtual queue logic 42a-42p associated with each input segment. If a VIQ has available space then the IRL will report that to a requesting network processor 14 (FIG. 1), via VIQ transmit ready bits. The network processor 14 can use this information to schedule transfers to the virtual queues.

[0031] The virtual queues VIQ's are associated with a particular output while there is valid data maintained in the virtual queue. The virtual queues can have a suitable storage depth e.g., 4 mpkts for 14 of the queues and to 8 mpkts for two, where each mpkt is 64 bytes. There are 16 Virtual queues associated with each input/output segment.

[0032] Other arrangements are possible. Each VIQ has an input pointer and an output pointer. The input pointer is used by the Input Segment Logic 40 (ISL) to push data into the VIQ, while the output pointer is used by the output Segment Logic to “pull” data from the VIQ for distribution out the transmit FBUS. In one implementation, the VIQ's are single ported random access memory devices. Since a read and write may be concurrently required for the full crossbar operation, the VIQ's are cycled twice as fast as the input fill rate. For example, if the input fill rate is 66-80 Mhz from the input segment FBUSES, the output drain rate would be a decoupled 66-80Mhz FBUS drain rate then the VIQ's would operate at 133 to 166 MHZ that is twice as fast as the faster of the Input or Output FBUS rates. Alternatively, the queues can be organized as 2 bytes in width and accessed on alternate cycles.

[0033] In order to maximize the efficiency of the Rotary switch 12, the switch fabric operates at twice the output FBUS drain rate. One way to accomplish this would be to cycle the VIQ's twice again as fast. Another way would be to have the VIQ's be twice as wide. Thus, if the VIQ's input segment is 8 bits wide the VA's are buffered to form 16 bits of write data. Read operations will fetch 16 bits of read data which will be supplied to the switch fabric at 133-160 Mhz 8 bit chunks.

[0034] The Output Segment Logic (OSL) 44 is a timeslot filler. The Output Segment Logic 44 uses Output Segment Arbitration 50 results to select which new Virtual Queue should be “connected” to an output port. The OSL examines Transmit ready bits which are collected by the Output Ready bit Logic (ORL) 48 to determine if the output port is ready to accept a new mpkt (64 bytes). The Output Segment Logic decouples the VIQ crossbar logic from the output drain rate, by employing a 16 mpkt queue at each output segment (16*64B*8=8 KB). This decoupling allows the crossbar to operate at a higher frequency. The OSL 44 includes a 16 entry timeslot queue. Each VIQ to Output Port has an explicit timeslot entry. If a VIQ is not available, its slot may be compressed. Up to n slots may be compressed (most likely n=2) before filling is “wait stated” until skipped VIQ's are available.

[0035] The Output Ready Logic (ORL) 48 interrogates the destination network devices 16 (FIG. 1) for transmit ready bits. The transmit ready bits are used by the RSC 12 in the Output Segment Logic 44 (OSL) to promote data from the RSC 12 to the appropriate output segment FBUS 31. The ORL 48 is a ready bus Master. It cycles through all attached MAC's fetching the transmit ready bits. The ORL 48 assembles all the transmit ready bits and provides them to their respective output segment. The OSL 48 uses these bits to determine if the tail of the queue should be filled with that output port's mpkt. This is done to avoid head of queue blocking.

[0036] The Output Segment Arbitration (OSA) 50 is used to link a virtual queue 42 (VIQ) to an output port. The RSC 12 employs a distributed crossbar selection scheme. The network processor 14 performs weighted fair queuing and provides the top elements for transmission to the RSC 12. The RSC 12 in turn uses a fair service algorithm and a non-blocking scheme so that efficiency is maintained.

[0037] Switch Arrangements

[0038] Referring to FIG. 4A, a rotary switch 14a, is coupled to provide a 2×2 FIFO BUS switching fabric. The rotary switches 14a is fed by buses B0-B1 which are each 32 bit byte sliced busses. The output of the rotary switch 14a is coupled to output busses e.g., FBUS—0, FBUS—1. On the input side, the four bytes of each bus B0-B1 are coupled in sequence to the rotary switch 14a and on the output side the first four output segments of each rotary switch provide the bytes of FBUS—0, the next four output segments provide the bytes of FBUS—1. The mapping for this arrangement is shown in FIG. 5A. In this manner a byte sliced architecture is provide. This byte sliced architecture, is non-blocking. That is, any input port can be connected to any output port without blocking any other input port from connecting to any other output port. In any one cycle, all input ports can couple data to different ones of all of the output ports.

[0039] Referring to FIG. 4B, a pair of rotary switches 14a, 14b are coupled to provide a 4×4 FIFO BUS switching fabric. The rotary switches 14a, 14b have input segments coupled by buses B0-B3 which are each 32 bit byte sliced buses. The output segments of the rotary switches 14a, 14b are coupled to output busses e.g., FBUS—0 to FBUS—3. On the input side, the first two bytes of each bus B0-B3 are coupled to the input segments of the first rotary switch 14a, whereas, the last two bytes of each bus are coupled to the input segments of the second rotary switch 14b. On the output side the first two output segments of each rotary switch provide the bytes of FBUS—0, the next two output segments the bytes of FBUS—1 and so forth. The mapping for this arrangement is shown in FIG. 5B. In this manner a byte sliced architecture is provide. This byte sliced architecture, is a 4×4 architecture and is non-blocking. That is, any input port can be connected to any output port and not block any other input port from connecting to any other output port. In any one cycle, all input ports can couple data to different ones of all of the output ports.

[0040] Thus, rotary switches can be coupled to provide larger switching fabrics. Four switches (a mapping of which is set out below) can be coupled such that eight, 4 byte buses could be coupled to the four switches with first bytes of a each bus coupled to the first switch, second bytes of each bus coupled to the second switch, third bytes of each bus coupled to the third switch and fourth bytes of each bus coupled to the fourth switch. Moreover, with larger rotary switches i.e., that can interface to larger buses, e.g., 8 byte buses, even larger configurations could be provided in a similar manner. On the output side a similar connection arrangement is provided.

[0041] This switching fabric is scalable, i.e., easily expanded from a 2×2 FIFO bus configuration (32 ports to 32 ports) up to an 8×8 FIFO bus configuration (128 ports to 128 ports) without adding additional hierarchial levels of switches. That is, expansion occurs on a single level of switches which reduces latency and complexity.

[0042] Referring to FIG. 5A, the mapping as a 2×2 FIFO bus switching fabric requires one RSC 12, with bytes output mapped as follows:

[0043] 1. output segment 0—byte 0 (bits(31:24)) output FIFO bus 0

[0044] 2. output segment 1—byte 1 (bits(23:16)) output FIFO bus 0

[0045] 3. output segment 2—byte 2 (bits(15:08)) output FIFO bus 0

[0046] 4. output segment 3—byte 3 (bits(07:00)) output FIFO bus 0

[0047] 5. output segment 4—byte 0 (bits(31:24)) output FIFO bus 1

[0048] 6. output segment 5—byte 1 (bits(23:16)) output FIFO bus 1

[0049] 7. output segment 6—byte 2 (bits(15:08)) output FIFO bus 1

[0050] 8. output segment 7—byte 3 (bits(07:00)) output FIFO bus 1

[0051] and the input segments mapped as;

[0052] 1. input segment 0—byte 0 (bits(31:24)) input FIFO bus 0

[0053] 2. input segment 1—byte 1 (bits(23:16)) input FIFO bus 0

[0054] 3. input segment 2—byte 2 (bits(15:08)) input FIFO bus 0

[0055] 4. input segment 3—byte 3 (bits(07:00)) input FIFO bus 0

[0056] 5. input segment 4—byte 0 (bits(31:24)) input FIFO bus 1

[0057] 6. input segment 5—byte 1 (bits(23:16)) input FIFO bus 1

[0058] 7. input segment 6—byte 2 (bits(15:08)) input FIFO bus 1

[0059] 8. input segment 7—byte 3 (bits(07:00)) input FIFO bus 1

[0060] where FBUSxY corresponds to byte “x” of FBUS “Y.” Thus, the output segments 0, 1, 2, 3 connect concurrently to corresponding Virtual Queues either in input segments 0, 1, 2, 3 or 4, 5, 6, 7, respectively.

[0061] Referring to FIG. 5B, to expand to a 4×4 FIFO bus switching fabric requires two RSC devices 14. FIG. 5B shows the output mapping with the output mapped as,

[0062] 1. RSC—0 output segment 0—byte 0 (bits(31:24)) output FIFO bus 0

[0063] 2. RSC—0 output segment 1—byte 1 (bits(23:16)) output FIFO bus 0

[0064] 3. RSC—0 output segment 2—byte 0 (bits(31:24)) output FIFO bus 1

[0065] 4. RSC—0 output segment 3—byte 1 (bits(23:16)) output FIFO bus 1

[0066] 5. RSC—0 output segment 4—byte 0 (bits(31:24)) output FIFO bus 2

[0067] 6. RSC—0 output segment 5—byte 1 (bits(23:16)) output FIFO bus 2

[0068] 7. RSC—0 output segment 6—byte 0 (bits(31:24)) output FIFO bus 3

[0069] 8. RSC—0 output segment 7—byte 1 (bits(23:16)) output FIFO bus 3

[0070] 9. RSC—1 output segment 0—byte 2 (bits(15:08)) output FIFO bus 0

[0071] 10. RSC—1 output segment 1—byte 3 (bits(07:00)) output FIFO bus 0

[0072] 11. RSC—1 output segment 2—byte 2 (bits(15:08)) output FIFO bus 1

[0073] 12. RSC—1 output segment 3—byte 3 (bits(07:00)) output FIFO bus 1

[0074] 13. RSC—1 output segment 4—byte 2 (bits(15:08)) output FIFO bus 2

[0075] 14. RSC—1 output segment 5—byte 3 (bits(07:00)) output FIFO bus 2

[0076] 15. RSC—1 output segment 6—byte 2 (bits(15:08)) output FIFO bus 3

[0077] 16. RSC—1 output segment 7—byte 3 (bits(07:00)) output FIFO bus 3

[0078] The input would be mapped in a similar manner (not shown in FIG. 5B). The input segments mapped as;

[0079] 1. RSC—0 input segment 0—byte 0 (bits(31:24)) input FIFO bus 0

[0080] 2. RSC—0 input segment 1—byte 1 (bits(23:16)) input FIFO bus 0

[0081] 3. RSC—0 input segment 2—byte 0 (bits(31:24)) input FIFO bus 1

[0082] 4. RSC—0 input segment 3—byte 1 (bits(23:16)) input FIFO bus 1

[0083] 5. RSC—0 input segment 4—byte 0 (bits(31:24)) input FIFO bus 2

[0084] 6. RSC—0 input segment 5—byte 1 (bits(23:16)) input FIFO bus 2

[0085] 7. RSC—0 input segment 6—byte 0 (bits(31:24)) input FIFO bus 3

[0086] 8. RSC—0 input segment 7—byte 1 (bits(23:16)) input FIFO bus 3

[0087] 9. RSC—1 input segment 0—byte 2 (bits(15:08)) input FIFO bus 0

[0088] 10. RSC—1 input segment 1—byte 3 (bits(07:00)) input FIFO bus 0

[0089] 11. RSC—1 input segment 2—byte 2 (bits(15:08)) input FIFO bus 1

[0090] 12. RSC—1 input segment 3—byte 3 (bits(07:00)) input FIFO bus 1

[0091] 13. RSC—1 input segment 4—byte 2 (bits(15:08)) input FIFO bus 2

[0092] 14. RSC—1 input segment 5—byte 3 (bits(07:00)) input FIFO bus 2

[0093] 15. RSC—1 input segment 6—byte 2 (bits(15:08)) input FIFO bus 3

[0094] 16. RSC—1 input segment 7—byte 3 (bits(07:00)) input FIFO bus 3

[0095] where in FIG. 5B, FBUSxY corresponds to byte “x” of FBUS “Y.” Thus output segments (RSC—0 0,1/RSC—1 0,1), (RSC—0 2,3/RSC—1 2,3), (RSC—0 4,5/RSC—1 4,5), (RSC—0 6,7/RSC—1 6,7) representing output FIFO busses 0, 1, 2, and 3 respectively, connect concurrently to corresponding Virtual Input Queues in VIL 42 for the input segments of input FIFO busses 0, 1, 2, and 3.

[0096] Thus, an 8×8 FIFO bus crossbar requires 4 RSC chips, with the output mapped as:

[0097] 1. RSC—0 output segment 0—byte 0 (bits(31:24)) output FIFO bus 0

[0098] 2. RSC—0 output segment 1—byte 0 (bits(31:24)) output FIFO bus 1

[0099] 3. RSC—0 output segment 2—byte 0 (bits(31:24)) output FIFO bus 2

[0100] 4. RSC—0 output segment 3—byte 0 (bits(31:24)) output FIFO bus 3

[0101] 5. RSC—0 output segment 4—byte 0 (bits(31:24)) output FIFO bus 4

[0102] 6. RSC—0 output segment 5—byte 0 (bits(31:24)) output FIFO bus 5

[0103] 7. RSC—0 output segment 6—byte 0 (bits(31:24)) output FIFO bus 6

[0104] 8. RSC—0 output segment 7—byte 0 (bits(31:24)) output FIFO bus 7

[0105] 9. RSC—1 output segment 0—byte 1 (bits(23:16)) output FIFO bus 0

[0106] 10. RSC—1 output segment 1—byte 1 (bits(23:16)) output FIFO bus 1

[0107] 11. RSC—1 output segment 2—byte 1 (bits(32:16)) output FIFO bus 2

[0108] 12. RSC—1 output segment 3—byte 1 (bits(23:16)) output FIFO bus 3

[0109] 13. RSC—1 output segment 4—byte 1 (bits(23:16)) output FIFO bus 4

[0110] 14. RSC—1 output segment 5—byte 1 (bits(23:16)) output FIFO bus 5

[0111] 15. RSC—1 output segment 6—byte 1 (bits(23:16)) output FIFO bus 6

[0112] 16. RSC—1 output segment 7—byte 1 (bits(23:16)) output FIFO bus 7

[0113] 17. RSC—2 output segment 0—byte 2 (bits(15:08)) output FIFO bus 0

[0114] 18. RSC—2 output segment 1—byte 2 (bits(15:08)) output FIFO bus 1

[0115] 18. RSC—2 output segment 2—byte 2 (bits(15:08)) output FIFO bus 2

[0116] 19. RSC—2 output segment 3—byte 2 (bits(15:08)) output FIFO bus 3

[0117] 20. RSC—2 output segment 4—byte 2 (bits(15:08)) output FIFO bus 4

[0118] 21. RSC—2 output segment 5—byte 2 (bits(15:08)) output FIFO bus 5

[0119] 22. RSC—2 output segment 6—byte 2 (bits(15:08)) output FIFO bus 6

[0120] 23. RSC—2 output segment 7—byte 2 (bits(15:08)) output FIFO bus 7

[0121] 24. RSC—3 output segment 0—byte 3 (bits(07:00)) output FIFO bus 0

[0122] 25. RSC—3 output segment 1—byte 3 (bits(07:00)) output FIFO bus 1

[0123] 26. RSC—3 output segment 2—byte 3 (bits(07:00)) output FIFO bus 2

[0124] 27. RSC—3 output segment 3—byte 3 (bits(07:00)) output FIFO bus 3

[0125] 28. RSC—3 output segment 4—byte 3 (bits(07:00)) output FIFO bus 4

[0126] 29. RSC—3 output segment 5—byte 3 (bits(07:00)) output FIFO bus 5

[0127] 30. RSC—3 output segment 6—byte 3 (bits(07:00)) output FIFO bus 6

[0128] 31. RSC—3 output segment 7—byte 3 (bits(07:00)) output FIFO bus 7

[0129] The input segments would be mapped as follows:

[0130] 1. RSC—0 input segment 0—byte 0 (bits(31:24)) input FIFO bus 0

[0131] 2. RSC—0 input segment 1—byte 0 (bits(31:24)) input FIFO bus 1

[0132] 3. RSC—0 input segment 2—byte 0 (bits(31:24)) input FIFO bus 2

[0133] 4. RSC—0 input segment 3—byte 0 (bits(31:24)) input FIFO bus 3

[0134] 5. RSC—0 input segment 4—byte 0 (bits(31:24)) input FIFO bus 4

[0135] 6. RSC—0 input segment 5—byte 0 (bits(31:24)) input FIFO bus 5

[0136] 7. RSC—0 input segment 6—byte 0 (bits(31:24)) input FIFO bus 6

[0137] 8. RSC—0 input segment 7—byte 0 (bits(31:24)) input FIFO bus 7

[0138] 9. RSC—1 input segment 0—byte 1 (bits(23:16)) input FIFO bus 0

[0139] 10. RSC—1 input segment 1—byte 1 (bits(23:16)) input FIFO bus 1

[0140] 11. RSC—1 input segment 2—byte 1 (bits(32:16)) input FIFO bus 2

[0141] 12. RSC—1 input segment 3—byte 1 (bits(23:16)) input FIFO bus 3

[0142] 13. RSC—1 input segment 4—byte 1 (bits(23:16)) input FIFO bus 4

[0143] 14. RSC—1 input segment 5—byte 1 (bits(23:16)) input FIFO bus 5

[0144] 15. RSC—1 input segment 6—byte 1 (bits(23:16)) input FIFO bus 6

[0145] 16. RSC—1 input segment 7—byte 1 (bits(23:16)) input FIFO bus 7

[0146] 17. RSC—2 input segment 0—byte 2 (bits(15:08)) input FIFO bus 0

[0147] 18. RSC—2 input segment 1—byte 2 (bits(15:08)) input FIFO bus 1

[0148] 18. RSC—2 input segment 2—byte 2 (bits(15:08)) input FIFO bus 2

[0149] 19. RSC—2 input segment 3—byte 2 (bits(15:08)) input FIFO bus 3

[0150] 20. RSC—2 input segment 4—byte 2 (bits(15:08)) input FIFO bus 4

[0151] 21. RSC—2 input segment 5—byte 2 (bits(15:08)) input FIFO bus 5

[0152] 22. RSC—2 input segment 6—byte 2 (bits(15:08)) input FIFO bus 6

[0153] 23. RSC—2 input segment 7—byte 2 (bits(15:08)) input FIFO bus 7

[0154] 24. RSC—3 input segment 0—byte 3 (bits(07:00)) input FIFO bus 0

[0155] 25. RSC—3 input segment 1—byte 3 (bits(07:00)) input FIFO bus 1

[0156] 26. RSC—3 input segment 2—byte 3 (bits(07:00)) input FIFO bus 2

[0157] 27. RSC—3 input segment 3—byte 3 (bits(07:00)) input FIFO bus 3

[0158] 28. RSC—3 input segment 4—byte 3 (bits(07:00)) input FIFO bus 4

[0159] 29. RSC—3 input segment 5—byte 3 (bits(07:00)) input FIFO bus 5

[0160] 30. RSC—3 input segment 6—byte 3 (bits(07:00)) input FIFO bus 6

[0161] 31. RSC—3 input segment 7—byte 3 (bits(07:00)) input FIFO bus 7

[0162] For the 8×8 FIFO crossbar configuration each input/output segment of the RSC 12 switches 1 byte of the 32 bit FIFO bus concurrent with the other RSC 12 slices.

[0163] Referring to FIG. 6, distribution of the Output Segment Arbitration Logic (OSA) 50a-50h is shown. Each of the OSA logic elements 50 determine which virtual queue 42 to link to which of the output segment logic 44a-44h. The input FBUS segments at a start of a new packet provides a start of packet “SOP” flag, the destination port of this new packet and a virtual queue number. At this starting point the destination port is known, so a physical mapping to the output segment logic is performed. This mapping is stored in an output port Map Queue 60. Each physical port has an output port Map Queue 600-60127. These queues maintain pointers to the next virtual queue which has a packet for the port. Each Map Queue 60 maintains up to 8 entries (one for each input segment). The entry has the VIQ# of the next packet to be transmitted.

[0164] When the Output Segment Logic 44 completes the transmission of an packet to a particular port, the Output Segment Logic requests the Output Arbitration Logic 50 to supply the Output Segment Logic 44 with the NEXT_VQ number that is stored in that output ports' map queue60 NEXT<sub2>—</sub2>VQ. This NEXT_VQ number is an address that the Output Segment Logic 44 uses to control 8:1 multiplexers 62a-62h that feed the Output Segment Logic's 44 16 mpkt entry output queues. The VIQ number is a 7 bit value. The three most significant bits indicate which Input Segment and the least significant 4 bits indicate which VIQ within that input segment. Using these 7 bits the OSL can completely specify the next packet to be transmitted.

[0165] Disposed between the Input Segment Logic (ISL) 40 and the output port Map Queue 60 is a time division multiplex bus 70 used by the eight input segments to transmit destination information to the selected output segments. This multiplexing is straightforward since there are at a maximum 8 new packets to be sorted and 16 cycles to promote their VIQ# to their respective Map Queue. Therefore, by employing a very simple round robin technique the input segment Destination ports are sorted over the next 8 cycles. The Map Queues drain using a first in first out algorithm.

[0166] Other Embodiments

[0167] It is to be understood that while the invention has been described in conjunction with the detailed description thereof, the foregoing description is intended to illustrate and not limit the scope of the invention, which is defined by the scope of the appended claims. Other aspects, advantages, and modifications are within the scope of the following claims.

Contents4

Every citation, both ways

Citations
Document	Relation	Office	Cited during
US7336669B1	Cited by	United States of America	Applicant
US8068482B2	Cited by	United States of America	Search report
US2015003447A1	Cited by	United States of America	Pre-grant
US9098641B1	Cited by	United States of America	Search report
US7320037B1	Cited by	United States of America	Applicant
US2009319704A1	Cited by	United States of America	Pre-grant
US7339943B1	Cited by	United States of America	Applicant
US2007268825A1	Cited by	United States of America	Pre-grant
US7606248B1	Cited by	United States of America	Search report
US8868801B2	Cited by	United States of America	Search report
US8566487B2	Cited by	United States of America	Search report
US2010118880A1	Cited by	United States of America	Pre-grant
US8873546B2	Cited by	United States of America	Applicant
US9807034B2	Cited by	United States of America	Search report
US7593334B1	Cited by	United States of America	Applicant
US6002861A	Cites	United States of America	Pre-grant
US6201792B1	Cites	United States of America	Pre-grant
US6687246B1	Cites	United States of America	Pre-grant
US6868065B1	Cites	United States of America	Pre-grant

17 members in 10 offices

This recordMember, by publication datePriority claim

Priority claims6

Priority claims
Document	Office	Kind	Date
38704799	United States of America	A	1999-08-31
38704799	United States of America	A	1999-08-31
42310103	United States of America	A	2003-04-25
09387047	–	–	–
US19990387047	–	–	–
US20030423101	–	–	–

Members17

Family members, oldest first
Document	Office	Kind
CA2383473A1	Canada	A1	2001-03-08
WO0117180A1	World Intellectual Property Organization (WIPO)	A1	2001-03-08
AU6774500A	Australia	A	2001-03-26
EP1212869A1	European Patent Office (EPO)	A1	2002-06-12
TW502518B	Taiwan Province of China	B	2002-09-11
HK1043454A1	Hong Kong, China	A1	2002-09-13
CN1382333A	China	A	2002-11-27
US2003193936A1	United States of America	A1	2003-10-16
US6687246B1	United States of America	B1	2004-02-03
US7023844B2	United States of America	B2	2006-04-04
EP1212869B1	European Patent Office (EPO)	B1	2007-02-07
AT353509T	Austria	T	2007-02-15
CN1303795C	China	C	2007-03-07
DE60033295D1	Germany	D1	2007-03-22
CA2383473C	Canada	C	2007-07-03
HK1043454B	Hong Kong, China	B	2007-08-24
DE60033295T2	Germany	T2	2007-11-22

36 transactions on the USPTO file

Allowed after 2 non-final rejections.

Non-final rejections: 2
Final rejections: 0
RCEs: 0
Appeals: 0

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Transactions

Prosecution transactions, newest first
	Event	Code
2018-04-30	Expire PatentEXP.	EXP.
2017-11-13	Maintenance Fee Reminder MailedREM.	REM.
2010-05-28	Change in Power of Attorney (May Include Associate POA)PA..	PA..
2010-05-27	Correspondence Address ChangeC.AD	C.AD
2006-04-04	Recordation of Patent Grant MailedPGM/	PGM/
2006-04-04	Patent Issue Date Used in PTA CalculationAllowedPTAC	PTAC
2006-03-15	Issue Notification MailedAllowedWPIR	WPIR
2006-02-10	Dispatch to FDCD1935	D1935
2006-02-10	Application Is Considered Ready for IssuePILS	PILS
2006-01-23	Issue Fee Payment VerifiedN084	N084
2006-01-23	Issue Fee Payment ReceivedIFEE	IFEE
2005-11-29	Mail Notice of AllowanceAllowedMN/=.	MN/=.
2005-11-28	Notice of Allowance Data Verification CompletedAllowedN/=.	N/=.
2005-11-28	Case Docketed to Examiner in GAUDOCK	DOCK
2005-09-26	Date Forwarded to ExaminerFWDX	FWDX
2005-09-16	terminal disclaimer fee paidTDP	TDP
2005-09-16	Response after Non-Final ActionA...	A...
2005-08-09	Mail Non-Final RejectionNon-final rejectionMCTNF	MCTNF
2005-08-08	Non-Final RejectionNon-final rejectionCTNF	CTNF
2005-06-08	Date Forwarded to ExaminerFWDX	FWDX
2005-06-02	Response after Non-Final ActionA...	A...
2005-03-30	Mail Non-Final RejectionNon-final rejectionMCTNF	MCTNF
2005-03-29	Non-Final RejectionNon-final rejectionCTNF	CTNF
2005-03-01	Case Docketed to Examiner in GAUDOCK	DOCK
2004-11-29	Case Docketed to Examiner in GAUDOCK	DOCK
2004-09-22	IFW TSS Processing by Tech Center CompleteTSSCOMP	TSSCOMP
2004-09-22	Case Docketed to Examiner in GAUDOCK	DOCK
2003-09-27	Case Docketed to Examiner in GAUDOCK	DOCK
2003-07-10	Application Is Now CompleteCOMP	COMP
2003-07-09	Application Dispatched from OIPEOIPE	OIPE
2003-05-12	IFW Scan & PACR Auto Security ReviewSCAN	SCAN
2003-04-25	Reference capture on IDSRCAP	RCAP
2003-04-25	Preliminary AmendmentA.PE	A.PE
2003-04-25	Information Disclosure Statement (IDS) FiledM844	M844
2003-04-25	Information Disclosure Statement (IDS) FiledWIDS	WIDS
2003-04-25	Initial Exam Team nnIEXX	IEXX

6 legal events, as the office reported them to INPADOC

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Events

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	Event	Code
2018-05-22	Lapsed due to failure to pay maintenance feeLapsedFP	FP
2018-04-30	Lapse for failure to pay maintenance feesLapsedPATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.)LAPS	LAPS
2018-04-30	Information on status: patent discontinuationPATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362STCH	STCH
2017-11-13	Fee payment procedureMAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM.)FEPP	FEPP
2013-09-18	Fee paymentFPAY	FPAY
2009-09-30	Fee paymentFPAY	FPAY