Methods used to simultaneously perform automated at-speed testing of multiple gigabit per second high serial pin count devices

CROSS-REFERENCE TO RELATED APPLICATIONS

P-0001[0001] This application claims priority to U.S. Prov. App. No. 60/371,673 filed Apr. 12, 2002, entitled “SYSTEMS AND METHODS FOR AT-SPEED AUTOMATED TESTING OF INTEGRATED CIRCUITS,” which is incorporated by reference herein in its entirety.

P-0002[0002] This application is related to U.S. application Ser. No. ______, entitled “SYSTEM FOR AT-SPEED AUTOMATED TESTING OF HIGH SERIAL PIN COUNT MULTIPLE GIGABIT PER SECOND DEVICES” (Atty. Doc. No. 1875,2380001); U.S. application Ser. No. ______, entitled “TEST SYSTEM RIDER BOARD UTILIZED FOR AUTOMATED AT-SPEED TESTING OF HIGH SERIAL PIN COUNT MULTIPLE GIGABIT PER SECOND DEVICES” (Atty. Doc. No. 1875.2380002); and U.S. application Ser. No. ______, entitled “TEST HEAD UTILIZED IN A TEST SYSTEM TO PERFORM AUTOMATED AT-SPEED TESTING OF MULTIPLE GIGABIT PER SECOND HIGH SERIAL PIN COUNT DEVICES” (Atty. Doc. No. 1875.2380005), all filed concurrently herewith, which are all incorporated by reference herein in their entirety.

BACKGROUND OF THE INVENTION

P-0003[0003] 1. Field of the Invention

P-0004[0004] The present invention relates to automated testing systems and methods that perform at-speed testing of high serial pin count devices that transmit serial data at gigabit per second baud rates.

P-0005[0005] 2. Related Art

P-0006[0006] Traditional testing systems for semiconductor devices employ automated testing equipment (ATE). Today, high-speed (e.g., gigabit per second (Gbps) baud rate) semiconductors can be quad serial data input/output (I/O) port (having 4 serial data pins per port coupled to 4 transmit/receive differential pairs) stand-alone physical layer devices (PHY's) or high port count integrated application specific integrated circuits (ASIC's), switches, or backplane transceivers. Most ATE's become perpetually outdated in terms of being able to perform at-speed testing (testing at the rated speed of the semiconductor device) of high speed devices with high serial pin counts. Presently, two main ATE's performing tests on high speed high serial pin count devices are the Teradyne Tiger and the Agilent 93000 test platforms that can deliver 1.25 Gbps on standard single ended channels, where Teradyne can deliver 1.6 Gbps differential channels and Agilent can deliver 2.5 Gbps differential channels. Aside from these ATEs, specialized high-speed test options can cost hundreds of thousands of dollars and usually offer very limited functionality.

P-0007[0007] Aside from automated testing systems, non-automated testing equipment systems utilize “serial external loopback” (device transmitter connected directly to device receiver) configurations for at-speed testing (testing at the rated speed of the semiconductor device). There are also some single channel ATE instruments, such as digitizers and sine wave sources, as well as bench instrumentation with a few channel capability, such as bit error rate testers (BERTs), that can be used to test some semiconductor devices. Unfortunately, these testing systems are only effective for semiconductor devices with a very small number of serial data pins and channels. This is because it can be difficult to route many devices with a high number of serial data pins to a single ATE source or capture instrument due to limit device interface board (DIB) space allowed for application circuitry on test heads. Also, bench instrumentation are an expensive upgrade solution to an ATE and typically are not production worthy. Further, test time, which contributes to the cost of testing, is very high on bench instrumentations because they are not designed for automated production testing.

P-0008[0008] To overcome some of these problems, other systems have utilized a golden device concept. In these systems a same or complementary functioning semiconductor device as the device under test (DUT) is used as a golden device to test itself. For example, when the speed of a serializer is too fast for an ATE then a deserializer can be used to bring down the speed into a range in which the ATE can test. However, the use of the golden device becomes non-trivial when the serial data pin and channel count of a DUT increases. This is because the test complexity is compounded by the need to have connections to the golden device, external loopback devices, and analog instrument device for signal routing on one DIB, which makes the signal delivery or signal routing too complex to design for high serial pin counts.

P-0009[0009] Consequently, a result of all these problems has been a dramatic decrease in at-speed production test coverage. This has both lowered the quality of semiconductor devices and raised the rate of field defects and failures.

P-0010[0010] Therefore, an ATE is needed that is capable of at-speed testing of multiple Gbps and higher semiconductor devices with high serial pin counts that can be easily adapted to keep up with the constantly changing device speeds and configurations and that will be small enough to fit in the limit real estate available on a DIB. There is also a need for the ATE to have low capital costs for upgrades.

BRIEF SUMMARY OF THE INVENTION

P-0011[0011] Embodiments of the present invention provide a method for performing automated at-speed testing of devices. The method includes the steps of generating multiplexer control signals, forming various signal paths between a set of multiplexers and the devices based on the multiplexer control signals, and routing test signals having multiple gigabit per second (MGBPS) baud rates through the signal paths.

P-0012[0012] Embodiments of the present invention provide a method for performing automated at-speed testing of a device. The method includes the steps of coupling to a rider board a set of multiplexers that includes one multiplexer for each of pin on the device, individually controlling each pin of each multiplexer in the set of multiplexers, and forming signal paths through each of the multiplexers based on the individually controlling step.

P-0013[0013] An advantage of the embodiments of the present invention is that testing devices having high serial pin counts (e.g., 72 channels coupled to 72 pins) has a low capital cost, usually less than $5000.00.

P-0014[0014] Another advantage of the embodiments of the present invention is that the rider board has the ability to route DUT high-speed (e.g., gigabit per second baud rate) serial signals with adequate signal integrity to key test resources to obtain the highest level of test coverage. Thus, a testing system can perform at-speed testing on 72 channels, which accommodates even the highest integrated semiconductors manufactured to date. Also, there is no compromise on test coverage because the rider board also allows any serial pin to be routed to: other device pins for external loopback or snaking, BERT engines, ATE digital pins, and ATE analog pins.

P-0015[0015] A still further advantage of the embodiments of the present invention is that the testing system is capable of at-speed or high speed testing. This allows for at-speed testing of devices under test with random data sequences and specification compliant data packets. Also, a BERT engine tests the devices in real time and does not sub-sample or under-sample. The rider board BERT channels are clock and data recovery (CDR) based and are not reliant on phase or frequency of DUT signals and timing.

P-0016[0016] A still further advantage of the embodiments of the present invention is that because the rider board is installed as a “daughter board” to the DIB, the rider board does not interfere or require the removal of any ATE pin electronics. This is in sharp contrast to the prior art that required the removal of ATE tester standard digital pins from the ATE test system when installing new options in the ATE testers. That prior art systems and methods made the ATE test system less effective and not configured correctly for other high pin count devices.

P-0017[0017] A still further advantage of the embodiments of the present invention is that the rider board is easily and inexpensively upgradeable as the speed of tested devices increase. As an example, systems and methods according to embodiments of the present invention can test at least 5 Gbps and 6.25 Gbps devices.

P-0018[0018] A still further advantage of the embodiments of the present invention is that the rider board's RF connections to tester are generic, which means the rider board can be directly connected to any ATE instrument. In some embodiments, up to two differential ATE digitizers or bench instruments and up to 5 differential pairs of ATE sources or bench instruments can be connected. Also, if a future ATE analog instrument or a new bench instrument is required for testing a particular device specification, the rider board inherently can accommodate it.

P-0019[0019] Further embodiments, features, and advantages of the present inventions, as well as the structure and operation of the various embodiments of the present invention, are described in detail below with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS/FIGURES

P-0020[0020] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate the present invention and, together with the description, further serve to explain the principles of the invention and to enable a person skilled in the pertinent art to make and use the invention.

P-0021[0021]FIG. 1A shows an exemplary testing system according to embodiments of the present invention.

P-0022[0022]FIG. 1B shows a more detailed view of the testing system in FIG. 1A.

P-0023[0023]FIG. 1C shows connections between elements in the testing system in FIGS. <b>1</b>A-<b>1</b>B.

P-0024[0024]FIG. 2 shows device under test according to embodiments of the present invention.

P-0025[0025]FIG. 3 shows details of the testing system in FIGS. <b>1</b>A-<b>1</b>C.

P-0026[0026]FIG. 4 shows an exemplary perspective view of a testing head from a first side in the system of in the preceding figures.

P-0027[0027]FIG. 5 shows an exemplary perspective view of a testing head from a second side with a cut-out portion showing a rider board coupled to an inside surface of the testing head in the system in the preceding figures.

P-0028[0028]FIG. 6 shows an end view of exemplary connections between elements in a testing system in the preceding figures.

P-0029[0029]FIG. 7 shows elements on an exemplary rider board according to embodiments of the present invention.

P-0030[0030]FIG. 8 shows a more detailed view of elements on a rider board in the system in the preceding figures.

P-0031[0031]FIG. 9 shows a more detailed view of elements on a device interface board in the system in the preceding figures.

P-0032[0032]FIG. 10 shows a more detailed view of elements on a rider board in the system in the preceding figures.

P-0033[0033]FIG. 11 shows exemplary connections between elements on a rider board in the system in the preceding figures.

P-0034[0034]FIG. 12 shows a more detailed view of a connection and multiplexing system on a rider board in the system in the preceding figures.

P-0035[0035]FIG. 13 shows a more detailed view of a section of a multiplexing system on a rider board in the system in the preceding figures.

P-0036[0036]FIG. 14 shows a more detailed view of a section of a multiplexing system on a rider board in the system in the preceding figures.

P-0037[0037]FIG. 16 shows exemplary connections between a tester, a test head, and a rider board in the system in the preceding figures.

P-0038[0038] FIGS. <b>16</b>A-<b>16</b>B show exemplary connections between elements on a rider board in the system in the preceding figures.

P-0039[0039]FIG. 17A pictorially illustrates an exemplary self loopback method of testing a device under test (DUT) according to embodiments of the present invention.

P-0040[0040]FIG. 17B pictorially illustrates an exemplary full duplex adjacent core loopback method in a first direction of a DUT according to embodiments of the present invention.

P-0041[0041]FIG. 17C pictorially illustrates an exemplary full duplex adjacent core loopback method in a second direction of a DUT according to embodiments of the present invention.

P-0042[0042]FIG. 18A pictorially illustrates an exemplary internal snake down testing method of a DUT according to embodiments of the present invention.

P-0043[0043]FIG. 18B illustrates a signal path through elements in the system during the internal snake down testing method of FIG. 18A.

P-0044[0044]FIG. 19A pictorially illustrates an exemplary internal snake up testing method of a DUT according to embodiments of the present invention.

P-0045[0045]FIG. 19B illustrates a signal path through elements in the system during the internal snake up testing method of FIG. 19A.

P-0046[0046]FIG. 20 pictorially illustrates a flow path of a signal during an exemplary external snake down testing method of a DUT according to embodiments of the present invention.

P-0047[0047]FIG. 21 pictorially illustrates a flow path of a signal during an exemplary external snake up testing method of a DUT according to embodiments of the present invention.

P-0048[0048]FIG. 22A shows an exemplary bit error rate tester (BERT) configuration to perform BERT testing methods of a DUT according to embodiments of the present invention.

P-0049[0049]FIG. 22B shows an exemplary multiplexer configuration to perform the operation in FIG. 22A.

P-0050[0050]FIG. 23A shows an exemplary transmit analog testing system configuration to perform analog testing methods of transmit pins of a DUT according to embodiments of the present invention.

P-0051[0051]FIG. 23B shows an exemplary receive analog testing system configuration to perform analog testing methods of receive pins of a DUT according to embodiments of the present invention.

P-0052[0052]FIG. 24 illustrates a flow chart depicting a method according to embodiments of the present invention.

P-0053[0053]FIG. 25 illustrates a flow chart depicting a method occurring during the method in FIG. 24.

P-0054[0054]FIG. 26 illustrates a flow chart depicting a method according to embodiments of the present invention.

P-0055[0055] The present invention will now be described with reference to the accompanying drawings. In the drawings, like reference numbers indicate identical or functionally similar elements. Additionally, the left-most digit(s) of a reference number identifies the drawing in which the reference number first appears.

DETAILED DESCRIPTION OF THE INVENTION

P-0056[0056] Overview of Testing System and Operation

P-0057[0057] According to embodiments of the present invention, an automated testing system <b>100</b> comprises a testing system (e.g., automated test equipment (ATE)) <b>102</b> coupled to a tested system <b>104</b>, as shown in FIGS. <b>1</b>A-<b>1</b>C. The ATE <b>102</b> can be a Teradyne Tiger ATE or any other ATE now developed or developed in the future. The tested system <b>104</b> includes a test head <b>106</b> that includes a device interface board (DIB) <b>108</b> having a device under test (DUT) holding device <b>110</b>, which can be a socket or contactor. The DIB <b>108</b> is coupled to a rider board <b>112</b> via a coupling system <b>114</b> (<b>114</b>A-<b>114</b>C). The rider board <b>112</b> can be essentially a “daughter” board that connects to a surface the DIB <b>108</b> opposite a surface with the DUT holding device <b>110</b> via board connectors <b>114</b>C, which may be high-density parallel board connectors described in more detail below with reference to FIGS. 6 and 10. The ATE <b>102</b> includes analog <b>116</b> and digital <b>118</b> signal stimulus and capture/measure devices.

P-0058[0058] It is to be appreciated that throughout the specification the use of “coupled” can mean electrically coupled, mechanically coupled, or both depending on the situation so that signals can be routed through the system <b>100</b>. Also, throughout the specification, the use of “internal” and “external” testing systems refer to whether the testing system is on rider board <b>112</b> (internal) or not on rider board <b>112</b> (external).

P-0059[0059]FIG. 2 shows a device <b>200</b> secured by the DUT holding device <b>110</b> according to embodiments of the present invention. The device <b>200</b> can be a transmitter-receiver (transceiver) device including a plurality of transceivers <b>202</b>(<b>0</b>-<b>3</b>). In some embodiments, device <b>200</b> can be a serializer-deserializer (SerDes) device, as will be described below. Device <b>200</b> can be constructed on a single IC substrate. As an example, transceiver <b>202</b>(<b>0</b>) includes a serial data transmitter <b>204</b>(<b>0</b>) and a serial data receiver <b>206</b>(<b>0</b>). The transmitter <b>204</b>(<b>0</b>) receives parallel data <b>208</b> over a parallel bus (not shown). Transmitter <b>204</b>(<b>0</b>) converts parallel data <b>208</b> into a serial data signal <b>210</b> that travels through channels <b>222</b> (e.g., wires, microstrip, conductive material, etc). The transmitter <b>204</b>(<b>0</b>) includes output pins <b>212</b>A and <b>212</b>B coupled to corresponding ones of channels <b>222</b>. Transmitter <b>204</b>(<b>0</b>) transmits a serial data signal <b>210</b> as a differential serial data signal including first and second differential data signals <b>210</b>A and <b>210</b>B (also referred to as digital data signal components <b>210</b>A and <b>210</b>B), which are complementary to each other. Transmitter <b>204</b>(<b>0</b>) transmits serial data signals <b>210</b>A and <b>210</b>B from respective pins <b>212</b>A and <b>212</b>B through respective channels <b>222</b>. Data signals <b>210</b>A and <b>210</b>B (signal <b>210</b>) have baud rates in the multi-gigabit per second range.

P-0060[0060] With continuing reference to FIG. 2, the receiver <b>206</b>(<b>0</b>) includes input pins <b>214</b>A and <b>214</b>B coupled to respective channels <b>222</b> for receiving a differential serial data signal <b>216</b>. Serial data signal <b>216</b> includes first and second differential signals <b>216</b>A and <b>216</b>B, which have baud rates in the multi-gigabit per second range. Receiver <b>206</b>(<b>0</b>) converts the serial data signal <b>216</b> into a corresponding parallel data signal <b>218</b>, and transmits the parallel data signal over a parallel data bus (not shown). The remaining transceivers <b>202</b>(<b>1</b>-<b>3</b>) are configured and operate in substantially the same manner as transceiver <b>202</b>(<b>0</b>). The serial input/output (I/O) portion of each transceiver <b>202</b>, which includes the pins <b>212</b>A-B and <b>214</b>A-B, is referred to as a port <b>220</b>.

P-0061[0061] In some embodiments, there are nine devices <b>200</b> with four ports <b>220</b> per device. Thus, there are 36 ports with 36 pairs of serial transmit and receive differential signals <b>210</b> and <b>216</b>, totaling 72 differential signals <b>210</b> and <b>216</b>, and <b>144</b> pins <b>212</b> and <b>214</b> having baud rates in the multi-Gbps range. Throughout the specification, the device <b>200</b> is referred to interchangeably as a device or core and the port <b>220</b> is referred to interchangeable as a port or a lane.

P-0062[0062] One example of a device <b>200</b> can be a SerDes Chip manufactured by Broadcom Corporation. This chip is further described in: U.S. provisional application titled, “High-Speed Serial Transceiver,” Ser. No. 60/200,813, filed Apr. 28, 2000; U.S. non-provisional patent application titled, “Timing Recovery and Frequency Tracking System and Method,” Ser. No. 09/844,432, filed Apr. 30, 2001; U.S. non-provisional patent application titled, “Timing Recovery and Phase Tracking System and Method,” Ser. No. 09/844,296, filed Apr. 30, 2001; U.S. non-provisional patent application titled, “Methods and systems for adaptive receiver equalization,” Ser. No. 09/844,283, filed Apr. 30, 2001; U.S. non-provisional patent application titled, “High-Speed Serial Data Transceiver and Related Methods,” Ser. No. 09/844,441, filed Apr. 30, 2001; and U.S. non-provisional patent application titled, “Phase Interpolator Device and Method,” Ser. No. 09/844,266, filed Apr. 30, 2001, all of which are incorporated herein by reference in their entireties.

P-0063[0063] With continuing reference to FIGS. <b>1</b>A-<b>1</b>C, <b>2</b>, <b>3</b>, and <b>7</b>, the system <b>100</b> is configured to allow the DUT holding device <b>110</b> to hold a plurality of high serial pin count devices <b>200</b>. The system <b>100</b> routes serial data at high speeds (e.g., at gigabit per second baud rates). The devices <b>200</b> are coupled to each other and the ATE <b>102</b> in various connectivity configurations via a multiplexing system <b>302</b> and a controlling system <b>306</b> on the rider board <b>112</b>, described in more detail below. These systems on the rider board <b>112</b> allow for simultaneous functional, parametric, analog, and digital at-speed testing. At-speed testing means that the testing is performed at the rated I/O speed of the semiconductor device <b>200</b>. By performing simultaneous at-speed testing, the testing time, and in turn the testing costs, are reduced 1/x for x devices.

P-0064[0064] As seen in FIGS. 1C, 3, and <b>7</b> the rider board <b>112</b> is coupled to the DIB <b>108</b> via the coupling system <b>114</b>, which includes nine connectors <b>114</b>A on the DIB <b>108</b> and nine corresponding connectors <b>114</b>B on the rider board <b>112</b> that are coupled via connector <b>114</b>C. In some embodiments, more or less connectors can be provided based on the amount of devices <b>200</b> being tested. Also, in some embodiments receptacle or female type connectors <b>114</b>A can reside on the DIB <b>108</b> and plug or male type connectors <b>114</b>B can reside on the rider board <b>112</b>, or vice versa. The connectors <b>114</b>A and <b>114</b>B are coupled together via board connectors <b>114</b>C, described in more detail below. Each connector <b>114</b>B on the rider board <b>112</b> is coupled to a core/connecting system multiplexer <b>308</b> in multiplexing system <b>302</b>. Throughout the specification, the multiplexing system <b>302</b> can be interchangeably referred to as a multiplexing system, a switching matrix, a switching fabric, or the like. When there are devices <b>200</b> installed in holding device <b>110</b>, the main core mulitplexer <b>308</b> connects from each device <b>200</b> to: a transmit analog mulitplexer <b>310</b>A (FIG. 10) in the multiplexing system <b>302</b>, a receive analog multiplexer <b>310</b>B (FIG. <b>10</b>) in the multiplexing system <b>302</b>, and an internal testing system multiplexer <b>312</b> (FIG. 10) in the multiplexing system <b>302</b>. The internal system multiplexer <b>312</b> is coupled to an internal testing system <b>304</b>, which can include bit error rate test engines (BERT engines). In some embodiments, the multiplexing system <b>302</b> can be made up of <b>226</b> high bandwidth GaAs switches <b>1202</b> (FIG. 12) controlled by a controlling system <b>306</b> via over <b>600</b> control lines. The controlling system <b>306</b> can include two field programmable gate array (FPGA) controllers <b>808</b> (FIGS. 8A, 10, <b>11</b>, and <b>15</b>).

P-0065[0065] Test Head

P-0066[0066]FIG. 4 illustrates a perspective view of a portion <b>400</b> facing outward from the test head <b>106</b> according to embodiments of the present invention. The portion <b>400</b> of the test head <b>106</b> includes the DIB <b>108</b> with the DUT holding device <b>110</b> and DIB connectors <b>904</b> (FIG. 9), which are part of the DIB connecting system <b>114</b>A. Also, the portion <b>400</b> includes a restricted section <b>404</b> and a coupling or connection section <b>406</b>, which couples the external testing system <b>102</b> to the test head <b>106</b>. As was discussed above, the test head <b>106</b> generally has some areas that cannot include any additional user or proprietary equipment or devices. The restricted section <b>404</b> is located in these areas. This, along with the coupling or connection section <b>406</b>, substantially reduces the available space on the test head <b>106</b> for the DIB <b>108</b>. This has in prior art systems limited the space available to couple more than a two DUTs because of the amount of space needed for their respective connection wiring. Thus, according to embodiments of the present invention, in order to test a plurality of devices <b>200</b>, such a nine devices, connections between different ones of the devices <b>200</b> are provided by the multiplexing system <b>302</b> and control system <b>306</b> on the rider board <b>112</b>, as will be described in more detail below.

P-0067[0067]FIG. 5 illustrates a perspective view with a cut-away section showing a portion <b>500</b> facing inward from the test head <b>106</b> according to embodiments of the present invention. The portion <b>500</b>, which is coupled on a surface of the test head <b>106</b> opposite a surface with the DUT holding device <b>110</b>, is substantially made up of the rider board <b>112</b>. The dashed square <b>502</b> on the portion <b>500</b> is where the DUT holding device <b>110</b> resides on the DIB <b>108</b>. The portion <b>500</b> includes connectors <b>804</b> (FIG. 8), which are part of the rider board connecting system <b>114</b>B. The connectors <b>804</b> correlate with and are coupled to the connectors <b>904</b> via connectors <b>114</b>C. The portion <b>500</b> also includes controllers <b>808</b> (FIG. 8), which are part of the controlling system <b>306</b>, and testers <b>810</b> (FIG. 8), which are part of the internal testing system <b>304</b>.

P-0068[0068]FIG. 6 illustrates an end view of a portion of the system <b>100</b> according to embodiments of the present invention. As can be seen, a DUT <b>600</b> is coupled to the DUT holding device <b>110</b> on the DIB <b>108</b>. Also, the DIB connecting system <b>114</b>A (not shown in this figure) are coupled via connectors <b>602</b>, which are part of the connector <b>114</b>C, to the rider board connectors <b>114</b>B (not shown in this figure). The connector <b>114</b>C can be a Teradyne connection system called “NexLev” that is rated to carry signals at to over 3.2 Gbps with a density of 145 signals per inch. For example, if the DUT <b>600</b> includes nine cores <b>200</b> there would be nine connectors <b>602</b> (one for each core), which would provide 100 signal pins and 90 grounds per connector, or a total capacity of 900 signals.

P-0069[0069] Accordingly, in order to accommodate nine devices <b>200</b>, the rider board <b>112</b> is utilized to move all signal switching/multiplexing functions <b>302</b> and the internal testing system <b>304</b> off of the DIB <b>108</b>. Hence, the necessary real estate needed on the DIB <b>108</b> for the DUT holding device <b>110</b> that can hold a plurality of cores <b>200</b>, for example nine cores <b>200</b> with 36 transmit and receive differential serial pairs, remains.

P-0070[0070] Rider Board and DIB

P-0071[0071] As seen in FIG. 8, the rider board <b>112</b> according to embodiments of the present invention includes multiple connecting sections <b>800</b>. Each of the connecting sections <b>800</b> includes hundreds or thousands of connecting devices (not shown), which can be copper strips, wires, fiber optics, or the like. The connecting devices couple all the components in the system <b>100</b> together in various configurations to route a testing signal through the system <b>100</b> in order to perform the various automated testing operations described below. In one embodiment, there are twenty connecting sections <b>800</b>. Most of the components of the rider board <b>112</b> are located on a top section <b>802</b> of the connecting sections. The top section <b>802</b> includes connector/multiplexer devices <b>804</b> (labeled C/M-<b>0</b> through C/M-<b>8</b>). The C/M devices <b>804</b> are comprised of the connectors <b>114</b>B and a set of multiplexers in the multiplexing system <b>302</b>. Although nine C/M devices <b>804</b> are shown, it is to be appreciated there may be more of less based on the amount of cores <b>200</b> being tested. The rider board <b>112</b> further includes controllers <b>808</b> and testers <b>810</b>. The controllers <b>808</b> can be field programmable gate array (FPGAs) in the controlling system <b>306</b>. The testers <b>810</b> can be BERT and/or PRBS (pseudo random bit sequence) engines in the testing system <b>304</b>. The BERT engines <b>810</b> can be located in SerDes devices (similar to devices <b>200</b>) utilized in the testing system <b>304</b>, which allows for the at-speed testing of the cores <b>200</b>.

P-0072[0072]FIG. 9 shows an arrangement of components on the DIB <b>108</b> according to embodiments of the present invention. The DUT holding device <b>110</b> includes nine cores <b>200</b> (labeled DUT-<b>0</b> through DUT-<b>8</b>), a controller <b>900</b>, and a switching system <b>902</b>. Each of the cores <b>200</b> is coupled to a corresponding connector <b>904</b> (labeled C-<b>0</b> through C-<b>8</b>). For example, nodes <b>212</b> and <b>214</b> of each core <b>200</b> are connected to a corresponding connector C<b>0</b>-C<b>8</b>. As can be seen in FIGS. 8 and 9, the C/Ms <b>804</b> are located in the same position on rider board <b>112</b> as the connectors (Cs) <b>904</b> on the DIB <b>108</b>. C/Ms <b>804</b> and Cs <b>904</b> are connected via connectors <b>602</b> (FIG. 6).

P-0073[0073]FIG. 10 is a block diagram showing more details of the elements on the rider board <b>112</b> and the DIB <b>108</b> according to embodiments of the present invention. The multiplexing system <b>302</b> on the rider board <b>112</b> is coupled to the nine cores <b>200</b> via the connecting device <b>602</b> that connects the Cs <b>904</b> on the DIB <b>108</b> to the C/Ms <b>200</b> on the rider board <b>112</b>. Signal paths associated with each of the nine cores <b>200</b> in the DUT <b>600</b> are coupled (e.g., electrically) to each other and to the external testing system <b>102</b> in various signal paths based on signal paths provided through a main core multiplexer <b>308</b> to perform during various testing operations as described in more detail below.

P-0074[0074] For example, during analog testing operations, as described in more detail below with reference to FIG. 23, the cores <b>200</b> in the DUT <b>600</b> are coupled to an analog transmit testing system <b>116</b>A in the analog testing system <b>116</b> via the transmit analog multiplexer <b>310</b>A and/or to an analog receive testing system <b>116</b>B in the analog testing system <b>116</b> via the receive analog multiplexer <b>310</b>B. In another example, during BERT testing operations, as described in more detail below with respect to FIG. 22A, the cores <b>200</b> in the DUT <b>600</b> are coupled to one of two BERT engines <b>1010</b>A and <b>1010</b>B via BERT multiplexers <b>312</b>A and <b>312</b>B located in the multiplexing system <b>302</b>. Input and output (I/O) nodes in the analog testing multiplexers <b>310</b> and the BERT multiplexers <b>312</b> are controlled via the multiplexer controller <b>306</b> to form signal paths through the multiplexers <b>308</b>, <b>310</b>, and <b>312</b> and to take signals off-board. All of the components on the rider board <b>112</b> are powered via a power management system <b>1014</b>.

P-0075[0075]FIG. 11 shows a portion of connections made between elements on the rider board <b>112</b> according to embodiments of the present invention. A first set of C/Ms <b>804</b> (e.g., all but two C/Ms) can be coupled to controller <b>808</b>-<b>1</b> via control lines <b>1102</b> and a second set of C/Ms <b>804</b> (e.g., the remaining ones not coupled to <b>808</b>-<b>1</b>) and all other multiplexers (e.g., multiplexers <b>310</b> and <b>312</b>) on rider board <b>112</b> can be coupled to <b>808</b>-<b>2</b> via control lines <b>1102</b>. As will be discussed in more detail below, there are 16 multiplexers <b>1202</b> (FIG. 12) connected to each controller <b>808</b>, where each multiplexer <b>1202</b> receives 6 control lines that carry control signals from the controller <b>808</b> to the C/M <b>804</b>. Thus, each line <b>1102</b> entering a C/M <b>804</b> in FIG. 11 equates to 8×6=48 control lines. Hence, there are at least 48×9=432 total control lines between the controllers <b>808</b> and the C/Ms <b>804</b> to control the routing of signals <b>210</b> and <b>216</b> between the devices <b>200</b>, the internal testing system <b>304</b>, and the external testing system <b>102</b>. Also, there are other control lines <b>1102</b> to the other multiplexers (e.g., <b>310</b> and <b>312</b>) that are controlled by controllers <b>808</b>. In total, there can be over <b>800</b> control lines <b>1102</b>. The controlling forms signal paths through the system <b>100</b>, and more specifically through the connecting devices (now shown) on the multiple layers of connecting sections <b>800</b>. In various embodiments, either one or both of the controllers <b>808</b> can be connected to each of the C/Ms <b>804</b>. Also in various embodiments, each of the C/Ms <b>804</b> is coupled to one of the testers <b>810</b>, which can be through the BERT multiplexer <b>312</b> as shown in FIG. 10.

P-0076[0076] Rider Board Multiplexing/Switching System

P-0077[0077] Throughout the rest of the specification, the following protocol will be used to describe the system <b>100</b> and operations performed by the system <b>100</b>. TX# and RX#. This is meant to convey: T=transmitter and R=receiver; X=core number, and #=port number of the identified core. For example T00 is a transmitter in port 0 of core 0 and R21 is a receiver in port 1 of core 2. If only X is used, then no particular core is being discussed, just the cores in general.

P-0078[0078] FIGS. <b>12</b>-<b>14</b> show a more detailed view of the C/M <b>804</b> according to embodiments of the present invention. Each of the C/Ms <b>804</b> include a connector <b>1200</b> and switches or multiplexers <b>1202</b> that are located in the main core multiplexer <b>1004</b>. The multiplexers <b>1202</b> can be high bandwidth 1:6 multiplexers, i.e., multiplexers capable of passing signals having frequencies in the multi-gigabit per second range with little attenuation. The number of multiplexers <b>1202</b> coupled to the connector <b>1200</b> is based on the number of pins <b>212</b> and <b>214</b> associate with each core <b>200</b>. In the example being used throughout the specification, each core <b>200</b> has four ports <b>220</b> with four pins <b>212</b>A-B and <b>214</b>A-B per port <b>220</b> for a total of 16 pins. Thus, the connector <b>1200</b> would need to be coupled to 16 multiplexers <b>1202</b>, one for each pin <b>212</b> and <b>214</b>.

P-0079[0079]FIG. 13 illustrates a pair <b>1300</b> of multiplexers <b>1202</b>(TX) and <b>1202</b>(RX) according to embodiments of the present invention. Signal paths through the multiplexers <b>1202</b> are shown as dashed lines. If multiplexer <b>1202</b>(TX) is routing a signal <b>210</b> originating from pin <b>212</b>(TX), the signal <b>210</b> is input at node <b>1302</b> and can be selectively routed under control of the controller <b>808</b> via control line <b>1303</b> carrying at least six control signals to one of six nodes: (1) a TX Core Loopback first direction node <b>1306</b>; (2) a TX Core Loopback second direction node <b>1308</b>, (3) a TX Analog node <b>1310</b>; (4) a BERT multiplexer node <b>1312</b>; (5) a high speed digital (HSD) node <b>1314</b> (coupled to the digital testing system <b>118</b>); or (6) a RX node <b>1316</b>. Multiplexer <b>1202</b>(TX) routes a signal from node <b>1302</b> to a selected on of nodes <b>1306</b>-<b>1316</b> by connecting node <b>1302</b> to the selected node.

P-0080[0080] With continuing reference to FIG. 13, similarly, if multiplexer <b>1202</b>(RX) is routing a signal <b>216</b> going to <b>214</b>(RX), the signal <b>216</b> is output from node <b>1302</b> and can be selectively routed under control of the controller <b>808</b> via control line <b>1303</b> carrying at least six control signals. The signal <b>216</b> is input at one of six nodes: (1) a RX Core Loopback first direction node <b>1318</b>; (2) a RX Core Loopback second direction node <b>1320</b>; (3) a RX Analog node <b>1322</b>; (4) a BERT multiplexer node <b>1324</b>, (5) a HSD node <b>1326</b>; or (6) a TX node <b>1328</b>. A more detailed discussion of the signal paths through the pair of multiplexers <b>1300</b> during testing operations will be discussed below. It is to be appreciated, multiplexers do not have to be in pairs, but can be by themselves.

P-0081[0081]FIG. 14 shows one embodiment of an arrangement of the multiplexer pairs <b>1300</b>. In this figure, the pairs <b>1300</b> are arranged corresponding to a device <b>200</b> having 4 ports/lanes <b>220</b> with differential transmit <b>212</b> and receive <b>214</b> pins.

P-0082[0082]FIG. 15 shows connections between components in a portion of the system <b>100</b> according to embodiments of the present invention. Thus, if core <b>200</b>(<b>5</b>) on DIB <b>108</b> is designated to transmit a signal <b>210</b>, the signal <b>210</b> leaving from the core <b>200</b>(<b>5</b>) along the channels <b>222</b>(T<b>50</b>) travels to a corresponding DIB connector <b>904</b>(C<b>5</b>), through connector <b>602</b>(<b>5</b>), to corresponding rider board connector <b>1200</b>(C<b>5</b>), to the node <b>1302</b> on multiplexer <b>1202</b>(T<b>50</b>). Then, the controller <b>808</b> sends a control signal to the multiplexer <b>1202</b>(T<b>50</b>) to select the node (e.g., <b>1306</b>-<b>1316</b>) through which the signal <b>210</b> will be routed. In a similar fashion, when the core <b>200</b>(<b>5</b>) is designated to receive signal <b>216</b>, signal <b>216</b> will enter the multiplexer <b>1202</b>(R<b>50</b>) from one of the nodes (e.g. <b>1318</b>-<b>1328</b>) and be routed under control of the controller <b>808</b> out node <b>1304</b>. The signal <b>216</b> then travels through the connectors <b>1200</b>(C<b>5</b>), <b>602</b>(<b>5</b>), and <b>904</b>(C<b>5</b>) to the pin <b>214</b>A(R<b>50</b>) or <b>214</b>B(R<b>50</b>) of core <b>200</b>(<b>5</b>).

P-0083[0083] FIGS. <b>16</b>A-<b>16</b>B, which are unlabeled for convenience, are schematic diagrams showing the connections on the rider board between multiplexers <b>1202</b>, <b>1004</b>, <b>1006</b>, and <b>312</b> for cores <b>200</b>(<b>0</b>)-<b>200</b>(<b>2</b>). This figure only shows the TX+ and RX+ multiplexers <b>1202</b> corresponding to TX+ and RX+ pins <b>212</b>A and <b>212</b>B and <b>214</b>A and <b>214</b>B of the cores <b>200</b>(<b>0</b>)-<b>200</b>(<b>2</b>). As will be described in more detail below regarding the operation of system <b>100</b>, various automated testing operations are performed on the cores <b>200</b> based on the connections and signal paths formed between the multiplexers <b>1202</b>, <b>1006</b>/<b>1008</b>, and <b>1012</b>.

P-0084[0084] The rider board <b>112</b> accomplishes routing of serial data signals having Gbps baud rates in some embodiments with high bandwidth switches <b>1202</b> (e.g., GaAs switches) implemented as various stages of multiplexers in the multiplexing system <b>302</b>. This arrangement allows for complete (e.g., end-to-end) routing of serial data signals from the DUT <b>600</b> to all necessary resources. The routing allows for many instances of parallel testing operations (e.g., simultaneous core loop back, snaking, BERT, etc.), as well as the ability to route any DUT serial data signal to an external testing system <b>102</b> resource. Radio frequency (RF) cables from the external testing system <b>102</b>, which are for carrying signals, are directly coupled to the rider board <b>112</b>. Full connectivity allows for at least the following testing operations: differential signal connectivity to BERT/PRBS engines <b>1010</b>, differential signal connectivity to analog instruments <b>116</b>, differential connectivity to external testing system devices <b>102</b>, self core loopback, adjacent core loopback, and snaking configurations.

P-0085[0085] The ability to perform simultaneous or parallel testing of multiple cores <b>200</b>, which can be integrated and/or fabricated on one semiconductor, greatly reduces test time and the cost of testing. Also, because the rider board <b>112</b> provides high bandwidth signal paths to the analog testing system <b>116</b>, as the external testing system <b>102</b> gradually introduces higher and higher bandwidth instrumentation, the DUT <b>600</b> can immediately make use of the external testing system improvements via the rider board <b>112</b>.

P-0086[0086] As discussed above, in some embodiments of the rider board <b>112</b> the internal testing system <b>304</b> can include one or more SerDes chips or other silicon technology manufactured by Broadcom Corporation as the source for at-speed digital functional testing and BERT testing. These embodiments can make use of Broadcom's design-for-test (DFT) approach to manufacturing chips that have integrated BERT and PRBS generators complete with on-chip memory and programmable transmit amplitudes. Therefore, by using Broadcom semiconductors in these embodiments, the need for focused external testing system instruments or BERT/PRBS bench instrumentation is substantially reduced. Also, the rider board <b>112</b> allows for rapid upgrades with silicon speed improvements with a simple board re-design for new semiconductor device(s). In the embodiments using Broadcom semiconductors on the rider board <b>112</b>, the semiconductors can be programmed via industry standard Managed Data Interface (MDI-IEEE 802.3 clause 22 and 45), which allows rapid programming to alleviate the need for slow external general purpose interface bus (GPIB) interface to BERT/PRBS bench instrumentation.

P-0087[0087] Automated At-Speed Self Testing Operations

P-0088[0088] Throughout the rest of the figures, external arrows between cores <b>200</b> or between ports <b>220</b> of a core <b>200</b> represent a signal path traversing the multiplexer system <b>302</b> on the rider board <b>112</b> or established through the multiplexer system <b>302</b> on the rider board <b>112</b>. This routing is illustrated in detail in FIGS. 18B, 19B, <b>22</b>, and <b>23</b>. Arrows shown inside the cores <b>200</b> represent internal looping either within the core <b>200</b> or through the DUT socket circuitry. In FIGS. <b>17</b>A-<b>17</b>C, <b>18</b>A-<b>18</b>B, <b>22</b>A-<b>22</b>B, and <b>23</b>B, signals that appear to be generated from a core <b>200</b> can be generated by a signal source (e.g., a BERT engine) in that core <b>200</b>. Other signals can be generated, as shown, from sources outside cores <b>200</b>. Although not shown, a device and/or apparatus can be coupled to the individual cores <b>200</b> or to tested system <b>104</b> to gather the data accumulated during the testing to evaluate the performance of the DUTs <b>110</b>.

P-0089[0089] FIGS. <b>17</b>A-<b>17</b>C, <b>18</b>A-<b>18</b>B, and <b>19</b>A-<b>19</b>B illustrate automated self testing operations in the system <b>100</b> according to embodiments of the present invention. Throughout the description of the operations of system <b>100</b> it is to be appreciated that, although not always described, every signal can be a serial data signal <b>210</b> and can be routed through signal paths formed through the multiplexers <b>1202</b> based on control signals from the controller <b>808</b>. The control signal determines which output node on the multiplexer <b>1202</b> an input signal <b>210</b> is output. It is to be appreciated that almost all the automated testing operations involve full duplex serial data signal transmission. That means that all the pins <b>212</b> and <b>214</b> are transmitting and receiving serial data signals <b>210</b> and <b>216</b> at the same time. Thus, in our example of having nine cores <b>200</b> with four ports <b>220</b> per core <b>200</b> and four channels <b>222</b> (or four pins <b>212</b> and <b>214</b>) per port <b>220</b>, 144 serial data signals <b>210</b> and <b>216</b> are routed by a core <b>200</b> to an adjacent core <b>200</b> at the same time.

P-0090[0090]FIG. 17A shows an automated self loopback method <b>1700</b> according to embodiments of the present invention. During this operation <b>1700</b>, serial data signals <b>210</b> generated in the core <b>200</b> are routed through the multiplexers <b>1202</b> corresponding to that core <b>200</b> and back to that core <b>200</b>. For example, serial data signals <b>210</b> transmitted from the core <b>200</b>(X) are received at node <b>1302</b> of the corresponding transmit multiplexer <b>1202</b>(TX) and routed to and output from node <b>1316</b>. The serial data signals <b>210</b>/<b>216</b> are then received at node <b>1328</b> of the receive multiplexer <b>1202</b>(RX) and routed to and output from node <b>1304</b>. The serial data signals <b>216</b> then travel back to the same core <b>200</b>(X). Similarly, all the other cores <b>200</b>(<b>1</b>-<b>8</b>) and their corresponding multiplexer can be routing serial data signals.

P-0091[0091]FIG. 17B shows an automated full duplex adjacent core loopback method <b>1710</b> in a first “direction,” where a direction can be a grouping of adjacent cores <b>200</b>. The first direction configures cores <b>200</b> as follows: 0-1, 23, 4-5, and 6-7, where core 8 is not involved. During this operation, serial data signals <b>210</b> output from all the pins <b>212</b>A-B in a first core <b>200</b> are routed through the multiplexers <b>1202</b> to a second, adjacent core <b>200</b>, while serial data signals <b>210</b> output from all the pins <b>212</b>A-B in the second core <b>200</b> are sent from the second core <b>200</b> and routed through the multiplexers <b>1202</b> to the first core <b>200</b>. For example, serial data signals <b>210</b> generated from core <b>200</b>(<b>0</b>) are received at nodes <b>1302</b> on corresponding transmit multiplexer <b>1202</b>(TO) and routed to and output from nodes <b>1306</b>. The signals <b>210</b>/<b>216</b> are then received at nodes <b>1318</b> in the multiplexers <b>1202</b>(R<b>1</b>) and routed to and output from nodes <b>1304</b> to core <b>200</b>(<b>1</b>). Also, core <b>200</b>(<b>1</b>) simultaneously sends serial data signals <b>210</b> to core <b>200</b>(<b>0</b>) based on the same functionality of the system <b>100</b>. Further, all the other core pairs, 2-3, 4-5, and 6-7, can be simultaneously routing serial data signals <b>210</b>/<b>216</b> between each other through their corresponding multiplexers.

P-0092[0092]FIG. 17C shows an automated full duplex adjacent core loopback method <b>1720</b> in a second direction. The second direction configures cores <b>200</b> as follows: 1-2, 3-4, 5-6, and 7-8, where core 0 is not involved. During this operation, serial data signals <b>210</b> output from all the pins <b>212</b>A-B in a first core <b>200</b> are routed through the multiplexers <b>1202</b> to a second, adjacent core <b>200</b>, while serial data signals <b>210</b> output from all the pins <b>212</b>A-B in the second, adjacent core <b>200</b> are sent from the second core <b>200</b> and routed through the multiplexers <b>1202</b> to the first core <b>200</b>. For example, serial data signals <b>210</b> generated from core <b>200</b>(<b>1</b>) received at nodes <b>1302</b> on corresponding transmit multiplexer <b>1202</b>(T<b>1</b>) and routed to and output from the nodes <b>1308</b>. The signals <b>210</b>/<b>126</b> are then received at nodes <b>1320</b> in the multiplexers <b>1202</b>(R<b>2</b>) and routed to and output from nodes <b>1304</b> to core <b>200</b>(<b>2</b>). Also, core <b>200</b>(<b>2</b>) simultaneously sends serial data signals to core <b>200</b>(<b>1</b>) based on the same functionality of the system <b>100</b>. Further, all the other pairs, 3-4, 5-6, and 7-8, are simultaneously sending serial data signals <b>210</b>/<b>126</b> between each other.

P-0093[0093] FIGS. <b>18</b>A-B pictorially show an automated internal snake down testing operation <b>1800</b> according to embodiments of the present invention. During this operation <b>1800</b> signals generated in core <b>200</b>(<b>0</b>) are sequentially routed through all the cores <b>200</b> until they reach core <b>200</b>(<b>8</b>). In order to perform this operation <b>1800</b>, both the adjacent core loopback operations <b>1710</b> and <b>1720</b> are performed in alternating fashion. For example, operation <b>1710</b> is performed to send signals from core <b>200</b>(<b>0</b>) to core <b>200</b>(<b>1</b>), then operation <b>1720</b> is performed to send signals from core <b>200</b>(<b>1</b>) to core <b>200</b>(<b>2</b>), then operation <b>1710</b> is performed to send signals from core <b>200</b>(<b>2</b>) to core <b>200</b>(<b>3</b>), and so on.

P-0094[0094] With continuing reference to FIG. 18B, the signal path for the operation <b>1800</b> is shown. Only the first three stages are shown for convenience. During a first stage, a signal generated in core <b>200</b>(<b>0</b>) is transmitted from pin <b>212</b>A(T<b>00</b>) to connector <b>904</b>(C<b>0</b>), to connector <b>1200</b>(C<b>0</b>), to node <b>1302</b>(T<b>00</b>), to node <b>1306</b>(T<b>00</b>), to node <b>1318</b>(R<b>10</b>), to node <b>1304</b>(R<b>10</b>), to connector <b>1200</b>(C<b>1</b>), to connector <b>904</b>(C<b>1</b>), and to pin <b>214</b>A(R<b>10</b>) in core <b>200</b>(<b>1</b>). During a second stage, the signal is passed through the core <b>200</b>(<b>1</b>) to be transmitted from pin <b>212</b>A(T<b>10</b>), to connector <b>904</b>(C<b>1</b>), to connector <b>1200</b>(C<b>1</b>), to node <b>1302</b>(T<b>10</b>), to node <b>1308</b>(T<b>10</b>), to node <b>1320</b>(R<b>20</b>), to node <b>1304</b> (R<b>20</b>), to connector <b>1200</b>(C<b>2</b>), to connector <b>904</b>(C<b>2</b>), and to pin <b>214</b>A(R<b>20</b>) in core <b>200</b>(<b>2</b>). During a third stage, the signal is passed through the core <b>200</b>(<b>2</b>) to be transmitted from pin <b>212</b>A(T<b>20</b>), to connector <b>904</b>(C<b>2</b>), to connector <b>1200</b>(C<b>2</b>), to node <b>1302</b>(T<b>20</b>), to node <b>1306</b>(T<b>20</b>), to node <b>1318</b>(R<b>30</b>), and so on. The subsequent stages follow a similar pattern for the signal path.

P-0095[0095] FIGS. <b>19</b>A-B pictorially show an automated internal snake-up testing operation <b>1900</b> according to embodiments of the present invention. During this operation <b>1900</b> signals generated in core <b>200</b>(<b>8</b>) are routed in reverse sequence through all the cores <b>200</b> until they reach core <b>200</b>(<b>0</b>). In order to perform this operation <b>1900</b>, both the adjacent core loopback operations <b>1710</b> and <b>1720</b> are performed in alternating fashion. For example, operation <b>1720</b> is performed to send signals from core <b>200</b>(<b>8</b>) to core <b>200</b>(<b>7</b>), then operation <b>1710</b> is performed to send signals from core <b>200</b>(<b>7</b>) to core <b>200</b>(<b>6</b>), then operation <b>1720</b> is performed to send signals from core <b>200</b>(<b>6</b>) to core <b>200</b>(<b>5</b>), and so on.

P-0096[0096] With continuing reference to FIG. 19B, the signal path for the operation <b>1900</b> is shown. Only the first three stages are shown for convenience. During a first stage, a signal generated in core <b>200</b>(<b>8</b>) is transmitted from pin <b>212</b>A(T<b>80</b>) to connector <b>904</b>(C<b>8</b>), to connector <b>1200</b>(C<b>8</b>), to node <b>1302</b>(T<b>80</b>), to node <b>1308</b>(T<b>80</b>), to node <b>1320</b>(R<b>70</b>) to node <b>1304</b>(R<b>70</b>), to connector <b>1200</b>(C<b>7</b>), to connector <b>904</b>(C<b>7</b>), and to pin <b>214</b>A(R<b>70</b>) of core <b>200</b>(<b>7</b>). During a second stage, the signal is passed through the core <b>200</b>(<b>7</b>) to be transmitted from pin <b>212</b>A(T<b>70</b>) to connector <b>904</b>(C<b>7</b>), to connector <b>1200</b>(C<b>7</b>), to node <b>1302</b>(T<b>70</b>), to node <b>1306</b>(T<b>70</b>), to node <b>1318</b>(R<b>60</b>), to node <b>1304</b>(R<b>60</b>), to connector <b>1200</b>(C<b>6</b>), to connector <b>904</b>(C<b>6</b>), and to pin <b>214</b>A(R<b>60</b>) in core <b>200</b>(<b>6</b>). During a third stage, the signal is passed through the core <b>200</b>(<b>6</b>) to be transmitted from pin <b>212</b>A(T<b>60</b>) to connector <b>904</b>(C<b>6</b>), to connector <b>1200</b>(C<b>6</b>), to node <b>1302</b>(T<b>60</b>), to node <b>1308</b>(T<b>60</b>), to node <b>1320</b>(R<b>50</b>), and so on.

P-0097[0097] Thus, as can be seen through the description to FIGS. <b>17</b>A-<b>19</b>B, the operations are based on a certain protocol. That protocol can be summarized as follows: (1) determine what core <b>200</b> a signal (e.g., a first signal) will be transmitted from; (2) determine which core <b>200</b> a signal (e.g., a second signal) will be transmitted to; (3) determine which pin the signal will be transmitted from; and (4) generate at least one control signal in the controller <b>808</b> that is transmitted to the multiplexers <b>1202</b> associated with the cores <b>200</b> and pins <b>212</b> and <b>214</b> based on the determinations. This protocol follows through for almost all automated testing operations discussed above and below.

P-0098[0098] Automated At-Speed External System Testing Operations

P-0099[0099] In FIGS. <b>20</b>-<b>22</b>B, automated full duplex at-speed (e.g., multiple gigabit per second baud rate) functional system testing methods and operations are shown. These tests can involve using a test signal from the internal <b>304</b> testing systems in the signal path. Thus, test signals may not be generated from a core under test as was done in the automated self testing operations described above. However, the general protocol still applies, as do the signal paths as described above. Thus, a main difference between the self testing and functional testing operations is that signals will be input from, output to, or routed through internal <b>304</b> testing system instead of directly between multiplexers <b>1202</b>. Therefore, for convenience of discussion, only additional steps or signal paths will be discussed and previous signal paths will be referenced. Full duplex testing allows for testing using different frequencies (e.g., a core clock and a BERT engine clock), so there will be asynchronous frequency offset between a near end and far end of the system.

P-0100[0100]FIG. 20 pictorially shows an exemplary automated external snake down testing operation <b>2000</b>, which is similar to the automated internal snake down testing operation <b>1800</b>. A main difference between operation <b>2000</b> and operation <b>1800</b> is that instead of core <b>200</b>(<b>0</b>) generating a test signal, core <b>200</b>(<b>0</b>) receives a test signal <b>2002</b> from the external tester <b>304</b>. After receiving the test signal at core <b>200</b>(<b>0</b>), the system utilizing rider board <b>112</b> routes the signal sequentially in an ascending core order to the other cores <b>200</b> using the signal path as described above with reference to FIGS. <b>18</b>A-<b>18</b>B and the internal snake down operation <b>1800</b>. After passing through core <b>200</b>(<b>8</b>), the signal is sent back to the internal testing system <b>304</b>.

P-0101[0101]FIG. 21 pictorially shows an exemplary automated external snake up testing operation <b>2100</b>, which is similar to the automated internal snake up testing operation <b>1900</b>. A main difference between operation <b>2100</b> and operation <b>1900</b> is that instead of core <b>200</b>(<b>8</b>) generating a test signal, core <b>200</b>(<b>8</b>) receives a test signal <b>2102</b> from the internal testing system <b>304</b>. After receiving the test signal at core <b>200</b>(<b>8</b>), the system <b>100</b> utilizing rider board <b>112</b> routes the signal sequentially in a descending core order to the other cores <b>200</b> using the signal path as described above with reference to FIGS. <b>19</b>A-<b>19</b>B and the internal snake down operation <b>1900</b>. After passing through core <b>200</b>(<b>8</b>), the signal is sent back to the internal testing system <b>304</b>.

P-0102[0102]FIG. 22A pictorially shows an exemplary automated BERT testing operation <b>2200</b> according to embodiments of the present invention. This testing operation <b>2200</b> is most similar to the self loopback method <b>1700</b> shown in FIG. 17A. One different is that two signals are flowing through the system, one from a BERT engine in a core <b>200</b> and one from BERT engines on rider board <b>112</b>, are utilized. Another difference is that the signal received from a core <b>200</b> at node <b>1302</b> of the pair of multiplexers <b>1300</b> is routed to and output from node <b>1312</b> to the BERT engine <b>1010</b>A/B via the BERT multiplexer <b>1012</b>A/B. After passing through the BERT engine <b>1010</b>A/B, the signal is received at node <b>1324</b> and routed to and output through node <b>1304</b> back to the same core <b>200</b> from which it was transmitted. Thus, the signal interacts with the internal testing system <b>304</b> before being routed back to its initial core <b>200</b>.

P-0103[0103] As seen in FIG. 22A, four cores <b>200</b>(<b>0</b>-<b>3</b>) are coupled to the first BERT engine <b>1010</b>A through the first BERT multiplexer <b>1012</b>A and five cores <b>200</b>(<b>4</b>-<b>8</b>) are coupled to the second BERT engine <b>1010</b>B through the second BERT multiplexer <b>1012</b>B. In alternative configurations, more or less BERT multiplexers <b>312</b> can be used, thus changing the number of cores <b>200</b> coupled to a single the BERT engine <b>1010</b>.

P-0104[0104] Automated Analog Testing Methods

P-0105[0105]FIG. 23A pictorially illustrates an automated analog transmit testing operation <b>2300</b> according to embodiments of the present invention. A signal generated by a core <b>200</b> is received at node <b>1302</b> of the pair of multiplexers <b>1300</b> and routed to and output from node <b>1310</b> to analog transmit multiplexers <b>310</b> and then to an analog transmit testing system <b>116</b>A in external testing system <b>102</b>. As shown, cores <b>200</b>(<b>0</b>)-<b>200</b>(<b>3</b>) use analog system multiplexer <b>310</b>A-<b>1</b> and cores <b>200</b>(<b>4</b>)-<b>200</b>(<b>8</b>) use analog system multiplexer <b>310</b>A-<b>2</b>. It is to be appreciated, the cores can be grouped in any manner, so long as the multiplexer <b>310</b>A receiving the signal from four of cores <b>200</b> is a 16:1 multiplexer and the multiplexer <b>310</b>A receiving the signal from five of cores <b>200</b> is a 20:1 multiplexer. Once received, the signals are processed in analog transmit testing system <b>116</b>A by a digital processing device (e.g., a GigaDig device) and evaluated.

P-0106[0106] During an automated analog transmit testing operation, the transmit multiplexers <b>1202</b>A are controlled by controller <b>808</b> to route signals received at node <b>1302</b> to node <b>1310</b> and then to the analog transmit multiplexers <b>310</b>A. In turn, the analog transmit multiplexers <b>310</b>A are controlled by controller <b>808</b> to route signals to the analog transmit signal testing system <b>116</b>A.

P-0107[0107]FIG. 23B pictorially illustrates an automated analog receive testing operation <b>2350</b> according to embodiments of the present invention. During automated analog receive testing operation <b>2350</b> signals are generated in analog testing system <b>116</b> and transmitted to core <b>200</b> via signal paths established on rider board <b>112</b> by controllers <b>808</b>. There are several embodiments of signal generation. A first embodiment includes signal generators <b>116</b>B-<b>1</b> (e.g., ATE source1, ports 1 and 2) that route signals through analog receive multiplexers <b>310</b>B-<b>1</b> and <b>310</b>B-<b>2</b> and through C/Ms <b>804</b> to be received at cores <b>200</b>. A second embodiment includes signal generators <b>116</b>B-<b>2</b> (e.g., ATE source2, ports 1 and 2) that route signals through analog receive multiplexers <b>310</b>B-<b>1</b> and <b>310</b>B-<b>2</b> and through C/Ms <b>804</b> to be received at cores <b>200</b>. A third embodiment includes signal generator <b>116</b>B-<b>3</b> (e.g., ATE source3, ports 1 and 2) that routes signals through analog receive multiplexer <b>310</b>B-<b>3</b> to analog receive multiplexers <b>3101</b>B-<b>1</b> and <b>3101</b>B-<b>2</b> and through C/Ms <b>804</b> from node <b>1322</b> out node <b>1304</b> to be received at cores <b>200</b>. Signal generators <b>116</b>B can be sine wave generators. In other embodiments, two or three of the signal generators <b>116</b>B can be used to simultaneously or sequentially route different types of signals (e.g., sine waves and jitter modulation) through the rider board <b>112</b> to the cores <b>200</b>.

P-0108[0108] During an automated analog receive testing operation, the analog receive signal testing system <b>116</b>B generates a signal that is passed to the analog receive multiplexers <b>1008</b>, which are controlled by controller <b>808</b> to route the signal to node <b>1322</b> of the receive multiplexers <b>1202</b>. The receive multiplexers <b>1202</b> are controlled by controller <b>808</b> to route the signal to node <b>1304</b> from which it is output the core <b>200</b> it came from.

P-0109[0109] Overall Methodology

P-0110[0110]FIG. 24 illustrates a flow chart depicting a method <b>2400</b> for performing automated at-speed testing of devices (e.g., <b>200</b>) according to embodiments of the present invention. At step <b>2402</b> multiplexer control signals are generated. At step <b>2404</b>, various signal paths are formed between a set of multiplexers and the devices based on the multiplexer control signals. At step <b>2406</b>, test signals having multiple gigabit per second (MGBPS) baud rates are routed through the signal paths.

P-0111[0111]FIG. 25 illustrates a flowchart depicting a method <b>2500</b> occurring during the generating multiplexer control signals step <b>2402</b>. At step <b>2502</b>, first signals are generated indicating where the test signals are being transmitted from. At step <b>2504</b>, second signals are generated indicating where the test signals are being transmitted to. At step <b>2506</b>, the multiplexer control signals are generated from the first and second signals.

P-0112[0112]FIG. 26 illustrates a flowchart depicting a method for performing automated at-speed testing of a device. At step <b>2602</b>, a set of multiplexers that includes one multiplexer for each of pin on the device is coupled to a rider board. At step <b>2604</b>, each pin of each multiplexer in the set of multiplexers is individually controlled. At step <b>2606</b>, signal paths are formed through each of the multiplexers based on the individually controlling step <b>2604</b>.

P-0113[0113] Conclusion

P-0114[0114] While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. It will be apparent to persons skilled in the relevant art that various changes in form and detail can be made therein without departing from the spirit and scope of the invention. Thus, the breadth and scope of the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.