Exposure apparatus and method

BACKGROUND OF THE INVENTION

[0001] The present invention relates generally to exposure apparatuses and methods, and more particularly to an exposure apparatus and method for projecting and exposing an object, such as a single crystal substrate for a semiconductor wafer, a glass plate for a liquid crystal display (“LCD”).

[0002] The fabrication of a device, such as a semiconductor device, an LCD device, and a thin film magnetic head using the lithography technique has employed a projection exposure apparatus that uses a projection optical system to project a circuit pattern formed on a mask or reticle (these terms are used interchangeably in this application) onto a wafer and the like, thereby transferring the circuit pattern.

[0003] The projection exposure apparatus has been required to project and expose a circuit pattern on a reticle onto a wafer with higher resolution along with the finer process and higher density of integrated circuits devices. The critical dimension or resolution transferable in the projection exposure apparatus is in proportion to a wavelength of light used for the exposure and in reverse proportion to a numerical aperture (NA) in the projection optical system. Therefore, recent light sources have been in transition from the ultra-high pressure mercury lamp (including g-line (with a wavelength of about 436 nm) and i-line (with a wavelength of about 365 nm)) to a KrF excimer laser with a shorter wavelength (i.e., a wavelength of about 248 nm) to the ArF excimer laser (with a wavelength of about 193 nm), and practical use of the F₂laser (with a wavelength of about 157 nm) is also being promoted. A further expansion of the exposure area has been also required.

[0004] In order to satisfy these requirements, a step-and-repeat exposure apparatus (also referred to as a “stepper”) for entirely projecting and exposing an approximately square exposure area onto a wafer with a reduced exposure area has been replaced mainly with a step-and-scan exposure apparatus (also referred to as a “scanner”) for accurately exposing a wide screen of exposure area through a rectangular slit with relatively and quickly scanning the reticle and the wafer.

[0005] In exposure, the scanner uses a surface-position detector in an oblique light projection system to measure a surface position at a certain position on the wafer before the exposure slit area moves to the certain position on the wafer, and correctingly accords the wafer surface with an optimal exposure image-surface position when exposing the certain position, thereby reducing influence of the flatness of the wafer. In particular, there are plural measurement points in longitudinal direction of the exposure slit, i.e., a direction orthogonal to the scan direction, at front and back stages to the exposure slit area to measure an inclination or tilt of the surface as well as a height or focus of the wafer surface position. In general, the scan exposure proceeds in both directions from the upper stage and from the back stage. Therefore, these measurement points are arranged at front and back stages to the exposure slit area so as to measure the focus and tilt on the wafer before exposure. Japanese Laid-Open Patent Application No. 9-45609 (corresponding to U.S. Pat. No. 5,750,294) discloses, for example, a method for measuring such focus and tilt.

[0006] Japanese Laid-Open Patent Application No. 6-260391 (corresponding to U.S. Pat. No. 5,448,332) proposes, as a method for measuring a surface position on a wafer in a scanner and for correction the same, an arrangement of plural measurement points on a pre-scan area other than the exposure area to measure the focus and tilt in scan and non-scan directions. Japanese Laid-Open Patent Application No. 6-283403 (corresponding to U.S. Pat. No. 5,448,332) proposes as a method for measuring the focus and tilt in the scan and non-scan directions and for driving and correcting the same, by arranging plural measurement points in the exposure area.

[0007] A description will be given of these proposals with reference to FIGS. 10 and 11. Here, FIG. 10 is a schematic sectional view of focus and tilt measurement points FP<b>1</b> to FP<b>3</b> on the wafer <b>1000</b>. FIG. 11 is a schematic sectional view showing the wafer <b>1000</b> that has been driven to an optimal exposure image-surface position based on the measurement results. Referring to FIG. 10, the focus and tilt are sequentially measured at the measurement points FP<b>1</b> to FP<b>3</b> on the wafer <b>1000</b>. A pre-scan plane PMP is calculated based on the measurement results from the measurement points FP<b>1</b> to FP<b>3</b>, and the orientation of the wafer is driven and adjusted to the best focus plane BFP in moving the wafer <b>1000</b> to the exposure position or exposure slit <b>2000</b>, as shown in FIG. 11.

[0008] However, the recent increasingly shortened wavelength of the exposure light and the higher NA of the projection optical system have required an extremely small depth of focus (“DOF”) and a stricter accuracy with which the wafer surface to be exposed is aligned to the best focus position BFP or so-called focus accuracy.

[0009] In particular, they have also required stricter measurement and precise correction of the tilt of the wafer surface in the scan direction or width direction of the exposure slit. A wafer having an insufficiently flat surface has disadvantageous focus detection accuracy in the exposure area. For example, when the exposure apparatus has a DOF with 0.4 μm, the flatness of the wafer requires several nanometer order, for example, the flatness of the wafer needs 0.08 μm where it is one-fifth as long as the DOF, or 0.04 μm where it is one-tenth as long as the DOF.

[0010] In addition, while a surface-position detector in the oblique light projection system measures the wafer's surface position before the area hangs over the exposure slit, the measurement timing is discrete and no information is available or considered about the wafer's flatness between two timings. As a result, there is no information available between timings of the flatness of the wafer.

[0011] For example, this measurement timing is at an interval of 3 mm on the wafer <b>1000</b> in the scan direction as shown in FIG. 12. Then, the wafer <b>1000</b> has such an insufficient flatness due to lack of the information for a distance of 3 mm, e.g., between points P<b>1</b> to P<b>2</b> in FIG. 12 that the front position may offset by Δ from the pre-scan plane PMP calculated by the measurement at the interval of 3 mm. Here, FIG. 12 is a schematic sectional view showing an offset of flatness between the pre-scan plane PMP and the wafer <b>1000</b>.

[0012] In exposure, the pre-scan plane PMP is adjusted to the best focus plane BFP, and the exposure in FIG. 12 needs a shift by the amount of Δ. This shift occurs in a direction orthogonal to the scan direction as well as the scan direction. This results from an arrangement of measurement points in the above oblique light projection system, rather than the measurement timing.

[0013] The finer measurement timing in the scan direction and the increased number of measurement points in the oblique light projection system would reduce an offset error, but might disadvantageously lower the throughput due to the deteriorated scan speed in exposure time, increase measurement time, rise cost together with the complicated apparatus structure, and grows likelihood of troubles.

BRIEF SUMMARY OF THE INVENTION

[0014] Accordingly, it is an exemplified object of the present invention to provide an exposure method and apparatus for performing a superior focus correction for the flatness of the wafer surface without lowering the throughput.

[0015] An exposure method of one aspect of the present invention for exposing a pattern formed on a reticle onto an object includes a flatness measurement step for measuring and for storing the flatness of the object, a position measurement step for measuring positions at plural points on the object, and a control step for controlling at least one of the position and tilt of the object using information of the flatness obtained by the flatness measurement step, and information on the position obtained by the position measurement step. The position measurement step may be conducted in an exposure apparatus, whereas the flatness measurement step measures the flatness of the object inside or outside the exposure apparatus.

[0016] Other objects and further features of the present invention will become readily apparent from the following description of the embodiments with reference to accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0017]FIG. 1 is a schematic block diagram of an exposure apparatus of one embodiment according to the present invention.

[0018]FIG. 2 is a schematic view of an exposure area that includes three measurement points.

[0019]FIG. 3 is a schematic view of an exposure area that includes five measurement points.

[0020]FIG. 4 is a schematic optical view showing a measurement system of an exposure station shown in FIG. 1.

[0021]FIG. 5 is a schematic arrangement view of a measurement optical system that realizes an arrangement of measurement points shown in FIG. 4.

[0022]FIG. 6 is a schematic perspective view showing exposure position and focus and tilt measurement positions on a wafer.

[0023]FIG. 7 is a schematic perspective view showing the wafer that has been drive to the exposure position based on flatness information of the wafer obtained by measurement and exposure stations in FIG. 1.

[0024]FIG. 8 is a flowchart for explaining a device fabrication method using an inventive exposure apparatus.

[0025]FIG. 9 is a detailed flowchart for Step <b>4</b> shown in FIG. 8.

[0026]FIG. 10 is a schematic sectional view showing focus and tilt measurement positions on a wafer.

[0027]FIG. 11 is a schematic sectional view showing the wafer that has been driven to an optimal image-surface position based on the measurement result.

[0028]FIG. 12 is a schematic sectional view showing an offset between a pre-scan plane and the wafer.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0029] The instant inventor has discovered that the flatness of the wafer, in particular, the flatness among measurement points (e.g., at an interval of 3 mm) of a wafer supported on a wafer chuck in an exposure apparatus does not vary during a semiconductor process. In other words, the flatness of the original wafer without a resist or pattern before the semiconductor fabrication process is the same as the flatness of the wafer that has experienced the process including, for example, an oxide-film formation and a metal process.

[0030] A process that heats up the entire wafer might cause a whole contraction, a temperature difference between the front and rear surfaces, and thus a rough shape as a whole. However, when the wafer is supported on a wafer chuck in an exposure apparatus, which rectifies its flatness, the wafer surface does not have such a rough shape. The issue in this case is the flatness in a minute interval of, for example, 3 mm that has existed in the wafer before the semiconductor fabrication process.

[0031] A description will be given of an exposure apparatus of one embodiment according to the present invention with reference to the accompanying drawings. However, the present invention is not limited to these embodiments, and each element is replaceable within a scope of the present invention. Here, FIG. 1 is a schematic block diagram of the exposure apparatus <b>1</b> of one embodiment according to the present invention.

[0032] The exposure apparatus includes, as shown in FIG. 1, a measurement station <b>100</b> and an exposure station <b>200</b>, and serves as a projection exposure apparatus that exposes onto a wafer a circuit pattern created on the reticle, e.g., in a step-and-repeat or a step-and-scan manner. Such an exposure apparatus is suitable for a sub-micron or quarter-micron lithography process, and this embodiment exemplarily describes a step-and-scan exposure apparatus (which is also called “a scanner”).

[0033] A description will now be given of the measurement station <b>100</b> that measures the flatness of the entire wafer <b>300</b> before the semiconductor fabrication process starts. Each wafer <b>300</b>, a silicon wafer without a resist or pattern which is ready for the semiconductor process, is fed to the measurement station <b>100</b>, which in turn measures the entire flatness before the wafer is fed to the exposure station <b>200</b> in order to lead the wafer to the semiconductor process. A spin coater has not yet formed any resist on a surface of the wafer <b>300</b>. The instant embodiment measures a surface shape of the entire wafer <b>300</b> using,a principle of a Fizeau interferometer.

[0034] The light emitted from a light source of the interferometer, such as a He—Ne laser <b>110</b>, is reflected by a beam splitter <b>111</b>, and expanded to a wafer size to be inspected by a beam expander <b>112</b>, before entering a mirror <b>113</b> used to generate reference light. The reference-light mirror <b>113</b> has one reflective surface, and uses the reflected light on the surface as the reference light that interferes with the reflected light from an object to be inspected. Although the light reflected by mirror <b>113</b> is used as the reference light and thus <b>113</b> is referred to as a reference-light mirror, the transmission light through this mirror is more than the reflected light in order to improve the visibility as contrast of interference fringes. The instant embodiment inspects the silicon wafer, and its reflectance is about 60% for the He—Ne laser with an oscillation wavelength of 633 nm. Since more improved visibility of interference fringes is available when the reflected light from the inspected object and reference light has the same intensity on a surface that forms interference fringes, i.e., a surface of a CCD camera <b>116</b>, the transmittance T on the one surface of the reference-light mirror <b>113</b> is calculated by the following equation 1 where R is the reflectance on the one surface of the reference-light mirror <b>113</b>:

<i>T+</i>R=1

0.6<i>T</i>²=R   EQUATION 1

[0035] It is thus understood that the transmittance T is 0.703 and the reference-light mirror <b>113</b> preferably transmits 70% of light.

[0036] The light that has passed the reference-light mirror <b>113</b> illuminates the surface of the wafer <b>300</b> as an object to be inspected, which has been supported on a wafer chuck <b>114</b>. The light reflected on the wafer <b>300</b> passes through the reference-light mirror <b>113</b>, the beam expander <b>112</b>, and the beam splitter <b>111</b>, and is expanded by a beam expander <b>115</b> to the size suitable for the CCD camera <b>116</b> for photoelectric conversion of the interference fringes of the light that has transmitted through the beam splitter <b>111</b>. The light incident upon the CCD camera <b>116</b> is photo-electrically converted into a video signal representative of information of flatness of the wafer <b>300</b>.

[0037] Then, the interval available to obtain from the flatness information on the wafer <b>300</b> is calculated. Suppose that the CCD camera <b>116</b> has a photoelectric surface of ⅔ inches and each interval of light receiving cells are 13 μm. In addition, suppose that the wafer size to be inspected has a diameter of 12 inches or 300 mm. The size of photoelectric surface of ⅔ inches is 6.6×8.8 mm and thus may receive light with a diameter of 6 mm.

[0038] Accordingly, the diameter of 300 mm is set to be a diameter of 6 mm. In other words, when the optical magnification from the wafer <b>300</b> to the CCD camera <b>116</b> is set to {fraction (6/300)}={fraction (1/50)}, the separable interval on the wafer <b>300</b> becomes 13×50=650 μm from the interval between the light receiving cells of 13 μm in the CCD camera <b>116</b>.

[0039] Thus, one piece of information on the flatness is obtained from one pixel in the CCD camera <b>116</b>. This may measure the flatness of the wafer <b>300</b> for each 0.65 mm, and provide the information of flatness between the measurement interval of, for example, 3 mm, the focus measurement in the scan direction in the exposure station <b>200</b>.

[0040] The measurement station <b>100</b> may measure the flatness of the wafer <b>300</b> using the principle of the Fizeau interferometer more precisely than a detection system <b>260</b> for detecting the focus and tilt in the exposure station <b>200</b>, and obtain the flatness information of the wafer <b>300</b> between detection intervals of the detection system <b>260</b>. When this flatness information is converted into a database for each wafer and made available as a reference table to a controller <b>270</b> in the exposure station <b>200</b>, each wafer may be recognized in the advanced stage in the semiconductor process and exposed based on this flatness information and focus and tilt information of the wafer <b>300</b> detected in the exposure station <b>200</b>.

[0041] The wafer <b>300</b> is moved to the exposure station <b>200</b> as shown in FIG. 1 after its flatness information has been measured by the measurement station <b>100</b> before the exposure, and then the exposure station <b>200</b> exposes the wafer <b>300</b> based on the flatness information of the wafer <b>300</b>. The moving wafer <b>300</b> is the best configuration because one by one movement does not stop the whole stream for high throughput, but the wafer carrier (not shown) etc. may move every twenty-five wafers, for example, to the exposure station <b>200</b> when the decreased throughput is permissible to some extent.

[0042] A description will now be given of the exposure station <b>200</b>. The light emitted from a light source <b>210</b>, such as an excimer laser, illuminates a pattern formed on a reticle <b>230</b> through an illumination optical system <b>220</b> that converts the light into exposure light with an optimal shape. The pattern on the reticle <b>230</b> includes an IC circuit pattern to be exposed, and the light emitted through the pattern forms an image near the wafer <b>300</b> surface as an image surface through a projection optical system <b>240</b>.

[0043] The reticle <b>230</b> is mounted on a reticle stage <b>235</b> movable in a plane orthogonal to an optical axis of the projection optical system <b>240</b> and in the optical-axis direction.

[0044] The wafer <b>300</b> is brought in from the measurement station <b>100</b> and mounted on a wafer stage <b>250</b> movable in a plane orthogonal to an optical axis of the projection optical system <b>240</b> and in the optical-axis direction.

[0045] Each shot area on the reticle <b>230</b> is exposed by relatively scanning the reticle stage <b>235</b> and wafer stage <b>250</b> at a speed corresponding to a ratio of an exposure magnification. After one shot of exposure ends, the wafer stage <b>250</b> is stepped to the next shot and next shot is exposed by the scan exposure in the reverse direction to the previous one. This repeats to expose the entire shot area on the wafer <b>300</b>.

[0046] During the scan exposure of one shot, the detection system <b>260</b> obtains surface position information on the surface of the wafer <b>300</b> to measure the focus and tilt, calculates the offset amount from the exposure image surface, and drives the stage <b>250</b> in focus (or height) and tilt (or inclination) directions, aligning the wafer <b>300</b> surface in the height direction for almost each exposure slit.

[0047] The detection system <b>260</b> uses an optical height measurement system using a method for introducing light to the wafer <b>300</b> surface at a large angle (or low incident angle) and detecting an image offset of the reflected light from the wafer using a position detecting element, such as a CCD camera. It projects light to plural measurement points on the wafer <b>300</b>, introduces each light to an individual sensor, and calculates the tilt of a surface to be exposed based on the height measurement information of different positions.

[0048] Plural measurement points K<b>1</b> to K<b>5</b> are arranged, as shown in FIGS. 2 and 3, to form a surface shape in the front and back areas <b>510</b> and <b>520</b> in the exposure area <b>500</b> (or exposure slit) <b>500</b>, so as to simultaneously measure focus and tilt information of the wafer <b>300</b>, in particular, tilt information in the scan direction before the exposure slit in the scan exposure moves to the exposure area <b>500</b>. FIGS. 2 and 3 are schematic views of the measurement points K<b>1</b> to K<b>5</b> for the exposure area <b>500</b>, in which FIG. 2 shows three measurement points K<b>1</b> to K<b>3</b> while FIG. 3 shows five measurement points K<b>1</b> to K<b>5</b>.

[0049]FIG. 3 arranges five measurement points K<b>1</b> to K<b>5</b> to be projected in the front area <b>510</b> for the exposure area <b>500</b> so as to precisely obtain focus and tilt information just before the exposure to the exposure area <b>500</b>, and drive and correct an exposure position. Similarly, five measurement points K<b>1</b> to K<b>5</b> are to be projected in the back area <b>520</b> for the scan exposure in the reverse direction.

[0050]FIG. 4 shows an enlarged view of an area A in FIG. 1. Here, FIG. 4 is a schematic optical view showing a focus and tilt measurement system in the exposure station <b>200</b>, although FIG. 4 shows only five measurement points K<b>1</b> to K<b>5</b> in the focus and tilt measurement area (for instance, the front area <b>510</b>) for illustrative convenience. In particular, the instant embodiment illustrates an arrangement of marks M<b>2</b> to M<b>5</b> wherein an interval between the measurement points K<b>2</b> and K<b>4</b> is different from that among the measurement points K<b>1</b>, K<b>3</b> and K<b>5</b>. Plural optical axes for the focus and tilt measurement are aligned with a direction orthogonal to the scan direction. These marks M<b>1</b> to M<b>5</b> to be projected at the measurement points K<b>1</b> to K<b>5</b> are rotated by a certain amount in a section perpendicular to the optical axis of the focus and tilt measurement optical system and then projected. As a result, the measurement slit faces obliquely on the wafer <b>300</b><i>nd </i>the slit pitch direction directs to the central measurement position.

[0051]FIG. 5 is a schematic arrangement view of the measurement optical system for realizing an arrangement of the measurement points shown in FIG. 4. Five illumination lenses <b>261</b> allows the light supplied from the light source (not shown) to illuminate slit marks for the focus measurement formed on the projection pattern mask <b>262</b> for the focus and tilt measurements. The light source preferably employs a halogen lamp or LED with such a relatively wide wavelength that the light does not expose the photoresist on the wafer <b>300</b> or is not affected by interference in the resist thin film. The mask <b>262</b> forms slit marks for plural measurement points as shown in a diagram viewed from a direction A. An optical-path synthesizer prism <b>263</b> synthesizes optical paths of beams formed from illuminated plural measurement marks, and a focus mark projection optical system <b>264</b> projects the light onto the wafer <b>300</b> obliquely.

[0052] The light reflected on the wafer <b>300</b> surface forms an intermediate imaging point in an optical-path division prism <b>266</b> through the focus light-receiving optical system <b>265</b>. After the optical-path division prism <b>266</b> divides the optical path for each measurement point, an enlargement detection optical system <b>267</b> arranged for each measurement point in order to improve measurement resolution introduces the light to a position detection element <b>268</b> for each measurement point. Each position detection element <b>268</b> uses one-dimensional CCD in this embodiment, and the arrangement direction of the elements is the measurement direction. A diagram viewed from the direction B shows a relationship among the measurement marks, the position detection element <b>268</b>, and the enlargement detection optical system <b>267</b>. The position detection element <b>268</b> for each measurement point is provided in a direction orthogonal to the slit mark.

[0053] The position detection element <b>268</b> uses a one-dimensional CCD, but may arrange a two-dimensional CCD. Alternatively, it may be adapted to form a reference slit plate on a light-receiving element imaging surface, scan light in front of the reference slit plate, and detect a transmission light volume through the reference slit plate.

[0054] A description will be given of an overview of a surface position correction in the focus and tilt measurement at the scan exposure. Before the exposure position EP moves to the wafer <b>300</b> with a rough shape in a scan direction SD, the focus of the surface position of the wafer <b>300</b>, the tilt in the longitudinal direction in the exposure slit (or a direction perpendicular to the scan direction SD) (which tilt is referred to as “tilt X”) as well as the tilt in the width direction in the exposure slit (which tilt is referred to as “tilt Y”) are conducted, as shown in FIG. 6, plural focus and tilt positions FP arranged so as to form a plane in front of the exposure slit. Based on the information of the measurement and flatness information of the wafer <b>300</b> as a database, the controller <b>270</b> provides a corrective driving, as shown in FIG. 7, to drive the wafer stage <b>250</b> to the exposure position EP. In FIG. 7, the correction has been completed so as to expose the exposure slit when the exposure slit moves to the area that has been measured before the exposure. The controller <b>270</b> may communicate with the measurement station <b>100</b>, and obtains and stores a database of the flatness of the wafer <b>300</b> that has been obtained from the measurement station <b>100</b>. Here, FIG. 6 is a schematic perspective view showing the exposure position EP, focus and tilt measurement positions FP on a wafer <b>300</b>. FIG. 7 is a schematic perspective view showing the wafer <b>300</b> that has been drive to the exposure position EP based on flatness information of the wafer <b>300</b> obtained by measurement and exposure stations <b>100</b> and <b>200</b>.

[0055] The above description refers to an arrangement of five measurement points in each surface position measurement area, but is applicable to an arrangement of three measurement points.

[0056] Referring now to FIGS. 8 and 9, a description will be given of an embodiment of a device fabrication method using the above mentioned exposure apparatus <b>1</b>. FIG. 8 is a flowchart for explaining how to fabricate devices (i.e., semiconductor chips such as IC and LSI, LCDs, CCDs, and the like). Here, a description will be given of the fabrication of a semiconductor chip as an example. Step <b>1</b> (circuit design) designs a semiconductor device circuit. Step <b>2</b> (mask fabrication) forms a mask having a designed circuit pattern. Step <b>3</b> (wafer making) manufactures a wafer using materials such as silicon. Step <b>4</b> (wafer process), which is also referred to as a pretreatment, forms actual circuitry on the wafer through lithography using the mask and wafer. Step <b>5</b> (assembly), which is also referred to as a post-treatment, forms into a semiconductor chip the wafer formed in Step <b>4</b> and includes an assembly step (e.g., dicing, bonding), a packaging step (chip sealing), and the like. Step <b>6</b> (inspection) performs various tests for the semiconductor device made in Step <b>5</b>, such as a validity test and a durability test. Through these steps, a semiconductor device is finished and shipped (Step <b>7</b>).

[0057]FIG. 9 is a detailed flowchart of the wafer process in Step <b>4</b> in FIG. 8. Step <b>11</b> (oxidation) oxidizes the wafer's surface. Step <b>12</b> (CVD) forms an insulating film on the wafer's surface. Step <b>13</b> (electrode formation) forms electrodes on the wafer by vapor disposition and the like. Step <b>14</b> (ion implantation) implants ion into the wafer. Step <b>15</b> (resist process) applies a photosensitive material onto the wafer. Step <b>16</b> (exposure) uses the exposure apparatus <b>300</b> to expose a circuit pattern on the mask onto the wafer. Step <b>17</b> (development) develops the exposed wafer. Step <b>18</b> (etching) etches parts other than a developed resist image. Step <b>19</b> (resist stripping) removes disused resist after etching. These steps are repeated, and multi-layer circuit patterns are formed on the wafer. Use of the fabrication method in this embodiment helps fabricate higher-quality devices than ever. Thus, the device fabrication method using the exposure apparatus <b>1</b> and the resultant device constitute one aspect of the present invention.

[0058] Further, the present invention is not limited to these preferred embodiments and various variations and modifications may be made without departing from the scope of the present invention.

[0059] According to the inventive exposure method and apparatus, may perform a superior focus correction for the flatness of the wafer surface without lowering the throughput. The device fabrication method using this device and method may fabricate high-quality devices.