Radio receiver for receiving both vsb and qam digital hdtv signals

[0001] The invention relates to radio receivers having the capability of receiving digital high-definition television (HDTV) signals, no matter whether they are transmitted using quadrature amplitude modulation (QAM) of the principal carrier wave or they are transmitted using vestigial sideband (VSB) amplitude modulation of the principal carrier wave.

BACKGROUND OF THE INVENTION

[0002] Vestigial sideband (VSB) signals that are used in certain transmissions of HDTV signal have their natural carrier wave, which would vary in amplitude depending on the percentage of modulation, replaced by a pilot carrier wave of fixed amplitude, which amplitude corresponds to a prescribed percentage of modulation. This percentage modulation can be made the same as that associated with the smallest change in symbol code level. Such VSB signals using <b>8</b>-level symbol coding will be used in over-the-air broadcasting within the United States, for example, and can be used in over-the-air narrowcasting systems or in cable-casting systems. However, certain cable-casting is likely to be done using suppressed-carrier quadrature amplitude modulation (QAM) signals instead, rather than VSB signals. This presents television receiver designers with the challenge of designing receivers that are capable of receiving either type of transmission and of automatically selecting suitable receiving apparatus for the type of transmission currently being received.

[0003] A television receiver designer of ordinary skill in the art will readily observe that processing after symbol decoding is similar in receivers for the VSB HDTV signals and in receivers for the QAM HDTV signals, since the data format supplied for symbol encoding is the same in transmitters for the VSB HDTV signals and in transmitters for the QAM HDTV signals. The data recovered by symbol decoding are supplied as input signal to a data de-interleaver, and the de-interleaved data are supplied to a Reed-Solomon decoder. Error-corrected data are supplied to a data de-randomizer which regenerates packets of data for a packet decoder. Selected packets are used to reproduce the audio portions of the HDTV program, and other selected packets are used to reproduce the video portions of the HDTV program. A television receiver designer of ordinary skill in the art will readily observe also that the tuners are quite similar in receivers for the VSB HDTV signals and in receivers for the QAM HDTV signals. The differences in the receivers reside in the synchrodyning procedures used to translate the final IF signal to baseband and in the symbol decoding procedures. A television receiver designer of ordinary skill in the art will readily deduce that a receiver that is capable of receiving either VSB or QAM HDTV signals is more economical in design if it does not duplicate the similar tuner circuitry prior to synchrodyning to baseband and the similar receiver elements used after the symbol decoding circuitry. The challenge is in optimally constructing the circuitry for synchrodyning to baseband and for symbol decoding to accommodate both HDTV transmission standards and in arranging for the automatic selection of the appropriate mode of reception for the HDTV transmission currently being received.

[0004] Digital HDTV signal radio receivers are known of a type that uses double-conversion in the tuner followed by synchronous detection. A frequency synthesizer generates first local oscillations that are heterodyned with the received television signals to generate first intermediate frequencies (e. g., with 920 MHz carrier). A passive LC bandpass filter selects these first intermediate frequencies from their image frequencies for amplification by a first intermediate-frequency amplifier, and the amplified first intermediate frequencies are filtered by a first surface-acoustic-wave (SAW) filter that rejects adjacent channel responses. The first intermediate frequencies are heterodyned with second local oscillations to generate second intermediate frequencies (e. g., with 41 MHz carrier), and a second SAW filter selects these second intermediate frequencies from their images and from remnant adjacent channel responses for amplification by a second intermediate-frequency amplifier. The response of the second intermediate-frequency amplifier is supplied to a third mixer to be synchrodyned to baseband with third local oscillations of fixed frequency. The third local oscillations of fixed frequency can be supplied in 0°- and 90°-phasing, thereby implementing separate in-phase and quadrature-phase synchronous detection procedures during synchrodyning. Synchrodyning is the procedure of multiplicatively mixing a modulated signal with a wave having a fundamental frequency the same as the carrier of the modulated signal, being locked in frequency and phase thereto, and lowpass filtering the result of the multiplicative mixing to recover the modulating signal at baseband, baseband extending from zero frequency to the highest frequency in the modulating signal. Separately digitizing in-phase and quadrature-phase synchronous detection results generated in the analog regime presents problems with regard to the synchronous detection results satisfactorily tracking each other after digitizing; quantization noise introduces pronounced phase errors in the complex signal considered as a phasor. These problems can be avoided in HDTV signal radio receivers of types performing the in-phase and quadrature-phase synchronous detection procedures in the digital regime. By way of example, the response of the second intermediate-frequency amplifier is digitized at twice the Nyquist rate of the symbol coding. The successive samples are considered to be consecutively numbered in order of their occurrence; and odd samples and even samples are separated from each other to generate respective ones of the in-phase (or real) and quadrature-phase (or imaginary) synchronous detection results. Quadrature-phase (or imaginary) synchronous detection takes place after Hilbert transformation of one set of samples using appropriate finite-impulse-response (FIR) digital filtering, and in-phase (or real) synchronous detection of the other set of samples is done after delaying them for a time equal to the latency time of the Hilbert-transformation filter. The methods of locking the frequency and phase of synchronous detection and the methods of locking the frequency and phase of symbol decoding differ in the VSB and QAM HDTV receivers.

[0005] The inventors point out that these types of known digital HDTV signal radio receiver present some problem in the design of the tuner portion of the receiver because the respective carrier frequencies of VSB HDTV signals and of QAM HDTV signals are not the same as each other. The carrier frequency of a QAM HDTV signal is at mid-channel of the transmission frequencies. The carrier frequency of a VSB HDTV signal is 2.375 MHz below mid-channel frequency. Accordingly, the third local oscillations of fixed frequency, which are used for synchrodyning to baseband, must be of different frequency when synchrodyning VSB HDTV signals to baseband than when synchrodyning QAM HDTV signals to baseband. The 2.375 MHz difference in frequency is larger than that which is readily accommodated by applying automatic frequency and phase control to the third local oscillator. A third oscillator that can switchably select between two frequency-stabilizing crystals is a practical necessity. In such an arrangement, of course, alterations in the tuner circuitry are involved with arranging for the automatic selection of the appropriate mode of reception for the HDTV transmission currently being received. The radio-frequency switching that must be done reduces the reliability of the tuner. The RF switching and the additional frequency-stabilizing crystal for the third oscillator increase the cost of the tuner appreciably.

[0006] Radio receivers for receiving VSB HDTV signals, in which receiver the third mixer output signal is a final intermediate-frequency signal somewhere in the 1-8 MHz frequency range rather than at baseband, are described by the inventors in the U. S. patent applications listed below, incorporated by reference herein, and commonly assigned herewith:

[0007] Ser. No. 08/237,896 filed May 4, 1994 and entitled DIGITAL VSB DETECTOR WITH BANDPASS PHASE TRACKER, AS FOR INCLUSION IN AN HDTV RECEIVER;

[0008] Ser. No. 08/243,480 filed May 19, 1994 and entitled DIGITAL VSB DETECTOR WITH BANDPASS PHASE TRACKER USING RADER FILTERS, AS FOR USE IN AN HDTV RECEIVER; and

[0009] Ser. No. 08/247,753 filed May 23, 1994 and entitled DIGITAL VSB DETECTOR WITH FINAL I-F CARRIER AT SUBMULTIPLE OF SYMBOL RATE, AS FOR HDTV RECEIVER.

[0010] The final IF signal is digitized and the synchrodyne procedures are carried out in the digital regime. Radio receivers that receive QAM signals, convert them to a final IF signal just above baseband, and synchrodyne the final IF signal in the digital regime are known; and such receivers can be adapted for receiving HDTV signals, it is believed to be evident at this time to a television receiver designer of ordinary skill in the art. In radio receivers that are to have the capability of receiving digital HDTV signals no matter whether they are transmitted using VSB or QAM, the inventors point out, conversion of the signals to final IF signals just above baseband permits the frequency of the oscillations of the third local oscillator to remain the same no matter whether VSB or QAM transmissions are being received. The differences in carrier frequency location within the channel can be accommodated in the synchrodyning procedures carried out in the digital regime.

SUMMARY OF THE INVENTION

[0011] The invention is embodied in a radio receiver for receiving a selected one of digital HDTV signals each including symbol codes descriptive of digital signals, irrespective of whether said selected HDTV signal is a quadrature-amplitude-modulation (QAM) signal or is a vestigial sideband (VSB) signal including a pilot carrier having an amplitude related to signal levels in said symbol codes thereof. A tuner within the receiver includes elements for selecting one of channels at different locations in a frequency band used for transmitting HDTV signals, a succession of mixers for performing a plural conversion of signal received in the selected channel to a final intermediate-frequency (IF) signal, a respective frequency-selective amplifier between each earlier one of the mixers in that succession and each next one of said mixers in that succession, and a respective local oscillator for supplying oscillations to each of the mixers. Each of these local oscillators supplies respective oscillations of substantially the same frequency irrespective of whether the selected HDTV signal is a QAM signal or is a VSB signal. The final IF signal is digitized, and the differences in signal processing depending on whether the selected HDTV signal is a QAM signal or is a VSB signal are accommodated principally in digital circuitry including QAM synchrodyning circuitry and VSB synchrodyning circuitry. The QAM synchrodyning circuitry generates real and imaginary sample streams of interleaved QAM symbol code, by synchrodyning the digitized final IF signal to baseband providing it is a QAM signal and otherwise processing the digitized final IF signal as if it were a QAM signal to be synchrodyned to baseband. The VSB synchrodyning circuitry generates a real sample stream of interleaved VSB symbol code, by synchrodyning the digitized final IF signal to baseband providing it is a VSB signal and otherwise processing the digitized final IF signal as if it were a VSB signal to be synchrodyned to baseband.

[0012] In preferred embodiments of the invention, a detector is provided for determining whether the final IF signal is a QAM signal or a VSB signal to generate a control signal, which is in a first condition when the final IF signal is a QAM signal and is in a second condition when the final IF signal is a VSB signal. Responsive to the control signal being in its first condition, the radio receiver is automatically switched to operate in a QAM signal reception mode; and responsive to the control signal being in its second condition, the radio receiver is automatically switched to operate in a VSB signal reception mode. This detector is one which senses the presence of a pilot carrier accompanying a digital HDTV signal of VSB type in certain preferred embodiments of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013]FIG. 1 is a block schematic diagram of initial portions of a digital HDTV signal radio receiver of a type embodying the invention, including circuitry for detecting symbols in an HDTV signal of QAM type, circuitry for detecting symbols in an HDTV signal of VSB type, and an amplitude-and-group-delay equalizer for symbols selected from the circuitry for detecting symbols in an HDTV signal of QAM type and the circuitry for detecting symbols in an HDTV signal of VSB type.

[0014]FIG. 2 is a block schematic diagram of the remaining portions of the digital HDTV signal radio receiver of a type embodying the invention, which are not shown in FIG. 1.

[0015]FIG. 3 is a detailed block schematic diagram of circuitry for providing the sample clock generator, the look-up table read-only memories (ROMs) for supplying digital descriptions of the complex carriers used for synchrodyning digital QAM signals and digital VSB signals at final IF signal frequencies each to baseband, and the address generators for those ROMs, which circuitry is included in certain digital HDTV signal radio receivers of the type embodying the invention.

[0016]FIG. 4 is a table of subharmonics of the 21.52 MHz sampling frequency and of 43.04 MHz, the second harmonic of the 21.52 MHz sampling frequency.

[0017]FIG. 5 is a detailed block schematic diagram of circuitry similar to that of FIG. 3, modified so that the address generator for the ROMs supplying digital descriptions of the complex carrier used for synchrodyning digital QAM signals to baseband and the ROMs supplying digital descriptions of the complex carrier used for synchrodyning digital VSB signals to baseband share an address counter in common.

[0018]FIG. 6 is a detailed block schematic diagram of circuitry for converting digital samples to complex form in digital HDTV signal radio receivers embodying the invention, which circuitry includes a Hilbert transformation filter for generating imaginary samples from real samples, and which includes delay compensation for the real samples equivalent to the latency of that filter.

[0019]FIG. 7 is a detailed block schematic diagram of a pair of all-pass digital filters designed based on Jacobian elliptic functions and exhibiting a constant π/2 difference in phase response for the digitized bandpass signals, as can be employed for converting digital samples to complex form in digital HDTV signal radio receivers embodying the invention.

[0020]FIGS. 8 and 9 are block schematic diagrams of changes that can be made the filter circuitry of FIG. 7 to remove redundant delay.

[0021]FIG. 10 is a detailed block schematic diagram of digital circuitry for synchrodyning QAM HDTV signals to baseband, of digital circuitry for synchrodyning VSB HDTV signals to baseband, and of circuitry associated with applying input signals to that QAM and VSB synchrodyning circuitry, as used in a digital HDTV signal radio receiver of the type shown in FIGS. 1 and 2.

[0022]FIG. 11 is a detailed block schematic diagram of automatic gain control (AGC) circuitry and of a VSB pilot carrier presence detector, as used in a digital HDTV signal radio receiver of the type shown in FIGS. 1 and 2.

[0023]FIG. 12 is a detailed block schematic diagram of the preferred construction of portions of the FIG. 11 AGC circuitry in which digital lowpass filtering and digital-to-analog conversion are performed.

[0024] In the block schematic diagrams, clock or control signal connections are shown in dashed line, where it is desired to distinguish them from connections for the signals being controlled. To avoid overcomplexity in the block schematic diagrams, some shimming delays necessary in the digital circuitry are omitted, where a need for such shimming delay is normally taken into account by a circuit or system designer.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025]FIG. 1 shows a tuner <b>5</b> comprising elements <b>11</b>-<b>21</b> that selects one of channels at different locations in the frequency band for digital HDTV signals and performs plural frequency conversion of the selected channel to a final intermediate-frequency signal in a final intermediate-frequency band. FIG. 1 shows a broadcast receiving antenna <b>6</b> arranged to capture the digital HDTV signals for the tuner <b>5</b>. Alternatively, the tuner <b>5</b> can be connected for receiving digital HDTV signals from a narrowcast receiving antenna or from a cablecast transmission system.

[0026] More particularly, in the tuner <b>5</b> shown in FIG. 1, a channel selector <b>10</b> designed for operation by a human being determines the frequency of first local oscillations that a frequency synthesizer <b>11</b>, which functions as a first local oscillator, furnishes to a first mixer <b>12</b> for heterodyning with digital HDTV signals received from the antenna <b>6</b> or an alternative source of such signals. The first mixer <b>12</b> upconverts the received signals in the selected channel to prescribed first intermediate frequencies (e. g., with 920 MHz carrier), and an LC filter <b>13</b> is used to reject the unwanted image frequencies that accompany the upconversion result supplied from the first mixer <b>12</b>. The first intermediate-frequency signal resulting from the upconversion, supplied as the filter <b>13</b> response, is applied as the input signal to a first intermediate-frequency amplifier <b>14</b>, which supplies amplified first IF signal for driving a first surface-acoustic-wave (SAW) filter <b>15</b>. The upconversion to the rather high-frequency first intermediate frequencies facilitates the SAW filter <b>15</b> having a large number of poles and zeroes. Second local oscillations from a second local oscillator <b>16</b> are supplied to a second mixer <b>17</b> for heterodyning with the response of the first SAW filter <b>15</b>, to generate second intermediate frequencies (e. g., with 41 MHz carrier). A second SAW filter <b>18</b> is used for rejecting the unwanted image frequencies that accompany the downconversion result supplied from the second mixer <b>17</b>. During the period of transition from NTSC television transmissions to digital television transmissions, the second SAW filter <b>18</b> will usually include traps for sound and video carriers of adjacent-channel NTSC television transmissions. The second IF signal supplied as the response of the second SAW filter <b>18</b> is applied as input signal to a second intermediate-frequency amplifier <b>19</b>, which generates an amplified second IF signal response to its input signal. Oscillations from a third local oscillator <b>20</b> are heterodyned with the amplified second IF signal response in a third mixer <b>21</b>. The plural-conversion tuner <b>5</b> as thus far described resembles those previously proposed by others, except that the frequency of the oscillations from the third local oscillator <b>20</b> is chosen such that the third mixer <b>21</b> supplies a third intermediate-frequency signal response.

[0027] This third IF signal response is the final intermediate-frequency output signal of the tuner <b>5</b>, which is supplied to a subsequent analog-to-digital converter (ADC) <b>22</b> for digitization. This final IF signal occupies a frequency band 6 MHz wide, the lowest frequency of which is above zero frequency. The lowpass analog filtering of the third mixer <b>21</b> response done in the ADC <b>22</b> as a preliminary step in analog-to-digital conversion suppresses the image frequencies of the third intermediate frequencies, and the second SAW filter <b>18</b> has already restricted the bandwidth of the third intermediate-frequency signals presented to the ADC <b>22</b> to be digitized; so the ADC <b>22</b> functions as a bandpass analog-to-digital converter. The sampling of the lowpass analog filter response in the ADC <b>22</b> as the next step in analog-to-digital conversion is done responsive to pulses in a first clock signal supplied from a sample clock generator <b>23</b>.

[0028] The sample clock generator <b>23</b> preferably includes a crystal oscillator capable of frequency control over a relatively narrow range for generating cissoidal oscillations at a multiple of symbol rate. A symmetrical clipper or limiter generates a square-wave response to these cissoidal oscillations to generate the first clock signal, which the ADC <b>22</b> uses to time the sampling of the final IF signal after filtering to limit bandwidth. The frequency of the cissoidal generated by the crystal oscillator in the sample clock generator <b>23</b> can be determined by an automatic frequency and phase control (AFPC) signal developed in response to symbol frequency components of the received HDTV signal, for example, as will be described in detail further on in this specification. The pulses in the first clock signal recur at a 21.52 megasamples-per-second rate, twice the 10.76 megasymbols-per-second symbol rate for VSB signals and four times the 5.38 megasymbols-per-second symbol rate for QAM signals. The ADC <b>22</b> supplies real digital responses of 10-bit or so resolution to the samples of the band-limited final IF signal, which digital responses are converted to complex digital samples by the circuitry <b>24</b>. Various ways to construct the circuitry <b>24</b> will be described further on in this specification with reference to FIGS. 6, 7, <b>8</b> and <b>9</b>. If the frequency band 6 MHz wide occupied by the final IF signal has a lowest frequency of at least a megaHertz or so, it is possible to keep the number of taps in a Hilbert transformation filter within the circuitry <b>24</b> reasonably small and thus keep the latency time of the filter reasonably short. Placing the final IF signal so its mid-frequency is above 5.38 MHz reduces the number of 21.52 megasamples-per-second rate samples in the QAM carrier to less than four, which undesirably reduces the uniformity of synchrodyne response supplied for symbol decoding.

[0029] In the FIG. 1 receiver circuitry the complex digital samples of final IF signal supplied from the circuitry <b>24</b> are applied to circuitry <b>25</b> for synchrodyning the QAM signal to baseband to supply in parallel to a symbol de-interleaver <b>26</b> a stream of real samples and a stream of imaginary samples descriptive of the complex-amplitude-modulation modulating signal. The QAM synchrodyning circuitry <b>25</b> receives complex-number digital descriptions of two phasings of the QAM carrier, as translated to final intermediate frequency and in quadrature <b>25</b> relationship with each other, from read-only memory <b>27</b>. ROM <b>27</b>, which comprises sine and cosine look-up tables for QAM carrier frequency, is addressed by a first address generator <b>28</b>. The first address generator <b>28</b> includes an address counter (not explicitly shown in FIG. 1) for counting the recurrent clock pulses in the first clock signal generated by the sample clock generator <b>23</b>. The resulting address count is augmented by a symbol phase correction term generated by symbol phase correction circuitry, thereby to generate the addressing for the ROM <b>27</b>. The QAM synchrodyne circuitry <b>25</b>, the first address generator <b>28</b>, and the operation of each will be explained in greater detail further on in this specification.

[0030] In the FIG. 1 receiver circuitry the complex digital samples of final IF signal supplied from the circuitry <b>24</b> are also applied to circuitry <b>29</b> for synchrodyning the VSB signal to baseband to supply a stream of real samples descriptive of the vestigial-sideband modulating signal to an NTSC-rejection filter <b>30</b>, which functions as a symbol de-interleaver for the VSB signal. The VSB synchrodyning circuitry <b>29</b> receives complex-number digital descriptions of two phasings of the VSB carrier, as translated to final intermediate frequency and in quadrature relationship with each other, from read-only memory <b>31</b>. ROM <b>31</b>, which comprises sine and cosine look-up tables for VSB carrier frequency, is addressed by a second address generator <b>32</b>. The second address generator <b>32</b> includes an address counter (not explicitly shown in FIG. 1) for counting the recurrent clock pulses in the first clock signal generated by the sample clock generator <b>23</b>, which address counter in preferred embodiments of the invention is the same address counter used in the first address generator <b>28</b>. The resulting address count is augmented by a symbol phase correction term generated by QAM de-rotator circuitry, thereby to generate the addressing for the ROM <b>31</b>. The VSB synchrodyne circuitry <b>29</b>, the second address generator <b>32</b>, and the operation of each will be explained in greater detail further on in this specification.

[0031] The baseband response of the VSB synchrodyne circuitry <b>29</b> is supplied to an NTSC-rejection filter <b>30</b> for suppressing co-channel interference from NTSC signals, in which filter <b>30</b> the response is applied as input signal to a clocked delay line <b>301</b> and as a first summand input signal to a two-input digital adder <b>302</b>. The clocked delay line <b>301</b> supplies a response to its input signal after a delay equal to twelve symbol epochs, which delayed response is applied to the digital adder <b>302</b> as its second summand input signal. The clocked delay line <b>301</b> and the digital adder <b>302</b> in the NTSC-rejection filter <b>30</b> cooperate so as to suppress co-channel interference from NTSC signals. The NTSC-rejection filter <b>30</b>, which is a comb filter, is required as long as NTSC signals are being transmitted over the same channel allocations as digital HDTV signals. The filter <b>30</b> suppresses the NTSC luminance carrier and its lower-frequency sidebands containing synchronizing information, very strongly rejects the color subcarrier, suppresses the chrominance sidebands, and suppresses the FM audio carrier. The filter <b>30</b> supplies a fifteen-coding-level signal in response to the eight-coding-level signal it receives from the VSB synchrodyne circuitry <b>29</b>.

[0032] A digital-signal multiplexer <b>33</b> functions as a synchrodyne result selector that selects as its response either a first or a second one of two complex digital input signals thereto, the selection being controlled by a detector <b>34</b> for detecting the zero-frequency term of the real samples from the VSB synchrodyne circuitry <b>29</b>. When the zero-frequency term has essentially zero energy, indicating the absence of pilot carrier signal that accompanies a VSB signal, the multiplexer <b>33</b> selectively responds to its first complex digital input signal, which is the de-interleaved QAM synchrodyne-to-baseband result supplied from the de-interleaver <b>26</b>. When the zero-frequency term has substantial energy, indicating the presence of pilot carrier signal that accompanies a VSB signal, the multiplexer <b>33</b> selectively responds to its second complex digital input signal, the real terms of which are supplied from the NTSC-rejection filter <b>30</b> and the imaginary terms of which are all wired arithmetic zero.

[0033] The response of the synchrodyne result selection multiplexer <b>33</b> is resampled in response to a second clock signal from the sample clock generator <b>23</b> in 2:1 decimation circuitry <b>35</b>, to reduce the sample rate of complex baseband response down to the 10.76 MHz VSB symbol rate, which is twice the 5.38 MHz QAM symbol rate. The 2:1 decimation of the multiplexer <b>33</b> response prior to its application as input signal to an amplitude-and-group-delay equalizer <b>36</b> reduces the hardware requirements on the equalizer. Alternatively, rather than 2:1 decimation circuitry <b>35</b> being used after the synchrodyne result selection multiplexer <b>33</b>, the baseband responses of the QAM synchrodyne circuitry <b>25</b> and of the VSB synchrodyne circuitry <b>29</b> can each be resampled in response to a second clock signal from the sample clock generator <b>23</b> to carry out 2:1 decimation before the synchrodyne result selection multiplexer <b>33</b>.

[0034]FIG. 2 shows the amplitude-and-group-delay equalizer <b>36</b>, which converts a baseband response with an amplitude-versus-frequency characteristic that tends to cause inter-symbol error to a more optimum amplitude-versus-frequency characteristic that has linear phase delay and minimizes the likelihood of inter-symbol error. The equalizer <b>36</b> can be a suitable one of the monolithic ICs available off-the-shelf for use in equalizers. Such an IC includes a multiple-tap digital filter used for amplitude equalization, the tap weights of which filter are programmable; circuitry for selectively accumulating training signal and temporarily storing the accumulation results; and a microcomputer for comparing the temporarily stored accumulation results with an ideal training signal as known a priori and for calculating updated tap weights of the multiple-tap digital filter used for amplitude equalization. These calculations also use decision feedback based on the received data and the least-mean-squares (LMS) algorithm to reduce intersymbol errors.

[0035] The response of the equalizer <b>36</b> is applied as input signal to a two-dimensional trellis decoder <b>37</b>, which performs the symbol decoding that recovers a digital data stream from a QAM-origin signal. The response of the equalizer <b>36</b> is also applied as input signal to a one-dimensional trellis decoder <b>38</b>, which performs the symbol decoding that recovers a digital data stream from a VSB-origin signal. A digital-signal multiplexer <b>39</b> functions as a data source selector that selects as its response either a first or a second one of two digital input signals thereto, the selection being controlled by the detector <b>34</b> for detecting the zero-frequency term of the real samples from the VSB synchrodyne circuitry <b>29</b>. When the zero-frequency term has essentially zero energy, indicating the absence of pilot carrier signal that accompanies a VSB signal, the multiplexer <b>39</b> selectively responds to its first digital input signal, selecting as the source of its digital data output the two-dimensional trellis decoder <b>37</b> that decodes the symbols received in the QAM signal. When the zero-frequency term has substantial energy, indicating the presence of pilot carrier signal that accompanies a VSB signal, the multiplexer <b>39</b> selectively responds to its second digital input signal, selecting as the source of its digital data output the one-dimensional trellis decoder <b>38</b> that decodes the symbols received in the VSB signal.

[0036] The data selected by the data source selection multiplexer <b>39</b> are applied to a data de-interleaver <b>40</b> as its input signal, and the de-interleaved data supplied from the data de-interleaver <b>40</b> are applied to a Reed-Solomon decoder <b>41</b>. The data de-interleaver <b>40</b> is often constructed within its own monolithic IC and is made so as to respond to the output indications from the pilot carrier presence detector <b>34</b> to select the de-interleaving algorithm suitable to the HDTV signal currently being received, whether it be of QAM or VSB type; this is a mere matter of design. The Reed-Solomon decoder <b>41</b> is often constructed within its own monolithic IC and is made so as to respond to the output indications from the pilot carrier presence detector <b>34</b> to select the appropriate Reed-Solomon decoding algorithm for the HDTV signal currently being received, whether it be of QAM or VSB type; this also is a mere matter of design. Error-corrected data are supplied from the Reed-Solomon decoder <b>41</b> to a data de-randomizer <b>42</b>, which regenerates packets of data for a packet sorter <b>43</b>. The data de-randomizer <b>42</b> is made so as to respond to the output indications from the pilot carrier presence detector <b>34</b> to select the appropriate data de-randomizing algorithm for the HDTV signal currently being received, whether it be of QAM or VSB type; this is a mere matter of design, too.

[0037] First data synchronization recovery circuitry <b>44</b> recovers the data synchronizing information included in the data output of the two-dimensional trellis decoder <b>37</b>, and second data synchronization recovery circuitry <b>45</b> recovers the data synchronizing information included in the data output of the one-dimensional trellis decoder <b>38</b>. A data sync selector <b>46</b> selects between the data synchronizing information as provided by the data sync recovery circuitry <b>44</b> and as provided by the data sync recovery circuitry <b>45</b>, the selection being controlled by the detector <b>34</b> for detecting the zero-frequency term of the real samples from the VSB synchrodyne circuitry <b>29</b>. When the zero-frequency term has essentially zero energy, indicating the absence of pilot carrier signal that accompanies a VSB signal, the data sync selector <b>46</b> selects for its output signals the data synchronizing information provided by the data sync recovery circuitry <b>44</b>. When the zero-frequency term has substantial energy, indicating the presence of pilot carrier signal that accompanies a VSB signal, the data sync selector <b>46</b> selects for its output signals the data synchronizing information provided by the data sync recovery circuitry <b>45</b>.

[0038] A VSB HDTV signal comprises a succession of consecutive-in-time data fields each containing 314 consecutive-in-time data lines. Each line of data starts with a line synchronization code group of four symbols having successive values of +S, −S, −S and +S. The value +S is one level below the maximum positive data excursion, and the value −S is one level above the maximum negative data excursion. The lines of data are each of 77.7 microsecond duration, and there are 832 symbols per data line for a symbol rate of about 10 megabits/second. The initial line of each data field is a field synchronization code group that codes a training signal for channel-equalization and multipath suppression procedures. The training signal is a 511-sample pseudo-random sequence (or “PR-sequence”) followed by three 63-sample PR sequences. This training signal is transmitted in accordance with a first logic convention in the first line of each odd-numbered data field and in accordance with a second logic convention in the first line of each even-numbered data field, the first and second logic conventions being one's complementary respective to each other. When the data sync selector <b>46</b> selects for its output signals the data synchronizing information provided by the data sync recovery circuitry <b>45</b>, the initial data lines of each data field are selected for application to the equalizer <b>36</b> as training signal. The occurrences of two consecutive 255-sample PR sequences are detected within the data sync recovery circuitry <b>45</b> to provide data-field indexing information to the data sync selector <b>46</b>.

[0039] The standards for a QAM HDTV signal are not as well defined at this time as the standards for a VSB HDTV signal. A 32-state QAM signal provides sufficient capacity for a single HDTV signal, without having to resort to compression techniques outside MPEG standards, but commonly some compression techniques outside MPEG standards are employed to encode the single HDTV signal as a 16-state QAM signal. The occurrence of a prescribed 24-bit word is detected the data sync recovery circuitry <b>44</b> to generate data-field indexing information for application to the data sync selector <b>46</b>. A multiplexer within the data sync selector <b>46</b> selects between the data-field indexing information respectively supplied by the data sync recovery circuitry <b>44</b> and the data sync recovery circuitry <b>45</b>; the data-field indexing information thus selected is supplied to the data de-interleaver <b>40</b>, the Reed-Solomon decoder <b>41</b>, and the data de-randomizer <b>42</b>. At the time this specification is written there is no training signal included in the QAM HDTV signal. Accordingly, the amplitude-and-group-delay equalizer <b>36</b> is arranged to provide a flat amplitude-versus-frequency characteristic in response to the VSB pilot carrier presence detector <b>34</b> indicating the absence of pilot carrier, and the VSB training signal selected by the data sync recovery circuitry <b>45</b> is wired through the data sync selector <b>46</b> without need for a multiplexer. Also, there is no data line synchronization signal for QAM HDTV transmission, at least not one selected as a standard. The data sync recovery circuitry <b>44</b> includes counting circuitry for counting the samples in each data field to generate intra-data-field synchronizing information. This intra-data-field synchronizing information and the intra-data-field synchronizing information (such as data line count) generated by the data sync recovery circuitry <b>45</b> are selected between by appropriate multiplexers in the data sync selector <b>46</b>, for application to the data de-interleaver <b>40</b>, the Reed-Solomon decoder <b>41</b>, and the data de-randomizer <b>42</b>, as required.

[0040] The packet sorter <b>43</b> sorts packets of data for different applications, responsive to header codes in the successive packets of data. Packets of data descriptive of the audio portions of the HDTV program are applied by the packet sorter <b>43</b> to a digital sound decoder <b>47</b>. The digital sound decoder <b>47</b> supplies left-channel and right-channel stereophonic sound signals to a plural-channel audio amplifier <b>48</b> that drives the plurality of loudspeakers <b>49</b>, <b>50</b>. Packets of data descriptive of the video portions of the HDTV program are applied by the packet sorter <b>43</b> to an MPEG decoder <b>51</b>. The MPEG decoder <b>51</b> supplies horizontal (He and vertical (V) synchronizing signals to kinescope deflection circuitry <b>52</b> that provides for the raster scanning of the viewing screen of a kinescope <b>53</b>. The MPEG decoder <b>51</b> also supplies signals to the kinescope driver amplifiers <b>54</b> for applying amplified red (R), green (G) and blue (B) drive signals to the kinescope <b>53</b>. In variations of the HDTV receiver shown in FIGS. 1 and 2, a different display device may be used instead of or in addition to the kinescope <b>53</b>, and the sound recovery system may be different, consisting of but a single audio channel, or being more elaborate than a simple stereophonic reproduction system.

[0041] Referring back to FIG. 1, in order that ROMs <b>27</b> and <b>31</b> can be used to generate digital complex-number descriptions of the QAM and VSB signal carriers as translated to respective final intermediate frequencies, in response to addressing generated by counting first clock signals, provision must be made to lock the one those final intermediate frequencies that is the carrier of the currently received HDTV signal to a submultiple of a multiple of the first clock signal frequency. That is, those final intermediate frequencies must be in whole number ratios with the first clock signal frequency. An automatic phase and frequency control (AFPC) signal is developed in the digital circuitry following the analog-to-digital converter <b>22</b> and is used to control the frequency and phase of one of the local oscillators <b>11</b>, <b>16</b> and <b>20</b> in the tuner. Using a fixed-frequency third local oscillator <b>20</b>, and controlling the frequency and phase of the oscillations the second local oscillator <b>16</b> provides, is preferred in that alignment of the second IF signal with the second SAW filter <b>18</b> can be readily assured. The second SAW filter <b>18</b> usually contains traps for adjacent-channel signal components, in which case proper alignment of the second IF signal between these traps is important for preserving its integrity. The symbol clocking is made to exhibit a high degree of frequency stability. By locking the carrier of the final intermediate-frequency (IF) signal in frequency and phase to a submultiple of a multiple of the symbol clock frequency, the AFPC for correcting frequency and phase error in the carrier as translated to a final intermediate frequency invariably operates to correct dynamic symbol phase error as well, eliminating the need for a separate phase tracker to correct dynamic symbol phase error.

[0042]FIG. 1 denominates a digital multiplexer <b>55</b> as “AFPC selector”. The multiplexer <b>55</b> responds to the pilot carrier presence detector <b>34</b> indicating that a pilot carrier is included in the currently received HDTV signal for selecting, as an input signal for a digital lowpass filter <b>56</b>, the imaginary output signal of the baseband response of the VSB synchrodyne circuitry <b>29</b>. The response of lowpass filter <b>56</b> is a digital AFPC signal supplied as input signal to a digital-to-analog converter (DAC) <b>57</b>. The output signal from the DAC <b>57</b> is an analog AFPC signal, which is subjected to further lowpass filtering in an analog lowpass filter <b>58</b>, the response of which filter <b>58</b> is used for controlling the frequency and phase of the oscillations that the second local oscillator <b>16</b> provides. Analog lowpass filtering is advantageous to use for realizing long-time-constant lowpass filtering because there is reduced need for active devices as compared to digital lowpass filtering. Since the shunt capacitor of a resistance-capacitance lowpass filter section can be at the interface between a tuner <b>5</b> IC and the IC containing the digital synchrodyning circuitry, the analog lowpass filtering can be done without any cost in IC pin-out. Doing some digital lowpass filtering is advantageous, however, since the digital lowpass filter response can be subsampled to the DAC <b>57</b>; the reduced speed requirements on the digital-to-analog conversion reduces the cost of the DAC <b>57</b>. This procedure is similar to that used in the AGC circuitry described at the end of this specification with reference to FIG. 12 of the drawing, and the third clock signal developed for the AGC circuitry can be used by the DAC <b>57</b> and can be used to reset an accumulator the digital lowpass filter <b>56</b> includes for averaging samples of filter input signal.

[0043] The multiplexer <b>55</b> responds to the pilot carrier presence detector <b>34</b> indicating that a pilot carrier is not included in the currently received HDTV signal for selecting the input signal for the digital lowpass filter <b>56</b> from the circuitry for processing a QAM HDTV signal. FIG. 1 shows the product output signal of a digital multiplier <b>59</b> being provided for such selection. The digital multiplier <b>59</b> multiplies together the real and imaginary output signals of the QAM synchrodyne circuitry <b>25</b> to generate an unfiltered digital AFPC signal. The generation of the unfiltered digital AFPC signal is very similar to that in the well-known Costas loop. In the Costas loop the AFPC signal is used to control the frequency and phase of the digital local oscillations used for synchrodyning received signals to baseband. The FIG. 1 arrangement departs from this procedure, the AFPC signal being used instead to control the frequency and phase of the analog oscillations generated by the second local oscillator <b>16</b>. This regulates the frequency and phase of the final IF signal supplied to the ADC <b>22</b> for digitization and for subsequent synchrodyning to baseband in the digital regime. As is the case with the Costas loop, the multiplier <b>59</b> is preferably of especial design in which the real signal is converted to a ternary signal for multiplying the imaginary signal; this simplifies the digital multiplier and improves the pull-in characteristics of the AFPC loop.

[0044] Although not explicitly shown in FIGS. 1 and 2, preferably circuitry is provided to sense when there is co-channel interference from NTSC signal, to by-pass the filter <b>30</b> when no co-channel interference from NTSC signal is sensed, and to adjust symbol decoding ranges in the one-dimensional trellis decoder <b>38</b> in accordance with the number of coding levels to be expected. There is less likelihood of the occurrence of erroneous decisions as to symbol identity when eight coding levels have to be discerned than when fifteen coding levels have to be discerned.

[0045] The second intermediate-frequency amplifier <b>19</b>, the third local oscillator <b>20</b> (except for its outboard crystal and other frequency selection components), and the third mixer <b>21</b> are advantageously constructed within the confines of a monolithic IC; since the output signal of the third mixer <b>21</b> is at a different frequency than the input signal to the second IF amplifier <b>19</b>, the second IF amplifier <b>19</b> can have high gain without attendant high risk of unwanted regeneration. The first IF amplifier <b>14</b>, the second local oscillator <b>16</b> (except for its outboard crystal and other frequency selection components) and the second mixer <b>17</b> can be constructed within the confines of the same IC, or they may be constructed otherwise—e.g., within other integrated circuitry. The analog-to-digital converter (ADC), as customary, will be a flash type with at least ten bits resolution and is preferably constructed within the confines of a different monolithic IC than the IF amplifiers. The analog lowpass filter at the input of the converter isolates the sampling circuitry, with its associated switching transients, from the IC in which the high-gain second IF amplifier <b>19</b> is located (and in some cases, in which the first IF amplifier <b>14</b> is also located). This reduces the likelihood of unwanted regeneration in the tuner <b>5</b>. Considerable die area is required for the resistance ladder used in establishing the quantizing levels and for the large number of analog comparators involved in an ADC of flash type, so often such an ADC does not share a monolithic IC with other elements anyway.

[0046] The sample clock generator <b>23</b> and the circuitry <b>24</b> for converting the digitized final IF signal supplied from the ADC <b>22</b> to complex digital samples of final IF signal are advantageously shared by the circuitry for synchrodyning VSB HDTV signals to baseband and by the circuitry for synchrodyning QAM HDTV signals to baseband, as are portions of the address generators <b>28</b> and <b>32</b> in preferred embodiments of the invention, the inventors point out. Accordingly, the circuitry for synchrodyning VSB HDTV signals to baseband and the circuitry for synchrodyning QAM HDTV signals to baseband are advantageously constructed within the confines of a single monolithic. The inventors further point out that it is advantageous that this single monolithic IC and the following circuitry include all the circuitry for automatically selecting the appropriate mode of reception for the HDTV transmission currently being received. Such practice avoids the need for operating the third local oscillator at two markedly different frequencies, depending on whether an HDTV signal is of QAM type or is of VSB type. Operation of the third local oscillator at two markedly different frequencies is normally associated with the use of two different crystals for setting those frequencies. Operating the third local oscillator at essentially the same frequency, no matter whether the HDTV signal is of QAM type or is of VSB type, saves the cost of the extra crystal and of the electronic switching circuitry involved with the use of two crystals. Furthermore, the reliability of the tuner <b>5</b> is improved by the reduction in the amount of circuitry located outside the monolithic integrated circuitry.

[0047] If the ADC is not constructed within an IC, all or substantially all its own, it is advantageous to include it in the IC that contains the circuitry for synchrodyning VSB HDTV signals and the circuitry for synchrodyning QAM HDTV signals to baseband, since the signals for clocking the sampling of the final IF signal by the ADC are to be generated within that IC. Furthermore, the analog lowpass filter at the input of the converter still isolates the sampling circuitry, with its associated switching transients, from the IC(s) in which high-gain IF amplification is done.

[0048]FIG. 3 shows in detail a representative construction of the sample clock generator <b>23</b>. This construction includes a voltage-controlled oscillator <b>230</b> that generates cissoidal oscillations nominally of 21.52 MHz frequency. The oscillator <b>230</b> is a voltage controlled oscillator, the frequency and phase of its oscillations being controlled by an automatic frequency and phase control (AFPC) signal. This AFPC signal is generated by an automatic frequency and phase control (AFPC) detector <b>231</b>, which compares the oscillations of the oscillator <b>230</b> with a 21.52 MHz reference carrier supplied from a digital-to-analog converter (DAC) <b>232</b>. Preferably, oscillator <b>230</b> is of a type using a crystal for stabilizing the natural frequency and phase of its oscillations. A symmetrical clipper or limiter <b>233</b> generates a squarewave response to these cissoidal oscillations, which is used as the first clock signal for timing the sampling of the final IF signal in the ADC <b>22</b>. A frequency-divider flip-flop <b>234</b> responds to transitions of the first clock signal in a prescribed sense for generating another square wave which an AND circuit <b>235</b> ANDs with the first clock signal for generating a second clock signal used by the 2:1 decimator <b>35</b> shown in FIG. 1.

[0049] The 21.52 MHz reference carrier supplied from the digital-to-analog converter <b>232</b> is generated by detecting the strong symbol frequency component of the received HDTV signal, as synchrodyned to baseband, and multiplying the symbol frequency up by an appropriate factor through squaring a suitable number of times. These procedures will now be described, first presuming the received HDTV signal is a VSB signal with a 10.76 MHz symbol frequency that must be squared once to generate the 21.52 MHz reference carrier, and then presuming the received HDTV signal is a QAM signal with a 5.38 MHz symbol frequency that must be squared twice to generate the 21.52 MHz reference carrier.

[0050] A digital multiplexer <b>236</b> responds to the pilot carrier presence detector <b>34</b> detecting pilot carrier accompanying the received HDTV signal, which is indicative that the received HDTV signal is a VSB signal, to select the real samples of this signal supplied from a VSB in-phase synchronous detector <b>290</b> for application to a bandpass FIR digital filter <b>237</b> that provides a selective response centered at 10.76 MHz, which selects the 10.76 MHz symbol frequency of the VSB signal. The filter <b>237</b> response is squared by a digital multiplier <b>238</b>, which multiplier <b>238</b> can either be constructed from logic gates or provided by a ROM storing a look-up table of squares. The product output signal from the digital multiplier <b>238</b> operated to square samples has a strong component at the second harmonic of the 10.76 MHz component of the filter <b>237</b> response, and a bandpass FIR digital filter <b>239</b> that provides a selective response centered at 21.52 MHz selects this second harmonic for application to the DAC <b>232</b> as its digital input signal descriptive of its 21.52 MHz reference carrier analog output signal.

[0051] The digital multiplexer <b>236</b> responds to the pilot carrier presence detector <b>34</b> not detecting pilot carrier accompanying the received HDTV signal, which is indicative that the received HDTV signal is a QAM signal, to select the product output signal of a digital multiplier <b>23</b>A for application to the bandpass filter <b>237</b> that provides a selective response centered at 10.76 MHz. The digital multiplier <b>23</b>A, which multiplier <b>23</b>A can either be constructed from logic gates or provided by a ROM storing a look-up table of squares, squares the samples supplied from a bandpass FIR digital filter <b>23</b>B that provides a selective response centered at 5.38 MHz, which selects the 5.38 MHz symbol frequency of a baseband QAM signal. This baseband QAM signal can be supplied either from a QAM in-phase synchronous detector <b>250</b>, as shown in FIG. 3, or from a QAM quadrature-phase synchronous detector <b>255</b>, as shown in FIG. 5.

[0052]FIG. 3 also shows in more detail a representative construction of the first address generator <b>28</b>, which supplies addresses to a cosine look-up table portion <b>271</b> and a sine look-up table portion <b>272</b> of the ROM <b>27</b> that provides complex-number digital descriptions of two phasings of the QAM carrier, as translated to a final intermediate frequency and in quadrature relationship with each other. Transitions of the first clock signal are counted by a first address counter <b>281</b> in the first address generator <b>28</b> to generate a basic first address signal. This basic first address signal is applied as a first summand to a digital adder <b>282</b>. A first address correction signal, which is applied to the adder <b>282</b> as a second summand, adds to the basic first address signal in the adder <b>282</b> for generating as a sum output signal a corrected first address signal for addressing both the cosine look-up table portion <b>271</b> and the sine look-up table portion <b>272</b> of the ROM <b>27</b>. A symbol-clock-rotation detector <b>283</b> responds to the sequence of real samples of QAM signal as synchrodyned to baseband by the QAM in-phase synchronous detector <b>250</b> and to the sequence of imaginary samples of QAM signal as synchrodyned to baseband by the QAM quadrature-phase synchronous detector <b>255</b>. The symbol-clock-rotation detector <b>283</b> detects the misphasing between symbol clocking done at the receiver in accordance with the first clock signal and symbol clocking done at the transmitter, as evidenced in the received QAM signal heterodyned to a final intermediate frequency that is a submultiple of its symbol frequency. Several types of symbol-clock-rotation detector <b>283</b> are described and background literature describing certain of them are catalogued in U.S. Pat. No. 5,115,454 issued May 19, 1992 to A. D. Kucar, entitled METHOD AND APPARATUS FOR CARRIER SYNCHRONIZATION AND DATA DETECTION, and incorporated herein by reference. A digital lowpass filter <b>284</b> averages over many samples (e. g., several million) the misphasing of the symbol clocking done at the receiver as detected by the symbol-clock-rotation detector <b>283</b> to generate the first address correction signal supplied to the adder <b>282</b> to correct the basic first address. Averaging over so many samples can be done by procedures which accumulate lesser numbers of samples and dump them forward at a reduced sample rate for further accumulation, accumulation and subsampling being repeated a few times with progressively lower subsampling rates.

[0053]FIG. 3 also shows in more detail a representative construction of the second address generator <b>32</b>, which supplies addresses to a cosine look-up table portion <b>311</b> and a sine look-up table portion <b>312</b> of the ROM <b>31</b> that provides complex-number digital descriptions of two phasings of the VSB carrier, as translated to a final intermediate frequency and in quadrature relationship with each other. Transitions of the first clock signal are counted by a second address counter <b>321</b> in the second address generator <b>32</b> to generate a basic second address signal. This basic second address signal is applied as a first summand to a digital adder <b>322</b>. A second address correction signal, which is applied to the adder <b>322</b> as a second summand, adds to the basic second address signal in the adder <b>322</b> for generating as a sum output signal a corrected second address signal for addressing both the cosine look-up table portion <b>311</b> and the sine look-up table portion <b>312</b> of the ROM <b>31</b>.

[0054]FIG. 3 shows a clocked digital delay line <b>323</b> for delaying the samples from the in-phase synchronous detector <b>290</b> by a prescribed number of sample periods prior to their being applied as input signal to a quantizer <b>324</b>, which supplies the quantization level most closely approximated by the sample currently received by the quantizer <b>324</b> as input signal. The quantization levels can be inferred from the energy of the pilot carrier accompanying the VSB signal or can be inferred from the result of envelope detection of the VSB signal. The closest quantization level selected by the quantizer <b>324</b> as its output signal has the corresponding quantizer <b>324</b> input signal subtracted therefrom by a digital adder/subtractor <b>325</b>, which is operated as a clocked element by including a clocked latch at its output. The difference output signal from the adder/subtractor <b>325</b> describes the departure of the symbol levels actually recovered from those that should be recovered, but whether the polarity of the departure is attributable to symbol misphasing being leading or lagging remains to be resolved.

[0055] The samples from the in-phase synchronous detector <b>290</b> applied as input signal to the clocked digital delay line <b>323</b> are applied without delay as input signal to a mean-square-error gradient detection filter <b>326</b>. The filter <b>326</b> is a finite-impulse-response digital filter having a (−½), 1, 0, (−1), (+½) kernel, the operation of which is clocked by the first sampling clock. The prescribed number of sample periods of delay provided by the clocked digital delay line <b>323</b> is such that filter <b>326</b> response is in temporal alignment with the difference signal from the adder/subtractor <b>325</b>. A digital multiplier <b>327</b> multiplies the difference signal from the adder/subtractor <b>325</b> by the filter <b>326</b> response to resolve this issue. The sign bit and the next most significant bit of the two's complement filter <b>326</b> response suffice for the multiplication, which permits simplification of the digital multiplier <b>327</b> structure. The samples of the product signal from the digital multiplier <b>327</b> are indications of the misphasing of the symbol clocking done at the receiver that are averaged over many samples (e. g., several million) by a digital lowpass filter <b>328</b> for generating the second address correction signal supplied to the adder <b>322</b> to correct the basic second address.

[0056] The symbol synchronization techniques used in the second address generator <b>32</b> shown FIG. 3 (and in FIG. 5) are of the same general type as S. U. H. Qureshi describes for use with pulse amplitude modulation (PAM) signals in his paper “Timing Recovery for Equalized Partial-Response Systems, IEEE Transactions on Communications, December 1976, pp. 1326-1330. These symbol synchronization techniques as used in connection with symbol synchronization for VSB signals are specifically described by the inventors in their earlier-filed applications referenced earlier in this specification. In preferred designs of the general type of second address generator <b>32</b> shown FIGS. 3 and 5, the clocked digital delay line <b>323</b> does not exist as a separate element; instead, an input signal to the quantizer <b>324</b> with the requisite number of sample periods of delay for the difference signal from the adder/subtractor <b>325</b> being temporally aligned with the filter <b>326</b> response is taken from the tapped digital delay line included in the filter <b>326</b> for supplying differentially delayed samples to be weighted by the (−½), 1, 0, (−1), (+½) kernel before being summed to generate the filter <b>326</b> response.

[0057] The carrier of a QAM HDTV signal and the carrier of a VSB HDTV signal are translated to respective intermediate frequencies, each of which is a submultiple of a multiple of the 21.52 MHz sample rate that is the fourth harmonic of the 5.38 MHz symbol frequency of the QAM HDTV signal and that is the second harmonic of the 10.76 MHz symbol frequency of the VSB HDTV signal. These two respective intermediate frequencies are at a 2.375 MHz remove from each other, since the carrier of the QAM HDTV signal is at the center of a 6 MHz-wide TV channel, but the carrier of the VSB HDTV signal is only 625 kHz above the lowest frequency of a 6 MHz-wide TV channel. Preferably the frequencies of the local oscillators <b>11</b>, <b>16</b> and <b>20</b> in the tuner <b>5</b> are chosen so that the intermediate frequency to which the carrier of a VSB HDTV signal is translated is lower than that to which the carrier of a QAM HDTV signal is translated. This is strongly preferred since it facilitates symbol synchronization when a VSB HDTV signal is received. Preferably the intermediate frequency to which the carrier of a QAM HDTV signal is translated is not more than 5.38 MHz, so that it can be sampled at least four times per cycle in accordance with the 21.52 MHz sample clock, which preference constrains the lowest frequency in the final IF signal to being no higher than 2.38 MHz. Preferably the lowest frequency of the final IF signal is above 1 MHz, to keep the ratio of the highest frequency of the final IF signal thereto substantially below 8:1 and thereby ease the filtering requirements for the real-to-complex-sample converter <b>24</b>, so the intermediate frequency to which the carrier of a VSB HDTV signal is translated is preferably above 1.625 MHz.

[0058]FIG. 4 is a table of subharmonics of the 21.52 MHz sampling frequency and of 43.04 MHz, the second harmonic of the 21.52 MHz sampling frequency, which overlap the frequency range of interest. (A more complete table of subharmonics of low harmonics of the 21.52 MHz sampling frequency can be constructed, of course, but the number of addresses for the ROMs <b>27</b> and <b>31</b> will have to be extended as higher harmonics of the 21.52 MHz sampling frequency are added to the table and subharmonics of those higher harmonics are subsequently selected to approximate the QAM and VSB carrier frequencies in the final IF signal.) One wishes to select two of the frequencies from the FIG. 4 table that meet the criteria of the previous paragraph for the respective intermediate frequencies to which the carrier of a QAM HDTV signal and the carrier of a VSB HDTV signal are to be translated. The FIG. 4 table includes at the top extreme right therein a column of higher subharmonics of 43.04 MHz decremented by 2.375 MHz, which resulting frequency values can be compared to lower subharmonics of 43.04 MHz as an aid in selecting subharmonics with close to the desired 2.375 MHz offset between them. The ninth and the eighteenth subharmonics of 43.04 MHz exhibit a 16 kHz or 0.67% error in regard to the desired offset; the tenth and twenty-second subharmonics of 43.04 MHz exhibit a 27 kHz or 1.14% error in regard to the desired offset; the eleventh and twenty-eighth subharmonics of 43.04 MHz exhibit only a 1 kHz or 0.04% error in regard to the desired offset; and the twelfth and thirty-sixth subharmonics of 43.04 MHz exhibit only a 16 kHz or 0.67% error in regard to the desired offset. The correction of nominal second local oscillator <b>16</b> frequency required to lock each of the QAM and VSB carriers in the final IF signals to their desired submultiple frequencies is a very small percentage of the 960 MHz frequency of its oscillations, so the stability of its oscillations are little affected by its being AFPC'd. The shift of the second intermediate frequencies in as far as they fall into the traps of the second SAW filter <b>18</b> is the more significant consideration. The effects of this shift can be countered by changing the frequency of the third local oscillator <b>20</b> a few kHz by shunting its crystal tank circuit with switched capacitance during one reception mode. In past commercial designs for NTSC TV receivers, mistuning up to 30 kHz has been tolerated in IF amplifiers constructed with discrete stages having inductors and capacitors as frequency-selective elements, and somewhat greater mistuning has been tolerated in monolithic IF amplifiers using SAW filters.

[0059] Referring back to FIG. 3, assuming the tenth and twenty-second subharmonics of 43.04 MHz are to be used as the final intermediate frequencies to which the QAM and VSB HDTV carriers are respectively converted, so the converted VSB carrier is somewhat above 1.625 MHz, the first address counter <b>281</b> is arranged to count modulo ten thereby to generate one cycle of ROM <b>27</b> addressing, and the second address counter <b>322</b> is arranged to count modulo twenty-two thereby to generate one cycle of ROM <b>31</b> addressing. If the eleventh and twenty-eighth subharmonics of 43.04 MHz are used as the final intermediate frequencies to which the QAM and VSB HDTV carriers are respectively converted, the first address counter <b>281</b> is arranged to count modulo eleven thereby to generate one cycle of ROM <b>27</b> addressing, and the second address counter <b>322</b> is arranged to count modulo twenty-eight thereby to generate one cycle of ROM <b>31</b> addressing. If the twelfth and thirty-sixth subharmonics of 43.04 MHz are used as the final intermediate frequencies to which the QAM and VSB HDTV carriers are respectively converted, the first address counter <b>281</b> is arranged to count modulo twelve thereby to generate one cycle of ROM <b>27</b> addressing and the second address counter <b>322</b> is arranged to count modulo thirty-seven thereby to generate one cycle of ROM <b>31</b> addressing.

[0060]FIG. 5 shows a modification of the FIG. 3 circuitry that is possible when the ninth and the eighteenth subharmonics of 43.04 MHz are used as the final intermediate frequencies to which the QAM and VSB HDTV carriers are respectively converted. The VSB complex carrier ROM <b>31</b> is replaced with a ROM <b>310</b> that comprises a portion <b>313</b> that stores only one-half cycle of VSB carrier cosine values and a portion <b>314</b> that stores only one-half cycle of VSB carrier sine values. In a modification <b>320</b> of the second address generator <b>32</b> described above, the adder <b>322</b> receives the basic first address from the first address counter <b>281</b> as its first summand input signal, rather than the basic second address from the second address counter <b>321</b>. The second address counter <b>321</b> is not used in the modified second address generator <b>320</b>. The first address counter <b>281</b> is arranged to count modulo nine, thereby to generate one cycle of ROM <b>27</b> addressing and the one half cycle of ROM <b>310</b> addressing. A binary counter stage <b>319</b> counts overflow carries from the first address counter <b>281</b>. A selective bits complementor <b>315</b> exclusive-ORs the modulo-<b>2</b> count from the binary counter stage <b>319</b> with each of the bits of the VSB carrier cosine values read from the portion <b>313</b> of the ROM <b>310</b> for generating a first summand input for a digital adder <b>317</b>, and the modulo-<b>2</b> count from the binary counter stage <b>319</b> is provided with zero extension in the direction of increased significance for generating a second summand input for the adder <b>317</b>. The sum output from the adder <b>317</b> provides the full cycle of VSB carrier cosine values over eighteen first clock periods. A selective bits complementor <b>316</b> exclusive-ORs the modulo-<b>2</b> count from the binary counter stage <b>319</b> with each of the bits of the VSB carrier sine values read from the portion <b>314</b> of the ROM <b>310</b> for generating a first summand input for a digital adder <b>318</b>, and the modulo-<b>2</b> count from the binary counter stage <b>319</b> with zero extension in the direction of increased significance is also applied as a second summand input for the adder <b>318</b>. The sum output from the adder <b>318</b> provides the full cycle of VSB carrier sine values over eighteen first clock periods.

[0061] One skilled in the art of digital circuit design will understand that other hardware savings can be made in the FIG. 3 read-only memory circuitry taking advantage of symmetries in the cosine and sine functions or the 90° offset in the respective phases of these two functions. Arrangements where the sine and cosine values are not read from ROM, but rather are accumulated in parallel in accordance with the sin (A+B)=sin A cos B+cos A sin B and cos (A+B)=cos A cos B−sin A sin B trignometric formulae are another alternative.

[0062]FIG. 6 shows a form that the circuitry <b>24</b> can take, which comprises:

[0063] (a) a linear-phase, finite-impulse-response (FIR) digital filter <b>60</b> that generates imaginary (Im) digital samples as a Hilbert transform response to the real (Re) digital samples; and

[0064] (b) compensating, clocked digital delay of the real digital samples to compensate for the latency time of the Hilbert transformation filter <b>60</b>, which clocked digital delay can be provided by clocked latch elements <b>61</b>-<b>66</b> included in the Hilbert transformation filter <b>60</b>.

[0065] The use of such circuitry for implementing in-phase and quadrature-phase sampling procedures on bandpass signals is described by D. W. Rice and K. H. Wu in their article “Quadrature Sampling with High Dynamic Range” on pp. 736-739 of IEEE TRANSACTIONS ON AEROSPACE AND ELECTRONIC SYSTEMS, Vol. AES-18, No. 4 (November 1982). Since the frequency band 6 MHz wide occupied by the final IF signal has a lowest frequency of at least a megaHertz or so, it is possible to use as few as seven non-zero-weighted taps in the FIR filter <b>60</b> used for Hilbert transformation.

[0066] The seven-tap Hilbert transformation filter <b>60</b> includes a cascade connection of one-sample delay elements <b>61</b>, <b>62</b>, <b>63</b>, <b>64</b>, <b>65</b> and <b>66</b> from which samples taken to be weighted and summed to generate the Hilbert transform response. The Hilbert transform is linear phase in nature so the tap weights of the FIR filter <b>60</b> exhibit symmetry about median delay. Accordingly, a digital adder <b>67</b> sums the input signal to delay element <b>61</b> and the output signal from the delay element <b>66</b> to be weighted in common, a digital adder <b>68</b> sums the output signal from the delay element <b>61</b> and the output signal from the delay element <b>65</b> to be weighted in common, and a digital adder <b>69</b> sums the output signal from the delay element <b>62</b> and the output signal from the delay element <b>64</b> to be weighted in common. The output signal from the delay element <b>64</b> is applied as input address to a read-only memory <b>70</b>, which multiplies that signal by an appropriate weight W₀magnitude. The sum output signal from the digital adder <b>69</b> is applied as input address to a read-only memory <b>71</b>, which multiplies that signal by an appropriate weight W₁magnitude. The sum output signal from the digital adder <b>68</b> is applied as input address to a read-only memory <b>72</b>, which multiplies that signal by an appropriate weight W₂magnitude. The sum output signal from the digital adder <b>67</b> is applied as input address to a read-only memory <b>73</b>, which multiplies that signal by an appropriate weight W₃magnitude. The use of the ROMs <b>70</b>, <b>71</b>, <b>72</b> and <b>73</b> as fixed-multiplicand multipliers keeps the delay associated with multiplication negligibly short. The output signals of the ROMs <b>70</b>, <b>71</b>, <b>72</b> and <b>73</b> are combined by a tree of signed digital adders <b>74</b>, <b>75</b> and <b>76</b> operated as adders or subtractors, as required to appropriately assign signs to the magnitudes of the weights W₀, W₁, W₂and W₃stored in the ROMs <b>70</b>, <b>71</b>, <b>72</b> and <b>73</b>. The adders <b>67</b>, <b>68</b>, <b>69</b>, <b>74</b>, <b>75</b> and <b>76</b> are assumed to be clocked adders each exhibiting one-sample latency, which results in the seven-tap FIR filter <b>60</b> exhibiting a six-sample latency. Delay of the filter <b>60</b> input signal that compensates for this latency is provided by the cascade connection of the six one-sample delay elements <b>61</b>, <b>62</b>, <b>63</b>, <b>64</b>, <b>65</b> and <b>66</b>. The input address to the read-only memory <b>70</b> is taken from the output of the delay element <b>64</b>, rather than from the output of the delay element <b>63</b>, so the one-sample delay of delay element <b>64</b> compensates for the one-sample delays in the adders <b>67</b>, <b>68</b> and <b>69</b>.

[0067] C. M. Rader in his article “A Simple Method for Sampling In-Phase and Quadrature Components”, IEEE TRANSACTIONS ON AEROSPACE AND ELECTRONIC SYSTEMS, Vol. AES-20, No. 6 (November 1984), pp. 821-824, describes improvements in complex synchronous detection carried out on digitized bandpass signals. Rader replaces the Hilbert-transform FIR filter and the compensating-delay FIR filter of Rice and Wu with a pair of all-pass digital filters designed based on Jacobian elliptic functions and exhibiting a constant π/2 difference in phase response for the digitized bandpass signals. A preferred pair of such all-pass digital filters has the following system functions:

<i>H</i>₁(<i>z</i>)=<i>z</i>⁻¹(<i>z</i>⁻²<i>−a</i>²)/(1<i>−a</i>²<i>z</i>⁻²) <i>a</i>²=0.5846832

<i>H</i>₂(<i>z</i>)=−(<i>z</i>⁻²<i>−b</i>²)/(1<i>−b</i>²<i>z</i>⁻²) <i>b</i>²=0.1380250

[0068] Rader describes filter configurations which require only two multiplications, one by a²and one by b².

[0069]FIG. 7 shows an alternative form that the circuitry <b>24</b> can take, which comprises a pair of all-pass digital filters <b>80</b> and <b>90</b> of a type described by C. M. Rader and designed based on Jacobian elliptic functions. The filters <b>80</b> and <b>90</b> exhibit a constant π/2 difference in phase response for digitized bandpass signals. Since oversampled real samples better provide for symbol synchronization when synchrodyning VSB signals, the inventors prefer not to use the all-pass filters described by Rader that exploit sub-sampling to provide further reductions in the delay network circuitry.

[0070] The construction of the filter <b>80</b>, which provides the system function H₁(z)=z⁻¹(z⁻²−a²)/(1−a²z⁻²), where a²=0.5846832 in decimal arithmetic, is shown in FIG. 7 to be as follows. The samples from the ADC <b>22</b> are delayed by one ADC sample clock duration in a clocked delay element <b>88</b> for application to a node <b>89</b>. The signal at node <b>89</b> is further delayed by two ADC sample clock durations in cascaded clocked delay elements <b>81</b> and <b>82</b>, for application as its first summand signal to a digital adder <b>83</b>. The sum output signal of the adder <b>83</b> provides the real response from the filter <b>80</b>. The sum output signal of the adder <b>83</b> is delayed by two ADC sample clock durations in cascaded clocked delay elements <b>84</b> and <b>85</b>, for application as minuend input signal to a digital subtractor <b>86</b> that receives the signal at node <b>89</b> as its subtrahend input signal. The resulting difference output signal from the digital subtractor <b>86</b> is supplied as multiplier input signal to a digital multiplier <b>87</b> for multiplying an a²multiplicand signal, using a binary arithmetic. The resulting product output signal is applied to the digital adder <b>83</b> as its second summand signal.

[0071] The construction of the filter <b>90</b>, which provides the system function H₂(z)=−(z⁻²−b²)/(1−b²z⁻²), where b²=0.1380250 in decimal arithmetic, is shown in FIG. 7 to be as follows. The samples from the ADC <b>22</b> are delayed by two ADC sample clock durations in cascaded clocked delay elements <b>91</b> and <b>92</b>, for application as its first summand signal to a digital adder <b>93</b>. The sum output signal of the adder <b>93</b> provides the imaginary response-from the filter <b>90</b>. The sum output signal of the adder <b>93</b> is delayed by two ADC sample clock durations in cascaded clocked delay elements <b>94</b> and <b>95</b>, for application to a digital adder <b>96</b> as its second summand signa, which receives the samples from the ADC <b>22</b> as its subtrahend input signal. The resulting sum output signal from the digital adder <b>96</b> is supplied as multiplier input signal to a digital multiplier <b>97</b> for multiplying a b²multiplicand signal, using a binary arithmetic. The resulting product output signal is applied to the digital adder <b>93</b> as its second summand signal.

[0072]FIG. 8 shows a complex-signal filter resulting from modifying the FIG. 7 complex-signal filter as follows. The position of the clocked delay element <b>88</b> is shifted so as to delay the sum output signal of the adder <b>83</b>, rather than to delay the digital output signal of the ADC <b>22</b>, and the digital output signal of the ADC <b>22</b> is applied to the node <b>89</b> without delay, thereby to cause real response to be provided at the output port of the shifted-in-position clocked delay element <b>88</b>. The real response provided at the output port of the shifted-in-position clocked delay element <b>81</b> is the same as the response provided at the output port of the clocked delay element <b>84</b>. So, the real response is provided from the output port of the clocked delay element <b>84</b> instead of from the output port of the shifted-in-position clocked delay element <b>81</b>; and the shifted-in-position clocked delay element <b>81</b>, being no longer required, is dispensed with.

[0073]FIG. 9 shows a complex-signal filter resulting from modifying the FIG. 8 complex-signal filter as follows. The first summand signal for the adder <b>83</b> is then taken from the cascaded clocked delay elements <b>91</b> and <b>92</b>, rather than from the cascaded clocked delay elements <b>81</b> and <b>82</b>. The cascaded clocked delay elements <b>81</b> and <b>82</b>, being no longer required, are dispensed with. The FIG. 9 complex-signal filter is preferred over the complex-signal filters of FIGS. 7 and 8 in that redundant clocked delay elements are eliminated.

[0074]FIG. 10 shows in more detail the digital circuitry <b>25</b> for synchrodyning QAM HDTV signals to baseband. The QAM synchrodyning circuitry <b>25</b> includes the QAM in-phase synchronous detector <b>250</b> for generating the real portion of its output signal and the QAM quadrature-phase synchronous detector <b>255</b> for generating the imaginary portion of its output signal. The QAM synchrodyning circuitry <b>25</b> includes a digital adder <b>256</b>, a digital subtractor <b>257</b>, and respective first, second, third and fourth digital multipliers <b>251</b>-<b>254</b>. The QAM in-phase synchronous detector <b>250</b> includes the multiplier <b>251</b>, the multiplier <b>252</b>, and the adder <b>256</b> for adding the product output signals of the multipliers <b>251</b> and <b>252</b> to generate the real portion of the output signal of the QAM synchrodyning circuitry <b>25</b>. The first digital multiplier <b>251</b> multiplies the real digital samples of final IF signal supplied from the real-to-complex-sample converter <b>24</b> by digital samples descriptive of the cosine of the QAM carrier that are read from the look-up table <b>271</b> in the ROM <b>27</b>, and the second digital multiplier <b>252</b> multiplies the imaginary digital samples of final IF signal supplied from the real-to-complex-sample converter <b>24</b> by digital samples descriptive of the sine of the QAM carrier that are read from the look-up table <b>272</b> in the ROM <b>27</b>. The QAM quadrature-phase synchronous detector <b>255</b> includes the multiplier <b>253</b>, the multiplier <b>254</b>, and the subtractor <b>257</b> for subtracting the product output signal of the multiplier <b>253</b> from the product output signal of the multiplier <b>254</b> to generate the imaginary portion of the output signal of the QAM synchrodyning circuitry <b>25</b>. The third digital multiplier <b>253</b> multiplies the real digital samples of final IF signal supplied from the real-to-complex-sample converter <b>24</b> by digital samples descriptive of the sine of the QAM carrier that are read from the look-up table <b>272</b> in the ROM <b>27</b>, and the fourth digital multiplier <b>254</b> multiplies the imaginary digital samples of final IF signal supplied from the real-to-complex-sample converter <b>24</b> by digital samples descriptive of the cosine of the QAM carrier that are read from the look-up table <b>271</b> in the ROM <b>27</b>.

[0075]FIG. 10 also shows in more detail the digital circuitry <b>29</b> for synchrodyning VSB HDTV signals to baseband. The VSB synchrodyning circuitry <b>29</b> includes the VSB in-phase synchronous detector <b>290</b> for generating the real portion of its output signal and the VSB quadrature-phase synchronous detector <b>295</b> for generating the imaginary portion of its output signal. The VSB synchrodyning circuitry <b>29</b> includes a digital adder <b>296</b>, a digital subtractor <b>297</b>, and respective first, second, third and fourth digital multipliers <b>291</b>-<b>294</b>. The VSB in-phase synchronous detector <b>290</b> includes the multiplier <b>291</b>, the multiplier <b>292</b>, and the adder <b>296</b> for adding the product output signals of the multipliers <b>291</b> and <b>292</b> to generate the real portion of the output signal of the VSB synchrodyning circuitry <b>29</b>. The first digital multiplier <b>291</b> multiplies the real digital samples of final IF signal supplied from the real-to-complex-sample converter <b>24</b> by digital samples descriptive of the cosine of the VSB carrier that are read from the look-up table <b>291</b> in the ROM <b>29</b>, and the second digital multiplier <b>292</b> multiplies the imaginary digital samples of final IF signal supplied from the real-to-complex-sample converter <b>24</b> by digital samples descriptive of the sine of the VSB carrier that are read from the look-up table <b>292</b> in the ROM <b>29</b>. The VSB quadrature-phase synchronous detector <b>295</b> includes the multiplier <b>293</b>, the multiplier <b>294</b>, and the subtractor <b>297</b> for subtracting the product output signal of the multiplier <b>293</b> from the product output signal of the multiplier <b>294</b> to generate the imaginary portion of the output signal of the VSB synchrodyning circuitry <b>29</b>. The third digital multiplier <b>293</b> multiplies the real digital samples of final IF signal supplied from the real-to-complex-sample converter <b>24</b> by digital samples descriptive of the sine of the VSB carrier that are read from the look-up table <b>292</b> in the ROM <b>29</b>, and the fourth digital multiplier <b>294</b> multiplies the imaginary digital samples of final IF signal supplied from the real-to-complex-sample converter <b>24</b> by digital samples descriptive of the cosine of the VSB carrier that are read from the look-up table <b>291</b> in the ROM <b>29</b>.

[0076]FIG. 11 shows in more detail one way to construct the VSB pilot carrier presence detector <b>34</b>, which employs a digital lowpass filter <b>341</b> of a type that averages a sufficiently large number of samples supplied thereto from the VSB in-phase synchronous detector <b>290</b> to restrict the bandwidth of the filter <b>341</b> response, so that response is solely to the pilot carrier wave as synchrodyned to zero frequency. That is, the lowpass filter <b>341</b> does not exhibit substantial response to the higher frequencies to which the VSB signal synchrodynes. The response of the lowpass filter <b>341</b> is supplied as subtrahend signal to a digital subtractor <b>342</b>. The subtractor <b>342</b> functions as a digital comparator to perform threshold detection. The subtractor <b>342</b> has applied thereto a wired minuend of about half the value to which the automatic gain control of the HDTV receiver regulates the pilot carrier wave, to provide a threshold level against which to detect the presence or absence of the pilot carrier wave. The most significant bit of the two's complement difference output signal of the subtractor <b>342</b> is a sign bit, which is a ONE to indicate the presence of the pilot carrier wave, and which is a ZERO to indicate the absence of the pilot carrier wave. This sign bit is the digital comparator output signal supplied as the output indication from the VSB pilot carrier presence detector <b>34</b>.

[0077] An alternative way to construct the VSB pilot carrier presence detector <b>34</b> uses a digital-to-analog converter to convert samples supplied thereto from the VSB in-phase synchronous detector <b>290</b> to an analog input signal for an analog lowpass filter. The response of the analog lowpass filter is supplied to an analog comparator arranged to function as a threshold detector for determining the presence or absence of the pilot carrier wave. The digital construction of the VSB pilot carrier presence detector <b>34</b> shown in FIG. 11 is preferred in that the response of the digital lowpass filter <b>341</b> is also useful in implementing automatic gain control (AGC) circuitry in a digital HDTV signal radio receiver of the type shown in FIGS. 1 and 2.

[0078]FIG. 11 shows AGC circuitry <b>100</b> that uses the response of the digital lowpass filter <b>341</b> for developing AGC signals to control the conversion gain of the tuner <b>5</b> when the digital HDTV signal being currently received is of VSB type. The response of the filter <b>341</b> is supplied as minuend input signal to a digital subtractor <b>101</b>, to have subtracted therefrom a wired subtrahend descriptive of the desired level of the digitized pilot carrier wave. The difference output from the subtractor <b>101</b>, which is a digital AGC signal for VSB reception, is applied as a first input signal to a digital multiplexer <b>102</b>. The digital multiplexer <b>102</b> selects the source of the digital AGC signal supplied to a digital-to-analog converter <b>103</b> for conversion to an analog AGC signal. The analog AGC signal is supplied to an analog lowpass filter <b>104</b> to be subjected to further lowpass filtering, and the lowpass response of the filter <b>104</b> is supplied to a delayed AGC network <b>105</b> of conventional design that responds to apply suitably delayed AGC signals to the first and second IF amplifiers <b>14</b> and <b>18</b> shown in FIG. 1, and in some designs to the first mixer <b>12</b> (or to a preceding radio-frequency amplifier not shown in FIG. 1) as well. The output indication from the VSB pilot carrier presence detector <b>34</b>, as delayed a sample period or so of the multiplexer <b>102</b> input signals by a digital shim delay element <b>106</b>, is the control signal applied to the multiplexer <b>102</b>. When this signal is a ONE, indicative that an HDTV signal of VSB type is being received currently, the multiplexer <b>102</b> reproduces the difference output from the subtractor <b>101</b> to provide the filter <b>104</b> input signal.

[0079] The samples of output signal from either the QAM in-phase synchronous detector <b>250</b> or from the QAM quadrature-phase synchronous detector <b>255</b> are squared by a digital multiplier <b>107</b>. A digital lowpass filter <b>108</b> of a type similar to the filter <b>341</b> receives as its input signal the product output signal from the digital multiplier <b>107</b>. The response of the filter <b>108</b> is supplied as minuend input signal to a subtractor <b>109</b> to have subtracted therefrom a wired subtrahend descriptive of the desired mean square level of the QAM signal. The difference output from the subtractor <b>109</b>, which is a digital AGC signal for QAM reception, is applied as a second input signal to the digital multiplexer <b>102</b>. When the control signal applied to the multiplexer <b>102</b> is a ZERO, which is indirectly indicative that an HDTV signal of QAM type is being received currently, the multiplexer <b>102</b> reproduces the difference output from the subtractor <b>109</b> to provide the filter <b>104</b> input signal. The subtractor <b>109</b> will supply a digital AGC signal even during VSB reception, which signal suffices to provide a degree of AGC even when there is delay in.the VSB pilot carrier presence detector <b>34</b> indicating that pilot carrier is present; so VSB reception is enabled.

[0080] The DAC <b>103</b> is preferably of a special design, which supplies a predetermined direct level of analog AGC signal for all negative digital input signals and responds with varying level only to positive digital input signals. Since the AGC signal is of such narrow bandwidth, it is unnecessary to supply it to the DAC <b>103</b> at first clock rates. Indeed, to conserve operating energy, etc., it is desirable to operate the DAC <b>103</b> at much lower rates.

[0081]FIG. 12 shows in more detail the preferred construction of portions of the FIG. 11 circuitry in which digital lowpass filtering and digital-to-analog conversion are performed. A frequency divider <b>110</b> generates a third clock signal at a rate that is a large submultiple (e. g., 2¹⁰) of the second clock signal. For example, the frequency divider <b>110</b> comprises:

[0082] (a) a chain of binary counter stages that generates an overflow pulse whenever its final stage is toggled, and

[0083] (b) pulse shaping circuitry for shaping the overflow pulses into respective clocking pulses for the third clock signal.

[0084] This third clock signal clocks an input latch <b>1031</b> of the DAC <b>103</b> and an input latch <b>1061</b> in the digital shim delay element <b>106</b>. The digital lowpass filter <b>108</b> is realized as an accumulator comprising a digital adder <b>1081</b>; an output latch <b>1082</b> for the adder <b>1081</b>, clocked by said first clock signal; and a digital multiplexer <b>1083</b> conditioned by the third clock signal to reset the accumulation. The digital lowpass filter <b>341</b> is also realized as an accumulator comprising a digital adder <b>3411</b>; an output latch <b>3412</b> for the adder <b>3411</b>, clocked by said first clock signal; and a digital multiplexer <b>3413</b> conditioned by the third clock signal to reset the accumulation.

[0085] Variants of the VSB synchrodyne circuitry <b>29</b> in which the digitized final IF signal is narrowband bandpass filtered prior to VSB quadrature-phase synchronous detection are possible in less preferred embodiments of the invention described in this specification and claimed in the ensuing claims; some of these variants also require modification of the ROM circuitry <b>31</b> used for generating digital complex-number descriptions of the VSB signal carrier as translated to final intermediate frequency. Such variants are described in more detail in the inventors' previous patent applications incorporated herein by reference.

[0086] Embodiments of the invention are contemplated which do not use the pilot carrier presence detector <b>34</b> to determine whether the HDTV signal being currently received is of QAM or VSB type. For example, the imaginary samples from the VSB quadrature-phase synchronous detector <b>295</b> are squared, the squared samples are lowpass filtered, and the lowpass filter response is threshold detected. If the HDTV signal being currently received is of VSB type, the imaginary samples from the VSB quadrature-phase synchronous detector <b>295</b> are substantially zero-valued, the squared samples are substantially zero-valued, and the lowpass filter response is substantially zero-valued, so it does not exceed the threshold level of the threshold detector. If the HDTV signal being currently received is of QAM type, the imaginary samples from the VSB quadrature-phase synchronous detector <b>295</b> have at least at times values other than zero, and the lowpass filter response to the squared imaginary samples contains a direct term that exceeds the threshold level of the threshold detector. The preference of the inventors for the pilot carrier presence detector <b>34</b> is because of its also being useful in the AGC circuitry for controlling the conversion gain of the tuner <b>5</b>.

[0087] Less preferred embodiments of the invention are contemplated in which the output signals of the two-dimensional trellis decoder <b>37</b> and of the one-dimensional trellis decoder <b>38</b> are supplied to respective data de-interleavers, with data source selection being deferred until data de-interleaving is completed. Other less preferred embodiments of the invention are contemplated in which embodiments the output signal of the two-dimensional trellis decoder <b>37</b> is de-interleaved by a respective data de-interleaver and then decoded by a respective Reed-Solomon decoder to generate a first stream of error-corrected data, in which embodiments the output signal of the one-dimensional trellis decoder <b>38</b> is de-interleaved by a respective data de-interleaver and then decoded by a respective Reed-Solomon decoder to generate a second stream of error-corrected data, and in which embodiments data source selection is made between the first and second streams of error-corrected data. In modifications of these other less preferred embodiments of the invention the first and second streams of error-corrected data are supplied to separate data de-randomizers before data source selection is made. In other variants separate Reed-Solomon decoders are used for the QAM and VSB signals, but one data de-interleaver is used for both the QAM and VSB signals, or one data de-randomizer is used for both the first and second streams of error-corrected data.

[0088] In the claims which follow, the word “said” is used whenever reference is made to an antecedent, and the word “the” is used for grammatical purposes other than to refer back to an antecedent.