X-y addressable CMOS APS with compact pixel pitch

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This is a continuation-in-part of application Ser. No. 08/821,988, filed Mar. 21, 1997, entitled AN X-Y ADDRESSABLE CMOS APS WITH COMPACT PIXEL PITCH.

FIELD OF INVENTION

[0002] The present invention relates generally to the operation of an active pixel sensor and more specifically to an x-y addressable feature of such a sensor that allows each and every one of the pixels in the array to be selected and read out singly or in groups.

BACKGROUND OF THE INVENTION

[0003] In an x-y addressable image such as an active pixel sensor (APS), the conventional method of selecting pixels to be read out is by employing a full address decoding circuit which translates the binary encoded addresses into the specific x-y signaling lines. By changing the addresses in a pre-determined fashion, any arbitrary rectangular window, or single pixel can be selected for output. This method requires a decoder for each of the x and y signaling lines and therefore requires packing the circuit to fit the pixel pitch of the imager.

[0004] A simpler method of generating x-y addresses is to use serial shift registers instead of address decoders. The serial shift register design is simpler to implement and allows smaller spacing between pixels, but is not capable of performing the sub-windowing function.

[0005] It should be apparent from the foregoing discussion that there remains a need in the art for an x-y addressable pixel sensor that allows smaller spacing between pixels as well as for retaining the capability of sub-windowing.

SUMMARY OF THE INVENTION

[0006] The present invention overcomes the previously discussed shortcomings within the prior art by using additional circuits to pre-load the shift registers so that read-out of the sub-windows can be accomplished. The result is that the present invention provides x-y addressable features to active pixel sensors (APS) that allow each and every one of the pixels in the array to be selected and read out singly or in groups. This feature allows the readout of the image sensor in sub-window format where the array of pixels read out can be programmed to be a portion of the total imager. The sub-window format allows trading off the number of pixels per image output (resolution) with the frame rate of the read out and also enables electronic zoom and pan operations.

[0007] Advantageous Effect of the Invention

[0008] By using serial shift registers to select the signaling lines both in x and y directions, the per row and per column circuit required is simplified from a full address decoder which takes up more area to shift register design. This allows shrinking the pixel size of the imager to a smaller dimension. For example, the conventional APS pixel design is 20 times the smallest allowed line length of the integrated circuit fabrication technology. This 20× limit is due to the size of the address decoder. By using the serial shift register integration, this limit can be reduced from between 7 to 15 times the size of the line length. Therefore, the overall size of the imager can be reduced by 24% to 67% without using higher cost smaller geometry fabrication technology. The present invention maintains the important feature of sub-windowing when the shift register design is used to achieve smaller pixel and therefore smaller die-size.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009]FIG. 1 is a prior art conventional x-y addressable imager;

[0010]FIG. 2 is an x-y addressable imager employing shift registers as envisioned by the present invention;

[0011]FIG. 3 is another x-y addressable imager embodiment of the present invention employing shift registers; and

[0012]FIG. 4 illustrates detailed operation of the present invention.

[0013] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures.

DETAILED DESCRIPTION OF THE INVENTION

[0014]FIG. 1 shows a prior art conventional x-y addressable imager, generally referred to as <b>10</b>, having x-y addressable imager <b>12</b> with a contained sub-window image <b>13</b> within imager <b>12</b>, row decoder <b>15</b>, column decoder <b>17</b>, and column signal processing <b>19</b>.

[0015]FIG. 2 illustrates a sensor <b>20</b> as envisioned by the present invention having x-y addressable imager <b>12</b> with sub-window image <b>13</b>. The additional circuits added to the x and the y signaling control are shift registers <b>23</b>, <b>28</b>. The shift registers <b>23</b>, <b>28</b> are used to interface the row address <b>24</b> and the column address <b>26</b>, respectively, to the imager. The shift registers <b>23</b>, <b>28</b> allow for a pre-determined starting location of each shift register to be loaded with a digital “1” to select the starting x-y location. The shift register then subsequently scans through a pre-determined number of locations to select the size of the sub-window to be read out through the column signal processing circuit <b>29</b>. The added circuit controls the shifting of the digital “1” so that the scans in x and y are repeated for subsequent output frames. Since only one scanning control circuit is required for each of the x and y dimension, the pixel pitch can remain at the smaller size achieved using the shift registers.

[0016] An alternate embodiment of the present invention is shown in FIG. 3, generally indicated as <b>30</b>. In the alternate embodiment shown in FIG. 3, switch-enabling circuits <b>34</b>, <b>36</b> are used in place of scanning control circuits to allow only a pre-determined sub-window <b>13</b> to be read out through column signal processing circuit <b>29</b>. The switch enabling circuits are set up by loading a pre-determined sequence of digital “1's” on the rows and columns of interest, from the row and column serial shift registers, <b>33</b> and <b>38</b> respectively, only this portion of the imager is output. The drawback of this approach is that since all the pixels are scanned by the shift registers, there is no effective change in the frame rates of the readout.

[0017] Employing serial shift registers to select the signaling lines in both x and y directions simplifies the per row and per column circuit required compared to a full address decoder which takes up more area. This allows shrinking the pixel size of the imager to a smaller dimension. For example, the conventional APS pixel design is 20 times the smallest allowed line length of the integrated circuit fabrication technology. This 20 times limit is due to the size of the address decoder. By using the serial shift register integration, this limit can be reduced from between 7 to 15 times the size of the line length. Therefore, the overall size of the imager can be reduced by 25% to 67% without using higher cost smaller geometry fabrication technology. The present invention maintains the important features of sub-windowing when the shift register design is used to achieve smaller pixel and therefore smaller die-size.

[0018] Detailed operation of the present invention is further exemplified in FIG. 4. A shift register <b>51</b> is shown connected to a whole or a portion of a x-y addressable imager <b>52</b> having m (x direction) by n (y direction) imaging sites. For simplicity sake, only the columns (x) addressing is shown. This same column addressing scheme is applicable to the row (y) addressing circuit <b>53</b>. Only a single output from the column signal processor <b>54</b> is shown. Multiple outputs would require replication of the shift register scheme for multiple sets of the columns in the x-y addressable imager. In its simplest operation, the shift register <b>51</b> selects a single column at any one instance of time by having a logical 1 in one of its locations (starting from the first location furthest to the left) and in coincidence with a specific row address, selects a single pixel to be processed by the column signal processor <b>54</b> to have its light sensing output <b>60</b>. The column address is sequenced by propagating this logical 1 in one direction (for example to the right).

[0019] In order to select a sub-window to be read out of this portion of the x-y addressable imager, prior art teaches skipping columns by the use of counters to keep track of the start and stop column counts, hierarchical (block addressing) shift registers with one enabling a block of columns and then individual column within the selected block is selected by another shift register. In the first method, a latency is incurred while the shift register clocks through the columns but the selection is disabled. In the second method, multiple shift registers are needed. In this invention, a single shift register is employed and no there is no latency. Output is enabled immediately on the first clock signal. This is accomplished by pre-loading (programming in real time by a user) a logical 1 into the selected start column by the use of circuitry in the shift register initializer <b>55</b> under the control signals of start column address load <b>61</b> (from a micro-controller or hard-wired logic). Subsequent columns are selected and read out by shifting this logical 1 to the right at each clock signal <b>56</b>. This clock signal is gated by the clock enable circuit (shown as an AND gate) <b>57</b>. The clock is allowed to effect the shifting of the logical 1 in the shift register at the start of each frame. The image sub-window size to be read out is controlled by the location of the last column. A shift register stop condition comparator circuit <b>58</b> which compares the location of the shift register logical one and the pre-determined location is used to disable the shift register clock by presenting a logical 0 in the window end signal <b>63</b> which is decoded from the command end column address load <b>62</b>.

[0020] The invention has been described with reference to a preferred embodiment. However, it will be appreciated that variations and modifications can be effected by a person of ordinary skill in the art without departing from the scope of the invention.

[0021] PARTS LIST:

[0022]<b>10</b> x-y addressable imager

[0023]<b>12</b> x-y addressable imager

[0024]<b>13</b> sub-window image

[0025]<b>15</b> row decoder

[0026]<b>17</b> column decoder

[0027]<b>19</b> column signal processing

[0028]<b>20</b> sensor

[0029]<b>23</b> shift register

[0030]<b>24</b> row address

[0031]<b>26</b> column address

[0032]<b>28</b> shift register

[0033]<b>29</b> column signal processing circuit

[0034]<b>30</b> alternate embodiment

[0035]<b>33</b> row serial shift register

[0036]<b>34</b> row (switch) enabling circuits

[0037]<b>36</b> column (switch) enabling circuits

[0038]<b>38</b> column serial shift register

[0039]<b>51</b> shift register

[0040]<b>52</b> x-y addressable imager

[0041]<b>53</b> row addressing circuit

[0042]<b>54</b> column signal processor

[0043]<b>55</b> shift register initializer

[0044]<b>56</b> clock signal

[0045]<b>57</b> clock enable circuit

[0046]<b>58</b> shift register stop condition comparator circuit

[0047]<b>60</b> light sensing output

[0048]<b>61</b> start column address load

[0049]<b>62</b> command end column address load

[0050]<b>63</b> window end signal