Imaging device

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-094745, filed on Mar. 29, 2002, the entire contents of which arc incorporated herein by reference.

BACKGROUND OF THE INVENTION

[0002] The present invention relates to an imaging device incorporating a boosting circuit for generating a boosted voltage.

[0003] Batteries are used as power supplies in imaging devices, such as digital cameras, that employ solid state imaging devices (CCD image sensors). A battery has a predetermined output voltage width. Thus, an imaging device is provided with a boosting circuit and a regulating circuit to drive the CCD image sensor.

[0004]FIG. 1 is a schematic block diagram of a prior art imaging device <b>50</b>. The imaging device <b>50</b> includes a CCD image sensor <b>1</b>, a boosting circuit <b>2</b>, a regulating circuit <b>3</b>, a vertical driver circuit <b>4</b>, a horizontal driver circuit <b>5</b>, and a timing control circuit <b>6</b>. In the imaging device <b>50</b>, the boosting circuit <b>2</b> is located at the input side of the vertical driver circuit <b>4</b>. The boosting circuit <b>2</b> boosts a power supply voltage, which is supplied from a battery, to a predetermined voltage to generate a boosted voltage. The boosted voltage drives the CCD image sensor <b>1</b>.

[0005] The CCD image sensor <b>1</b> has a light receiving section (plane), which includes a matrix of a plurality of light receiving pixels. Each light receiving pixel receives light at the light receiving plane and performs photoelectric conversion to generate information charges. The CCD image sensor <b>1</b> stores the information charges in the light receiving pixels and then sequentially transfers the information charges in accordance with clock signals from the vertical driver circuit <b>4</b> and the horizontal driver circuit <b>5</b>. An output section <b>1</b><i>d</i>, which is located at the final stage of the transfer route, converts the information charges to a voltage having a certain value to generate an image signal Y(t). There are different types of CCD imaging devices that transfer the information charges in different ways. For example, the CCD image sensor <b>1</b> is a frame transfer type CCD image sensor, which includes an imaging section <b>1</b><i>i</i>, a storage section <b>1</b><i>s</i>, a horizontal transfer section <b>1</b><i>h</i>, and an output section <b>1</b><i>d. </i>

[0006] The boosting circuit <b>2</b>, which is, for example a charge pump circuit, receives and boosts the power supply voltage VD, to generate a positive boosted voltage VOH (e.g., 5V) and a negative boosted voltage (e.g., 5V). The regulating circuit <b>3</b> receives the power supply voltage VD, generates a predetermined adjusted voltage (e.g., 2.0V to 2.5V) VK, and supplies the adjusted voltage VK to the horizontal driver circuit <b>5</b>.

[0007] The vertical driver circuit <b>4</b> receives the boosted voltage VOL from the boosting circuit <b>2</b> and generates a frame transfer clock signal Øf and a vertical transfer clock signal Øv. The frame transfer clock signal Øf is provided to the imaging section <b>1</b><i>i</i>, and the vertical transfer clock signal Øv is provided to the storage section <b>1</b><i>s</i>. The frame transfer clock signal Øf and the vertical transfer clock signal Øv are generated in synchronism with a vertical synchronization signal VD and a horizontal synchronization signal HD, which are generated by the timing control circuit <b>6</b>. This results in the information charges, which are stored in the imaging section <b>1</b><i>i</i>, simultaneously entering the storage section <b>1</b><i>s</i>. Further, the information charges in the storage section <b>1</b><i>s </i>are sequentially transferred to the horizontal transfer section <b>1</b><i>h </i>in units of single lines in synchronism with the horizontal synchronization signal HD.

[0008] The horizontal driver circuit <b>5</b> receives an adjusted voltage VK from the regulating circuit <b>3</b> and generates a horizontal transfer clock signal Øh and a reset clock signal Ør in accordance with the adjusted voltage VK. The horizontal transfer clock signal Øh is provided to the horizontal transfer section <b>1</b><i>h</i>, and the reset clock signal Ør is provided to the output section <b>1</b><i>d</i>. The horizontal transfer clock signal Øh and the reset clock signal Ør, which are generated in the horizontal driver circuit <b>5</b>, are generated in synchronism with the horizontal synchronization signal HD. This results in a single line of information charges stored in the horizontal transfer section <b>1</b><i>h </i>being transferred to the output section <b>1</b><i>d </i>in units of single pixels during a single cycle (<b>1</b>H) of the horizontal synchronization signal HD.

[0009] The timing control circuit <b>6</b> includes a plurality of counters for counting a reference clock signal CK, which has a constant cycle. The timing control circuit <b>6</b> divides the reference clock signal CK by a predetermined ratio to generate the vertical and horizontal synchronization signals VD and HD. Further, the timing control circuit <b>6</b> receives a start trigger ST, which determines the timing for starting operation of the imaging device <b>50</b> (imaging mode). In, for example, an imaging device incorporated in electronic equipment, the start trigger signal ST is set because there is a standby mode. In the standby mode, the supply of power to the imaging device <b>50</b> is cut when a camera function of the electronic equipment is not in use. This reduces the power consumption of the electronic equipment.

[0010] The timing control circuit <b>6</b> generates a boosting clock signal CKV in response to the start trigger signal ST and provides the boosting clock signal CKV to the boosting circuit <b>2</b>. Further, the timing control circuit <b>6</b> provides a boosting signal to the signal processing circuit (not shown), which performs a predetermined signal process on the output signal of the CCD image sensor <b>1</b>. In other words, the timing control circuit <b>6</b> synchronizes the operation of each circuit in the imaging device <b>50</b> with the operation timing of the CCD image sensor <b>1</b>.

[0011]FIG. 2 is a timing chart illustrating an operation of the boosting circuit <b>2</b> that prevents the boosting operation of the boosting circuit <b>2</b> from affecting the image signal Y(t). In FIG. 2, (H) represents a high level, and (L) represents a low level.

[0012] The start trigger signal ST is a signal for determining the timing for supplying power to the imaging device <b>50</b>. For example, the supply of power to the imaging device <b>50</b> is enabled when the start trigger signal ST is high and stopped when the start trigger signal ST is low. Accordingly, at timing t0 in FIG. 2, the electronic equipment exits the standby mode and starts the imaging operation.

[0013] The image signal Y(t) is the output signal of the CCD image sensor <b>1</b>. The image signal Y(t) is output when the horizontal synchronization signal HD is high. The output of the image signal Y(t) is stopped when the horizontal synchronization signal HD is low (blanking period). The image signal Y(t) corresponding to a single line is output during a single cycle of the horizontal synchronization signal HD. In FIG. 2, the image signal Y(t) corresponding to a single line is output in a single cycle of the horizontal synchronization signal HD at timings t1 to t2, t3 to t4, t5 to t6, and t7 to t9. The image signal Y(t) is output before the boosted voltage VOH reaches a predetermined voltage VH and invalidated by the signal processing circuit of the following stage during timings t1 to t2, t3 to t4, t5 to t6 and t7 to t9.

[0014] The boosting clock signal CKV, which is a clock signal for controlling the boosting operation of the boosting circuit <b>2</b>, is generated during the blanking period of the horizontal synchronization signal HD, that is, during timings t1 to t2, t3 to t4, t5 to t6, and t7 to t9. Accordingly, the boosting circuit <b>2</b>, which receives the boosting clock signal CKV, performs a boosting operation during the blanking period of the horizontal synchronization signal HD. The boosting operation is also performed during the blanking period of the horizontal synchronization signal HD for a negative output voltage VOL.

[0015] In, for example, Japanese Laid-Open Patent Publication No. 2001-218119, the applicant has disclosed the imaging device <b>50</b> that generates the boosting clock signal CKV during the blanking period of the horizontal synchronization signal HD or the vertical synchronization signal VD and prevents noise, which is produced by the boosting clock signal CKV, from mixing with the image signal Y(t).

[0016] However, the boosting operation of the boosting circuit <b>2</b> is performed intermittently in the imaging device <b>50</b>. Thus, the boosted voltage VOH increases gradually. As a result, a certain amount of time is required for the voltage supplied to a drive circuit to reach the desired voltage value. This interferes with increasing the activating speed of the imaging device.

SUMMARY OF THE INVENTION

[0017] One aspect of the present invention is an imaging device for performing an imaging operation to generate an image signal. The imaging device includes a boosting circuit for boosting an input voltage to generate a boosted voltage. A solid state imaging device is connected to the boosting circuit to receive the boosted voltage and generate the image signal. A clock signal generation unit is connected to the boosting circuit to determine a timing for generating the image signal in correspondence with a vertical synchronization signal and a horizontal synchronization signal and to generate a boosting clock signal for operating the boosting circuit. There is a blanking period for the vertical and horizontal synchronization signals. The clock signal generation unit continuously generates the boosting clock signal during a predetermined period after the imaging operation starts and after the predetermined period, generates the boosting clock signal during at least part of the blanking period of the vertical synchronization signal and the horizontal synchronization signal.

[0018] A further aspect of the present invention is an imaging device having a standby mode and an imaging mode. The imaging device includes a boosting circuit for boosting an input voltage to generate a boosted voltage. A solid state imaging device is connected to the boosting circuit to receive the boosted voltage and generate the image signal. A clock signal generation unit is connected to the boosting circuit to determine a timing for generating the image signal in correspondence with a vertical synchronization signal and a horizontal synchronization signal and to generate a boosting clock signal for operating the boosting circuit. There is a blanking period for the horizontal and vertical synchronization signals. The clock signal generation unit continuously generates the boosting clock signal during a predetermined period from when the standby mode is switched to the imaging mode and after the predetermined period, generates the boosting clock signal during at least part of the blanking period of the vertical synchronization signal and the horizontal synchronization signal.

[0019] A further aspect of the present invention is a method for controlling an imaging device that performs an imaging operation to generate an image signal. The imaging device includes a boosting circuit, which boosts an input voltage in accordance with a boosting clock signal to generate a boosted voltage, and a solid state imaging device, which receives the boosted voltage and generates the image signal in correspondence with a vertical synchronization signal and a horizontal synchronization signal. There is a blanking period for the vertical and horizontal synchronization signals. The method includes validating a start trigger signal to have the imaging device start the imaging operation, starting continuous generation of the boosting clock signal when the start trigger signal is validated, stopping the continuous generation of the boosting clock signal after a predetermined period from when the start trigger signal is validated, and after the predetermined period, generating the boosting clock signal during at least part of the blanking period of the vertical synchronization signal and the horizontal synchronization signal.

[0020] Other aspects and advantages of the present invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

P-0021[0021] The invention, together with objects and advantages thereof, may best be understood by reference to the following description of the presently preferred embodiments together with the accompanying drawings in which:

P-0022[0022]FIG. 1 is a schematic block diagram of an imaging device in the prior art;

P-0023[0023]FIG. 2 is a timing diagram illustrating the operation of the imaging device of FIG. 1;

P-0024[0024]FIG. 3 is a schematic block diagram of an imaging device according to a first embodiment of the present invention;

P-0025[0025]FIG. 4 is a timing diagram illustrating the operation of the imaging device of FIG. 3;

P-0026[0026]FIG. 5 is a schematic block diagram of an imaging device according to a second embodiment of the present invention; and

P-0027[0027]FIG. 6 is a timing diagram illustrating the operation of the imaging device of FIG. 5.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

P-0028[0028] In the drawings, like numerals are used for like elements throughout.

P-0029[0029]FIG. 3 is a schematic block diagram of an imaging device <b>100</b> according to a first embodiment of the present invention. The imaging device <b>100</b> includes a CCD image sensor <b>1</b>, a boosting circuit <b>2</b>, a regulating circuit <b>3</b>, a vertical driver circuit <b>4</b>, a horizontal driver circuit <b>5</b>, and a timing control unit <b>11</b>, which is a clock signal generation unit.

P-0030[0030] In the first embodiment, a feature of the imaging device <b>100</b> is in that the boosting circuit <b>2</b> is continuously provided with the boosting clock signal CKV when the imaging operation is started. Further, modes for generating the boosting clock signal CKV are switched when the output voltage (boosted voltage) of the boosting circuit <b>2</b> increases to the required value.

P-0031[0031] The timing control unit <b>11</b> includes a VD/HD generation circuit <b>12</b>, an FT generation circuit <b>13</b>, a VT/HT generation circuit <b>14</b>, a boosting clock signal generation circuit <b>15</b>, a counter <b>16</b>, and a control circuit <b>17</b>.

P-0032[0032] The VD/HD generation circuit <b>12</b> includes a plurality of counters for counting a reference clock signal CK, which has a constant cycle, and dividing the reference clock signal CK by a predetermined ratio to generate a vertical synchronization signal VD and a horizontal synchronization signal HD. The FT generation circuit <b>13</b> receives the vertical synchronization signal VD and generates a frame shift timing signal FT, which is in synchronism with the vertical synchronization signal VD. The frame shift timing signal FT is a trigger signal that determines the timing of a frame transfer clock signal Øf, which is generated by the vertical driver circuit <b>4</b>. The frame shift timing signal FT goes high during the blanking period of the vertical synchronization signal VD. Thus, clocking for the frame transfer clock signal Øf is performed during the blanking period of the vertical synchronization signal VD, and the information charges corresponding to a single image stored in an imaging section <b>1</b><i>i </i>are simultaneously transferred and output.

P-0033[0033] The VT/HT generation circuit <b>14</b> retrieves the vertical synchronization signal VD and the horizontal synchronization signal HD to generate a vertical transfer signal VD synchronized with the synchronization signal VD and a horizontal transfer timing signal HT synchronized with the synchronization signal HD. The vertical transfer timing signal VT is a trigger signal that determines the timing of a vertical transfer clock signal Øv, which is generated by the vertical driver circuit <b>4</b>. The vertical transfer timing signal VT goes high in synchronism with the frame shift timing signal FT and the horizontal synchronization signal HD. Thus, the information charges transferred from the imaging section <b>1</b><i>i </i>are acquired in a storage section <b>1</b><i>s</i>, and the acquired information charges are transferred to a horizontal transfer section <b>1</b><i>h </i>in units of single lines and in synchronism with the horizontal synchronization signal HD.

P-0034[0034] The horizontal timing signal HT is a trigger signal that determines the timing of a horizontal transfer clock signal Øh, which is generated by the horizontal driver circuit <b>5</b>. The horizontal transfer timing signal HT is generated in synchronism with the horizontal synchronization signal HD. Thus, the information charges stored in the horizontal transfer section <b>1</b><i>h </i>are sequentially transferred to an output section <b>1</b><i>d </i>in units of single pixels and in synchronism with the horizontal synchronization signal HD.

P-0035[0035] The boosting clock signal generation circuit <b>15</b> generates a boosting clock signal CKV in response to a start trigger signal ST, which is provided from an external device. The boosting clock signal CKV is a clock signal that controls the boosting operation of the boosting circuit <b>2</b> and is provided to the boosting circuit <b>2</b>. The boosting circuit <b>2</b> performs the boosting operation when the boosting clock signal CKV is generated. The counter <b>16</b> counts the boosting clock signal CKV from when the start trigger signal ST goes high to generate a count signal (count value) CA and provides the count value CA to the control circuit <b>17</b>.

P-0036[0036] The control circuit <b>17</b> compares the count value CA of the counter <b>16</b> with a predetermined target value. In accordance with the comparison result, the control circuit <b>17</b> generates a first control signal MC, which controls the mode for generating the boosting clock signal CKV, and provides the first control signal MC to the boosting clock signal generation circuit <b>15</b>. The control circuit <b>17</b> provides a second control signal NC, which controls the timing for starting the generation of each type of timing signal, to the FT generation circuit <b>13</b> and the VT/HT generation circuit <b>14</b>.

P-0037[0037] The operation of the imaging device <b>100</b> will now be discussed with reference to the timing chart of FIG. 4. At timing t0 in FIG. 4, the imaging device <b>100</b> is set in the standby mode and does not perform the imaging operation. At timing t1, the imaging device <b>100</b> exits the standby mode and starts the imaging operation (imaging mode). The boosting circuit <b>2</b> generates two types of boosted voltages, a positive voltage VOH and a negative voltage VOL. Only the positive boosted voltage VOH is shown in FIG. 4.

P-0038[0038] At timing t0 during which the imaging device <b>100</b> is set in the standby mode, the start trigger signal ST is low. In accordance with the low start trigger signal ST, the boosting clock signal CKV is also low and the boosted voltage VOH is equal to the ground voltage VG (e.g., 0V).

P-0039[0039] When the start trigger signal ST goes high at timing t1, the generation of the boosting clock signal CKV is started. Simultaneously with the generation of the boosting clock signal CKV, the counter <b>16</b> starts the counting operation. In accordance with the count operation, the first control signal MC goes high.

P-0040[0040] Then, when the count value CA reaches its target value at timing t3, the first control signal MC goes low. This temporarily stops the generation of the boosting clock signal CKV. The boosting clock signal generation circuit <b>15</b> continuously generates the boosting clock signal CKV from timing t1 in which the imaging operation is started to when the count value CA reaches the target value. Thus, the boosted voltage VOH increases immediately to a predetermined voltage VOH. The generation of the boosting clock signal CKV is temporarily stopped at timing t3 in which the boosted voltage VOH reaches voltage VH.

P-0041[0041] At timing t3, when the count value CA reaches the target value, the second control signal NC goes high. In the FT generation circuit <b>13</b> and the VT/HT generation circuit <b>14</b>, which receive the high second control signal NC, the output of each type of timing signal is enabled. Thus, the output of each timing signal is started subsequent to timing t3. In other words, when the boosted voltage VOH is increasing, the image signal Y(t) is not output, and the image signal Y(t) is output after the boosted voltage VOH increases to a sufficient level.

P-0042[0042] Subsequent to timing t3, the boosting clock signal CKV is generated during a horizontal scan blanking period, or only during timings t4 to t5, t6 to t7, and t8 to t9. Further, the image signal Y(t) is output during the period excluding the blanking period, that is, during a horizontal scan period. This prevents noise components, which result from the generation of the boosting clock signal CKV, from mixing with the image signal Y(t).

P-0043[0043] In the first embodiment, the boosting clock signal CKV is continuously generated for a predetermined period when the imaging operation is started. After the predetermined period elapses, the boosting clock signal CKV is generated only during the blanking period of the horizontal synchronization signal HD. This prevents deterioration of the image signal Y(t) while increasing the activating speed of the imaging device <b>100</b>. By positively performing the boosting operation of the boosting circuit <b>2</b> from timing t0 in which the imaging operation is started, the boosted voltage VOH goes high quickly. After the boosted voltage VOH stabilizes, boosting is performed only in the horizontal scan blanking period. This prevents noise components that are produced by the generation of the boosting clock signal CKV from mixing with the image signal Y(t).

P-0044[0044] Further, until the count value CA of the counter <b>16</b> reaches the target value, the output of timing signals from the FT generation circuit <b>13</b> and the VT/HT generation circuit <b>14</b> is stopped. This prevents unnecessary output of the image signal Y(t) and avoids unnecessary consumption of power by the vertical driver circuit <b>4</b> and the horizontal driver circuit <b>5</b>.

P-0045[0045] The target value compared with the count value may be changed when necessary. Thus, if the period for continuously generating the boosting clock signal CKV is long enough, a margin is provided for activation of the imaging device <b>100</b>. This provides a margin for the imaging device <b>100</b> to proceed from activation to the output of the image signal Y(t).

P-0046[0046]FIG. 5 is a schematic block diagram of an imaging device <b>200</b> according to a second embodiment of the present invention. The second embodiment differs from the first embodiment in that a comparator <b>22</b>, which compares the boosted voltage with a predetermined reference voltage, is used in lieu of the counter <b>16</b>. In the imaging device <b>200</b>, the mode for generating the boosting clock signal CKV is changed in accordance with the comparison result of the comparator <b>22</b>.

P-0047[0047] The imaging device, <b>200</b> includes a CCD image sensor <b>1</b>, a boosting circuit <b>2</b>, a regulating circuit <b>3</b>, a vertical driver circuit <b>4</b>, a horizontal driver circuit <b>5</b>, and a timing control unit (clock signal generation unit) <b>21</b>. The timing control unit <b>21</b> includes the comparator <b>22</b>, a control circuit <b>23</b>, a boosting clock signal generation circuit <b>15</b>, a VD/HD generation circuit <b>12</b>, an FT generation circuit <b>13</b>, and a VT/HT generation circuit <b>14</b>.

P-0048[0048] The comparator <b>22</b> compares a positive output voltage VOH and a negative output voltage VOL of the boosting circuit <b>2</b> with two predetermined reference voltages VRH and VRL to generate a comparison signal KA, which is provided to the control circuit <b>23</b>. The reference voltages VRH and VRL correspond to a positive voltage value VH and a negative voltage value VL that are respectively set in correspondence with the operational voltage at the vertical driver circuit <b>4</b> or the output section <b>1</b><i>d </i>of the CCD image sensor <b>1</b>. The reference voltage VRH is slightly higher than the positive voltage VH, and the reference voltage VRL is slightly lower than the negative voltage VL.

P-0049[0049] The control circuit <b>23</b> detects whether the boosted voltages VOH and VOL have reached the associated predetermined voltages VH and VL in accordance with the comparison signal KA from the comparator <b>22</b>. In accordance with the detection result, the control circuit <b>23</b> switches the mode for generating the boosting clock signal CKV of the boosting clock signal generation circuit <b>15</b> and switches the mode for outputting the timing signals of the FT generation circuit <b>13</b> and the VT/HT generation circuit <b>14</b>.

P-0050[0050]FIG. 6 is a timing diagram illustrating the operation of the imaging device <b>200</b>. At timing t0 in FIG. 6, the imaging device <b>200</b> is in the standby mode and does not perform the imaging operation. At timing t1, the imaging device <b>200</b> exits the standby mode and starts the imaging operation.

P-0051[0051] At timing t0, the start trigger signal ST and the boosting clock signal CKV are low. Further, the output voltage VOH of the boosting circuit <b>2</b> is equal to the ground voltage VG[V] (0V).

P-0052[0052] When the start trigger signal ST goes high at timing t1, the comparison signal KA goes high in response to the high start trigger signal ST. When the comparison signal KA goes high, the boosting clock signal CKV is continuously generated. Further, the boosted voltage VOH is quickly increased to the desired voltage VH in accordance with the boosting clock signal CKV.

P-0053[0053] Then, when the boosted voltage VOH reaches a reference voltage VRH, the comparison signal KA goes low. When the comparison signal KA goes low, the boosting clock signal CKV is intermittently oscillated. Further, in response to the comparison signal KA, the FT generation circuit <b>13</b> and the VT/HT generation circuit <b>14</b> start outputting timing signals.

P-0054[0054] Subsequent to timing t3, the boosting clock signal CKV is generated during the horizontal scan blanking period, or only during timings t4 to t5, t6 to t7, and t8 to t9. Further, the image signal Y(t) is output during the period excluding the blanking period, that is, during the horizontal scan period. This prevents noise components, which result from the generation of the boosting clock signal CKV, from mixing with the image signal Y(t).

P-0055[0055] In the second embodiment, the timing control unit <b>21</b> compares the boosted voltage VOH with the reference voltage VRH and switches the mode for generating the boosting clock signal CKV in accordance with the comparison result. Thus, the second embodiment has the same advantages as the first embodiment.

P-0056[0056] In the second embodiment, the boosting operation of the boosting circuit <b>2</b> is positively performed from timing t1. After the boosted voltages VOH and VOL stabilize, boosting is performed only in the blanking period. This quickly increases the boosted voltage and prevents deterioration of the image signal.

P-0057[0057] In the second embodiment, the timing at which the positive boosted voltage VOH reaches the reference voltage VRH may differ from the timing at which the negative boosted voltage VOL reaches the reference voltage VOL. In such a case, the comparison signal KA goes low when the two boosted voltages VOH and VOL both reach the associated reference voltages VRH and VRL.

P-0058[0058] It should be apparent to those skilled in the art that the present invention may be embodied in many other specific forms without departing from the spirit or scope of the invention. Particularly, it should be understood that the present invention may be embodied in the following forms.

P-0059[0059] The boosting clock signal CKV may be generated during the blanking period of the vertical synchronization signal VD.

P-0060[0060] The CCD image sensor <b>1</b> may be any type of sensor as long as an image signal is generated with the boosted voltage of a boosting circuit.

P-0061[0061] The present examples and embodiments are to be considered as illustrative arid not restrictive, and the invention is not to be limited to the details given herein, but may be modified within the scope and equivalence of the appended claims.