High voltage lateral DMOS transistor having low on-resistance and high breakdown voltage

REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority of Korean patent application Serial No. 01-20168, filed Apr. 16, 2001.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to a power semiconductor device, and more particularly, to a high voltage lateral Double diffused Metal Oxide Semiconductor (DMOS) transistor having low on-resistance and high breakdown voltage.

[0004] 2. Description of the Related Art

[0005] Integrated circuits in which a control function and a driver function are combined are usually referred to as smart power devices. Such a smart power device has a lateral DMOS transistor at its output terminal which is designed to usually operate with high voltage. In such a high voltage lateral DMOS transistor, breakdown voltage is critical in terms of the stability of a device, and on-resistance is critical in terms of the operational characteristics of the device. In order to decrease the on-resistance of the device, the doping concentration within a drift region between a drain region and a channel region should be increased. However, in this case, the drift region is not completely depleted resulting in a decrease in breakdown voltage. To overcome this problem, recently, lateral DMOS transistors employing a double Reduced Surface Field (RESURF) structure have been developed. A lateral DMOS transistor employing the double RESURF structure is disclosed in U.S. Pat. No. 6,087,232.

[0006]FIG. 1 is a layout diagram of an example of a conventional high voltage lateral DMOS transistor employing the double RESURF structure. FIG. 2 is a cross-section of the high voltage lateral DMOS transistor of FIG. 1, taken along the line II-II.

[0007] Referring to FIGS. 1 and 2, a p⁻ well region <b>11</b> and an n-well region <b>12</b> are formed in the upper portion of a p-type semiconductor substrate <b>10</b>. A p-body region <b>13</b> having a channel region on its surface and a deep p⁺ region <b>14</b> surrounded by the p-body region <b>13</b> are formed in the upper portion of the p⁻ well region <b>11</b>. An n⁺ source region <b>15</b> and a p⁺ contact region <b>16</b> surrounded by the n-source region <b>15</b> are formed in the upper portion of the p-body region <b>13</b> including its surface. The channel region is formed in the upper portion of the p-body region <b>13</b>, that is, between the n⁺ source region <b>15</b> and the n-well region <b>12</b>. A p-top region <b>17</b> and an n⁺ drain region <b>18</b> are formed in the upper portion of the n-well region <b>12</b> at a predetermined distance from each other.

[0008] A gate insulation layer <b>19</b> and a gate electrode <b>20</b> are sequentially formed on the channel region of the p-body region <b>13</b>. The n⁺ source region <b>15</b> and the p⁺ contact region <b>16</b> are electrically connected to a source electrode <b>21</b>. The n⁺ drain region <b>18</b> is electrically connected to a drain electrode <b>22</b>. The gate electrode <b>20</b>, the source electrode <b>21</b> and the drain electrode <b>22</b> are insulated from one another by an interlayer insulation layer <b>23</b>. Reference numeral <b>24</b> denotes an isolation layer.

[0009] In such a lateral DMOS transistor, when a bias voltage is applied to the n⁺ drain region <b>18</b>, a reverse bias voltage is applied to a first junction J₁between the semiconductor substrate <b>10</b> and the n-well region <b>12</b>, and to a second junction J₂between the p-top region <b>17</b> and the n-well region <b>12</b>. Here, a depletion region is vertically formed around the first and second junctions J₁and J₂. Particularly, since a depletion region in the n-well region <b>12</b> is formed out of not only the first junction J₁but also the second junction J₂, the n-well region <b>12</b> is completely depleted. When the n-well region <b>12</b> is completely depleted, a surface electric field is uniformly formed between the n⁺ source region <b>15</b> and the n⁺ drain region <b>18</b> so that the breakdown voltage of the device increases.

[0010] However, the on-resistance of the device may increase due to the p-top region <b>17</b>. In addition, an area, in which carriers move, between the n˜ source region <b>15</b> and the n⁺ drain region <b>18</b> is reduced so that the current carrying performance of the device is reduced.

SUMMARY OF THE INVENTION

[0011] To solve the above problems, it is an object of the present invention to provide a high voltage lateral Double diffused Metal Oxide Semiconductor (DMOS) transistor having low on-resistance and high breakdown voltage without reducing current carrying performance between a source and a drain.

[0012] Accordingly, to achieve the above object of the invention, there is provided a high voltage lateral DMOS transistor including a semiconductor substrate of a first conductivity type. A gate electrode is partially formed on the semiconductor substrate to be insulated from the semiconductor substrate. A body region of the first conductivity type with a channel region overlapping with the gate electrode is formed in a first area of the semiconductor substrate. A source region of a second conductivity type is formed within the body region. A drift region of the second conductivity type is formed in a second area of the semiconductor substrate adjacent to the channel region. A drain region of the second conductivity type is formed within the drift region. Pluralities of well regions of the first conductivity type are formed to be horizontally spaced out within the drift region.

[0013] Preferably, each of the well regions of the first conductivity type has the shape of a column, the top surfaces of the well regions and the top surface of the drift region are on the same plane, and the bottom surfaces of the well regions and the bottom surface of the drift region are on the same plane. Preferably, each of the top and bottom surfaces of each well region of the first conductivity type having the shape of a column has a circular shape. Preferably, the well regions of the first conductivity type are disposed between the channel region and the drain region. Preferably, the high voltage lateral DMOS transistor further includes a source electrode electrically connected to the source region, and a drain electrode electrically connected to the drain region. Preferably, the first conductivity type is a p-type, and the second conductivity type is an n-type. Alternatively, the first conductivity type may be an n-type, and the second conductivity type may be a p-type.

BRIEF DESCRIPTION OF THE DRAWINGS

P-0014[0014] The above objective and advantages of the present invention will become more apparent by describing in detail a preferred embodiment thereof with reference to the attached drawings in which:

P-0015[0015]FIG. 1 is a layout diagram of an example of a conventional high voltage lateral Double diffused Metal Oxide Semiconductor (DMOS) transistor employing a double Reduced Surface Field (RESURF) structure;

P-0016[0016]FIG. 2 is a cross-section of the high voltage lateral DMOS transistor of FIG. 1, taken along the line <b>11</b>-<b>11</b>′;

P-0017[0017]FIG. 3 is a layout diagram of a high voltage lateral DMOS transistor according to the present invention;

P-0018[0018]FIG. 4 is a cross-section of the high voltage lateral DMOS transistor of FIG. 3, taken along the line IV-W′; and

P-0019[0019]FIG. 5 is a cross-section of the high voltage lateral DMOS transistor of FIG. 3, taken along the line V-V′.

DETAILED DESCRIPTION OF THE PRESENT INVENTION

P-0020[0020] Hereinafter, an embodiment of the present invention will be described in detail with reference to the attached drawings. The present invention is not restricted to the following embodiment, and many variations are possible within the sprit and scope of the present invention. The embodiment of the present invention is provided in order to more completely explain the present invention to anyone skilled in the art. For example, n-type regions may be p-type regions, and vice versa. In the drawings, the thicknesses of layers or regions are exaggerated for clarity and the same reference numerals denote the same members.

P-0021[0021] Referring to FIGS. 3 through 5, a p⁻well region <b>110</b> and an n⁻ well region <b>120</b> are formed in the upper portion of a p-type semiconductor substrate <b>100</b>. The p-well region <b>110</b> may be omitted. The n⁻ well region <b>120</b> is used as a drift region. A p-body region <b>130</b> having a channel region <b>135</b> on its surface and a deep p⁺ body region <b>140</b> surrounded by the p-body region <b>130</b> are formed in the upper portion of the p⁻ well region <b>110</b>. An n⁺ source region <b>150</b> and a p⁺ contact region <b>160</b> surrounded by the n⁺ source region <b>150</b> are formed in the upper portion of the pbody region <b>130</b> including its surface. The channel region <b>135</b> is formed in the upper portion of the p-body region <b>130</b>, that is, between the n⁺ source region <b>150</b> and the n-well region <b>120</b>.

P-0022[0022] A plurality of p-well regions <b>170</b> and an n⁺ drain region <b>180</b> are formed within the n-well region <b>120</b>. The p-well regions <b>170</b> are horizontally spaced out between the channel region <b>135</b> within the p-body region <b>130</b> and the n⁺ drain region <b>180</b>. As seen from a plan view shown in FIG. 3 and a cross-section shown in FIG. 5, each p-well region <b>170</b> is shaped like a column. The top surfaces of the p-well regions <b>170</b> and the top surface of the n-well region <b>120</b> are on the same horizontal plane, and the bottom surfaces of the p-well regions <b>170</b> and the bottom surface of the n-well region <b>120</b> are on the same horizontal plane. The top and bottom surfaces of each p-well region <b>170</b> have a circular shape. It is apparent that each p-well region <b>170</b> may be formed to have polygon-shaped top and bottom surfaces. However, the circular shape is most preferable in order to suppress concentration of an electric field on each comer.

P-0023[0023] A gate insulation layer <b>190</b> and a gate electrode <b>200</b> are sequentially formed on the channel region <b>135</b> in the p-body region <b>130</b>. The n⁺ source region <b>150</b> and the p⁺ contact region <b>160</b> are electrically connected to a source electrode <b>210</b>. The n⁺ drain region <b>180</b> is electrically connected to a drain electrode <b>220</b>. The gate electrode <b>200</b>, the source electrode <b>210</b> and the drain electrode <b>220</b> are insulated from one another by an interlayer insulation layer <b>230</b>. Reference numeral <b>240</b> denotes an isolation layer formed by LOCal Oxidation of Silicon (LOCOS).

P-0024[0024] Only the n-well region <b>120</b> appears in some portions of the n-well region <b>120</b>, i.e., the drift region of the high voltage lateral Double diffused Metal Oxide Semiconductor (DMOS) transistor, between the channel region <b>135</b> and the n⁺ drain region <b>180</b>, as shown in FIG. 4, while the n-well region <b>120</b> and the p-well regions <b>170</b> alternately appear in other portions thereof, as shown in FIG. 5. Current carrying performance within the drift region, i.e., the n-well region <b>120</b>, is not reduced due to this structure although a double REduced SURface Field (RESURF) structure is applied. In other words, only the n-well region <b>120</b> exists in some portions between the channel region <b>135</b> and the n⁺ drain region <b>180</b>, and most current is carried through these portions. Accordingly, a problem of reduction of current carrying performance within a drift region due to existence of the p-well regions <b>170</b> does not occur. In addition, high breakdown voltage and low on resistance can be accomplished by using the principle of the double RESURF structure. In other words, when a bias voltage is applied to the n⁺ drain region <b>180</b>, a depletion region is horizontally formed around the junction between each p-well region <b>170</b> and the n-well region <b>120</b>. Simultaneously, a depletion region is vertically formed around the junction between the semiconductor substrate <b>100</b> and the n-well region <b>120</b>. Accordingly, the n-well region <b>120</b> can be completely depleted. Therefore, a surface electric field is uniformly formed between the n˜ source region <b>150</b> and the n⁺ drain region <b>180</b> so that the breakdown voltage of the device increases. In addition, since the n-well region <b>120</b> is depleted both horizontally and vertically, the breakdown characteristic of the device is not degraded even if the impurity concentration of the n-well region <b>120</b> is sufficiently increased to obtain desirable on-resistance. Accordingly, the operational characteristic of the device can be improved by decreasing the on-resistance by increasing the impurity concentration.

P-0025[0025] Stated another way, the invention provides a plurality of depletion wells <b>170</b> disposed in the drift region<b>120</b>. The depletion wells <b>170</b> are doped with the first conductivity type (p⁻ type) for depleting the drift region <b>120</b> in transverse directions. The depletion wells extend from the insulated layer <b>240</b> toward the opposite surface of the semiconductor substrate and terminate on the lower boundary of the drift region <b>120</b>. The wells <b>170</b> have a column-like shape, including a circular cross section to define cylindrical columns. The opposite ends of the columns terminate on the opposite boundaries of the drift region.

P-0026[0026] As described above, according to the present invention, a plurality of p-well regions are formed to be spaced out within the n-well region between a channel region and a drain region so that the breakdown voltage of a device can be increased and the on-resistance of the device can be decreased. In addition, current carrying performance within the n-well region can be improved.