Method and system for dynamically operating memory in a power-saving error correction mode

TECHNICAL FIELD

[0001] The invention relates to memory devices, and, more particularly, to a method and system for allowing a memory to operate in a manner that corrects data errors that may be generated by operating the memory in a mode that consumes relatively little power.

BACKGROUND OF THE INVENTION

[0002] Substantially all modem computers and other digital systems rely on semiconductor memory devices to store data and instructions for processing by a central processing unit (CPU). Most of these systems have a system memory, which usually consists of dynamic random access memory (“DRAM”) devices. The memory storage cost/bit of DRAM devices is relatively low because a DRAM memory cell needs relatively few circuit components to store a data bit as compared with other types of memory cells, such as static random access memory (“SRAM”) devices. Thus, a high capacity system memory can be implemented using DRAM devices for a relatively low cost.

[0003] Although DRAM devices have the advantage of providing relatively low-cost data storage, they also have the disadvantage of significantly consuming power, In fact, DRAM devices used in a digital system, such as a computer, can consume a significant percentage of the total power consumed by the system. The power consumed by computers and other digital systems can be a critical factor in their utility in certain applications. For example, the power consumed by portable personal computers greatly affects the length of time they can be used without the need to recharge batteries powering such computers. Power consumption can also be important even where memory devices are not powered by batteries because it may be necessary to limit the heat generated by the memory devices.

[0004] One operation that tends to consume power at a substantial rate is refreshing memory cells in a DRAM device. As is well-known in the art, DRAM memory cells, each of which essentially consists of a capacitor, must be periodically refreshed to retain data stored in the DRAM device. Refresh is typically performed by activating each row of memory cells in an array, which essentially reads data bits from the memory cells in each row and then internally writes those same data bits back to the same cells in the row. This refresh is generally performed at a rate needed to keep charge stored in the memory cells from leaking excessively between refreshes. Since refresh involves accessing data bits in a large number of memory cells at a rapid rate, refresh tends to be a particularly power-hungry operation. Thus many attempts to reduce power consumption in DRAM devices have focused on reducing the rate at which power is consumed during refresh.

[0005] The amount of power consumed by refresh also depends on which of several refresh modes is active. A self-refresh mode is normally active during periods when data are not being read from or written to the DRAM device. Since many electronic devices, such as notebook computers, are often inactive for substantial periods of time, the amount of power consumed during self-refresh can be an important factor in determining how long the electronic device can be used after a battery charge. While power is also consumed at a significant rate during other refresh modes when the DRAM device is active, the DRAM device is consuming power at a significant rate anyway while the data stored therein are being accessed. Therefore, if the power consumption during self-refresh can be reduced, the rate of power consumption during refresh can be significantly reduced.

[0006] One technique that has been used to reduce the amount of power consumed by refreshing DRAM memory cells varies the refresh rate as a function of temperature. As is well known in the art, the rate at which charge leaks from a DRAM memory cell increases with temperature. The refresh rate must be sufficiently high to ensure that no data is lost at the highest temperature in the specified range of operating temperatures of the DRAM device. Yet, DRAM devices normally operate at temperatures that are substantially lower than their maximum operating temperature. Therefore, DRAM devices are generally refreshed at a rate that is higher than the rate actually need to prevent data from being lost, and, in doing so, unnecessarily consume power. To address this problem, some commercially available DRAM devices allow the user to program a mode register to select a lower maximum operating temperature. The DRAM device then adjusts the refresh rate to correspond to the maximum operating temperature selected by the user. Although adjusting the refresh rate to correspond to a lower maximum operating temperature does reduce the rate of power consumed during refresh, it nevertheless still allows power to be consumed at a significant rate. If the refresh rate was reduced beyond a safe limit, at least some of the memory cells might not be refreshed before that data stored therein was lost. Data subsequently read from the DRAM device would then contain erroneous data bits.

[0007] There is therefore a need for a method and system that reduces the power consumed by a DRAM device during refresh in at least some operating modes without risking a loss of data stored in the DRAM device.

SUMMARY OF THE INVENTION

[0008] A method and system for storing data in a dynamic random access memory (“DRAM”) device in either a normal operating mode when the DRAM device is active or a power-saving mode when the DRAM device is inactive. In the normal operating mode, data may be read from or written to the DRAM device, and memory cells in the DRAM device are refreshed at a first rate that is sufficiently high to prevent any data errors from being generated. In the power-saving mode, the memory cells in the DRAM device are scrubbed at a second rate that is substantially less than the first rate. The second rate may be sufficiently low that data errors are generated, but error correction techniques used in the memory scrubbing procedure correct any errors that are generated. The relatively low scrubbing rate inherently refreshes the memory cells at a sufficiently low rate that substantially less power is consumed compared to refresh in the normal operating mode.

BRIEF DESCRIPTION OF THE DRAWINGS

P-0009[0009]FIG. 1 is a block diagram of a computer system according to an embodiment of the invention.

P-0010[0010]FIG. 2 is a block diagram of a scrubbing controller used in the computer system of FIG. 1.

P-0011[0011]FIG. 3 is a flow chart showing the operation of a computer system using a scrubbing controller according to one embodiment of the invention.

P-0012[0012]FIG. 4 is a flow chart showing the manner of setting a scrub rate according to one embodiment of the invention.

P-0013[0013]FIG. 5 is a flow chart showing the manner of setting a scrub rate according to another embodiment of the invention.

P-0014[0014]FIG. 6 is a flow chart showing the operation of a computer system using a scrubbing controller according to another embodiment of the invention.

P-0015[0015]FIG. 7 is a block diagram of a DRAM device containing a scrubbing controller according to one embodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION

P-0016[0016] One embodiment of a computer system <b>10</b> containing a DRAM device <b>12</b> that uses relatively little refresh power in at least some operating modes is shown in FIG. 1. The computer system <b>10</b> includes a central processing unit (“CPU”) <b>14</b> for performing various computing functions, such as executing software to perform specific calculations or tasks. The CPU <b>14</b> includes a processor bus <b>16</b> that normally includes an address bus, a control bus, and a data bus. The CPU <b>14</b> is also coupled through a system controller <b>20</b> to system memory implemented using the DRAM device <b>12</b>. The system controller <b>20</b> includes a control bus <b>24</b>, an address bus <b>26</b> and a data bus <b>28</b>, all of which are coupled to the DRAM device <b>12</b> in a conventional manner. However, the system controller <b>20</b> also includes an additional data bus, which will be referred to as a check bit bus <b>30</b>. The system controller <b>20</b> also includes a memory controller <b>34</b> for controlling the operation of the DRAM device <b>12</b> and a scrubbing controller <b>38</b>, the function of which will be explained below.

P-0017[0017] The computer system <b>10</b> also includes a conventional Peripheral Interface and Power Management Module <b>40</b> coupled to the system controller <b>20</b> through a peripheral bus <b>44</b>. The Peripheral Interface and Power Management Module <b>40</b> is coupled to a conventional Power Regulation and Control circuit <b>46</b> thorough signals lines <b>48</b>. The system controller <b>20</b> may also be coupled to a video device (not shown) through a graphics bus <b>50</b>.

P-0018[0018] As is well known in the art, the Peripheral Interface and Power Management Module <b>40</b> couples the CPU <b>14</b> through the system controller <b>20</b> to various peripheral devices (not shown), including an input device such as a keyboard or a mouse, an output device such as a printer, and a data storage device such as a hard disk or a floppy disk. The Peripheral Interface and Power Management Module <b>40</b> also couples the CPU <b>14</b> to the Power Regulation and Control circuit <b>46</b>, The Power Regulation and Control circuit <b>46</b> generates various signals on respective signals lines <b>52</b> for controlling the power consumed by the computer system <b>10</b>.

P-0019[0019] As explained in greater detail below, the DRAM device <b>12</b> uses the scrubbing controller <b>32</b> to operate in either of two modes. When the DRAM device <b>12</b> is active, it operates in a normal mode in which it refreshes the memory cells in an array either periodically or in response to refresh commands. In this normal mode, the DRAM device <b>12</b> consumes a relatively large amount of power. When the DRAM device <b>12</b> is inactive, it operates in a power-saving mode in which it essentially refreshes the DRAM memory cells at a rate that is sufficiently low that data bits may be lost from memory cells in the array. However, in this power-saving mode, the DRAM device <b>12</b> performs a “memory scrubbing” process in which data are stored in the DRAM device <b>12</b> in a conventional error correcting code (“ECC”) format. The data are then periodically read from the DRAM device <b>12</b>, and, if any errors have developed, corrected data are written to the DRAM device <b>12</b> in ECC format. More specifically, when transitioning to the power-saving mode, the data are read from the DRAM device <b>12</b>, and check bits are derived from the read data in a conventional manner. As is known in the art, the number of check bits generated will depend on the number of data bits, the number of errors that are to be correctable, and whether an additional bit will be used to detect an additional error that cannot be corrected. The check bits and data bits, which together constitute an ECC, are then stored in the DRAM device <b>12</b>.

P-0020[0020] Thereafter, in the memory scrubbing procedure, the ECC is read from the DRAM device <b>12</b>, and check bits are derived from the data portion of the read ECC in the same manner that the check bits stored in the DRAM device <b>12</b> were derived. The derived check bits are then compared to the check bits in the read ECC to generate a syndrome. The syndrome indicates whether any of the bits of the read ECC are in error, and, if so, the location of the bit error(s). The information provided by the syndrome is used to correct the bit(s), and a corrected ECC is then written to the DRAM device <b>12</b> device. By periodically correcting “soft” errors in the DRAM device, the memory cells in the DRAM device <b>12</b> can be refreshed at a rate that is sufficiently low that may allow some data storage errors to be developed, thereby substantially reducing the power consumption of the DRAM device <b>12</b>.

P-0021[0021] The memory scrubbing process inherently refreshes the memory cells because it requires that data be read from the memory array. However, the rate at which the memory scrubbing occurs can be relatively low since any errors that are created by the low refresh rate can be corrected. As a result, the power consumption of the DRAM device <b>12</b> is substantially reduced during refresh.

P-0022[0022] The above-described error correcting procedure is performed using conventional algorithms that have been used in memory devices where refresh occurs at the normal rate but absolute reliability of data storage is required. Conventional DRAM devices have used ECC even though the error rate of DRAM devices is relatively small, since data errors can occur even when there are no “hard” errors resulting from inoperative memory cells. Such “soft” errors can be caused by, for example, stray alpha particles, power supply fluctuations, noise, or by a variety of other conditions. Typical approaches to checking and correcting memory errors rely upon some form of error correction code that are typically generated by a mathematical algorithm that is applied to the data to be checked and corrected. Any of these conventional error correcting processes may be used in the memory scrubbing process.

P-0023[0023] The system may also include a temperature sensor <b>56</b> for use by some embodiments of the invention to control the scrub rate during the power-saving mode. As is known in the art, the rate at which charge leaks from DRAM memory cells increases with temperature. By using the temperature sensor <b>56</b>, the rate at which the scrubbing process is performed can be increased with increasing ambient temperature and decreased with decreasing ambient temperature to provide optimum power saving without permitting excessive data errors.

P-0024[0024] One embodiment of the scrubbing controller <b>38</b> is shown in FIG. 2. The scrubbing controller <b>38</b> includes a Memory Control State Machine <b>60</b> that is coupled to the control bus <b>24</b> of the DRAM device <b>12</b> (FIG. 1). The Memory Control State Machine <b>60</b> receives a periodic clock signal on the line <b>62</b> as well as “Done” and “Error” control signals from components that will be described. The State Machine generates conventional signals for controlling the operation of the DRAM device <b>12</b> to read data from and write data to the DRAM device <b>12</b>.

P-0025[0025] The location in the DRAM device <b>12</b> from which the data are read and to which the data are written responsive to these control signals is determined by an address generated by an SC Counter/Comparator <b>66</b> that is coupled to the DRAM device <b>12</b> through the address bus <b>26</b>. The SC counter/comparator <b>66</b> receives data “MemSize” indicative of the data capacity of the DRAM device <b>12</b> from another component in the computer system <b>10</b>, such as the CPU <b>14</b> (FIG. 1). The address generated by the SC Counter/Comparator <b>66</b> is incremented by an SC Incr pulse that is also generated by another component in the computer system <b>10</b>, such as the CPU <b>14</b>.

P-0026[0026] The data bus <b>28</b> of the DRAM device <b>12</b> is coupled to an input of a data input register <b>70</b> and to an output from a data output register <b>72</b>. Similarly, the check bit bus <b>30</b> is coupled to an input of a check bit input register <b>76</b> and to an output from a check bit output register <b>78</b>. Outputs from the data input register <b>78</b> and the check bit input register <b>76</b> are coupled to inputs of an ECC Generator Checker <b>80</b>, and outputs from the ECC Generator Checker <b>80</b> are applied to inputs of the check bit output register <b>78</b> and the data output register <b>72</b>.

P-0027[0027] In operation, after the start of a memory scrubbing procedure, the state machine <b>60</b> generates control signals, and the SC Counter/Comparator <b>66</b> generates an address, to read data and an associated check bits from the DRAM device <b>12</b>. The data and check bits are coupled through input registers <b>70</b>, <b>76</b>, respectively, to the ECC Generator Checker <b>80</b>, which performs a conventional ECC algorithm to determine if there are any errors in the data or check bits. If so, the ECC Generator Checker <b>80</b> generates corrected data and/or check bits in a conventional manner, which are coupled through output register <b>72</b>, <b>78</b>, respectively, for storage in the DRAM device <b>12</b>. When the ECC Generator Checker <b>80</b> detects an error, it generates an “Error” signal that is applied to the Memory Control State Machine <b>60</b>. In response, the State Machine <b>60</b> generates appropriate control signals to cause the DRAM device <b>12</b> to store the corrected data and check bits, preferably at the same location from which the data and check bits were read. The SC Counter/Comparator <b>66</b> is then incremented to cause the data and check bits stored at the next memory location to be analyzed. This process is repeated until the data and check bits stored in all memory locations have been analyzed and, if necessary, corrected. The SC Counter/Comparator <b>66</b> then generates a “Done” signal, which is applied to the Memory Control State Machine <b>60</b> so that the State Machine <b>38</b> can terminate the memory scrubbing process.

P-0028[0028] After the memory scrubbing process has been completed, the scrubbing controller <b>38</b> remains inactive until the scrubbing process is to be repeated. For this purpose, a scrub refresh counter (“SRC”) <b>90</b> is loaded with a time constant “Tconst” from a Tconst Register <b>94</b> at the end of the prior scrubbing process responsive to a “Load” pulse applied to the SRC <b>90</b>. The SRC <b>90</b> is then periodically decremented by successive SRC Decr pulses generated by another component in the computer system <b>10</b>, such as the CPU <b>14</b>. When the count of the SRC <b>90</b> reaches zero, the SRC <b>90</b> generates a “Zero” pulse, which indicates that the time period from the prior scrubbing procedure has lapsed and a new scrubbing procedure must be performed. The “Zero” pulse may be applied to, for example, an interrupt port the CPU <b>14</b> to allow the CPU <b>14</b> to initiate the memory scrubbing procedure.

P-0029[0029] In one embodiment of the invention, the value of the time constant Tconst may be incremented responsive to Tconst Incr pulses applied to the register <b>94</b> and decremented responsive to Tconst Decr pulses applied to the register <b>94</b>. As a result, the value of the time constant Tconst may be adapted to operational parameters, such as the number of errors found during the scrubbing process or the temperature of the DRAM device <b>12</b>.

P-0030[0030] The operation of the computer system <b>10</b> using the scrubbing controller <b>38</b> according to one embodiment of the invention will now be explained with reference to the flow chart shown in FIG. 3. The process is entered at step <b>100</b> and proceeds to step <b>102</b> wherein the SC Counter/Comparator <b>66</b> (FIG. 2) is reset and an Error Flag is set “False.” The “Load” pulse is then generated at step <b>104</b> to load the time constant Tconst stored in the register <b>94</b> into the SRC <b>90</b>. The process then remains in a loop in which the count in the SRC <b>90</b> is periodically decremented at step <b>108</b> and the value of the count in the SRC <b>90</b> is checked at <b>110</b>. When the count has reached zero, the SRC <b>90</b> generates the “Zero” signal, and the memory scrubbing process begins.

P-0031[0031] As explained above, the State Machine <b>60</b> generates appropriate control signals to read data and the associated check bits from a memory location at step <b>114</b>. The ECC Generator Checker <b>80</b> then generates check bits in a conventional manner from the read data at step <b>118</b>. A syndrome is generated at step <b>120</b> by comparing the generated check bits to the check bits read from memory, and a determination is made from the Syndrome whether the read ECC is correct. The syndrome may indicate that no errors exist in the data or check bits of the ECC read from the DRAM device <b>12</b>. If, however, the syndrome indicates that an error exists in the read data or check bits, the ECC Generator Checker corrects the read data and/or check bits, and the State Machine <b>60</b> generates appropriate control signals at step <b>124</b> to write the corrected data and/or check bits to the DRAM device <b>12</b> at step <b>124</b>, as previously explained. An ErrorFlag is then set True at step <b>128</b>.

P-0032[0032] After data and the associated check bits are read from the DRAM device <b>12</b> and, if necessary, corrected data and check bits are stored in the DRAM device <b>12</b>, the scrub count value SC indicative of the current memory location is incremented at step <b>130</b>. The incremented value SC is then compared to the capacity of the DRAM device <b>12</b> at step <b>134</b> to determine if all of the memory locations in the DRAM device <b>12</b> have been scrubbed. The capacity of the DRAM device <b>12</b> is indicated by the MemSize data applied to the SC Counter/Comparator <b>66</b>, as previously explained. If all of the memory locations have not been scrubbed, the process returns to step <b>114</b> to scrub the next memory location in the DRAM device <b>12</b>. If all the memory locations have been scrubbed, a check is made at step <b>138</b> to determine if the DRAM device <b>12</b> has been transitioned out of the inactive, power-saving mode. If so, the process exits at <b>140</b>. Otherwise, the process returns to step <b>102</b> to wait until the next scrubbing process should be initiated, as previously explained.

P-0033[0033] The value of the time constant Tconst stored in the register <b>94</b> (FIG. 2) may be a value that does not change under any circumstances. However, as previously mentioned, the value of the time constant Tconst may alternatively be adapted to the operation of the DRAM device <b>12</b>. For example, a time constant adjusting process <b>150</b> shown at FIG. 4 may be used to vary the rate at which the scrubbing procedure is initiated to permit a desired level of memory errors. The process <b>150</b> may be performed just upstream from the “Continue Scrubbing?” step <b>138</b> shown in FIG. 3. Accordingly, the Error Flag is checked at <b>152</b> after a determination was made at step <b>134</b> (FIG. 3) that the entire memory array had been scrubbed. It will be recalled that the Error Flag was reset False at step <b>102</b> and, in the event a memory error was detected at step <b>120</b>, was set True at step <b>128</b>. Thus, if any memory error was detected during the scrubbing process, the Error Flag will be True, thereby causing the time constant Tconst to be decremented at step <b>154</b>. The reduced value of the time constant Tconst will cause a reduction in the time delay until the next memory scrubbing procedure is performed. The process then proceeds to step <b>138</b> to determine if memory scrubbing should continue, as previously explained.

P-0034[0034] If no memory error is detected at <b>152</b>, a determination is made at <b>156</b> whether the maximum value of the time constant has been reached. If not, the time constant Tconst is incremented at <b>158</b> before a determination is made at <b>138</b> whether memory scrubbing should continue. If the maximum value of the time constant has been reached, the process reaches step <b>138</b> without any increase in the value of the time constant. If the time constant adjusting process <b>150</b> shown in FIG. 4 is not used, then the step <b>102</b> of setting the Error Flag False and the step <b>128</b> of setting the Error Flag True may be eliminated.

P-0035[0035] The time constant adjusting process <b>150</b> adjust the value of the time constant Tconst so that the number of memory errors detected and corrected each scrubbing procedure will generally be either zero or one error. However, the process <b>150</b> can be easily adapted to set the time constant Tconst so that any desired number of errors within the error correcting capability of the ECC Generator Checker <b>80</b> will be detected and corrected. For example, instead of setting a Error Flag True responsive to detecting an error, the count of a counter could be incremented each time an error was detected. Instead of checking the state of the Error Flag at step <b>152</b>, the count of the counter would then the compared to a value corresponding to the desired number of errors to determine if the time constant should be incremented or decremented. Other variations will be apparent to one skilled in the art.

P-0036[0036] The value of the time constant Tconst may be adapted to operating conditions other than the number of memory errors. For example, as previously mentioned, the frequency at which the scrubbing procedure is performed may be adjusted as a function of the temperature of the DRAM device <b>12</b>. The initial value of the time constant Tconst may be adjusted as a function of temperature using the procedure <b>170</b> shown in FIG. 5. The procedure <b>170</b> is entered from the “Reset Scrub Counter (SC)” step <b>102</b> and exits to the “SRC=0?” step at <b>110</b>. The temperature is read from the temperature sensor <b>56</b> (FIG. 1) at step <b>172</b>. A lookup table is then accessed at step <b>174</b> to determine a time constant Tconst corresponding to the measure temperature. Smaller values for the time constant Tconst correspond to hotter temperatures because charge leaks from DRAM memory cells a faster rate with higher temperatures of the DRAM device <b>12</b>, thus requiring more frequent memory scrubbing to refresh the memory cells. Thereafter, the time constant Tconst can be adjusted from the value initially set as a function of temperature using a suitable procedure, such as the procedure <b>150</b> shown in FIG. 4. If the procedure <b>170</b> shown in FIG. 5 is not used, the temperature sensor <b>56</b> may, of course, be eliminated.

P-0037[0037] To the scrubbing procedure shown in FIG. 3 periodically performs a scrubbing procedure and then scrubs all that the memory cells during that procedure. Alternatively, memory scrubbing may be performed in a continuous procedure in which there is a time delay between the scrubbing of memory cells in each location of the DRAM device <b>12</b>. A scrubbing procedure having these characteristics is shown in FIG. 6. The procedure is entered at <b>180</b>, and the count of the SC Counter/comparator <b>66</b> (FIG. 2) is reset and an Error Flag is set False at step <b>182</b>. The time constant Tconst stored in the register <b>94</b> is then loaded into the SRC <b>90</b> at step <b>184</b>. The procedure then it remains in a loop in which the count of the SRC <b>90</b> is checked at step <b>186</b> to determine if the count has been decremented to zero. If not, the count is decremented by one at step <b>188</b> until the zero count is reached. A single location in the DRAM device <b>12</b> is then scrubbed.

P-0038[0038] The single location is scrubbed by first reading date and an associated check bits from the DRAM device <b>12</b> at step <b>190</b>. The ECC Generator Checker <b>80</b> generates check bits corresponding to the read data at step <b>192</b>. The generated check bits and the read check bits are then processed to generate a syndrome at step <b>196</b>. If the syndrome indicates there are errors in the read data and/or check bits, the ECC Generator Checker <b>80</b> uses the information provided by the syndrome to correct the erroneous data and/or check bits. The corrected data and check bits are then written to the DRAM device <b>12</b> at step <b>200</b>. The Error Flag is also set True at step <b>202</b>. A determination is then made at step <b>206</b> as to whether the end of the memory array has been reached. Also, if the syndrome indicates at step <b>196</b> that no errors are detected, the procedure jumps to step <b>206</b> without writing corrected data and/or check bits at step <b>200</b> or setting the Error Flag True at step <b>202</b>.

P-0039[0039] If the last memory location in the DRAM device <b>12</b> has not been reached, the SC count in the SC Counter/Comparator <b>90</b> is incremented at step <b>208</b> before returning to reset the time constant Tconst at step <b>184</b>. The procedure then waits in the loop <b>186</b>, <b>188</b> before scrubbing the next location in memory, as previously explained. If a determination is made at <b>206</b> that the entire memory array has been scrubbed, a determination is made at <b>210</b> if scrubbing is to continue. If so, the procedure returns to step <b>182</b> to reset the count of the SC Counter/Comparator <b>66</b> to the first memory location and to set the Error Flag False at step <b>182</b>. If a determination is made at step <b>210</b> that memory scrubbing will terminate, the procedure exits at <b>212</b>.

P-0040[0040] The presence of the Error Flag presumes, of course, that the time constant adjusting procedure <b>150</b> shown in FIG. 4 is used between step <b>206</b> and step <b>210</b>. If the time constant Tconst does not change or another time constant adjusting procedure, such as the temperature adjusting procedure <b>170</b> shown in FIG. 5, is used, the Error Flag would not be used.

P-0041[0041] The advantage of the scrubbing procedure shown in FIG. 6 is that it provides the lowest peak power by spreading the memory scrubbing out over a longer duration. This procedure could also be used even if the DRAM device <b>12</b> was not operated in an inactive power-saving mode by integrating the procedure into any standard error scrubbing system.

P-0042[0042] FIGS. <b>3</b>-<b>6</b> illustrate the memory scrubbing procedures during the power saving mode when the DRAM device <b>12</b> is inactive. They do not show the procedure is that would be required for transitioning into and out of the power saving mode. However, when transitioning into the power saving mode, the scrubbing procedure shown in FIGS. 3 and 6 may be used with some slight modifications that will be apparent to one skilled in the art. For example, the time constant Tconst will initially be set to a minimum value corresponding to the normal refresh rate since the data will not yet have been stored in the DRAM device <b>12</b> in error correcting mode. Also, since the data will not be saved in ECC format, data will be read from the DRAM device <b>12</b> at step <b>114</b> or <b>190</b>, check bits will be generated at step <b>118</b> or <b>192</b>, and the data and check bits will be written to the DRAM device <b>12</b> at step <b>124</b> or <b>200</b>. Thereafter, the time constant Tconst may be set to a value that will provide memory scrubbing at a relatively low rate.

P-0043[0043] Although the check bits are shown in FIG. 2 as being coupled to and from the DRAM device <b>12</b> through a check bit bus <b>30</b> that is separate from the data bus <b>28</b>, it will be understood that the check bits and data bits may be combined in a predetermined manner in the ECC Generator Checker to form an ECC containing both the data and check bits. The ECC can then be coupled to and from the DRAM device <b>12</b> through a single bus (not shown) for storage in the DRAM device <b>12</b>. However, storing the data in the DRAM device <b>12</b> separately from the check bits is preferred because it may then not necessary to alter the manner in which the data are stored when transitioning into and out of the power-saving mode in which memory scrubbing occurs. After transitioning from the power-saving mode to the normal operating mode, the normal refresh logic, as well as external refresh commands, will ensure that the memory cells in the DRAM device <b>12</b> are refreshed at an adequate rate.

P-0044[0044] Although FIG. 1 shows the check bits being stored in the same DRAM device <b>12</b> that the data are stored, it will be understood that the data and check bits can be stored in different DRAM devices, or they can be stored in the same DRAM device <b>12</b> but in different arrays or areas of the same array.

P-0045[0045] Another embodiment of the invention is shown in FIG. 7 in which a DRAM <b>230</b> device of conventional design includes an internal scrubbing controller <b>232</b>. The DRAM device <b>230</b> also includes an array <b>236</b> of memory cells arranged in rows and columns that are accessed to write data to and read data from the DRAM device <b>230</b>. The data are coupled between the array <b>236</b> and a data bus <b>238</b> through a data path <b>240</b>. The locations of the memory cells in the array <b>236</b> that are accessed for a read or a write operation are designated by an externally applied memory address that is received and decoded by an addressing circuit <b>244</b> of conventional design. The operation of the DRAM device <b>230</b> is determined by control signals generated by a command decoder <b>248</b> responsive to externally applied memory commands that are received and decoded by the command decoder <b>248</b>. The DRAM device <b>230</b> also includes a refresh controller <b>250</b> that causes rows of memory cells in the array <b>236</b> to be refreshed responsive to either externally applied memory commands or internally generated signals.

P-0046[0046] The command decoder <b>248</b> causes the DRAM device <b>230</b> to operate in either of two modes. In a normal operating mode, the DRAM device <b>230</b> is active and able to write data to or read data from the array <b>236</b>. During this operating mode, the refresh controller <b>250</b> refreshes the memory cells in the array <b>236</b> at a rate that is sufficiently high to ensure that no data errors are generated in the array <b>236</b>. In a power-saving mode, the scrubbing controller <b>232</b> causes the memory cells in the array <b>236</b> to be scrubbed, as previously explained.

P-0047[0047] Although the scrubbing controller <b>232</b> may be substantially as shown in FIG. 2, if my also have other configurations. For example, the scrubbing controller <b>232</b> may use various components that are normally in DRAM devices, such as the addressing circuit <b>244</b> or the refresh controller <b>250</b>, to perform some of the functions performed by various components in the scrubbing controller <b>38</b> of FIG. 2. Also, the functions of a control state machine for the scrubbing controller <b>232</b> may simply be performed by the command decoder <b>248</b>. Therefore, the scrubbing controller <b>232</b> may not include some of the components shown in FIG. 2, and it may also include additional components. By using a scrubbing controller <b>232</b> that is internal to the DRAM device <b>230</b>, the DRAM device <b>230</b> may be included in a conventional electronic system (not shown), such as a computer system, without specially modifying the electronic system to provide memory scrubbing in a power-saving mode. A scrubbing controller may also be included in locations other than the system controller <b>20</b> shown in FIG. 2 or the DRAM device <b>230</b> shown in FIG. 7.

P-0048[0048] From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims.