System and method for address broadcast synchronization using a plurality of switches

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] This invention relates to cache synchronization, and more particularly to address broadcast synchronization to a plurality of potentially responding devices.

[0003] 2. Description of the Relevant Art

[0004] Maintaining cache coherency in an N-way system, where N is the number of processors in the system, is essential. In a system where N is small (N<4), the address buses of all cacheable devices may be physically connected together. Therefore, all cacheable devices may see a cache miss address simultaneously. On the other hand, when a system of N is large (N>4), it becomes electrically unfeasible to connect the address buses of all cacheable devices together.

[0005] One approach for achieving cache coherency in a system with large N, is by broadcasting the cache miss addresses to all cacheable devices simultaneously, through an address broadcast network. The address broadcast network has an address-in and an address-out connection to each of the cacheable devices. When a device sends a cache miss address to the address broadcast network, the address gets buffered, and then broadcast to all devices concurrently, so that all devices may check or update their tags appropriately.

[0006] One problem with building an address network in hardware for large systems (N>4) is that one needs a very large pin count ASIC (Application Specific Integrated Circuit) to accommodate all address-ins and address-outs for all cacheable devices to maintain address synchronization. The expense of building a large pin count ASIC to accommodate all address-ins and all address-outs for all cacheable devices limits this solution to only a very small number of computer systems.

[0007] Another possible solution is to slice the address network into X (X>1) slices for a small ASIC solution. The problem with address slicing is that using typical request and grant flow control techniques between address slices to maintain address synchronization requires a computer system performance degradation that is unacceptable.

[0008] What is needed is a mechanism for achieving synchronization between address network slices without substantial performance degradation. The request and grant flow control technique used should require a minimum number of control signals passing between each switch.

SUMMARY OF THE INVENTION

[0009] The problems outlined above are in large part solved by a system and method providing address broadcast synchronization using multiple switches. Each switch may be an application specific integration circuit (ASIC) or a separate switching device. By dividing address requests between more than one switch, addresses may be broadcast concurrently to a plurality of devices, which may advantageously provide for a higher system performance at a lower cost.

[0010] In one embodiment, the system for concurrently providing addresses to a plurality of devices includes a first switch and a second switch. The first switch is coupled to receive address requests from a first plurality of sources. The first switch is configured to output the address request from the first plurality of sources. The second switch is coupled to receive address requests from a second plurality of sources. The second switch is configured to receive the address request from the first plurality of sources from the first switch. The second switch is further configured to delay the address request from the second plurality of sources prior to arbitrating between ones of the address request from the second plurality of sources and ones of the address request from the first party of sources received from the first switch. The second switch selects a selected address request, and the first and the second switch are further configured to broadcast concurrently a corresponding address to the selected address request.

[0011] A method is also contemplated, in one embodiment, for concurrently providing addresses to a plurality of devices. In one embodiment, the method comprises receiving at a first switch a first address and a corresponding first request from a first device. The method receives at a second switch a second address and a corresponding second request from a second device, with the first switch being different from the second switch. The method transfers the second address and the corresponding second request to the first switch. The method delays the corresponding first request in the first switch. The method arbitrates in the first switch between the corresponding first request and the corresponding second request but rather the first address or the second address will comprise a first transmission. The method concurrently broadcasts to a plurality of devices the first transmission from the first switch and the first transmission from the second switch where the first transmission from the first switch and the first transmission from the second switch are identical.

[0012] In another embodiment, a system for concurrently providing addresses to a plurality of devices includes a first switch and a second switch. The first switch is coupled to receive address requests from a first plurality of sources. The first switch is configured to output the address request from the first plurality of sources. The second switch is coupled to receive address requests from a second plurality of sources. The second switch comprises a broadcast buffer, an incoming buffer, a delay circuit, and a broadcast arbiter. The broadcast buffer is coupled to receive addresses of the address requests from the second plurality of sources. The incoming buffer is coupled to receive addresses of the output of the address requests from the first plurality of sources from the first switch. The delay circuit is coupled to receive the address requests from the second plurality of sources. The delay circuit is configured to delay the address requests from the second plurality of sources for a predetermined length of time. The broadcast arbiter is coupled to arbitrate between ones of the address request from the second plurality of sources and ones of the output of the address request from the first plurality of sources from the first switch for a selected address request. The first switch and the second switch are further configured to broadcast concurrently a corresponding address to the selected address request selected in the broadcast arbiter.

[0013] In still another embodiment, a method of arbitrating in a first switch and a second switch between requests to the first switch and the second switch is disclosed. The comprises tracking which switch was most recently selected and tracking which switch is next to be selected. In response to a reset, the method selects the first switch and indicates that the second switch is next to be selected. In response to only a local request to the first switch or only a remote request to the second switch, the method selects the first switch and indicates that the first switch is next to be selected. In response to only a local request to the second switch or only a remote request to the first switch, the method selects the second switch and indicates that the second switch is next to be selected. In response to both a local request and a remote request concurrently, the method selects the switch which was not most recently selected, and the method indicates that the switch not most recently selected will be the next to be selected. Otherwise, the method selects the first switch and indicates the switch most recently selected as the next to be selected.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Other objects and advantages of the invention will become apparent upon reading the following detailed description and upon reference to the accompanying drawings in which:

[0015]FIG. 1 is a block diagram of an embodiment of a computer system including two switches that concurrently provide addresses to a plurality of devices;

[0016]FIG. 2 is a block diagram of an embodiment of the two switches shown in FIG. 1; and

[0017]FIGS. 3A and 3B are a flowchart of an embodiment of a method for arbitrating in a first switch and a second switch between request to the first switch and the second switch.

[0018] While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present invention as defined by the appended claims.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] Similar features are designed herein using identical reference numerals. It is noted that the use of a reference numeral with an additional letter may designate a particular one of a group that may referenced as a while with the reference numeral by itself.

[0020]FIG. 1—Computer System Including Two Switches

[0021]FIG. 1 is a block diagram of a computer system including two switches, switch <b>110</b>A and switch <b>110</b>B. As shown, the computer system includes CPUs <b>115</b>A-<b>115</b>H, input and output devices (I/O) <b>120</b>A-<b>120</b>D, and memories <b>125</b>A-<b>125</b>D. Data signals beginning with a P have a processor <b>115</b> as a destination, and data signals beginning with an I/O have an I/O device <b>120</b> as a destination. Switches <b>110</b>A and <b>110</b>B are shown receiving input from various groupings of the processors <b>115</b> and the I/O devices <b>120</b>. The switches <b>110</b>A and <b>110</b>B are also shown outputting signals to various ones of the processors <b>115</b>, the I/O devices <b>120</b>, and to the memories <b>125</b>.

[0022] A plurality of processors (CPUs) <b>115</b>A-<b>115</b>H (eight as shown), each receives an input, preferably addresses, appropriately referenced as P0-P7. Each of the processors <b>115</b>A-<b>115</b>H outputs an output, preferably an address and an address request, such as an address request packet, to one of the two switches <b>110</b>A and <b>110</b>B. As shown, switch <b>110</b>A also accepts address request packets from I/O device <b>120</b>A and I/O device <b>120</b>B. Also as shown, switch <b>110</b>B accepts address request packets from I/O device <b>120</b>C and I/O device <b>120</b>D. Switch <b>110</b>A outputs an output signal, preferably address signals, to the CPUs <b>115</b>A-<b>115</b>D, the I/O devices I/O0-I/O1, and memories <b>125</b>A-<b>125</b>B. Switch <b>110</b>B outputs an output signal, preferably address signals, to processors <b>115</b>E-<b>115</b>H, I/O devices I/O2-I/O3, and memories <b>125</b>C-<b>125</b>D. Switch <b>110</b>A and switch <b>110</b>B also exchange data, preferably including addresses and address requests.

[0023] It is noted that while a particular number of processors <b>115</b>, I/O devices <b>120</b>, and memories <b>125</b> are illustrated, any number of processors, I/O devices, and/or memories, or other devices are contemplated. It is also noted that while unidirectional data paths are illustrated, bi-directional data paths may also be used as desired.

[0024]FIG. 2—Address Broadcast Synchronization Switches

[0025]FIG. 2 is a block diagram of one embodiment of the switches <b>110</b>A and <b>110</b>B. As shown, each switch <b>110</b> includes a plurality of input FIFOs (First-In, First Out buffers) <b>205</b>, a request arbiter <b>215</b>, an input multiplexer (MUX) <b>210</b>, a broadcast FIFO <b>225</b>, an incoming FIFO <b>230</b>, a delay circuit <b>235</b>, a broadcast arbiter <b>240</b>, and an output MUX <b>245</b>. The switches <b>110</b> exchange output requests from their respective request arbiters <b>215</b> and output addresses from their respective input MUXes <b>210</b>.

[0026] As illustrated, switch <b>110</b>A accepts addresses P0P3 and I/O0-I/O1, as well as address requests P0_req-P3_req and I/O0_req and I/O1_req. Switch <b>110</b>A outputs address signals P0-P3, I/O0-I/O1, and M0-M1. Each incoming address P0-P3 and I/O0-I/O1 is received into an input FIFO <b>205</b>A-<b>205</b>F. The address requests that correspond to the addresses received in the input FIFOs <b>205</b>A-<b>205</b>F are received at a request arbiter <b>215</b>A. In the preferred embodiment, the request arbiter <b>215</b>A is a round-robin arbiter, although any other means of arbitration may be used as desired for choosing requests received by request arbiter <b>215</b>A. When the request arbiter <b>215</b>A chooses (or arbitrates) for a particular address request, the request arbiter <b>215</b>A controls the selection at input MUX <b>210</b>A with regard to the output of the input FIFOs <b>205</b>A-<b>205</b>F. The selected address request is output as SW0_req to delay circuit <b>235</b>A. The output of input MUX <b>210</b>A, shown as signal <b>220</b>A, is provided to a broadcast FIFO <b>225</b>A. It is noted that output signal <b>220</b>A is also provided to switch <b>110</b>B, and that the address request SW0_req is also provided to switch <b>110</b>B.

[0027] Switch <b>110</b>A is also coupled to receive the address request SW1_req from switch <b>110</b>B, as well as address output signal <b>220</b>B. Signal <b>220</b>B is received at incoming FIFO <b>230</b>A. As shown, broadcast FIFO <b>225</b>A and incoming FIFO <b>230</b>A each output data to output MUX <b>245</b>A, broadcast FIFO <b>225</b>A as ‘0’ (zero) and incoming FIFO <b>230</b>A as ‘1’ (one). Address request SW0_req is delayed for a period of time in delay circuit <b>235</b>A before being provided to broadcast arbiter <b>240</b>A. The period of time of the delay may be a predetermined period of time. It is noted that in a preferred embodiment, the predetermined period of time is equal to the time required for switch <b>110</b>A to receive the address request SW1_req and the address output signal <b>220</b>B. Broadcast arbiter <b>240</b>A chooses (or arbitrates) between request SW1_req and request SW1_req. The broadcast arbiter <b>240</b>A controls the output of output MUX <b>245</b>A choosing between ‘0’ and ‘1’. The output of output MUX <b>245</b>A, the selected address for the first transmission, is provided concurrently to various groups of the processors <b>115</b>, I/O devices <b>120</b>, and/or memories <b>125</b> through signals P0-P3, I/O0-I/O1, and M0-M1.

[0028] As illustrated, switch <b>110</b>B accepts addresses P4-P7 and I/O2-I/O3, as well as address requests P4_req-P7_req and I/O2_req and I/O3_req. Switch <b>110</b>B outputs address signals P4-P7, I/O2-I/O3, and M2-M3. Each incoming address P4-P7 and I/O2-I/O3 is received into an input FIFO <b>205</b>G-<b>205</b>L. The address requests that correspond to the addresses received in the input FIFOs <b>205</b>G-<b>205</b>L are received at a request arbiter <b>215</b>B. In the preferred embodiment, the request arbiter <b>215</b>B is a round-robin arbiter, although any other means of arbitration may be used as desired for choosing requests received by request arbiter <b>215</b>B. When the request arbiter <b>215</b>B chooses (or arbitrates) for a particular address request, the request arbiter <b>215</b>B controls the selection at input MUX <b>210</b>B with regard to the output of the input FIFOs <b>205</b>G-<b>205</b>L. The selected address request is output as SW1_req to delay circuit <b>235</b>B. The output of input MUX <b>210</b>B, shown as signal <b>220</b>B, is provided to a broadcast FIFO <b>225</b>B. It is noted that output signal <b>220</b>B is also provided to switch <b>110</b>A, and that the address request SW1_req is also provided to switch <b>110</b>A.

[0029] Switch <b>110</b>B is also coupled to receive the address request SW0_req from switch <b>110</b>A, as well as address output signal <b>220</b>A. Signal <b>220</b>A is received at incoming FIFO <b>230</b>B. As shown, broadcast FIFO <b>225</b>B and incoming FIFO <b>230</b>B each output data to output MUX <b>245</b>B, broadcast FIFO <b>225</b>B as ‘1’ (one) and incoming FIFO <b>230</b>B as ‘0’ (zero). Address request SW1_req is delayed for a period of time in delay circuit <b>235</b>B before being provided to broadcast arbiter <b>240</b>B. The period of time of the delay may be a predetermined period of time. It is noted that in a preferred embodiment, the predetermined period of time is equal to the time required for switch <b>110</b>B to receive the address request SW0_req and the address output signal <b>220</b>A. Broadcast arbiter <b>240</b>B chooses (or arbitrates) between request SW1_req and request SW1_req. The broadcast arbiter <b>240</b>B controls the output of output MUX <b>245</b>B choosing between ‘0’ and ‘1’. The output of output MUX <b>245</b>B, the selected address for the first transmission, is provided concurrently to various groups of the processors <b>115</b>, I/O devices <b>120</b>, and/or memories <b>125</b> through signals P4-P7, I/O2-I/O3, and M2-M3.

[0030] It is noted that the delay circuits <b>235</b>A and <b>235</b>B may include any circuit that is configured to delay the output of a received signal. In one embodiment, a delay circuit <b>235</b> delays the received signal longer than the minimum time required to propagate the received signal through delay circuit <b>235</b>. In another embodiment, delay circuit <b>235</b> includes one or more flip-flops. It is also noted that in various embodiments various incoming and outgoing signals to and from switches <b>110</b>A and <b>110</b>B may be buffered at input to the switch <b>110</b> and/or on output from the switch <b>110</b>.

[0031] Generally speaking, the system of FIG. 1 operates as described herein. The first switch <b>110</b>A is coupled to receive address requests from a first plurality of sources. For example, one plurality of sources may be processors <b>115</b>A-<b>115</b>D and/or I/O devices <b>120</b>A-<b>120</b>B. The first switch <b>110</b>A is configured to output a received address request from the first plurality of sources.

[0032] The second switch <b>110</b>B is coupled to receive address requests from a second plurality of sources. For example, the second plurality of sources may include processors <b>115</b>E-<b>115</b>H and/or I/O devices <b>120</b>C-<b>120</b>D. Switch <b>110</b>B is also configured to receive the address request from the first plurality of sources from the first switch <b>110</b>A. The second switch is further configured to delay internally address requests from the second plurality of sources. It is noted that the length of the delay may be predetermined, and is preferably equal in length of time to the time delay in receiving the address request from the first plurality of sources from the first switch. The second switch <b>110</b>B is further configured to arbitrate between ones of the address requests from the second plurality of sources and ones of the address request from the first plurality of sources output from the first switch. The arbitration between the address requests is to determine a selected address request. Once a selected address request has been selected, the first switch and the second switch are further configured to broadcast concurrently the corresponding address to the selected address request. It is noted that the corresponding address will broadcast to any or all devices, including the CPUs <b>115</b>A-<b>115</b>H, I/O devices <b>120</b>A-<b>120</b>B, and memories <b>125</b>A-<b>125</b>D.

[0033] In one embodiment, the second switch <b>110</b>B is further configured to output the address request from the second plurality of sources, and the first switch <b>110</b>A is further configured to receive this request from the second plurality of sources. First switch <b>110</b>A is further configured to delay internally the address request from the first plurality of sources. The time of the delay of the address request from the first plurality of sources may be a predetermined length of time and is preferably a length of time approximately equal to the time required for the second switch <b>110</b>B to provide the address request in the second plurality of sources to first switch <b>110</b>A. The first switch is further configured to arbitrate between ones of the address request from the first plurality of sources and ones of the address requests from the second plurality of sources from the second switch. The arbitration is to determine the selected address request, as noted above for the second switch <b>110</b>B. It is noted that the selected address provided by the first switch <b>110</b>A and the selected address provided by the second switch <b>110</b>B are the same and are concurrently provided to the devices as described above.

[0034] FIGS. <b>3</b>A-<b>3</b>B—Arbitration by a Broadcast Arbiter

[0035]FIGS. 3A and 3B illustrate a flowchart of an embodiment of a method for operating an arbiter, such as broadcast arbiters <b>240</b>A and <b>240</b>B. The method tracks which switch was most recently selected, and the method also tracks which switch is next to be selected. At decision block <b>305</b>, the method checks to see if reset has been asserted. If reset has been asserted in decision box <b>305</b>, then an output MUX selects output ‘0’ (i.e. switch <b>110</b>A) and the next granted switch will be the other switch (i.e. switch <b>110</b>B) (step <b>310</b>).

[0036] If reset has not been asserted in decision block <b>305</b>, then the method determines if only a local request has been made to the first switch <b>110</b>A or only a remote request has been made to the second switch <b>110</b>B in decision block <b>315</b>. If only a local request has been made to the first switch <b>110</b>A or only a remote request is made to the second switch <b>110</b>B, then the method selects output MUX output ‘0’ and the next granted switch will be the same switch (step <b>320</b>).

[0037] If there has not been only a local request to the first switch <b>110</b>A or only a remote request to the second switch <b>110</b>B, then the method moves to decision block <b>325</b>. If only a local request has been made to the second switch <b>110</b>B or only a remote request has been made to the first switch <b>110</b>A in decision box <b>325</b>, then the method selects output MUX output ‘1’ and the next granted switch will be the same switch (step <b>330</b>).

[0038] If only a local request to the second switch <b>110</b>B or only a local request to the first switch <b>110</b>A has not been made in decision block <b>325</b>, then the method moves to decision block <b>335</b>. In decision block <b>335</b>, if both a local request and a remote request have concurrently been made, and the current granted switch is switch <b>110</b>A, then the output MUX selects ‘1’ and the next granted switch is switch <b>110</b>A (step <b>340</b>). If in decision block <b>335</b> both the local request and remote request have been made concurrently but the current granted switch is not switch 0, then the method moves to decision block <b>345</b>.

[0039] In decision block <b>345</b>, if both the local request and a remote request have been made concurrently and the current granted switch is switch <b>110</b>B, then the output MUX selects ‘0’ and the next granted switch is switch <b>110</b>A (step <b>350</b>). It is noted that in decision blocks <b>335</b> and <b>345</b>, an affirmative decision is made in either case when a local request and a remote request have both been made concurrently. In either case the selected output MUX output is to the switch not most recently selected and the indicated switch as the next granted switch is also the switch not most recently selected.

[0040] The default action when all decision blocks are negative, is for the outgoing MUX to select ‘0’, and the next granted switch is the current granted switch (step <b>355</b>).

[0041] In various embodiments, the switches <b>110</b>A and <b>110</b>B may be application specific integrated circuits ASCIC0 and ASCIC1. In one embodiment, ASCIC0 and ASCIC1 are location strapped via jumpers. It is noted that ASCIC0 preferably will have a pull-up resistor, while ASIC1 preferably has a pull-down resistor, both of which get latched on reset to identify which is ASCIC0 and which is ASCIC1. Note that the priority toggles between the broadcast arbiters based on the switch that had the last request granted and the current outstanding request. The method disclosed may advantageously ensure that both arbiters are synchronized to each other without a need for request/grant flow control mechanisms beyond the address and the corresponding address request that was initially received.

[0042] As an example of an embodiment of the operations of switches <b>110</b>A and <b>110</b>B, right after a reset, both processors <b>115</b>A and <b>115</b>E have an outstanding address packet in the address network. The P0 address packet is received in switch <b>110</b>A's input FIFO <b>205</b>A from processor <b>115</b>A, whereas the P4 address packet is received and stored in switch <b>110</b>B's input FIFO <b>205</b>G from processor <b>115</b>E. The request arbiter <b>215</b>A in switch <b>110</b>A will receive the P0 request associated with the address stored in input FIFO <b>205</b>A. Similarly, request arbiter <b>215</b>B receives the P4_req address request associated with the P4 address stored in input FIFO <b>205</b>G.

[0043] Request arbiter <b>215</b>A in switch <b>110</b>A controls input MUX <b>210</b>A to output the address associated with input signal P0 as output signal <b>220</b>A, which is provided to broadcast FIFO <b>225</b>A and to incoming FIFO <b>230</b>B. Likewise, request arbiter <b>215</b>B controls input MUX <b>210</b>B to output the address from P4 as output signal <b>220</b>B. Output signal <b>220</b>B is provided to broadcast FIFO <b>225</b>B and also to incoming FIFO <b>230</b>A. Concurrently with the addresses being routed from the input FIFO <b>205</b> to the broadcast FIFOs <b>225</b> and incoming FIFOs <b>230</b>, switch <b>110</b>A has asserted SW0_req line indicating the presence of an address from switch <b>110</b>A in broadcast FIFO <b>225</b>A and incoming FIFO <b>230</b>B.

[0044] As a finite amount of time is required for the address and the request line to be provided from one switch <b>110</b> to the other switch <b>110</b>, in this case from switch <b>110</b>A to switch <b>110</b>B, signal SW0_req is first provided to a delay circuit <b>235</b>A, before being provided to broadcast arbiter <b>240</b>A. In the preferred embodiment, the delay circuit <b>235</b>A delays the address request SW1_req by approximately an equal amount of time as required for switch <b>110</b>A to receive the address and corresponding address request from switch <b>110</b>B. In this embodiment, broadcast arbiter <b>240</b>A receives notice that an address is present in the broadcast FIFO <b>225</b>A concurrently with an address being available in the incoming FIFO <b>230</b>A. The broadcast arbiter <b>240</b>A chooses (or arbitrates) for priority between the SW0_req and SW1_req. The preferred arbitration method is described above with respect to FIGS. 3A and 3B. Broadcast arbiter <b>240</b>A selects either ‘0’ or ‘1’ denoting the address from switch <b>110</b>A or switch <b>110</b>B, respectively, in controlling the output of the output multiplexer <b>245</b>A.

[0045] It is noted that since SW1_req and SW1_req are both required to cross from one switch to the other, the signals endure a delay, such as two clock cycles in one embodiment. Therefore, each switch <b>110</b>A and <b>110</b>B delays the address request that it sends, SW0_req and SW1_req, respectively, to the broadcast arbiter <b>240</b> of the other switch by an equivalent time period of 2 clock cycles. This delay ensures that the broadcast arbiters <b>240</b>A and <b>240</b>B in each switch <b>110</b>A and <b>110</b>B receive the address request concurrently.

[0046] Switch <b>110</b>A has the P0 address placed in its broadcast FIFO <b>225</b>A and the P4 address placed in incoming FIFO <b>230</b>A. Switch <b>110</b>B has the P0 address placed in its incoming FIFO <b>230</b>B and P4 packet placed in broadcast FIFO <b>225</b>B. At this time broadcast arbiter <b>240</b>A has received address request SW0_req and address request SW1_req, whereas broadcast arbiter <b>240</b>B has likewise received address request SW1_req and address request SW1_req.

[0047] The arbitration method described above with respect to FIGS. 3A and 3B illustrates a preferred embodiment of how the broadcast arbiter <b>245</b> works for each address request that it receives. After a reset, the last granted switch defaults to switch <b>110</b>A, so that switch <b>110</b>A broadcast arbiter now has the highest priority. When the broadcast arbiter <b>240</b>A has highest priority, then both broadcast arbiter <b>240</b>A and broadcast arbiter <b>240</b>B will select the ‘0’ of the multiplexer <b>245</b>B. It is noted that both broadcast arbiter <b>240</b>A and broadcast arbiter <b>240</b>B are at decision block <b>345</b> of FIG. 3B. Both a local request and a remote request have been received and the current granted switch is switch <b>110</b>B (the default upon a reset), therefore the output MUXes <b>245</b>A and <b>245</b>B both select ‘0’ and the next granted which will be switch <b>110</b>A (step <b>350</b>). Thus, the address from P0 is provided as output <b>250</b>A and output <b>250</b>B, concurrently on address lines P0-P7, I/O0-I/O3, and M0-M3.

[0048] Continuing, at decision block <b>325</b>, as the request is now only the request from switch <b>1110</b>B, the output MUXes <b>245</b> will select ‘1’ and the next granted will be switch <b>110</b>B (step <b>330</b>). It is noted that broadcast arbiter <b>240</b>A and broadcast arbiter <b>240</b>B, following an arbitration method similar to that disclosed in FIGS. 3A and 3B, make selections between local and remote requests which are identical in all cases. It is also noted the broadcaster arbiter <b>240</b>A knows that upon a reset that it will have priority just as broadcast arbiter <b>240</b>B knows that after a reset it will not have priority.

[0049] Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications.