Registers for data transfers

BACKGROUND

P-0001[0001] Parallel processing is an efficient form of information processing of concurrent events in a computing process. Parallel processing demands concurrent execution of many programs, in contrast to sequential processing. In the context of parallel processing, parallelism involves doing more than one thing at the same time. Unlike a serial paradigm where all tasks are performed sequentially at a single station or a pipelined machine where tasks are performed at specialized stations, with parallel processing, many stations are provided, each capable of performing and carrying out various tasks and functions simultaneously. A number of stations work simultaneously and independently on the same or common elements of a computing task. Accordingly, parallel processing solves various types of computing tasks and certain problems are suitable for solution by applying several instruction processing units and several data streams.

BRIEF DESCRIPTION OF THE DRAWINGS

P-0002[0002]FIG. 1 is a block diagram of a processing system.

P-0003[0003]FIG. 2 is a detailed block diagram of the processing system of FIG. 1 where one of the embodiments of the invention may be advantageously practiced.

P-0004[0004]FIG. 3 is a block diagram of a functional pipeline unit of the processing system of FIG. 1.

P-0005[0005]FIG. 4 is a block diagram illustrating details of the processing system of FIG. 1 where one of the embodiments of the invention may be advantageously practiced.

P-0006[0006]FIG. 5 is a simplified block diagram of a context pipeline process.

P-0007[0007]FIG. 6 is a flowchart illustrating the process of a context pipeline where one of the embodiments of the invention may be advantageously practiced.

P-0008[0008]FIG. 7 is a flowchart illustrating the process of determining the address of the Next Neighbor registers.

DESCRIPTION

P-0009[0009] Architecture:

P-0010[0010] Referring to FIG. 1, a computer processing system <b>10</b> includes a parallel, hardware-based multithreaded network processor <b>12</b>. The hardware-based multithreaded processor <b>12</b> is coupled to a memory system or memory resource <b>14</b>. Memory system <b>14</b> includes dynamic random access memory (DRAM) <b>14</b><i>a </i>and static random access memory <b>14</b><i>b </i>(SRAM) . The processing system <b>10</b> is especially useful for tasks that can be broken into parallel subtasks or functions. Specifically, the hardware-based multithreaded processor <b>12</b> is useful for tasks that are bandwidth oriented rather than latency oriented. The hardware-based multithreaded processor <b>12</b> has multiple functional microengines or programming engines <b>16</b><i>a</i>-<b>16</b><i>h </i>(collectively, programming engines <b>16</b>) each with multiple hardware controlled threads that are simultaneously active and independently work on a specific task.

P-0011[0011] The programming engines <b>16</b> each maintain program counters in hardware and states associated with the program counters. Effectively, corresponding sets of context or threads can be simultaneously active on each of the programming engines <b>16</b> while only one is actually operating at any one time.

P-0012[0012] In this example, eight programming engines <b>16</b><i>a</i>-<b>16</b><i>h </i>are illustrated in FIG. 1. Each programming engine <b>16</b><i>a</i>-<b>16</b><i>h </i>processes eight hardware threads or contexts. The eight programming engines <b>16</b><i>a</i>-<b>16</b><i>h </i>operate with shared resources including memory resource <b>14</b> and bus interfaces (not shown). The hardware-based multithreaded processor <b>12</b> includes a dynamic random access memory (DRAM) controller <b>18</b><i>a </i>and a static random access memory (SRAM) controller <b>18</b><i>b</i>. The DRAM memory <b>14</b><i>a </i>and DRAM controller <b>18</b><i>a </i>are typically used for processing large volumes of data, e.g., processing of network payloads from network packets. The SRAM memory <b>14</b><i>b </i>and SRAM controller <b>18</b><i>b </i>are used in a networking implementation for low latency, fast access tasks, e.g., accessing look-up tables, memory for the core processor <b>20</b>, and the like.

P-0013[0013] The eight programming engines <b>16</b><i>a</i>-<b>16</b><i>h </i>access either the DRAM memory <b>14</b><i>a </i>or SRAM memory <b>14</b><i>b </i>based on characteristics of the data. Thus, low latency, low bandwidth data are stored in and fetched from SRAM memory <b>14</b><i>b</i>, whereas higher bandwidth data for which latency is not as important, are stored in and fetched from DRAM memory <b>14</b><i>a</i>. The programming engines <b>16</b> can execute memory reference instructions to either the DRAM controller <b>18</b><i>a </i>or SRAM controller <b>18</b><i>b. </i>

P-0014[0014] The hardware-based multithreaded processor <b>12</b> also includes a processor core <b>20</b> for loading microcode control for the programming engines <b>16</b>. In this example, although other types of processor cores may be used in embodiments of this invention, the processor core <b>20</b> is an XScale™ based architecture, designed by Intel® Corporation, of Santa Clara, Calif.

P-0015[0015] The processor core <b>20</b> performs general-purpose computer type functions such as handling protocols, exceptions, and extra support for packet processing where the programming engines <b>16</b> pass the packets off for more detailed processing such as in boundary conditions.

P-0016[0016] The processor core <b>20</b> executes an operating system (not shown). Through the operating system (OS), the processor core <b>20</b> can call functions to operate on the programming engines <b>16</b><i>a</i>-<b>16</b><i>h</i>. For the core processor <b>20</b> implemented as an XScale™ architecture, operating systems such as Microsoft® NT real-time of Microsoft® Corporation, of Seattle, Wash., VxWorks® real-time operating system of WindRiver®, of Alameda, Calif., or a freeware OS available over the Internet can be used.

P-0017[0017] Advantages of hardware multithreading can be explained by SRAM or DRAM memory accesses. As an example, an SRAM access requested by a context (e.g., Thread_—0), from one of the programming engines <b>16</b>, e.g., programming engine <b>16</b><i>a</i>, will cause the SRAM controller <b>18</b><i>b </i>to initiate an access to the SRAM memory <b>14</b><i>b</i>. The SRAM controller <b>18</b><i>b </i>accesses the SRAM memory <b>14</b><i>b</i>, fetches the data from the SRAM memory <b>14</b><i>b</i>, and returns data to a requesting programming engine <b>16</b>.

P-0018[0018] During an SRAM access, if one of the programming engines <b>16</b><i>a</i>-<b>16</b><i>h </i>has a single thread that could operate, that programming engine would be dormant until data was returned from the SRAM memory <b>14</b><i>b. </i>

P-0019[0019] By employing hardware context swapping within each of the programming engines <b>16</b><i>a</i>-<b>16</b><i>h</i>, the hardware context swapping enables other contexts with unique program counters to execute in that same programming engine. Thus, another thread e.g., Thread_—1 can function while the first thread, Thread_—0, is awaiting the read data to return. During execution, Thread_—1 may access the DRAM memory <b>14</b><i>a</i>. While Thread_—1 operates on the DRAM unit, and Thread_—0 is operating on the SRAM unit, a new thread, e.g., Thread_—2 can now operate in the programming engine <b>16</b>. Thread_—2 can operate for a certain amount of time until it needs to access memory or perform some other long latency operation, such as making an access to a bus interface. Therefore, simultaneously, the multi-threaded processor <b>12</b> can have a bus operation, an SRAM operation, and a DRAM operation all being completed or operated upon by one of the programming engines <b>16</b> and have one more threads or contexts available to process more work.

P-0020[0020] The hardware context swapping also synchronizes the completion of tasks. For example, two threads can access the shared memory resource, e.g., the SRAM memory <b>14</b><i>b</i>. Each one of the separate functional units, e.g., the SRAM controller <b>18</b><i>b</i>, and the DRAM controller <b>18</b><i>a</i>, when they complete a requested task from one of the programming engine threads or contexts reports back a flag signaling completion of an operation. When the programming engines <b>16</b><i>a</i>-<b>16</b><i>h </i>receive the flag, the programming engines <b>16</b><i>a</i>-<b>16</b><i>h </i>can determine which thread to turn on.

P-0021[0021] One example of an application for the hardware-based multithreaded processor <b>12</b> is as a network processor. As a network processor, the hardware-based multithreaded processor <b>12</b> interfaces to network devices such as a Media Access Controller (MAC) device, e.g., a 10/100 BaseT Octal MAC or a Gigabit Ethernet device compliant with IEEE 802.3. In general, as a network processor, the hardware-based multithreaded processor <b>12</b> can interface to any type of communication device or interface that receives or sends large amount of data. The computer processing system <b>10</b> functioning in a networking application can receive network packets and process those packets in a parallel manner.

P-0022[0022] Registers in Programming Engines:

P-0023[0023] Referring to FIG. 2, one exemplary programming engine <b>16</b><i>a </i>from the programming engines <b>16</b>, is shown. The programming engine <b>16</b><i>a </i>includes a control store <b>30</b>, which in one example includes a RAM of 4096 instructions, each of which is 40-bits wide. The RAM stores a microprogram that the programming engine <b>16</b><i>a </i>executes. The microprogram in the control store <b>30</b> is loadable by the processor core <b>20</b> (FIG. 1).

P-0024[0024] In addition to event signals that are local to an executing thread, the programming engine <b>16</b><i>a </i>employs signaling states that are global. With signaling states, an executing thread can broadcast a signal state to all programming engines <b>16</b><i>a</i>-<b>16</b><i>h</i>. Any and all threads in the programming engines can branch on these signaling states.

P-0025[0025] As described above, the programming engine <b>16</b><i>a </i>supports multi-threaded execution of eight contexts. This allows one thread to start executing just after another thread issues a memory reference and must wait until that reference completes before doing more work. Multi-threaded execution is critical to maintaining efficient hardware execution of the programming engine <b>16</b><i>a </i>because memory latency is significant. Multi-threaded execution allows the programming engines <b>16</b> to hide memory latency by performing useful independent work across several threads.

P-0026[0026] The programming engine <b>16</b><i>a</i>, to allow for efficient context swapping, has its own register set, program counter, and context specific local registers. Having a copy per context eliminates the need to move context specific information to and from shared memory and programming engine registers for each context swap. Fast context swapping allows a context to perform computations while other contexts wait for input-output (I/O), typically, external memory accesses to complete or for a signal from another context or hardware unit.

P-0027[0027] General Purpose Registers

P-0028[0028] The programming engine <b>16</b><i>a </i>executes the eight contexts by maintaining eight program counters and eight context relative sets of registers. A number of different types of context relative registers, such as general purpose registers (GPRs) <b>32</b>, inter-programming agent registers (not shown), Static Random Access Memory (SRAM) input transfer registers <b>34</b>, Dynamic Random Access Memory (DRAM) input transfer registers <b>36</b>, SRAM output transfer registers <b>38</b>, DRAM output transfer registers <b>40</b>.

P-0029[0029] The GPRs <b>32</b> are used for general programming purposes. The GPRs <b>32</b> are read and written exclusively under program control. The GPRs <b>32</b>, when used as a source in an instruction, supply operands to an execution datapath <b>44</b>.

P-0030[0030] The execution datapath <b>44</b> can take one or two operands, perform an operation, and optionally write back a result. The execution datapath <b>44</b> includes a content addressable memory (CAM) <b>45</b>. Each entry of the CAM <b>45</b> stores a 32-bit value, which can be compared against a source operand. All entries are compared in parallel and the result of the lookup is a 6-bit value.

P-0031[0031] When used as a destination in an instruction, the GPRs <b>32</b> are written with the result of the execution datapath <b>44</b>. The programming engine <b>16</b><i>a </i>also includes I/O transfer registers <b>34</b>, <b>36</b>, <b>38</b> and <b>40</b> which are used for transferring data to and from the programming engine <b>16</b><i>a </i>and locations external to the programming engines <b>16</b><i>a</i>, e.g., the DRAM memory <b>14</b><i>a</i>, the SRAM memory <b>14</b><i>b</i>, and the like.

P-0032[0032] Transfer Registers

P-0033[0033] The programming engine <b>16</b><i>a </i>also includes transfer registers <b>34</b>, <b>36</b>, <b>38</b> and <b>40</b>. Transfer registers <b>34</b>, <b>36</b>, <b>38</b> and <b>40</b> are used for transferring data to and from the programming engine <b>16</b><i>a </i>and locations external to the programming engine, e.g., DRAMs, SRAMs etc. There are four types of transfer registers as illustrated in FIG. 2, namely, input transfer registers and output transfer registers.

P-0034[0034] The input transfer registers, when used as a source in an instruction, supply operands to the execution datapath <b>44</b>, whereas output transfer registers are written with the result from the execution datapath <b>44</b> when utilized as a destination in an instruction.

P-0035[0035] Local Control and Status Registers (CSRs)

P-0036[0036] Local control and status registers (CSRs) <b>37</b> are external to the execution datapath <b>44</b> and hold specific purpose information. They can be read and written by special instructions (local_csr_rd and local_csr_wr) and are typically accessed less frequently than datapath registers.

P-0037[0037] Next Neighbor Registers

P-0038[0038] The programming engine <b>16</b><i>a </i>also includes one hundred and twenty eight (128) Next Neighbor (NN) registers, collectively referred to as NN registers <b>35</b>. Each NN Register <b>35</b>, when used as a source in an instruction, also supplies operands to the execution datapath <b>44</b>. Each NN register <b>35</b> is written either by an external entity, not limited to, an adjacent programming engine, or by the same programming engine <b>16</b><i>a </i>where each NN register <b>35</b> resides. The specific register is selected by a context-relative operation where the register number is encoded in the instruction, or as a ring operation, selected via, e.g., NN_Put (NN write address) and NN_Get (NN read address) in the CSR Registers.

P-0039[0039] NN_Put registers are used when the previous neighboring programming engine executes an instruction with NN_Put as a destination. The NN register selected by the value in this register is written, and the value in NN_Put is then incremented (a value of 127 wraps back to 0). The value in this register is compared to the value in NN_Get register to determine when to assert NN_Full and NN_Empty status signals.

P-0040[0040] NN_Get registers are used when the NN register <b>35</b> is accessed as a source, which is specified in the source field of the instruction. The NN register selected by the value in this register is read, and the value in NN_Put is then decremented (a value of 127 wraps back to 0). The value in this register is compared to the value in the NN_Put register to determine when to assert NN_Full and NN_Empty status signals.

P-0041[0041] Specifically, when each NN register <b>35</b> is used as a destination in an instruction, the instruction result data are sent out of the programming engine <b>16</b><i>a</i>, typically to another, adjacent programming engine. On the other hand, when the NN register <b>35</b> is used as a destination in an instruction, the instruction result data are written to the selected NN Register <b>35</b> in the programming engine <b>16</b><i>a</i>. The data are not sent out of the programming engine <b>16</b><i>a </i>as it would be when each NN register <b>35</b> is used as a destination. Each NN register <b>35</b> is used in a context pipelining method, as described below.

P-0042[0042] A local memory <b>42</b> is also used. The local memory <b>42</b> includes addressable storage located in the programming engine <b>16</b><i>a</i>. The local memory <b>42</b> is read and written exclusively under program control. The local memory <b>42</b> also includes variables shared by all the programming engines <b>16</b>. Shared variables are modified in various assigned tasks during functional pipeline stages by the programming engines <b>16</b><i>a</i>-<b>16</b><i>h</i>, which are described next. The shared variables include a critical section, defining the read-modify-write times. The implementation and use of the critical section in the computing processing system <b>10</b> is also described below.

P-0043[0043] Functional Pipelining and Pipeline Stages

P-0044[0044] Referring to FIG. 3, the programming engine <b>16</b><i>a </i>is shown in a functional pipeline unit <b>50</b>. The functional pipeline unit <b>50</b> includes the programming engine <b>16</b><i>a </i>and a data unit <b>52</b> that includes data, operated on by the programming engine, e.g., network packets <b>54</b>. The programming engine <b>16</b><i>a </i>is shown having a local register unit <b>56</b>. The local register unit <b>56</b> stores information from the data packets <b>54</b>.

P-0045[0045] In the functional pipeline unit <b>50</b>, the contexts <b>58</b> of the programming engines <b>16</b><i>a</i>, namely, Programming Engine0.1 (PE0.1) through Programming Engine0.n (PEO.n), remain with the programming engine <b>16</b><i>a </i>while different functions are performed on the data packets <b>54</b> as time <b>66</b> progresses from time=0 to time=t. A programming execution time is divided into “m” functional pipeline stages or pipe-stages <b>60</b><i>a</i>-<b>60</b><i>m</i>. Each pipeline stage of the pipeline stages <b>60</b><i>a</i>-<b>60</b><i>m </i>performs different pipeline functions <b>62</b><i>a</i>, <b>64</b>, or <b>62</b><i>p </i>on data in the pipeline.

P-0046[0046] The pipeline stage <b>60</b><i>a </i>is, for example, a regular time interval within which a particular processing function, e.g., the function <b>62</b><i>a </i>is applied to one of the data packets <b>54</b>. A processing function <b>62</b> can last one or more pipelines stages <b>60</b>. The function <b>64</b>, for example, lasts two pipeline stages, namely pipeline stages <b>60</b><i>b </i>and <b>60</b><i>c. </i>

P-0047[0047] A single programming engine such as the programming engine <b>16</b><i>a </i>can constitute a functional pipeline unit <b>50</b>. In the functional pipeline unit <b>50</b>, the functions <b>62</b><i>a</i>, <b>64</b>, and <b>62</b><i>p </i>move through the functional pipeline unit <b>50</b> from one programming engine (e.g., programming engine <b>16</b><i>a</i>), to another programming engine (e.g., programming engine <b>16</b><i>b</i>), as will be described next.

P-0048[0048] Referring to FIG. 4, the data packets <b>54</b> are assigned to programming engine contexts <b>58</b> in order. Thus, if “n” threads or contexts <b>58</b> execute in the programming engine <b>16</b><i>a</i>, the first context <b>58</b>, “PE0.1” completes processing of the data packet <b>54</b> before the data packets <b>54</b> from the “PE0.n” context arrives. With this approach the programming engine <b>16</b><i>b </i>can begin processing the “n+1” packet.

P-0049[0049] Dividing the execution time of the programming engine <b>16</b><i>a</i>, for example, into functional pipeline stages <b>60</b><i>a</i>-<b>60</b><i>c </i>results in more than one of the programming engines <b>16</b> executing an equivalent functional pipeline unit <b>70</b> in parallel. The functional pipeline stage <b>60</b><i>a </i>is distributed across two programming engines <b>16</b><i>a </i>and <b>16</b><i>b</i>, with each of the programming engines <b>16</b><i>a </i>and <b>16</b><i>b </i>executing eight contexts each.

P-0050[0050] In operation, each of the data packets <b>54</b> remains with one of the contexts <b>58</b> for a longer period of time as more programming engines <b>16</b> are added to the functional pipeline units <b>50</b> and <b>70</b>. In this example, the data packet <b>54</b> remains with a context sixteen data packet arrival times (8 contexts×2 programming engines) because context PE0.1 is not required to accept another data packet <b>58</b> until the other contexts <b>58</b> have received their data packets.

P-0051[0051] In this example, function <b>62</b><i>a </i>of the functional pipeline stage <b>60</b><i>a </i>can be passed from the programming engine <b>16</b><i>a </i>to the programming engine <b>16</b><i>b</i>. Passing of the function <b>62</b><i>a </i>is accomplished by using Next Neighbor registers, as illustrated by dotted lines <b>80</b><i>a</i>-<b>80</b><i>c </i>in FIG. 4.

P-0052[0052] The number of functional pipeline stages <b>60</b><i>a</i>-<b>60</b><i>m </i>is equal to the number of the programming engines <b>16</b><i>a </i>and <b>16</b><i>b </i>in the functional pipeline units <b>50</b> and <b>70</b>. This ensures that a particular pipeline stage executes in only one programming engine <b>16</b> at any one time.

P-0053[0053] Context Pipelining:

P-0054[0054] Each of the programming engine <b>16</b> supports multi-threaded execution of eight contexts. One reason for this is to allow one thread to start executing just after another thread issues a memory reference and must wait until that reference completes before doing more work. This behavior is critical to maintaining efficient hardware execution of the programming engines <b>16</b><i>a</i>-<b>16</b><i>f </i>because memory latency is significant. Stated differently, if only a single thread execution was supported, the programming engine would sit idle for a significant number of cycles waiting for references to complete and thereby reduce overall computational throughput. Multi-threaded execution allows a programming engine to hide memory latency by performing useful independent work across several threads.

P-0055[0055] The programming engines <b>16</b><i>a</i>-<b>16</b><i>h </i>(FIG. 1) each have eight available contexts. To allow for efficient context swapping, each of the eight contexts in the programming engine has its own register set, program counter, and context specific local registers. Having a copy per context eliminates the need to move context specific information to/from shared memory and programming engine registers for each context swap. Fast context swapping allows a context to do computation while other contexts wait for I/O, typically external memory accesses, to complete or for a signal from another context or hardware unit.

P-0056[0056] Referring now to FIG. 5, the context for a specific assigned task is maintained on the programming engines <b>16</b><i>a</i>-<b>16</b><i>c </i>using CAM <b>45</b><i>a</i>-<b>45</b><i>c</i>. The packets are processed in a pipelined fashion similar to an assembly line using NN registers <b>35</b><i>a</i>-<b>35</b><i>c </i>to pass data from one programming engine to a subsequent, adjacent programming engine. Data are passed from one stage <b>90</b><i>a </i>to a subsequent stage <b>90</b><i>b </i>and then from stage <b>90</b><i>b </i>to stage <b>90</b><i>c </i>of the pipeline, and so forth. In other words, data are passed to the next stage of the pipeline allowing the steps in the processor cycle to overlap. In particular, while one instruction is being executed, the next instruction can be fetched, which means that more than one instruction can be in the “pipe” at any one time, each at a different stage of being processed.

P-0057[0057] For example, data can be passed forward from one programming engine <b>16</b> to the next programming engine <b>16</b> in the pipeline using the NN registers <b>35</b><i>a</i>-<b>35</b><i>c</i>, as illustrated by example in FIG. 5. This method of implementing pipelined processing has the advantage that the information included in CAM <b>45</b><i>a</i>-<b>45</b><i>c </i>for each stage <b>90</b><i>a</i>-<i>c </i>is consistently valid for all eight contexts of the pipeline stage. The context pipeline method may be utilized when minimal data from the packet being processed must advance through the context pipeline.

P-0058[0058] Referring to FIG. 6, as described above, context pipelining requires that the data resulting from a pipe stage, such as pipe stage P, be sent to the next pipe stage, e.g., pipe stage P+1 (<b>100</b>). Then, Next Neighbor registers can be written from the ALU output of the processing engine <b>16</b><i>a </i>in pipe stage P (<b>102</b>), and the Next Neighbor registers can be read as a source operand by the next programming engine <b>16</b><i>b </i>at the pipe stage P+1 (<b>104</b>).

P-0059[0059] Referring to FIG. 7, two processes may be used to determine the address of the Next Neighbor registers to be written in the programming engine <b>16</b><i>b</i>. In one process, each context of the programming engine <b>16</b><i>a </i>may write to the same Next Neighbor registers for the same context in programming engine <b>16</b><i>b </i>(<b>200</b>). In another method, a write pointer register in the programming engine <b>16</b><i>a </i>and a read pointer register in the programming engine <b>16</b><i>b </i>may be used (<b>300</b>) to implement an inter processing engine FIFO (<b>302</b>). The values of write pointer register in the programming engine <b>16</b><i>a </i>and the read pointer register in the programming engine <b>16</b><i>b </i>are used to produce a full indication checked by the programming engine <b>16</b> before inserting data onto the FIFO (<b>304</b>), and an empty indication may be used the programming engine <b>16</b><i>b </i>before removing data from the FIFO (<b>306</b>). The FIFO Next Neighbor configuration may provide the elasticity between contexts in the pipe stages P and P+1. When a context in the pipe stage P+1 finds the Next Neighbor FIFO is empty, that context can perform a No-op function, allowing the pipe stage to maintain a predetermined execution rate or “beat” even if the previous pipe stage may not be supplying an input at this same rate.

P-0060[0060] Other Embodiments:

P-0061[0061] In the examples described above in conjunction with FIGS. <b>1</b>-<b>7</b>, the computer processing system <b>10</b> may implement programming engines <b>16</b> using a variety of network processors.

P-0062[0062] It is to be understood that while the invention has been described in conjunction with the detailed description thereof, the foregoing description is intended to illustrate and not limit the scope of the invention, which is defined by the scope of the appended claims. Other aspects, advantages, and modifications are within the scope of the following claims.