Apparatus for forming modular sockets using flexible interconnects and resulting structures

CROSS-REFERENCE TO RELATED APPLICATIONS

0001[0001] This application is a continuation of application Ser. No. 10/158,979, filed May 30, 2002, pending, which is a continuation of application Ser. No. 09/876,805, filed Jun. 7, 2001, now U.S. Pat. No. 6,478,627, issued Nov. 12, 2002, which is a continuation of application Ser. No. 09/487,935, filed Jan. 20, 2000, now U.S. Pat. No. 6,319,065 B1, issued Nov. 20, 2001, which is a continuation of application Ser. No. 09/072,260, filed May 4, 1998, now U.S. Pat. No. 6,089,920, issued Jul. 18, 2000.

BACKGROUND OF THE INVENTION

0002[0002] 1. Field of the Invention

0003[0003] This invention relates generally to methods and apparatus for electrically connecting semiconductor devices to circuit boards. More particularly, the invention relates to a socket into which one or more bare semiconductor die may be inserted for connection to a circuit board without wire bonding of the contact pads of the semiconductor die.

0004[0004] 2. State of the Art

0005[0005] The assembly of a semiconductor device from a leadframe and semiconductor die ordinarily includes bonding of the die to a paddle of the leadframe, and wire bonding bond pads on the die to inner leads i.e. lead fingers of the leadframe. The inner leads, semiconductor die, and bond wires are then encapsulated, and extraneous parts of the leadframe excised, forming outer leads for connection to a substrate such as a printed wiring board (PWB).

0006[0006] The interconnection of such packaged integrated circuits (IC) with circuit board traces has advanced from simple soldering of package leads to the use of mechanical sockets, also variably known as connectors, couplers, receptacles and carriers. The use of sockets was spurred by the desire for a way to easily connect and disconnect a packaged semiconductor die from a test circuit, leading to zero-insertion-force (ZIF), and low-insertion-force (LIF) apparatus. Examples of such are found in U.S. Pat. No. 5,208,529 of Tsurishima et al., U.S. Pat. No. 4,381,130 of Sprenkle, U.S. Pat. No. 4,397,512 of Barraire et al., U.S. Pat. No. 4,889,499 of Sochor, U.S. Pat. No. 5,244,403 of Smith et al., U.S. Pat. No. 4,266,840 of Seidler, U.S. Pat. No. 3,573,617 of Randolph, U.S. Pat. No. 4,527,850 of Carter, U.S. Pat. No. 5,358,421 of Petersen, U.S. Pat. No. 5,466,169 of Lai, U.S. Pat. No. 5,489,854 of Buck et al., U.S. Pat. No. 5,609,489 of Bickford et al., U.S. Pat. No. 5,266,833 of Capps, U.S. Pat. No. 4,995,825 of Korsunsky et al., U.S. Pat. Nos. 4,710,134 and 5,209,675 of Korsunsky, U.S. Pat. No. 5,020,998 of Ikeya et al., U.S. Pat. No. 5,628,635 of Ikeya, U.S. Pat. No. 4,314,736 of Demnianiuk, U.S. Pat. No. 4,391,408 of Hanlon et al., and U.S. Pat. No. 4,461,525 of Griffin.

0007[0007] New technology has enabled the manufacture of very small high-speed semiconductor dice having large numbers of closely spaced bond pads. However, wire bonding of such semiconductor dice is difficult on a production scale. In addition, the very fine wires are relatively lengthy and have a very fine pitch, leading to electronic noise.

0008[0008] In order to meet space demands, much effort has been expended in developing apparatus for stack-mounting of packaged dies on a substrate in either a horizontal or vertical configuration. For. example, vertically oriented semiconductor packages having leads directly connected to circuit board traces are shown in U.S. Pat. No. 5,444,304 of Hara et al., U.S. Pat. No. 5,450,289 of Kweon et al., U.S. Pat. No. 5,451,815 of Taniguchi et al., U.S. Pat. No. 5,592,019 of Ueda et al., U.S. Pat. No. 5,619,067 of Sua et al., U.S. Pat. No. 5,635,760 of Ishikawa, U.S. Pat. No. 5,644,161 of Burns, U.S. Pat. No. 5,668,409 of Gaul, and United States Reissue Patent Re. 34,794 of Farnworth.

0009[0009] However, none of the above patents relates to the socket interconnection of a bare i.e. unpackaged semiconductor die to a substrate such as a circuit board.

0010[0010] Sockets also exist for connecting daughter circuit boards to a mother board, as shown in U.S. Pat. No. 5,256,078 of Lwee et al. and U.S. Pat. No. 4,781,612 of Thrush. U.S. Pat. No. 4,501,461 and Re. 28,171 of Anhalt show connectors for connecting a socket to a circuit board, and wiring to an electronic apparatus, respectively.

0011[0011] U.S. Pat. No. 5,593,927 of Farnworth et al. discloses a semiconductor die having an added protective layer and traces, and which is insertable into a multi-die socket. The conductive edges of the semiconductor die are connected through an edge “connector” to circuit board traces. The number of insertable semiconductor dice is limited by the number of semiconductor die compartments in the socket, and using fewer dice is a waste of space.

BRIEF SUMMARY OF THE INVENTION

0012[0012] A modular bare die socket is provided by which any number of bare (unpackaged) semiconductor dice having bond pads along the edge of one major side may be interconnected with a substrate in a densely packed arrangement. The socket is particularly applicable to high speed, e.g. 300 MHZ dice of small size or those dice of even faster speeds.

0013[0013] The socket comprises a plurality of plates which have a semiconductor die slot structure for aligning and holding a bare die or dice in a vertical orientation, and interconnect structure for aligning and retaining a multi-layer lead tape in contact with conductive bond pads of an inserted die. The interconnect lead tapes have outer ends which are joined to conductive traces on a substrate such as a printed wiring board (PWB).

0014[0014] Each lead tape includes a node portion which is forced against a bond pad to make resilient contact therewith. Various means for providing the contact force include a resilient lead tape, an elastomeric layer or member biasing the lead tape, or a noded arm of the plate, to which the lead tape is fixed.

0015[0015] A multi-layer interconnect lead tape may be formed from a single layer of polymeric film upon which a pattern of fine pitch electrically conductive leads is formed. Methods known in the art for forming lead frames, including negative or positive photoresist optical lithography, may be used to form the lead tape. The lead tape may be shaped under pressure to the desired configuration.

0016[0016] The plates with intervening interconnect lead tapes are bonded together with adhesive or other means to form a permanent structure.

0017[0017] The plates are formed of an electrically insulative material and may be identical. Each plate has “left side structure” and “right side structure” which work together with the opposing structure of adjacent plates to achieve the desired alignment and retaining of the semiconductor die and the lead tape for effective interconnection.

0018[0018] Any number of plates may be joined to accommodate the desired number of bare semiconductor dice. Assembly is easily and quickly accomplished. If desired, end plates having structure on only one side may be used to cap the ends of the socket.

0019[0019] Thus, a socket is formed as a dense stack of semiconductor die-retaining plates by which the footprint per semiconductor die is much reduced.

0020[0020] The modular socket is low in cost and effectively provides the desired interconnection. A short interconnect lead distance is achieved, leading to reduced noise. The impedance may be matched up to the contact or semiconductor die.

0021[0021] The primary use of the modular bare semiconductor die socket is intended to be for permanent attachment to circuit boards of electronic equipment where die replacement will rarely be required. Although the socket may be used in a test stand for temporarily connecting dice during testing, new testing techniques performed at the wafer scale generally obviate the necessity for such later tests.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

0022[0022] The invention is illustrated in the following figures, wherein the elements are not necessarily shown to scale:

0023[0023]FIG. 1 is a perspective view of a modular socket of the invention;

0024[0024]FIG. 2 is a perspective view of partially assembled modules of a modular socket of the invention;

0025[0025]FIG. 3 is a cross-sectional edge view of a portion of a modular socket of the invention, as generally taken along line <b>3</b>-<b>3</b> of FIG. 1 and having an exploded portion;

0026[0026]FIG. 4 is a perspective view of a multi-layer lead tape useful in a modular bare die socket of the invention;

0027[0027]FIG. 5 is a plan view of a multi-layer lead tape useful in a modular bare die socket of the invention;

0028[0028]FIG. 5A is a plan view of another embodiment of a multi-layer lead tape of a modular bare die socket of the invention;

0029[0029]FIG. 6 is a perspective view of a further embodiment of a multi-layer lead tape of a modular bare semiconductor die socket of the invention;

0030[0030]FIG. 7 is a perspective view of partially assembled modules of a further embodiment of a modular bare semiconductor die socket of the invention;

0031[0031]FIG. 8 is a perspective view of partially assembled modules of an additional embodiment of a modular bare semiconductor die socket of the invention;

0032[0032]FIG. 9 is a cross-sectional edge view of a portion of a further embodiment of a modular bare semiconductor die socket of the invention, as taken along line <b>3</b>-<b>3</b> of FIG. 1, and having an exploded portion;

0033[0033]FIG. 10 is a cross-sectional edge view of a portion of another embodiment of a modular bare semiconductor die socket of the invention, as taken along line <b>3</b>-<b>3</b> of FIG. 1;

0034[0034]FIG. 11 is a view of a semiconductor die for use in the modular bare semiconductor die socket of FIG. 10;

0035[0035]FIG. 12 is a view of the semiconductor die of FIG. 11 used in the modular bare semiconductor die socket of FIG. 10; and

0036[0036]FIG. 13 is a view of an alternative embodiment of the semiconductor die and modular bare semiconductor die socket of FIG. 12 illustrating a modified lead tape.

DETAILED DESCRIPTION OF THE INVENTION

0037[0037] As depicted in drawing FIG. 1, a modular bare die socket <b>10</b> of the invention comprises a plurality of modules <b>12</b>A, <b>12</b>B and <b>12</b>C formed of plates <b>14</b>A, <b>14</b>B, <b>14</b>C, and <b>14</b>D which are stacked perpendicular to a substrate <b>16</b>. A bare (unpackaged) semiconductor die <b>18</b> with conductive bond pads (not visible) near one edge on a major surface <b>20</b> thereof, e.g. the “active surface” may be inserted as shown into a die slot <b>22</b> and have its bond pads interconnected to conductive traces (not visible) on the surface <b>24</b> of the substrate <b>16</b>.

0038[0038] The internal structures of plates <b>14</b>C and <b>14</b>D are depicted in drawing FIG. 2. Each of the plates <b>14</b>A, <b>14</b>B, <b>14</b>C and <b>14</b>D has a first side <b>26</b> and an opposing second side <b>28</b>. The plates have first ends <b>30</b> having die slots <b>22</b>, and second ends <b>32</b> having lead slots <b>44</b> through which lead tapes pass.

0039[0039] In these figures, the first side <b>26</b> is taken as the left side of each plate and the second side <b>28</b> is taken as the right side. The regular plates <b>14</b>A, <b>14</b>B and <b>14</b>C have structure on both sides <b>26</b>, <b>28</b> and may be the exclusive plates of the socket <b>10</b>. The structure provides for accommodating bare semiconductor dice <b>18</b> of a particular size, number and spacing of bond pads, etc. and for electrically interconnecting the semiconductor dice <b>18</b> to a substrate <b>16</b>. Typically, all regular plates <b>14</b>A, <b>14</b>B, <b>14</b>C of a bare die socket <b>10</b> are identical but in some cases may differ to accommodate semiconductor dice of different size, bond pad configuration, etc. within different modules <b>12</b>A, <b>12</b>B, <b>12</b>C, etc. of a socket.

0040[0040] Alternatively, one or two end plates <b>14</b>D may be used to cap any number of intervening regular plates <b>14</b>A, <b>14</b>B and <b>14</b>C. In contrast to the regular plates <b>14</b>A, <b>14</b>B and <b>14</b>C, such end plates <b>14</b>D have cooperating structure on one side only, i.e. the internal side, and may simply have a flat exterior side which in drawing FIGS. 1, 2 and <b>3</b> is the second side <b>28</b>. Specifically designed end plates <b>14</b>D may be used on either, neither or both ends of the socket <b>10</b>, and have structure on one side to complement the facing side of the adjacent regular plate <b>14</b>A, <b>14</b>B, <b>14</b>C.

0041[0041] The structure of the second side <b>28</b> of the regular plates <b>14</b>A, <b>14</b>B and <b>14</b>C is shown as including an upwardly opening die slot <b>22</b> with a side wall <b>34</b>, edge walls <b>38</b>, and stop end wall <b>36</b> of lower beam <b>40</b>. Lower beam <b>40</b> has an exposed surface <b>42</b> which is one side of an interconnect lead slot <b>44</b>. The lower beam <b>40</b> is shown as having a width <b>41</b> exceeding width <b>46</b> for accommodating means for accurate alignment and retention of a multi-layer interconnect lead tape <b>50</b>, not shown in drawing FIG. 2 but to be described later in relation to drawing FIGS. 3 through 6.

0042[0042] The first sides <b>26</b> of plates <b>14</b>A, <b>14</b>B, <b>14</b>C and <b>14</b>D are as shown with respect to end plate <b>14</b>D. In this embodiment, first side <b>26</b> is largely flat with a recess <b>48</b> for accommodating portions of the interconnect lead tape. Recess <b>48</b> has a width <b>60</b> which is shown to approximate the width <b>46</b> of the die slot <b>22</b>, and has a depth <b>62</b> which is sufficient to take up the lead tape <b>50</b> when it is compliantly moved into the recess upon insertion of a semiconductor die <b>18</b> into die slot <b>22</b>.

0043[0043] The module <b>12</b>C including the first side of plate <b>14</b>D and the second side of plate <b>14</b>C has alignment posts <b>52</b> and matching holes <b>54</b> for alignment of the plates <b>14</b>C, <b>14</b>D to each other. Also shown are alignment/retention posts <b>56</b> and matching holes <b>58</b> for (a) aligning and retaining an interconnect lead tape <b>50</b> in the module, and for (b) aligning the plates <b>14</b>C, <b>14</b>D with each other. The posts <b>52</b>, <b>56</b> and matching holes <b>54</b>, <b>58</b> together comprise a module alignment system.

0044[0044] Mating portions of adjacent plates are joined by adhesive following installation of the lead tape <b>50</b> on alignment/retention posts <b>56</b>. Each of the posts <b>52</b>, <b>56</b> is inserted into holes <b>54</b>, <b>58</b> so that all of the plates <b>14</b>A, <b>14</b>B, <b>14</b>C and <b>14</b>D are precisely aligned with each other to form a monolithic socket <b>10</b>. In drawing FIG. 3, all of the regular plates <b>14</b>A, <b>14</b>B, and <b>14</b>C are identical.

0045[0045] In the views of drawing FIGS. 3 through 5, a multi-layer interconnect lead tape <b>50</b> is shown as comprised of a first insulative layer <b>64</b>, with a second layer <b>66</b> of conductive leads <b>70</b> fixed to it. The insulative layer <b>64</b> may be formed of a film of polymeric material such as polyimide, polyimide siloxane, or polyester. A conductive layer <b>66</b>, typically of metal, is formed on the insulative layer <b>64</b> in the form of individual leads <b>70</b>A, <b>70</b>B, <b>70</b>C, etc. Methods well-known in the industry for producing multi-layer lead frames may be used for forming the fine pitch leads <b>70</b> on the insulative layer <b>64</b>. Thus, for example, the leads <b>70</b> may be formed by combining metal deposition with optical lithography using either a positive or negative photoresist process. Any method capable of providing fine pitch leads <b>70</b> on the first layer <b>64</b> of the lead tape <b>50</b> may be used.

0046[0046] The lead tape <b>50</b> has an upper portion <b>72</b> which is configured with a total width <b>76</b> of leads <b>70</b> which generally spans the semiconductor die <b>18</b>, but will be less than width <b>46</b> of die slot <b>22</b> (see FIG. 2). A lower portion <b>74</b> has a greater width <b>78</b> which may correspond generally to width dimension <b>41</b> of the lower beam <b>40</b> (see FIG. 2). Alignment apertures <b>80</b>, <b>82</b> are formed in the lower portion <b>74</b> to be coaxial along axes <b>84</b>, <b>86</b>, respectively, with alignment/retention posts <b>56</b>.

0047[0047] The upper portion <b>72</b> includes lead portions which contact the bond pads <b>90</b> of the dice. The lower portion <b>74</b> includes lead portions which are joined to substrate <b>16</b>.

0048[0048] In the embodiments of drawing FIGS. 3, 4, <b>5</b> and <b>5</b>A, the lead tape <b>50</b> is shown as being formed in the general shape of the letter “S.” A contact node <b>88</b> is formed in each lead <b>70</b> in the upper portion <b>72</b> by forming the upper portion as a bend. The node <b>88</b> is configured to be pushed away by contact with a bond pad <b>90</b> of a semiconductor die. The resistance to bending of the lead produces compression therebetween and enables consistent electrical contact with the bond pad <b>90</b> of a semiconductor die. Where the surfaces of the bond pads <b>90</b> of the semiconductor die <b>18</b> are essentially coplanar, contact between the bond pads <b>90</b> and the leads <b>70</b> is maintained. The compressive force between the semiconductor die <b>18</b> and the leads <b>70</b> is dependent upon the particular material of insulative layer <b>64</b> and its thickness, the thickness and material of conductive layer <b>66</b>, and lead displacement from the unbiased position which results from die insertion. Typically, the insulative layer <b>64</b> may vary in thickness from about 12 to about 300 μm. The preferred thickness of the conductive layer <b>66</b> is about 25 to about 75 μm. The total thickness of the combined first and second layers of the lead tape <b>50</b> is preferred to be from about 75 μm to about 100 μm.

0049[0049] The lower ends <b>92</b> of leads <b>70</b> are shown as bent to a nearly horizontal position for surface attachment to a substrate <b>16</b>.

0050[0050] The lower ends <b>92</b> are shown as having the insulative layer <b>64</b> removed to provide a metal surface for attachment by soldering or other method to a substrate <b>16</b>.

0051[0051] In a variation of the lead tape <b>50</b> shown in drawing FIG. 5A, the upper ends of the leads <b>70</b>, i.e. the leads in the upper portion <b>72</b>, may have both the insulative layer <b>64</b> and conductive layer <b>66</b> removed between the leads, thereby singulating them. Each lead <b>70</b> retains both layers <b>64</b>, <b>66</b> for retaining a required resistance to bending in each lead. Thus, each lead is independently compliant with respect to an inserted semiconductor die <b>18</b> to retain conductive contact with a bond pad <b>90</b> on the semiconductor die <b>18</b>.

0052[0052] An alternative embodiment of the interconnect lead tape <b>50</b> is depicted in drawing FIG. 6. The lower ends <b>92</b> of leads <b>70</b> are bent in the opposite direction from drawing FIGS. 5 and 5A and in addition, the insulative layer <b>64</b> is not removed from the lower ends <b>92</b>.

0053[0053] The lead tape <b>50</b> may be bent to the desired shape by a suitable stamping tool or the like, wherein the “at-rest” shape is uniform from tape to tape.

0054[0054] The placement of the module components, i.e. the die slot <b>22</b>, lower beam <b>40</b>, interconnect lead slot <b>44</b>, and recess <b>48</b> may be varied in the longitudinal direction <b>94</b> (see FIG. 3) of the plates, and may be apportioned in any convenient way between the first side <b>26</b> of one plate and the facing second side <b>28</b> of an adjacent plate.

0055[0055] Turning now to drawing FIGS. 7, 8 and <b>9</b>, several other embodiments of the modular socket <b>10</b> are illustrated. As depicted in drawing FIG. 7, a plurality of regular plates <b>14</b>A, <b>14</b>B and <b>14</b>C and an end plate <b>14</b>D, the plates providing for an interconnect lead tape <b>50</b> using a compressible elastomeric member <b>96</b> to bias the tape to the bond pads <b>90</b> of the semiconductor die <b>18</b>. The elastomeric member may be formed of silicone foam, solid silicone that has been perforated, or low durometer hardness silicone which is attached to the tape by adhesive. The elastomeric member <b>96</b> may be variably shaped as a narrow strip <b>96</b>A with limited biasing strength to a more general coverage <b>96</b>B with greater biasing strength. Both are illustrated in drawing FIG. 9. The narrow strip <b>96</b>A is intended to be used in the module design of drawing FIG. 7, and the high coverage member <b>96</b>B may be used in the module embodiment of drawing FIG. 8, wherein sufficient space is provided in the interconnect lead slot <b>44</b> for the elastomeric member. Preferably, the elastomeric member <b>96</b>A or <b>96</b>B comprises a single continuous unit extending across all of the leads <b>70</b>. Alternatively, a series of elastomeric members <b>96</b> may be arrayed on the tape <b>50</b>.

0056[0056] Referring to drawing FIG. 10, illustrated is another form of the invention, in which the compliant member of a module <b>12</b> comprises a projecting portion <b>100</b> of the plate <b>14</b>. The projecting portion <b>100</b> may be in the form of a ledge, as shown in the figure, and includes a longitudinal ridge <b>102</b> within a recess <b>48</b> in the side <b>26</b>. A multi-layer interconnect lead tape is attached, e.g. by adhesive to the projecting portion <b>100</b> and ridge <b>102</b>. The resulting node <b>104</b> in the lead tape <b>50</b> is forced away by an inserted die <b>18</b> and forcibly abuts the bond pads on the die surface <b>20</b>. The force holding the leads <b>70</b> against inserted bond pads <b>90</b> of a semiconductor die <b>18</b> will depend upon the distance <b>106</b> from the node <b>104</b> to the attachment point <b>108</b> of the ridge <b>102</b>. In order to provide the desired effect, the polymeric material of the plate <b>14</b> and projecting portion <b>100</b> is selected in combination with distance <b>106</b> and ledge thickness <b>110</b>. In this embodiment, it is unnecessary for the lead tape <b>50</b> to be aligned and retained on alignment posts.

0057[0057] Where a bare semiconductor die <b>18</b> has two rows of bond pads <b>90</b>, illustrated in drawing FIG. 11 as first row <b>112</b> and second row <b>114</b>, the lead tape <b>50</b> of the modular socket <b>10</b> may be adapted for lead contact with both rows. A lead tape <b>50</b> for providing contact with two rows <b>112</b>, <b>114</b> of bond pads <b>90</b> is shown in drawing FIG. 12. The tape <b>50</b> comprises three layers including a first insulative layer <b>64</b>, a second conductive layer <b>66</b> for contacting the first row <b>112</b> of bond pads <b>90</b>, and a third conductive layer <b>68</b> for contacting the second row <b>114</b> of bond pads on the die <b>18</b>. The first and second layers <b>64</b>, <b>66</b> are terminated at locations <b>116</b>, <b>118</b>, respectively, between the first and second rows <b>112</b>, <b>114</b> of bond pads. An elastomeric member <b>96</b>C such as a foam is attached to the third layer <b>68</b> and abuts the recess wall <b>120</b>. The member <b>96</b>C is compressed by insertion of the semiconductor die <b>18</b> into the socket and retains forced contact between the leads and bond pads.

0058[0058] As shown in drawing FIG. 13, the first (insulative polymer) layer <b>64</b> may alternatively be provided with holes <b>122</b> through which individual leads <b>70</b> of the third (conductive) layer <b>68</b> are preinserted for contact with the second row <b>114</b> of bond pads <b>90</b>.

0059[0059] The foregoing delineates several examples of the use of a multi-layer lead tape with means for contacting the bond pads of a bare die. Other types of biasing apparatus may be used for maintaining contact between interconnect leads <b>70</b> and the bond pads <b>90</b> of a semiconductor die <b>18</b>, including mechanical springs suitable for the miniature devices.

0060[0060] The plates <b>14</b>A, <b>14</b>B, <b>14</b>C, <b>14</b>D, etc. may be molded of a suitable insulative polymeric material, examples of which include polyether sulfone, polyether ether ketone (PEEK), or polyphenylene sulfide.

0061[0061] Following assembly of the modular socket <b>10</b> and attachment to a substrate <b>16</b>, the modular socket, or portions thereof, may be “glob-topped” with insulative sealant material, typically a polymer.

0062[0062] The socket <b>10</b> of the invention permits connection of bare semiconductor dice with very fine pitch bond pads to substrates, whereby short leads are used for improved performance. The semiconductor dice may be readily replaced without debonding of wires or other leads. Multiple semiconductor dice may be simultaneously connected to a substrate, and the apparatus permits high density “stacking” of a large number of dice. The socket uses leads which may be produced by well-developed technology, and is easily made in large quantity and at low cost.

0063[0063] It is apparent to those skilled in the art that various changes and modifications may be made to the bare die socket module of the invention, sockets formed therefrom and methods of making and practicing the invention as disclosed herein without departing from the spirit and scope of the invention as defined in the following claims. It is particularly noted that with respect to numbers and dimensions of elements, the illustrated constructions of the various embodiments of the modular bare semiconductor die socket are not presented as a limiting list of features but as examples of the many embodiments of the invention.