Semiconductor device and its manufacturing method

TECHNICAL FIELD

[0001] The present invention relates to field effect transistors including a heterojunction for a channel region, and more particularly relates to countermeasures against variation in threshold voltage of a field effect transistor.

BACKGROUND ART

[0002] In recent years, portable communication terminals represented by cellular phones are widely used. Such portable terminals are generally driven by batteries and it is strongly desired to reduce power consumption without sacrificing operation speed in portable terminals in order to prolong the lifetime of batteries. To achieve a portable communication terminal with low power consumption without reducing operation speed, it is effective to increase drain saturation current to maintain current driveability while lowering threshold voltage to reduce supply voltage in the portable terminal. To satisfy such demands, there have been many studies on heterojunction MOS transistors (which will be hereinafter called “hetero MOS”) using as a channel region a material with high-mobility carriers.

[0003] In a known MOS transistor, carriers travel along the interface between a gate oxide film and a silicon substrate. Energy level largely fluctuates around the interface between the gate oxide film that is an amorphous layer and the silicon substrate that is a crystal layer. Because of the energy level fluctuation, carriers are easily affected by interface scattering in the known MOS transistor, resulting in problems such as reduction of carrier mobility and increase in noise.

[0004] On the other hand, in the hetero MOS, which is a MOS transistor including a semiconductor heterojunction for a channel region, a semiconductor heterojunction interface is formed at a depth with a small distance apart from the gate insulating film of a semiconductor substrate. A channel is formed at the semiconductor heterojunction interface and carriers travel along the channel. The semiconductor heterojunction interface is an interface where crystal layers are joined together, and thus energy level at the interface does not fluctuate widely. Therefore, the influence of interface scattering on carriers is small. Accordingly, the hetero MOS has a great current driveability and an excellent characteristic of reduction in noise. Furthermore, the hetero MOS has another characteristic that its threshold voltage can be lower than that of the known MOS transistor.

[0005] Problems to be Solved

[0006] However, in the hetero MOS including a heterojunction for a channel region, the channel region is embedded and therefore threshold voltage largely depends on the thickness of an Si cap region.

[0007]FIG. 15 illustrates the structure of a known hetero MOS.

[0008] As shown in FIG. 15, the known hetero MOS <b>100</b> includes an Si substrate <b>101</b>, a gate insulating film <b>102</b> formed on the Si substrate <b>101</b>, a gate electrode <b>103</b> which is formed of polysilicon containing a p-type impurity of high concentration on the gate insulating film <b>102</b>, and a sidewall spacer <b>104</b> which is formed on the gate insulating film <b>102</b> to cover side faces of the gate electrode <b>103</b>. The Si substrate <b>101</b> includes p-type source and drain regions <b>105</b> and <b>106</b> which are formed on both sides of the gate electrode, an n-type Si cap region <b>107</b> formed in a region located between the source and drain regions <b>105</b> and <b>106</b>, an n-type SiGe channel region <b>108</b> formed under the Si cap region, <b>107</b> an n-type Si buffer region <b>109</b> formed under the SiGe channel region <b>108</b>, and an n-type Si body region <b>110</b> formed under the Si buffer region <b>109</b>.

[0009]FIG. 16 shows the results obtained from simulations of dependency of threshold voltage on the thickness of the Si cap region <b>107</b> in the known hetero MOS <b>100</b>.

[0010] As shown in FIG. 16, as the thickness of the Si cap region <b>107</b> is increased, the absolute value for its threshold voltage remarkably increases. In other words, the threshold voltage is remarkably increased. This is because as the position at which the channel is formed (i.e., the interface between the Si cap region <b>107</b> and the SiGe channel region <b>108</b>) is located a more distance apart from the gate electrode, i.e., further in depth, the potential at the channel changes less enough according to the gate voltage.

[0011] In terms of processing, however, the thickness of the Si cap region <b>107</b> is reduced through fabrication processes such as an SiO₂thermal oxide film formation process and a cleaning process, and thus it is very difficult to control the thickness of the Si cap region <b>107</b>. Therefore, nonuniformity in the thickness of the Si cap region <b>107</b> can be easily caused. Accordingly, variation in threshold voltage is easily caused and therefore there may be cases where a desired operation can not be performed because of increased threshold voltage.

[0012] Particularly, in an integrated circuit including a plural number of identical transistors, variation in threshold voltage among the transistors causes gaps of switching time among the transistors. As a result, the timing gaps among the transistors in the integrated circuit occur, so that the integrated circuit may not operate properly. Moreover, under consideration of variation in threshold voltage among the transistors, in order to ensure an operation margin, the latest switching timing should be set as a standard timing and therefore it is difficult to increase in operation speed of the integrated circuit.

DISCLOSURE OF INVENTION

[0013] The present invention has been contrived in order to solve the foregoing problems and an object of the present invention is to provide a semiconductor device in which an increase in threshold voltage is suppressed.

[0014] A semiconductor device according to the present invention includes: a substrate; a semiconductor layer formed in an upper part of the substrate; a gate insulating film formed on the semiconductor layer; a gate electrode formed on the gate insulating film; first source/drain regions of a first conductivity type formed on both sides of the gate electrode in the semiconductor layer, respectively; a first cap region of the first conductivity type which is formed of a first semiconductor in a region of the semiconductor layer which is located between the first source/drain regions; a first channel region which is formed under the first cap region in the semiconductor layer and formed of a second semiconductor which has a lower potential for carriers at a band edge along which the carriers travel than the corresponding potential of the first semiconductor; and a first body region of a second conductivity type which is formed of a third semiconductor under the first channel region in the semiconductor layer.

[0015] The inventive semiconductor has the structure in which the first cap region of the first conductivity type which is formed of the first semiconductor, the first channel region which is formed under the first cap region and of the second semiconductor in which at a band edge along which the carriers travel than the corresponding potential of the first semiconductor, and the first body region of the second conductivity type which is formed of the third semiconductor under the first channel region in the semiconductor layer. Accordingly, it is possible to achieve a semiconductor device in which an increase in threshold voltage according to an increase in the thickness of the first cap region is suppressed.

[0016] The gate electrode and the first body electrode may be electrically connected to each other.

[0017] Accordingly, when a gate bias voltage is applied to the gate electrode, forward bias voltage at the same level as the gate bias voltage is applied to the first channel region via the first body region. Therefore, when the gate bias is OFF, the inventive semiconductor device is in the same state as a regular MOS transistor, whereas when the gate bias is ON, the first body region is biased in the forward direction as the gate bias voltage is increased, and thus threshold voltage is reduced. That is to say, a semiconductor device which is operable with a lower threshold voltage can be achieved. Moreover, by forming the semiconductor device in the structure in which the gate electrode and the first body region are electrically connected to each other, the amount of variation in threshold voltage according to nonuniformity in the thickness of the first cap region can be further reduced.

[0018] The inventive semiconductor device has the structure in which the cap region is depleted when a gate bias is applied thereto.

[0019] It is preferable that the concentration of an impurity of the first conductivity contained in the first cap region is 1×10¹⁷atoms·cm⁻³or more.

[0020] It is preferable that the impurity of the first conductivity type is doped into the first cap region so that at zero bias the potential at a channel which is formed at the interface between the first channel region and the first cap region changes within the range of ±0.05 eV according to nonuniformity in the thickness of the first cap region.

[0021] Accordingly, it is possible to achieve a semiconductor device in which variation in threshold voltage is suppressed even if nonuniformity in the thickness of the cap region occurs.

[0022] It is preferable that the concentration of an impurity of the second conductivity type contained in the first body region is 5×10¹⁸atoms·cm⁻³or more.

[0023] Accordingly, the body current generated in the lateral parasitic bipolar transistor can be suppressed and kept at a low level. Furthermore, when a voltage is applied to between the source/drain regions, a depletion layer from the source/drain regions can be prevented from expanding. Therefore, even when the concentration of the impurity in the body region is increased, the threshold voltage can be kept at a low level. As a result, the short channel effect that is caused when the gate length is shortened can be prevented.

[0024] It is preferable that the thickness of the first cap region is 10 nm or less.

[0025] The first semiconductor may be silicon.

[0026] The inventive semiconductor device may be formed in the structure in which the second semiconductor is made of silicon and at least one of germanium and carbon.

[0027] The inventive semiconductor device may further include: an additional semiconductor layer formed in an upper part of the substrate; an additional gate insulating film formed on the additional semiconductor layer; an additional gate electrode formed on the additional gate insulating film; additional first source/drain regions of the first conductivity type formed on both sides of the additional gate electrode in the additional semiconductor layer, respectively; an additional first cap region of the first conductivity type which is formed of the first semiconductor in a region of the additional semiconductor layer which is located between the additional first source/drain regions; an additional first channel region which is formed of the second semiconductor under the additional first cap region in the additional semiconductor layer; and an additional first body region of the second conductivity type which is formed of the third semiconductor under the additional first channel region in the additional semiconductor layer.

[0028] Accordingly, even if nonuniformity in the thickness of the first cap region is caused in a fabrication process or between fabrication processes, it is possible to achieve a semiconductor device in which variation in threshold voltage between transistors is suppressed.

[0029] The inventive semiconductor device may include: an additional semiconductor layer formed in an upper part of the substrate; an additional gate insulating film formed on the additional semiconductor layer; an additional gate electrode formed on the additional gate insulating film; second source/drain regions of the second conductivity type formed on both sides of the additional gate electrode in the additional semiconductor layer, respectively; a second channel region formed of a fourth semiconductor in a region of the additional semiconductor layer which is located between the second source/drain regions; and a second body region of the first conductivity type which is formed of a fifth semiconductor under the second channel region in the additional semiconductor layer, and the semiconductor device may be formed in the structure that can function as a complementary device.

[0030] It is preferable that the second channel region is of the second conductivity type.

[0031] Accordingly, variation in threshold voltage in a transistor formed on the additional semiconductor layer can be suppressed.

[0032] The gate electrode and the first body region may be electrically connected to each other and the additional gate electrode and the second body region may be electrically connected to each other.

[0033] A method for fabricating a semiconductor device according to the present invention includes the steps of: a) forming in an upper part of a semiconductor substrate a first semiconductor layer including a first semiconductor region into which an impurity of a first conductivity type is doped and a second semiconductor region into which an impurity of a second conductivity type is doped as a complementary device; b) forming on the first semiconductor layer a second semiconductor layer and a third semiconductor layer which is formed of a semiconductor having a wider band gap than the second semiconductor layer; c) forming a mask on part of the third semiconductor layer located in the first semiconductor region, and then introducing an impurity of the first conductivity type into part of the third semiconductor located at least in the second semiconductor region, using the mask; d) removing the mask and then forming a gate insulating film and a gate electrode on part of the third semiconductor layer located in the first semiconductor region and part of the third semiconductor layer located in the second semiconductor region, respectively; and e) forming source/drain regions of the second conductivity type and source/drain regions of the first conductivity type in the first semiconductor region and in the second semiconductor region, respectively, by implanting ions of respective impurities into the first, second and third semiconductor layers using each of the gate electrodes as a mask.

[0034] According to the present invention, it is possible to achieve a semiconductor device which functions as a complementary device in which variation in threshold voltage in a hetero MIS formed in the second semiconductor region due to nonuniformity in the thickness of the third semiconductor layer that is to be the cap region can be suppressed. Furthermore, according to the present invention, no impurity of the first conductivity type is doped into the part of the third semiconductor layer which is located in the first semiconductor region. Therefore, in a semiconductor device which can be achieved according to the inventive method and functions as a complementary device, characteristics of a hetero MIS formed in the first semiconductor region are not degenerated.

[0035] It is preferable that in the step c), ions of the impurity of the first conductivity type are implanted so that the peak of the concentration profile of the impurity of the first conductivity type is in the second semiconductor layer or the third semiconductor layer.

[0036] Accordingly, variation in threshold voltage in a transistor formed in the first semiconductor region can be suppressed.

BRIEF DESCRIPTION OF DRAWINGS

[0037]FIG. 1 is a view illustrating the cross-sectional structure of a hetero MOS in accordance with the present invention.

[0038]FIG. 2 is a graph showing the correlation between threshold voltage and the thickness of an Si cap region for a known hetero MOS and the hetero MOS of the present invention.

[0039] FIGS. <b>3</b>(<i>a</i>) through <b>3</b>(<i>c</i>) are graphs showing band profiles at zero bias in three types of hetero MOS devices having the impurity profiles used for the simulations of FIG. 2.

[0040]FIG. 4 is a graph showing the Vg-Id characteristics of three types of hetero MOS devices including different Si cap regions.

[0041]FIG. 5 is a graph on which the peak concentrations of holes stored in a channel and a parasitic channel are plotted against gate voltage in a hetero MOS.

[0042]FIG. 6 is a view illustrating the cross-sectional structure of a hetero DTMOS in accordance with the present invention.

[0043]FIG. 7 is a plan view of the hetero DTMOS of the present invention.

[0044]FIG. 8 is a graph showing the correlation between threshold voltage and the thickness of an Si cap region for a known hetero DTMOS and the hetero DTMOS of the present invention.

[0045]FIG. 9 is a graph showing the results obtained from simulations of the Vg-Id characteristics of the known hetero DTMOS and the hetero DTMOS of the present invention.

[0046]FIG. 10 is a graph showing the Vg-Id characteristics of the known hetero DTMOS and the hetero DTMOS of the present invention.

[0047]FIG. 11 is a view illustrating the cross-sectional structure of a complementary hetero MOS in accordance with the present invention in which an SiGe layer is used as a channel region and an Si/SiGe heterojunction is utilized.

[0048]FIG. 12 includes cross-sectional views showing process steps of a method for fabricating the complementary hetero MOS of the present invention.

[0049]FIG. 13(<i>a</i>) is an illustration showing band profiles of a p-hetero MOS included in the complementary hetero MOS of the present invention when a gate bias voltage is applied whereas FIG. 13(<i>b</i>) is an illustration showing band profiles of an n-hetero MOS included in the complementary hetero MOS of the present invention when a gate bias voltage is applied.

[0050]FIG. 14 is an illustration showing the Ge contents and impurity profiles in an Si body region, an Si buffer region, an SiGe channel region and an Si cap region of a p-hetero MOS included in the complementary hetero MOS.

[0051]FIG. 15 is a cross-sectional view illustrating the structure of the known hetero MOS.

[0052]FIG. 16 is a graph showing the results obtained from simulations of dependency of threshold voltage on the thickness of the Si cap region in the known hetero MOS.

BEST MODE FOR CARRYING OUT THE INVENTION

[0053] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. For the sake of simplicity, components common to the embodiments are identified by the same reference numerals.

[0054] (Embodiment 1)

[0055] First, the structure of a hetero MOS in accordance with this embodiment will be described. FIG. 1 illustrates the cross-sectional structure of a p-channel hetero MOS <b>10</b> of this embodiment in which a SiGe layer is used as a channel region and an Si/SiGe heterojunction is utilized.

[0056] As shown in FIG. 1, the p-channel hetero MOS <b>10</b> of this embodiment includes a p-type Si substrate <b>11</b>, a gate insulating film <b>12</b> which is formed of an SiO₂film (having a thickness of about 6 nm) on the Si substrate <b>11</b>, a gate electrode <b>13</b> which is formed of polysilicon containing a p-type impurity of high concentration on the gate insulating film <b>12</b>, and a sidewall spacer <b>14</b> which is formed on the gate insulating film <b>12</b> to cover the side faces of the gate electrode <b>13</b>.

[0057] The p-channel hetero MOS <b>10</b> of this embodiment shown in FIG. 1 includes an Si layer <b>15</b>, which has been formed in an upper part of the Si substrate <b>11</b> by introducing an n-type impurity of high concentration (2×10¹⁸atoms·cm⁻³) by ion implantation before crystals are grown in a semiconductor fabrication process. On the Si layer <b>15</b>, an Si layer <b>16</b>, an SiGe layer <b>17</b> and an Si layer <b>18</b> are epitaxially grown in this order by a UHV-CVD method.

[0058] Furthermore, in the p-channel hetero MOS <b>10</b> of this embodiment, source and drain regions <b>19</b> and <b>20</b> which contain a p-type impurity of high concentration are formed in regions of the Si layer <b>15</b>, the Si layer <b>16</b>, the SiGe layer <b>17</b> and the Si layer <b>18</b> which are located on the sides of the gate electrode <b>13</b>.

[0059] A region of the Si layer <b>15</b> located between the source and drain regions <b>19</b> and <b>20</b> is an Si body region <b>21</b> containing the n-type impurity of high concentration. The Si layer <b>16</b> and the SiGe layer <b>17</b> are both undoped layers into which no n-type impurity is doped in an as-grown state. Regions of the Si layer <b>16</b> and the SiGe layer <b>17</b> located between the source and drain regions <b>19</b> and <b>20</b> are an Si buffer region <b>22</b> and an SiGe channel region <b>23</b>, respectively, which contain the n-type impurity of low concentration. A region of the Si film <b>18</b> located directly under the gate insulating film <b>12</b> is an Si cap region <b>24</b> into which a p-type impurity (5×10¹⁷atoms·cm⁻³) is introduced. The gate insulating film <b>12</b> is formed by thermally oxidizing the Si layer <b>18</b>. When the p-channel hetero MOS <b>10</b> of this embodiment is in operation, a gate bias voltage applied to the gate electrode <b>13</b> causes the SiGe channel region <b>23</b> and the Si cap region <b>24</b> to deplete and holes to travel along the SiGe channel region <b>23</b>.

[0060] The thickness of the Si layer <b>16</b> is 10 nm and the thickness of the SiGe layer <b>17</b>, i.e., the thickness of the SiGe channel region <b>23</b>, is 15 nm. The Ge content in the SiGe channel region <b>23</b> is 30%.

[0061]FIG. 2 shows the correlation between threshold voltage and the thickness of the Si cap region for the known hetero MOS <b>100</b> and the hetero MOS <b>10</b> of this embodiment.

[0062] In the known hetero MOS <b>100</b>, an n-type impurity is doped into the Si cap region <b>107</b>. The correlation between threshold voltage and the Si cap region for the known hetero MOS <b>100</b> is indicated by the dash-single-dot line (A) shown in FIG. 2.

[0063] On the other hand, as for the hetero MOS <b>10</b> of this embodiment including the Si cap region <b>24</b> into which the p-type impurity is doped at a concentration of about 5×10¹⁷atoms·cm⁻³, the correlation between threshold voltage and the thickness of the Si cap region is indicated by the solid line (B) shown in FIG. 2. As can be seen from FIG. 2, as for the hetero MOS <b>10</b> of this embodiment, the variation in threshold voltage is small, compared to the known hetero MOS <b>100</b>. Furthermore, at an increased concentration of the p-type impurity in the Si cap region <b>24</b> (i.e., a concentration of the p-type impurity of 1×10¹⁸atoms·cm⁻³), in contrast to the known hetero MOS <b>100</b>, the absolute value for threshold voltage becomes smaller, i.e., the threshold voltage decreases, as the thickness of the Si cap region <b>24</b> is increased, as indicated by the broken line (C) in FIG. 2. This is because the thickness of the Si cap region <b>24</b> is increased in the highly doped region and thereby the potential at the SiGe channel region <b>23</b> is reduced.

[0064] Accordingly, by doping a p-type impurity into the Si cap region <b>24</b>, an increase in threshold voltage can be suppressed even when the thickness of the Si cap region <b>24</b> is increased because of fluctuation in a fabrication process and a difference between fabrication processes.

[0065] As for the known hetero MOS <b>100</b>, the thickness of the Si cap region <b>107</b> is reduced through an SiO₂thermal oxide film formation process, a cleaning process and the like during fabrication processes and thus it is very difficult to control the thickness of the Si cap region <b>107</b>. Therefore, a difference in the thickness of the Si cap region <b>107</b> can be easily caused. This causes variation in threshold voltage even in a wafer and among identical wafers, which has been a big problem of the known hetero MOS.

[0066] According to this embodiment, however, by properly doping a p-type impurity into the Si cap region <b>24</b>, variation in threshold voltage can be suppressed even if a difference in the thickness of the Si cap region <b>24</b> occurs between fabrication processes. Further description of how the variation in threshold voltage can be suppressed will be made with reference to FIG. 3.

[0067] FIGS. <b>3</b>(<i>a</i>) through <b>3</b>(<i>c</i>) are graphs illustrating the band profiles at zero bias for three types of hetero MOS devices having the impurity profiles used in the simulations of FIG. 2. FIGS. <b>3</b>(<i>a</i>) through <b>3</b>(<i>c</i>) each illustrate four different band profiles in the respective cases where the thickness of the Si cap region <b>24</b> is 1 nm, 2 nm, 5 nm, or 10 nm.

[0068] As shown in FIG. 3(<i>a</i>), in the known hetero MOS <b>100</b>, the absolute value for the potential at the valance band in the SiGe channel region <b>23</b> (the convex upward slope segment in FIG. 3(<i>a</i>)) increases as the thickness of the Si cap region <b>24</b> is increased. This causes an increase in threshold voltage.

[0069] On the other hand, as shown in FIG. 3(<i>b</i>), in the hetero MOS <b>10</b> of this embodiment in which the p-type impurity at about 5×10¹⁷atoms·cm⁻³is doped into the Si cap region <b>24</b>, even if nonuniformity in the thickness of the Si cap region <b>24</b> occur, the potential at the valence band in the SiGe channel region <b>23</b> (the convex upward slope segment in FIG. 3(<i>b</i>)) is kept almost constant and the potential at an edge of the valence band around the interface between the SiGe channel region <b>23</b> and the Si cap region <b>24</b> changes within the range of ±0.05 eV. That is to say, variation in threshold voltage is suppressed.

[0070] Furthermore, when the concentration of the p-type impurity that is doped into the Si cap region <b>24</b> is increased, as shown in FIG. 3(<i>c</i>), the absolute value for the potential at the valence band in the SiGe channel region <b>23</b> (the convex upward slope segment in FIG. 3(<i>c</i>)) reduces as the thickness of the Si cap region <b>24</b> is increased. This reduction corresponds to the reduction in threshold voltage indicated by the broken line in FIG. 2.

[0071] From the foregoing description, it can be understood that in order to suppress variation in threshold voltage due to nonuniformity in the thickness of the Si cap region <b>24</b>, the concentration of an impurity to be doped can be set such that the potential at the SiGe channel region <b>23</b> is kept almost constant.

[0072] Next, the Vg-Id characteristics of the three types of hetero MOS devices each including a Si cap region of a different impurity concentration will be shown in FIG. 4. FIG. 4 shows the results obtained from simulations of the Vg-Id characteristics of the three types of hetero MOS devices shown in FIGS. 2 and 3. In this case, the thicknesses of the Si cap region <b>24</b> and the Si cap region <b>107</b> are both 5 nm.

[0073] As shown in FIG. 4, in the hetero MOS <b>10</b> of this embodiment indicated by the solid line (B) in which the p-type impurity at about 5×10¹⁷atoms·cm⁻³is doped into the Si cap region <b>24</b>, a predetermined drain current can flow at a lower gate voltage than in the known hetero MOS <b>100</b> indicated by the dash-single-dot line (A). Furthermore, when the concentration of the p-type impurity that is doped into the Si cap region <b>24</b> is increased, a predetermined drain current can flow at a further lower gate voltage as indicated by the broken line (C).

[0074] As can be understood from the foregoing description, the hetero MOS <b>10</b> of this embodiment in which the p-type impurity is doped into the Si cap region <b>24</b> can achieve the effect that threshold voltage can be lower than that in the known hetero MOS <b>100</b>. In order to suppress variation in threshold voltage in a hetero MOS due to nonuniformity in the thickness of the Si cap region <b>24</b>, the concentration of the p-type impurity contained in the Si cap region <b>24</b> need only be 1×10¹⁷atoms·cm⁻³or more. Furthermore, the concentration of the p-type impurity contained in the Si cap region <b>24</b> is preferably 1×10¹⁹atoms·cm⁻³or less. This is because a great effect of suppressing variation in threshold voltage in the hetero MOS due to nonuniformity in the thickness of the Si cap region <b>24</b> can be gained within the range of the p-type impurity described above, as shown in FIGS. 2 and 3.

[0075]FIG. 5 is a graph on which peaks of the concentration of holes which are stored around the interface between the gate insulating film <b>12</b> (SiO₂) and the Si cap region <b>24</b> (i.e., parasitic channel) and the interface between the Si cap region <b>24</b> and the SiGe channel region <b>23</b> (i.e., channel) by applying a gate voltage are plotted against the gate voltage.

[0076] As shown in FIG. 5, in the known hetero MOS <b>100</b> (indicated by the dash-single-dot line (A)) including the Si cap region <b>107</b> into which the n-type impurity is doped (at a concentration of 1×10¹⁷atoms·cm⁻³), the range in which the number of holes stored around the interface between the Si cap region <b>24</b> and the SiGe channel region <b>23</b> is larger than that of holes stored around the parasitic channel is indicated by the voltage range A of FIG. 5. On the other hand, in the hetero MOS <b>10</b> of this embodiment including the Si cap region <b>24</b> into which the p-type impurity is doped, it can be understood that the range in which the number of holes stored around the interface between the Si cap region <b>24</b> and the SiGe channel region <b>23</b> is larger than that of holes stored around the parasitic channel expands to the voltage range B and to the voltage range C in this order as the concentration of the p-type impurity is increased to 5×10¹⁷atoms·cm⁻³(indicated by the solid line (B)) and then to 1×10¹⁸atoms·cm⁻³(indicated by the broken line (C)). This shows that the parasitic channel in question in the known hetero MOS <b>100</b> can be suppressed, resulting in a high drive current.

[0077] As has been described, by properly introducing a p-type impurity into the Si cap region <b>24</b>, variation in threshold voltage in the hetero MOS due to nonuniformity in the thickness of the Si cap region <b>24</b> can be suppressed. Accordingly, even if nonuniformity in the thickness of the Si cap region <b>24</b> occurs because fluctuation in a fabrication process and a difference between the fabrication processes, variation in threshold voltage in a wafer, among wafers, and among lots can be reduced. Specifically, in the case of fabricating an integrated circuit using a plurality of the hetero MOS devices <b>10</b> of this embodiment, it is preferable that the thickness of the Si cap region <b>24</b> of each of the hetero MOS devices <b>10</b> does not change widely in order to further reduce variation in threshold voltage among the hetero MOS devices <b>10</b>. More specifically, the range of differences in the thickness of the Si cap region <b>24</b> is preferably 10 nm or less.

[0078] The threshold voltage in the hetero MOS can be also reduced. Furthermore, the parasitic channel in question in the known hetero MOS can be suppressed, resulting in a high drive current.

[0079] Although the p-channel hetero MOS using the SiGe channel region <b>23</b> has been described in this embodiment, the present invention is not limited thereto. Similar effects can be gained also in any n-channel hetero MOS devices into which are introduced respective impurities of opposite conductivity types to those of the p-channel hetero MOS. That is to say, as long as a hetero MOS has a structure in which an impurity whose conductivity is the same as that of carriers traveling along a channel is properly doped into a semiconductor layer (which corresponds to the Si cap region <b>24</b> of this embodiment) which exists between a channel region and a gate insulating film to form a heterojunction with the channel region, variation in threshold voltage in the hetero MOS can be suppressed. For example, a channel region formed of Si_1−xC_x, instead of the SiGe channel region <b>23</b>, and an Si cap region into which an n-type impurity is doped may be used to form an n-channel hetero MOS. Alternatively, SiGeC may be used as a channel to form an n-channel hetero MOS using an Si cap region into which an n-type impurity is doped or to form a p-channel hetero MOS using an Si cap region into which a p-type impurity is doped. Furthermore, these MOS devices may be integrated to form a CMOS.

[0080] (Embodiment 2)

[0081] Next, the structure of a hetero DTMOS in accordance with this embodiment will be described. FIG. 6 illustrates a cross-sectional structure of a p-channel hetero DTMOS <b>60</b> using a SiGe layer as a channel region and utilizing an Si/SiGe heterojunction according to this embodiment. FIG. 7 is a top view of the p-channel hetero DTMOS <b>60</b>.

[0082] As shown in FIG. 6, the p-channel hetero DTMOS <b>60</b> of this embodiment includes a p-type Si substrate <b>11</b>, a gate insulating film <b>12</b> which is formed of an SiO₂film (having a thickness of about 6 nm) on the Si substrate <b>11</b>, a gate electrode <b>13</b> which is formed of polysilicon containing a p-type impurity of high concentration on the gate insulating film <b>12</b>, and a sidewall spacer <b>14</b> which is formed on the gate insulating film <b>12</b> to cover the side faces of the gate electrode <b>13</b>.

[0083] The p-channel hetero DTMOS <b>60</b> of this embodiment shown in FIG. 6 includes an Si layer <b>15</b>, which has been formed in an upper part of the Si substrate <b>11</b> by introducing an n-type impurity at a high concentration (2×10¹⁸atoms·cm⁻³) by ion implantation before crystals are grown in a semiconductor fabrication process. On the Si layer <b>15</b>, an Si layer <b>16</b>, an SiGe layer <b>17</b> and an Si layer <b>18</b> are epitaxially grown in this order by a UHV-CVD method.

[0084] Furthermore, in the p-channel hetero DTMOS <b>60</b> of this embodiment, source and drain regions <b>19</b> and <b>20</b> that contain a p-type impurity of high concentration are formed in regions of the Si layer <b>15</b>, the Si layer <b>16</b>, the SiGe layer <b>17</b> and the Si layer <b>18</b> which are located on both sides of the gate electrode <b>13</b>.

[0085] A region of the Si layer <b>15</b> located between the source and drain regions <b>19</b> and <b>20</b>, is an Si body region <b>21</b> which contains the n-type impurity of high concentration. The Si body region <b>21</b> and the gate electrode <b>13</b> are electrically connected to each other by an interconnect <b>25</b>. Specifically, as shown in FIG. 7, the gate electrode <b>13</b> and the Si body region <b>21</b> are directly connected to each other outside of the region in which a channel is to be formed.

[0086] The Si layer <b>16</b> and the SiGe layer <b>17</b> are both undoped layers into which no n-type impurity is doped in an as-grown state. Regions of the Si layer <b>16</b> and the SiGe layer <b>17</b> located between the source and drain regions <b>19</b> and <b>20</b> are an Si buffer region <b>22</b> and an SiGe channel region <b>23</b>, respectively, which contain the n-type impurity of low concentration. A region of the Si film <b>18</b> located directly under the gate insulating film <b>12</b> is an Si cap region <b>24</b> into which a p-type impurity (5×10¹⁷atoms·cm⁻³) is introduced. The gate insulating film <b>12</b> is formed by thermally oxidizing the Si layer <b>18</b>. When the p-channel hetero MOS <b>10</b> of this embodiment is in operation, a gate bias voltage applied to the gate electrode <b>13</b> causes the SiGe channel region <b>23</b> and the Si cap region <b>24</b> to deplete and holes to travel along the SiGe channel region <b>23</b>.

[0087] The thickness of the Si layer <b>16</b> is 10 nm and the thickness of the SiGe layer <b>17</b>, i.e., the thickness of the SiGe channel region <b>23</b>, is 15 nm. The Ge content in the SiGe channel region <b>23</b> is 30%.

[0088] As can be understood from the foregoing description, the hetero DTMOS of this embodiment has basically the same structure as the hetero MOS described in Embodiment 1. However, the hetero DTMOS of this embodiment is different from the hetero MOS in that the gate electrode <b>13</b> and the Si body region <b>21</b> are electrically connected to each other.

[0089] In the hetero DTMOS <b>60</b> of this embodiment, as shown in FIG. 6, the gate electrode <b>13</b> and the Si body region <b>21</b> are electrically connected to each other. Because of this, when a gate bias voltage is applied to the gate electrode <b>13</b>, a forward bias voltage at the same level as the gate bias voltage is applied to the Si channel region <b>23</b> via the Si body region <b>21</b>. Therefore, when the gate bias is OFF, the hetero DTMOS is in the same state as a regular MOS transistor, whereas when the gate bias is ON, the Si body region <b>21</b> is biased in the forward direction as the gate bias voltage is increased, and thus threshold voltage is reduced. Accordingly, the hetero DTMOS of this embodiment is operable with a lower threshold voltage, compared to DTMOS using a known Si substrate.

[0090] Furthermore, in the hetero DTMOS <b>60</b> of this embodiment, since the substrate bias coefficient y can be set at a large value, the threshold voltage is largely reduced during operation and the effective gate overdrive is increased. As a result, a high ON current can be obtained. That is to say, according to the hetero DTMOS <b>60</b> of this embodiment, great current driveability and high speed switching can be achieved even at a low voltage.

[0091]FIG. 8 shows the correlation between threshold voltage and the thickness of the Si cap region for a hetero DTMOS which is obtained by electrically connecting the gate electrode <b>13</b> and the Si body region <b>21</b> in the known hetero MOS <b>100</b> (which will be hereinafter referred to a “known hetero DTMOS”) and for the hetero DTMOS <b>60</b> of this embodiment in which the p-type impurity is introduced into the Si cap region <b>24</b>.

[0092] In the known hetero DTMOS, the n-type impurity is doped into the Si cap region <b>107</b>. The correlation between threshold voltage and the thickness of the Si cap region is indicated by the dash-single-dot line (a) in FIG. 8.

[0093] On the other hand, the correlation between the threshold voltage and the thickness of the Si cap region <b>24</b> for the hetero DTMOS <b>60</b> of this embodiment including the Si cap region <b>24</b> into which a p-type impurity at about 5×10¹⁷atoms·cm⁻³is doped is indicated by the solid line (b) in FIG. 8. As can be seen from FIG. 8, in the hetero DTMOS <b>60</b> of this embodiment, the variation in threshold voltage is smaller than that in the known hetero DTMOS. Furthermore, at an increased concentration of the p-type impurity in the Si cap region <b>24</b> (i.e., where the concentration of the p-type impurity is 1×10¹⁸atoms·cm ⁻³as indicated by the broken line (c) in FIG. 8), the absolute value for threshold voltage becomes smaller as the thickness of the Si cap region <b>24</b> is increased, in contrast to the known hetero DTMOS (indicated by the dash-single-dot line (a)). In other words, the threshold voltage is reduced. This is because the thickness of the Si cap region <b>24</b> is increased in the highly doped region and thereby the potential at the SiGe channel region <b>23</b> decreases.

[0094] Furthermore, the amount of the variation in the threshold voltage in this embodiment is smaller than in the hetero MOS <b>10</b> of Embodiment 1. This shows that the hetero DTMOS <b>60</b> of this embodiment is more effective to stabilize threshold voltage than the hetero MOS <b>10</b> of Embodiment 1. In order to suppress variation in threshold voltage in the hetero DTMOS due to nonuniformity in the thickness of the Si cap region <b>24</b>, the concentration of the p-type impurity contained in the Si cap region <b>24</b> need only be 1×10¹⁷atoms·cm⁻³or more. Furthermore, the concentration of the p-type impurity contained in the Si cap region <b>24</b> is preferably 1×10¹⁸atoms·cm⁻³or less. This is because a great effect of suppressing variation in threshold voltage in the hetero MOS due to nonuniformity in the thickness of the Si cap region <b>24</b> can be gained within the range of the concentration of the p-type impurity described above, as shown in FIG. 8.

[0095]FIG. 9 shows the results obtained from simulations of the Vg-Id characteristics for the known hetero DTMOS, and the hetero DTMOS <b>60</b> of this embodiment in which the p-type impurity is introduced into the Si cap region <b>24</b>. In this case, the thicknesses of the Si cap region <b>107</b> of the known hetero DTMOS and the Si cap region <b>24</b> of the hetero DTMOS <b>60</b> are both 5 nm.

[0096] Referring to FIG. 9, when the results for the known hetero DTMOS indicated by the dash-single-dot line (a) and the hetero DTMOS <b>60</b> of this embodiment indicated by the solid line (b) are compared, it can be understood that the threshold voltage can be reduced.

[0097] In a DTMOS, in general, a lateral parasitic bipolar transistor is generated through a p-type gate, an n-type body (base), a p-type source region <b>19</b> (emitter) and a drain region <b>20</b> (collector). When the transistor turns on and body current flows, the body current might practically become a problem.

[0098] Referring to FIG. 9, however, no difference in the body current is shown between the known hetero DTMOS and the hetero DTMOS <b>60</b> of this embodiment. That is to say, in the hetero DTMOS <b>60</b> of this embodiment, the difference between the body and drain currents is enlarged, so that the operation voltage range that is controlled by the body current can be enlarged.

[0099]FIG. 10 is a graph showing the Vg-Id characteristics of each of the known hetero DTMOS (the concentration of the n-type impurity in the body region <b>21</b>: 2×10¹⁸atoms·cm⁻³) and the hetero DTMOS <b>60</b> of this embodiment, where the concentration of the n-type impurity in the Si body region <b>21</b> of the hetero DTMOS <b>60</b> of this embodiment is set at a higher level (2×10¹⁹atoms·cm⁻³) so that the threshold voltage of the hetero DTMOS <b>60</b> is equal to that of the known hetero DTMOS.

[0100] According to this embodiment, the p-type impurity is doped into the Si cap region <b>24</b> and thereby the threshold voltage is reduced. The concentration of the impurity in the body region <b>21</b> can be set a higher level in accordance with the reduction in threshold voltage. When the concentration of the impurity in the body region <b>21</b> is increased, a built-in potential is increased between the source and the body. Accordingly, the body current generated in the lateral parasitic bipolar transistor can be kept at a low level. That is to say, the operation voltage range can be enlarged. Furthermore, at an increased concentration of the impurity in the body region <b>21</b>, when a voltage is applied to between the source and the drain, a depletion layer from the source region <b>19</b> and the drain region <b>20</b> can be prevented from expanding. Therefore, even when the concentration of the impurity in the body region is increased, the threshold voltage can be kept at a low level and the short channel effect that is caused when the gate length is shortened can be prevented. In this embodiment, the concentration of the impurity in the body region <b>21</b> is set at 2×10¹⁹atoms·cm⁻³. However, similar effects can be achieved as long as the concentration is 5×10¹⁸atoms·cm⁻³or more.

[0101] As has been described, by properly doping a p-type impurity into the Si cap region <b>24</b>, variation in threshold voltage due to nonuniformity in the thickness of the Si cap region can be suppressed. Accordingly, even if nonuniformity in the thickness of the Si cap region <b>24</b> occurs because of fluctuation in a fabrication process and a difference between fabrication processes, variation in threshold voltage in a wafer, among wafers, and among lots can be reduced. Specifically, in fabricating an integrated circuit using a plurality of the hetero DTMOS devices <b>20</b> of this embodiment, in order to further suppress variation in threshold voltage among the hetero MOS devices <b>60</b>, it is preferable that nonuniformity in the thickness of the Si cap regions <b>24</b> of the hetero DTMOS devices <b>60</b> are not so wide. More specifically, the range of nonuniformity in the thickness of the Si cap regions <b>24</b> is preferably 10 nm or less.

[0102] Also, the threshold voltage can be reduced by properly doping a p-type impurity into the Si cap region <b>24</b>.

[0103] Moreover, the body current in question in the hetero DTMOS structure can be suppressed, and thereby a wide range of operation voltage can be achieved. Accordingly, the short channel effect can be sufficiently suppressed.

[0104] Although the p-channel hetero DTMOS using the SiGe channel region <b>23</b> has been described in this embodiment, the present invention is not limited to such a structure. Similar effects can be gained also in any n-channel hetero MOS devices into which are introduced respective impurities of the opposite conductivity types to those of the pchannel hetero DTMOS. That is to say, as long as a hetero DTMOS has a structure in which an impurity whose conductivity is the same as that of carriers traveling along a channel is properly doped into a semiconductor layer (corresponding to the Si cap region <b>24</b> of this embodiment) which exists between a channel region and a gate insulating film to form a heterojunction with the channel region, it is possible to achieve a hetero DTMOS in which variation in threshold voltage is suppressed. For example, a channel region formed of Si^1−xC_X, instead of the SiGe channel region <b>23</b>, and an Si cap region into which the n-type impurity is doped may be used to form an n-channel hetero DTMOS. Moreover, SiGeC may be used as a channel to form an n-channel hetero DTMOS using an Si cap region into which the n-type impurity is doped or to form a p-channel hetero MOS using an Si cap region into which a p-type impurity is doped. Furthermore, these MOS devices may be integrated to form a complementary DTMOS.

[0105] (Embodiment 3)

[0106] According to this embodiment, the structure of a complementary hetero MOS will be described. FIG. 11 illustrates a cross-sectional structure of the complementary hetero MOS <b>70</b> of this embodiment using an SiGe layer as a channel region and utilizing an Si/SiGe heterojunction.

[0107] As shown in FIG. 11, the complementary hetero MOS <b>70</b> of this embodiment includes an Si layer <b>15</b><i>a, </i>an embedded oxide layer <b>15</b><i>b </i>which is formed by implanting oxygen ions into the Si layer <b>15</b><i>a </i>or like methods, a semiconductor layer <b>30</b> for a p-channel hetero MOS (hereinafter referred to a “p-hetero MOS”) which is formed on the embedded oxide film <b>15</b><i>b, </i>and a semiconductor layer <b>90</b> for an n-channel hetero MOS (hereinafter referred to an “n-hetero MOS”) which is formed on the embedded oxide film <b>15</b><i>b. </i>On the semiconductor layer <b>30</b>, a gate insulating film <b>12</b> which is formed of an SiO₂film (having a thickness of about 6 nm), a gate electrode <b>13</b> which is formed of polysilicon containing a p-type impurity of high concentration on the gate insulating film <b>12</b>, and a sidewall spacer <b>14</b> which is formed on the gate insulating film <b>12</b> to cover the side faces of the gate electrode <b>13</b> are provided. On the semiconductor layer <b>90</b>, a gate insulating film <b>72</b> formed of an SiO₂film (having a thickness of about 6 nm), a gate electrode <b>73</b> which is formed of polysilicon containing an n-type impurity of high concentration on the gate insulating film <b>72</b>, and a sidewall spacer <b>74</b> which is formed on the gate insulating film <b>72</b> to cover the side faces of the gate electrode <b>73</b>.

[0108] In a fabrication process for the complementary hetero MOS <b>70</b> of this embodiment, an n-type impurity of high concentration (2×10¹⁸atoms·cm⁻³) is introduced into the semiconductor layer <b>30</b> for the p-hetero MOS by ion implantation before crystals are grown, and thereby an Si layer <b>15</b> is formed. On the Si layer <b>15</b>, an Si layer <b>16</b>, an SiGe layer <b>17</b> and an Si layer <b>18</b> are epitaxitially grown in this order by an UHV-CVD method. Furthermore, source and drain regions <b>19</b> and <b>20</b> which contain the p-type impurity of high concentration are formed in regions of the Si layer <b>15</b>, the Si layer <b>16</b>, the SiGe layer <b>17</b> and the Si layer <b>18</b> which are located on both sides of the gate electrode <b>13</b>.

[0109] A region of the Si layer <b>15</b> located between the source region <b>19</b> and the drain region <b>20</b> is an Si body region <b>21</b> which contains the n-type impurity of high concentration. The Si layer <b>16</b> and the SiGe layer <b>17</b> are both undoped layers into which no n-type impurity is doped in an as-grown state. Regions of the Si layer <b>16</b> and the SiGe layer <b>17</b> located between the source and drain regions <b>19</b> and <b>20</b>, are an Si buffer region <b>22</b> and an SiGe channel region <b>23</b>, respectively, which contain the n-type impurity of low concentration. A region of the Si film <b>18</b> located directly under the gate insulating film <b>12</b> is an Si cap region <b>24</b> into which a p-type impurity (5×10¹⁷atoms·cm⁻³) is introduced. The gate insulating film <b>12</b> is formed by thermally oxidizing the Si layer <b>18</b>.

[0110] A p-type impurity of high concentration (2×10¹⁸atoms·cm⁻³) is introduced into the semiconductor layer <b>90</b> for the n-hetero MOS at a high concentration by ion implantation before crystals are grown, and thereby an Si layer <b>75</b> is formed. On the Si layer <b>75</b>, an Si layer <b>76</b>, an SiGe layer <b>77</b> and an Si layer <b>78</b> are epitaxitially grown in this order by a UHV-CVD method. Furthermore, source and drain regions <b>79</b> and <b>80</b> which contain the n-type impurity of high concentration are formed in regions of the Si layer <b>75</b>, the Si layer <b>76</b>, the SiGe layer <b>77</b> and the Si layer <b>78</b> which are located on both sides of the gate electrode <b>73</b>.

[0111] A region of the Si layer <b>75</b> located between the source region <b>79</b> and the drain region <b>80</b> is an Si body region <b>81</b> which contains the p-type impurity of high concentration. The Si layer <b>76</b> and the SiGe layer <b>77</b> are both undoped layers into which no p-type impurity is doped in an as-grown state. Regions of the Si layer <b>76</b> and the SiGe layer <b>77</b> located between the source and drain regions <b>79</b> and <b>80</b> are an Si buffer region <b>82</b> and an SiGe channel region <b>83</b>, respectively, which contain the p-type impurity of low concentration. A region of the Si film <b>78</b> located directly under the gate insulating film <b>72</b> is an Si channel region <b>84</b>. Specifically, the Si channel region <b>84</b> of the n-type hetero MOS of this embodiment is an undoped layer into which no impurity is doped in an as-grown state.

[0112] The thicknesses of the Si layers <b>16</b> and <b>76</b> are both 10 nm and the thicknesses of the SiGe layers <b>17</b> and <b>77</b>, i.e., the thicknesses of the SiGe channel region <b>23</b> and the SiGe region <b>83</b>, are both 15 nm. The Ge contents in the SiGe channel region <b>23</b> and the SiGe region <b>83</b> are both 30%.

[0113] As can be understood from the foregoing desription, the complementary hetero MOS <b>70</b> of this embodiment includes: the p-hetero MOS which is formed on an SOI substrate and has the almost same structure as the hetero MOS <b>10</b> of Embodiment 1; and the n-hetero MOS which is formed on the SOI substrate and has the almost same structure as the hetero MOS <b>10</b> of Embodiment 1 but is different from the hetero MOS <b>10</b> in that the conductivity type of each member is opposite to that of the corresponding member of the hetero MOS <b>10</b>. Furthermore, in the n-hetero MOS, the p-type impurity is not doped into the Si channel region <b>84</b>.

[0114] Next, a method for fabricating the complementary hetero MOS of this embodiment will be described with reference to FIG. 12. FIG. 12 illustrates cross-sectional views showing process steps of the method of this embodiment for fabricating the complementary hetero MOS <b>70</b>.

[0115] First, in the process step shown in FIG. 12(<i>a</i>), an SOI substrate <b>71</b> formed of an Si layer <b>15</b><i>a, </i>an embedded oxide film <b>15</b><i>b </i>and an Si layer <b>15</b><i>c </i>is prepared. Subsequently, an n⁺Si region (i.e., a p-hetero MOS region) and a p+Si region (i.e., an n-hetero MOS region) into which different impurities are doped, respectively, at a concentration of about 2×10¹⁸atoms·cm⁻³are formed by ion implantation. Thereafter, an Si layer <b>16</b><i>a, </i>an SiGe layer <b>17</b><i>a, </i>an Si layer <b>18</b><i>a </i>are epitaxially grown on the Si layer <b>15</b><i>c </i>in this order by a UHV-CVD method. In this case, each of the layers is an undoped layer and the layers are formed so that the respective thicknesses of the Si layer <b>16</b><i>a, </i>the SiGe layer <b>17</b><i>a, </i>the Si layer <b>18</b><i>a </i>are 10 nm, 15 nm, and 5 nm and that the Ge content in the SiGe layer <b>17</b><i>a </i>is 30%.

[0116] Next, in the process step shown in FIG. 12(<i>b</i>), a resist mask is deposited on the n-hetero MOS region. Thereafter, a p-type impurity is doped into part of the Si layer <b>18</b><i>a </i>which is located in the p-hetero MOS region at a concentration of about 5×10¹⁷atoms·cm⁻³by ion implantation using the resist mask as a mask.

[0117] Next, in the process step shown in FIG. 12(<i>c</i>), the resist mask is removed and then the gate insulating films <b>12</b> and <b>72</b> are formed on parts of the Si layer <b>18</b><i>a </i>which are in the p-hetero MOS region and the n-hetero MOS region, respectively. Then, an n⁺gate electrode <b>13</b> formed of polysilicon, into which an n-type impurity of high concentration is doped, and a p⁺gate electrode <b>73</b> formed of polysilicon, into which a p-type impurity of high concentration is doped, are formed on the insulating films <b>12</b> and <b>72</b>, respectively. Thereafter, sidewall spacers <b>14</b> and <b>74</b> are formed to cover the side faces of the gate electrodes <b>13</b> and <b>73</b>.

[0118] Next, in the process step shown in FIG. 12(<i>d</i>), impurity ions are implanted at a high concentration using each of the gate electrodes and the sidewall spacers as a mask, thereby forming n⁺type source and drain regions <b>19</b> and <b>20</b> and p⁺type source and drain regions <b>79</b> and <b>80</b>.

[0119] Subsequently, a trench <b>86</b> is formed to isolate the p-hetero MOS region from the n-hetero MOS region. By this isolation, an Si layer <b>15</b>, an Si layer <b>16</b>, an SiGe layer <b>17</b> and an Si layer <b>18</b> are formed in the p-hetero MOS region whereas an Si layer <b>75</b>, an Si layer <b>76</b>, an SiGe layer <b>77</b> and an Si layer <b>78</b> are formed in the n-hetero MOS region.

[0120] At this time, in the region between the source and drain regions <b>19</b> and <b>20</b>, an Si body region <b>21</b>, an Si buffer region <b>22</b>, an SiGe channel region <b>23</b> and an Si cap region <b>24</b> are formed. In the region between the source and drain regions <b>79</b> and <b>80</b>, an Si body region <b>81</b>, an Si buffer region <b>82</b>, an SiGe region <b>83</b> and an Si channel region <b>84</b> are formed.

[0121] By the fabrication method which includes the foregoing process steps, the complementary hetero MOS <b>70</b> can be obtained.

[0122] Using the above-described fabrication method, a CMOS device using a high-performance hetero MOS can be fabricated in a simple manner. Note that a gate electrode and an Si body region may be electrically connected to each other by a contact in each of the p-hetero MOS and the n-hetero MOS to form a complementary hetero DTMOS.

[0123] According to this embodiment, by properly introducing a p-type impurity into the Si cap region <b>24</b> of the p-hetero MOS, variation in threshold voltage in a hetero MOS due to nonuniformity in the thickness of the Si cap region <b>24</b> can be suppressed. Accordingly, even if nonuniformity in the thickness of the Si cap region <b>24</b> occurs because of fluctuation in a fabrication process or between the fabrication processes, variation in threshold voltage in a wafer, among wafers, and among lots can be reduced. It is also possible to reduce the threshold voltage in the p-hetero MOS. Furthermore, the parasitic channel in question in the known hetero MOS can be suppressed, and thus a high drive current can be achieved.

[0124] Furthermore, in the complementary hetero MOS <b>70</b> of this embodiment, no p-type impurity is doped into the Si channel region <b>84</b> of the n-hetero MOS. Therefore, the characteristics of the n-hetero MOS are not degenerated. This will be further described with reference to FIGS. <b>13</b>(<i>a</i>) and <b>13</b>(<i>b</i>). FIG. 13(<i>a</i>) shows band profiles of the p-hetero MOS included in the complementary hetero MOS <b>70</b> of this embodiment when gate bias voltage is applied thereto and FIG. 13(<i>b</i>) shows band profiles of the n-hetero MOS included in the complementary hetero MOS <b>70</b> of this embodiment when the gate bias voltage is applied thereto.

[0125] As shown in FIG. 13(<i>a</i>), in the p-hetero MOS, a channel is formed in the SiGe channel region <b>23</b> and holes travel along the channel.

[0126] As shown in FIG. 13(<i>b</i>), in the n-hetero MOS, a channel is formed in the Si channel region <b>84</b> and electrons travel along the channel. In the above-described method for fabricating the complementary hetero MOS <b>70</b>, if the p-type impurity is introduced into the Si layer <b>18</b><i>a </i>by in-situ doping in the process step shown in FIG. 12(<i>a</i>), an Si layer <b>78</b> into which the p-type impurity is doped is formed at the end. Because of this, the valence band in the Si channel region <b>84</b> has such a potential as indicated by the broken line in FIG. 13(<i>b</i>) and, as a result, threshold voltage is increased.

[0127] According to this embodiment, however, in the process step shown in FIG. 12(<i>a</i>), the p-type impurity is not introduced by in-situ doping but by ion implantation into only the part of the Si layer <b>18</b><i>a </i>which is located in the p-hetero MOS region. As a result, almost no p-type impurity has been doped into the Si region <b>78</b> even at the end. Accordingly, the valence band in the Si channel region <b>84</b> has such a potential as one indicated by the solid line in FIG. 13(<i>b</i>). Therefore, the increase in threshold voltage in the n-hetero MOS is suppressed and thus the characteristics of the n-hetero MOS are hardly degenerated.

[0128]FIG. 14 shows the Ge contents and the impurity profiles in the Si body region <b>21</b>, the Si buffer region <b>22</b>, the SiGe channel region <b>23</b> and the Si cap region <b>24</b> of the p-hetero MOS included in the complementary hetero MOS of this embodiment.

[0129] As shown in FIG. 14, the concentration of the p-type impurity is the highest (5×10¹⁷atoms·cm⁻³) at the surface of the Si cap region <b>24</b> and the concentration is reduced with increasing depth from the surface.

[0130] In this manner, the Si cap region <b>24</b> is formed through introduction of a p-type impurity by ion implantation according to the method for fabricating the complementary hetero MOS of this embodiment and thus there may be cases where the p-type impurity reaches a region located directly under the Si cap region <b>24</b>. If the p-type impurity reaches the region located directly under the cap region <b>24</b>, a region through which holes travel may be formed, besides the interface between the Si cap region <b>24</b> and the SiGe channel region <b>23</b>, in a region located at a greater depth from the surface of the Si cap region <b>24</b> (e.g., in the Si buffer region <b>22</b>). Therefore, it is difficult to control the drain current to be ON/OFF by gate bias voltage that is applied to the gate electrode <b>13</b>. In other words, the characteristics of the p-hetero MOS are degenerated.

[0131] Therefore, it is preferable to adjust conditions for ion implantation such that the p-type impurity does not reach the Si buffer region <b>22</b> as much as possible. It is also preferable to set the concentration of the p-type impurity at the highest level in the Si cap region <b>24</b> or the SiGe channel region <b>23</b> (i.e., to put the peak of the p-type impurity profile in the Si cap region <b>24</b> or the SiGe channel region <b>23</b>). Specifically, it is preferable that the concentration of the p-type impurity is the highest in the Si cap region <b>24</b>. It is further preferable that the concentration of the p-type impurity is the highest at the surface of the Si cap region <b>24</b>.

[0132] In this manner, according to this embodiment, a complementary hetero MOS including a high-performance p-hetero MOS can be obtained without the characteristics of an n-hetero MOS being degenerated.

[0133] Industrial Applicability

[0134] The present invention can be utilized for field effective transistors, such as heterojunction MOS transistors and hetero junction DTMOS transistors, including a heterojunction for a channel region.