Process for making a silicon-on-insulator ledge and structures achieved thereby

FIELD OF THE INVENTION

P-0001[0001] An embodiment relates to semiconductor processing. One embodiment in particular relates to a process for making a silicon-on-insulator ledge structure that includes a partially isolated active area in a semiconductive substrate.

BACKGROUND

P-0002[0002] Semiconductor processing is an intensive activity during which several processes are integrated to achieve a working device. Miniaturization is the process of crowding more semiconductive devices onto a smaller substrate area in order to achieve better device speed, lower energy usage, and better device portability, among others. New processing methods must often be developed to enable miniaturization to be realized. Preferably, the processing methods needed to fabricate such devices are developed in a manner that existing processing equipment can be used.

P-0003[0003] The pressure to continue the miniaturization process also leads to new semiconductor device structures. As individual active devices become smaller and are fabricated closer together, leakage and second order effects become more significant. In the field of metal oxide semiconductor field-effect transistors (MOSFET), device leakage and miniaturization appear to be antagonistic challenges. Often, oxidation is carried out for the purpose of isolation, but oxidation often imparts stresses in the workpieces that lead to device failure. Deposition processes, although necessary, are time-consuming and costly. Further, deposition processes require masking and careful application. Further, deposition processes are preferentially applied when an integrated process can take advantage of a given deposition simultaneously in unrelated areas of a device.

SUMMARY

P-0004[0004] The above mentioned problems and challenges are overcome by embodiments of this invention. One embodiment is directed to a process of forming a partially isolated structure of sufficient size to permit the fabrication of an active device thereon. The process includes forming an etch-selective region in the semiconductive workpiece that restricts the effects of an isotropic etch. The etch-selective region is created by implantation that causes the semiconductive material to become amorphous.

P-0005[0005] Protective material, such as a polysilicon layer and a nitride layer, is deposited over a pad oxide layer to protect the pad oxide layer. An active area is defined by patterning a mask. The protective material, the pad oxide layer, and finally the substrate are etched to form a trench around the active area. A protective film that is typically nitride material, is formed upon exposed silicon. The substrate is etched to deepen the trench around what will become the active area to a level below the protective layer. The etch-selective implantation region is either then formed or exposed by the previous etch. An isotropic etch follows that acts to substantially insulate the active area by its undercutting effect. The implantation region is annealed to repair the crystal lattice of the substrate. Thereafter, an alternative oxidation process is done to further isolate the active area from adjacent active areas or other structures. Oxide spacers are formed on the sides of the active area, and the remainder of the trench is filled to form a shallow trench isolation (STI) structure.

P-0006[0006] An embodiment is also directed to a partially isolated structure of sufficient size to permit the fabrication of an active device thereon. The partially isolated structure is comprised of a portion of the a substrate that has an undercut lateral cavity that is shaped in a manner which defines the active area of the partially isolated structure.

P-0007[0007] The process and structure of various embodiments enable active devices to be packed into ultra-dense configurations using currently available fabrication equipment. Because the diode junctions of active devices are formed in areas of the substrate that are at least partially isolated from the remainder of the substrate, the diode junctions may be fabricated to be less leaky.

BRIEF DESCRIPTION OF THE DRAWINGS

P-0008[0008] In order that the manner in which embodiments of the present invention are obtained, a more particular description of the invention briefly described above will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings. Understanding that these drawings depict only typical embodiments of the invention that are not necessarily drawn to scale and are not therefore to be considered to be limiting of its scope, the invention will be described and explained with additional specificity and detail through the use of the accompanying drawings in which:

P-0009[0009]FIG. 1 is a cross section of a structure during processing according to an embodiment.

P-0010[0010]FIG. 2 is a cross section of the structure depicted in FIG. 1 after further processing.

P-0011[0011]FIG. 3 is a cross section of the structure depicted in FIG. 2 after further processing in which a nitride film has been grown on exposed silicon.

P-0012[0012]FIG. 4 is a cross section of the structure depicted in FIG. 3 after further processing.

P-0013[0013]FIG. 5 is a cross section of the structure depicted in FIG. 4 after further processing in which a lateral recess has been etched.

P-0014[0014]FIG. 6 is a cross section of the structure depicted in FIG. 5 after further processing.

P-0015[0015]FIG. 7 is a cross section of the structure depicted in FIG. 6 after further processing in which oxidation and oxide fill processes have been done.

P-0016[0016]FIG. 8 is a cross section of the structure depicted in FIG. 6 after alternative further processing in which minimal oxidation or no oxidation, and oxide fill processes have been done.

P-0017[0017]FIG. 9 is a cross section of the structure depicted in FIG. 6 after alternative further processing in which minimal oxidation or no oxidation, and oxide fill processes have been done.

P-0018[0018]FIG. 10 is a cross section that includes the structure depicted in FIG. 9 after further processing.

P-0019[0019]FIG. 11 is a cross section that includes a portion of the structure depicted in FIG. 10 after further processing.

P-0020[0020]FIG. 12 is a cross section of a structure during processing according to an embodiment.

P-0021[0021]FIG. 13 is a cross section of the structure depicted in FIG. 12 after an anisotropic etch.

P-0022[0022]FIG. 14 is a cross section of the structure depicted in FIG. 13 after further processing in which a nitride film has been grown on exposed silicon.

P-0023[0023]FIG. 15 is a cross section of the structure depicted in FIG. 14 after further processing.

P-0024[0024]FIG. 16 is a cross section of the structure depicted in FIG. 15 after further processing in which a lateral recess has been etched.

P-0025[0025]FIG. 17 is a cross section of the structure depicted in FIG. 16 after an anneal process.

P-0026[0026]FIG. 18 is a cross section of a structure during processing according to an embodiment.

P-0027[0027]FIG. 19 is a cross section of the structure depicted in FIG. 18 after an anisotropic etch.

P-0028[0028]FIG. 20 is a cross section of the structure depicted in FIG. 19 after further processing in which a nitride film has been grown on exposed silicon.

P-0029[0029]FIG. 21 is a cross section of the structure depicted in FIG. 20 after further processing.

P-0030[0030]FIG. 22 is a cross section of the structure depicted in FIG. 21 after further processing in which a lateral recess has been etched.

P-0031[0031]FIG. 23 is a cross section of the structure depicted in FIG. 22 after an anneal process.

P-0032[0032]FIG. 24 is a top view of a wafer or substrate containing semiconductor dies in accordance with an embodiment.

P-0033[0033]FIG. 25 is a block diagram of a circuit module in accordance with an embodiment.

P-0034[0034]FIG. 26 is a block diagram of a memory module in accordance with an embodiment.

P-0035[0035]FIG. 27 is a block diagram of an electronic system in accordance with another embodiment the present invention.

P-0036[0036]FIG. 28 is a block diagram of a memory system in accordance with an embodiment.

P-0037[0037]FIG. 29 is a block diagram of a computer system in accordance with an embodiment.

DETAILED DESCRIPTION

P-0038[0038] In one embodiment as depicted in FIG. 1, a substrate <b>10</b> is provided which includes a semiconductive material. The terms wafer and substrate used in the following description include any structure having an exposed surface with which to form the integrated circuit (IC) structure relating to embodiments of the invention. The term substrate is understood to include semiconductor wafers. The term substrate is also used to refer to semiconductor structures during processing, and may include other layers that have been fabricated thereupon. Both wafer and substrate include doped and undoped semiconductors, epitaxial semiconductor layers supported by a base semiconductor or insulator, as well as other semiconductor structures well known to one skilled in the art. The term conductor is understood to include semiconductors, and the term insulator or dielectric is defined to include any material that is less electrically conductive than the materials referred to as conductors.

P-0039[0039] The substrate <b>10</b> has a pad oxide layer <b>12</b> deposited thereon. As used herein, the term deposited is used broadly to mean layers which are not only deposited in the traditional sense, but layers of material which are grown or in any other manner caused to be formed. A protective layer <b>14</b> is deposited on top of the pad oxide layer <b>12</b> to act as a buffer during subsequent etch steps and other processing. In one embodiment, the protective layer <b>14</b> is polysilicon. In one embodiment, the protective layer <b>14</b> is a nitride material. In another embodiment, the protective layer <b>14</b> is a polysilicon layer that is covered with a nitride material. The specific combination is selected depending upon process integration choices.

P-0040[0040] A mask <b>16</b> is formed and patterned upon the protective layer <b>14</b>. In one embodiment, the mask <b>16</b> is a photoresist material that is spun on, exposed, cured, and patterned. In another embodiment, the mask <b>16</b> is a hard mask material such as a nitride or oxide. The area protected by the mask <b>16</b> defines what will become an active area in a partial silicon-on-insulator (SOI) structure.

P-0041[0041]FIG. 2 illustrates an embodiment after an etch process that has exposed the regions unprotected by the mask <b>16</b>. In the etch process, the protective layer <b>14</b> and the pad oxide layer <b>12</b> have also been patterned, and a recess <b>18</b> has been formed with a recess first bottom <b>20</b> and a recess first wall <b>22</b>.

P-0042[0042]FIG. 3 illustrates the structure depicted in FIG. 2 after further processing in which the mask <b>16</b> has been removed and a nitride film <b>24</b> has been grown onto the exposed semiconductive material of the substrate <b>10</b>. In one embodiment, the exposed semiconductive material of the substrate <b>10</b> is exposed silicon. The nitride film <b>24</b> is depicted as covering the recess first bottom <b>20</b> and the recess first wall <b>22</b>. The nitride film <b>24</b> may be grown by known processes under conditions that deposit only upon semiconductive material such as exposed silicon. One such process is remote-plasma nitridation (RPN). In RPN, a nitride-bearing plasma is struck, remote from substrate <b>10</b>, but within the deposition tool, and the nitride-bearing plasma is carried by convective force toward the substrate <b>10</b>. In one embodiment, an RPN process is carried out in a time range from about 10 seconds to about 10 minutes. In another embodiment, an RPN process is carried out in a time range from about 1 minute to about 3 minutes. Another process that may be used to form the nitride film <b>24</b> is rapid thermal nitridation (RTN). Such processing is also known in the art.

P-0043[0043] Alternative to the formation of a nitride film <b>24</b>, an oxide film may be formed, either by remote-plasma oxidation (RPO) or by rapid thermal oxidation (RTO). Similarly, a combination of an oxide and a nitride is formed according to an embodiment as set forth herein. In one embodiment, the placement of the oxide precedes the placement of the nitride, or visa versa. Similarly, an oxynitride film is formed in the place of the nitride film <b>24</b> according to an alternative embodiment. The process is carried out by either a remote plasma process or a rapid thermal process. Although not limiting the embodiments disclosed, for convenience throughout the remainder of the disclosure, the film <b>24</b> is referred to a the nitride film <b>24</b>.

P-0044[0044]FIG. 4 illustrates processing of the substrate <b>10</b> in which an etch has formed a recess second bottom <b>26</b> below the level of the recess first bottom <b>20</b>. The recess first bottom <b>20</b> now appears as a substrate ledge structure. Because of the presence of the nitride film <b>24</b>, the recess first wall <b>22</b> is protected, and a recess second wall <b>28</b> has been formed that is approximately coplanar with the lateral extremity of the nitride film <b>24</b>. In one embodiment, an anisotropic etch, such as a reactive ion etch, is used such that the nitride film <b>24</b> is left standing upon the ledge of what is left of the recess first bottom <b>20</b>.

P-0045[0045] For a 0.25-micron critical-dimension (CD or minimum feature) process, the remnant of the nitride film <b>24</b> has a height in a range from about 0.1 microns to about 0.15 microns. In this dimension, the distance from the remnant of the recess first bottom <b>20</b> to the recess second bottom <b>26</b> is in a range from about 0.1 microns to about 0.3 microns. Alternatively, for a 0.15-micron critical-dimension (CD or minimum feature) process, the remnant of the nitride film <b>24</b> has a height, H, in a range from about 0.07 microns to about 0.12 microns. In this dimension, the distance from the remnant of the recess first bottom <b>20</b> to the recess second bottom <b>26</b> is in a range from about 0.08 microns to about 0.2 microns.

P-0046[0046] At the level of the recess second bottom <b>26</b>, a deep implantation region <b>30</b> is formed. In one embodiment, the deep implantation region <b>30</b> is made of materials that are substantially identical to the bulk semiconductive material in the substrate <b>10</b>. Implantation is carried out at an energy level that achieves self-interstitial implantation, and that causes the implantation region <b>30</b> to become amorphous enough to have an etch responsiveness that is different from the bulk semiconductive material in the substrate <b>10</b>. In one embodiment, implantation conditions use a silicon source that is implanted to a monocrystalline-to-self interstitial ratio of about 3:1. By “silicon source” it is meant that silicon or another Group IV element is used, or a combination such as silicon and germanium. In one embodiment, the implanted concentration is from about 1E14 atoms/cm²to about 5E15 atoms/cm²at process conditions of ambient temperature (20 C. to about 30 C.) and an implantation energy from about 20 KeV to about 30 KeV. In one embodiment, a silicon source that is substantially equivalent to the silicon chemistry of the bulk of the semiconductive substrate <b>10</b>, is implanted to a concentration of about 1E15 atoms/cm²and process conditions are about 25 C. and an implantation energy of about 25 KeV.

P-0047[0047] After the deep implantation, an etch recipe is used in subsequent processing that is selective to the amorphous material of the implantation region <b>30</b> and to the nitride film <b>24</b>, but the etch recipe removes bulk semiconductive material in the substrate <b>10</b>. In one embodiment, the etch recipe is a wet tetramethyl ammonium hydroxide (TMAH) etch as is known in the art. In another embodiment, the wet etch uses a potassium hydroxide (KOH) etch chemistry that is known in the art. The TMAH etch chemistry is desirable because it is selective such that it etches the bulk silicon of the substrate <b>10</b>, but does not substantially etch the nitride film <b>24</b> or the implantation region <b>30</b>. In one embodiment, the selectivity is in a range from about 5:1 to about 20:1. In another embodiment, the selectivity is about 10:1. The isotropic etch may also be combined with an anisotropic etch, either before or after the isotropic etch. By using both an isotropic and an anisotropic etch, both the downward etching and the undercutting of the nitride film <b>24</b> may be varied to suit particular applications.

P-0048[0048] Various wet TMAH etch recipes are known that are selective to amorphous silicon and to nitride films (or oxide films, or oxynitride films), and that isotropically etch bulk monocrystalline silicon along crystallographic planes. FIG. 5 illustrates the results of a TMAH etch that has formed a lateral cavity <b>34</b> that has undercut what will become the active area <b>32</b>. By this undercutting etch, the active area <b>32</b> has been mostly isolated from the bulk semiconductive material in the substrate <b>10</b>, at the level of the ledge that is formed at the recess first bottom <b>20</b>.

P-0049[0049] Under the etch conditions, and due to the scale of the lateral cavity <b>34</b>, a distinctive contour may appear therein. The TMAH etch has an effect along crystallographic planes such that a faceted contour may appear within the lateral cavity <b>34</b>. It can be seen that faceted surfaces <b>36</b>, <b>38</b>, <b>40</b>, and <b>42</b> are illustrated on one side. However, these are depicted in arbitrary shape, angle and size for illustrative purposes, and the specific shapes, angles, and sizes of the faceted surfaces will depend upon the crystallographic orientation of the bulk semiconductive material in the substrate <b>10</b> and upon the specific etch recipe and conditions, among other factors. According to the specific etch conditions, a photomicrographic view of the lateral cavity <b>34</b> depicts substended crystallographic planes of bulk semiconductive material in the substrate <b>10</b> that have been exposed by the TMAH etch.

P-0050[0050] After formation of the lateral cavity <b>34</b>, the implantation region <b>30</b> is treated to form an annealed implantation region <b>44</b> as illustrated in FIG. 6. The annealed implantation region <b>44</b> has been returned to substantially the same semiconductive quality as the bulk semiconductive material in the substrate <b>10</b> by substantially repairing the monocrystalline lattice in what was the deep implantation region <b>30</b> (FIG. 5). The conditions for annealing are known in the art, and depend upon the depth of the deep implantation region <b>30</b>, the available thermal budget of the process, and other factors.

P-0051[0051]FIG. 7 illustrates further processing according to an embodiment. In one embodiment, the exposed surface of the active area <b>32</b> and the bulk semiconductive material of the substrate <b>10</b> is oxidized. Known thermal oxidation techniques are used. The oxidation <b>46</b> consumes silicon downward into the substrate <b>10</b>, sideways into the faceted surfaces <b>36</b>, <b>38</b>, <b>40</b>, and <b>42</b> (FIG. 6), and upward into the bottom of the active area <b>32</b>. The oxidation <b>46</b> is depicted as following the previously exposed contours of the recess second bottom <b>26</b> and the faceted surfaces <b>36</b>, <b>38</b>, <b>40</b>, and <b>42</b> within the lateral cavity <b>34</b>, but the exact shape depicted is for illustrative purposes and will vary, depending upon specific process conditions. The oxidation process, which may be referred to as a minifield oxidation, is precisely controlled to regulate the amount of substrate material that is consumed.

P-0052[0052] According to an embodiment, the residue of the nitride film (FIG. 6) is removed after forming the oxidation <b>46</b>. Thereby, the original dimension of the recess first wall <b>22</b> (FIG. 7) is substantially retained. In one photolithographic process, such as a 0.25-micron process, the dimensions are about 0.1 microns from the recess first wall <b>22</b> to the lateral border <b>48</b> of the substrate stem <b>50</b> that remains. In another photolithographic process, such as a 0.15-micron process, the dimensions are about 0.07 microns (not pictured) from the recess first wall <b>22</b> to the lateral border <b>48</b> of the silicon stem <b>50</b> that remains to this stage of processing.

P-0053[0053] It is also depicted in FIG. 7, that the protective layer <b>14</b> has remained while the nitride film <b>24</b> has been removed. This embodiment occurs where the protective layer <b>14</b> is chemically different from the nitride film <b>24</b>, such as a polysilicon protective layer <b>14</b>. In another embodiment, where the protective layer <b>14</b> is a nitride material, it is removed with the nitride film <b>24</b> after the minifield oxidation.

P-0054[0054] As mentioned for a given photolithographic process, the amount of the substrate <b>10</b> that is consumed sideways in the lateral cavity <b>34</b>, for example, is approximately 0.1 micron on each side of the active area <b>32</b>, beginning at the recess first wall <b>22</b> and ending at the lateral border <b>48</b> of the stem <b>50</b>. That oxidation process leaves the stem <b>50</b> that partially isolates the substrate portion that will become the active area <b>32</b> that is formed above a ledge, at the recess first bottom <b>20</b>, in relation to the bulk of the substrate <b>10</b>. In this embodiment, the stem <b>50</b> is on the order of 0.05 microns by 0.05 microns. Oxidation time will depend upon the area of the partially isolated structure of the active area <b>32</b> and the other parameters. In one embodiment, oxidation parameters include a processing temperature from about 850 C. to about 1,100 C. The ambient is with wet or dry oxygen (O₂), and atmospheric pressure or higher. In one example, a temperature of about 850 C. and a wet oxygen ambient is applied at about 1 atmosphere and for a sufficient time to allow about 0.1 micron horizontal oxidation under the active area <b>32</b>, and about 0.1 micron vertical oxidation upwardly into the active area <b>32</b>. High pressure may be used to reduce the time required for oxidation and to reduce the amount of oxide that forms behind the nitride film <b>24</b> (FIG. 5). High pressure includes atmospheric pressure, up to about 2 atmospheres and higher. After the thermal oxidation process, an oxide spacer <b>52</b> is formed by a blanket oxide deposition, such as by the decomposition of tetraethyl ortho silicate (TEOS), followed by a spacer etch as illustrated in FIG. 7.

P-0055[0055]FIG. 8 illustrates another embodiment, wherein the oxidation process is carried out under minimal conditions. The minimal oxidation relates to a lowered workpiece stress in the lateral cavity <b>34</b>. An oxidation <b>46</b> is formed that leaves the lateral cavity <b>34</b> mostly void. The oxidation <b>46</b> consumes silicon downward into the substrate <b>10</b>, sideways into the faceted surfaces <b>36</b>, <b>38</b>, <b>40</b>, and <b>42</b> (FIG. 6), and upward into bottom of the active area <b>32</b>. In one photolithographic process, such as a 0.25-micron process, the dimensions are about 0.03 microns growth of oxidation <b>46</b> within the lateral cavity <b>34</b> to the lateral border <b>48</b> of the substrate stem <b>50</b> that remains. In another photolithographic process, such as a 0.15-micron process, the dimensions are about 0.01 microns (not pictured) within the lateral cavity <b>34</b> to the lateral border <b>48</b> of the silicon stem <b>50</b> that remains to this stage of processing.

P-0056[0056] It is also depicted in FIG. 8, that the protective layer <b>14</b> has remained while the nitride film <b>24</b> has been removed. This embodiment occurs where the protective layer <b>14</b> is chemically different from the nitride film <b>24</b>, such as a polysilicon protective layer <b>14</b>. In another embodiment, where the protective layer <b>14</b> is a nitride material, it is removed with the nitride film.

P-0057[0057] As mentioned for one photolithographic process, the amount of the substrate <b>10</b> that is consumed sideways by the isotropic etch, for example, is approximately 0.07 micron on each side of the active area <b>32</b>. That oxidation process leaves the stem <b>50</b> that connects the substrate that will become the active area <b>32</b> to the bulk of the substrate <b>10</b>. In this embodiment, the stem <b>50</b> is on the order of about 0.05 microns by 0.05 microns. Oxidation time will depend upon the area of the partially isolated structure that forms the active area <b>32</b> and the other parameters. In one embodiment, oxidation parameters include a processing temperature from about 850 C. to about 1,100 C. The ambient is with wet or dry oxygen (O₂), atmospheric pressure or higher. In one example, a temperature of about 850 C. and a wet oxygen ambient is applied for a sufficient time to allow about 0.03 micron horizontal oxidation under the active area <b>32</b>, and about 0.01 micron vertical oxidation upwardly into the active area <b>32</b>. High pressure may be used to reduce the time required for oxidation and to reduce the amount of oxide that forms behind the nitride film <b>24</b> (FIG. 5). High pressure is defined as a pressure above ambient including a range from about 1 atmosphere to about 2 atmospheres, and higher. After the thermal oxidation process, an oxide spacer <b>52</b> is formed by a blanket oxide deposition, such as by the decomposition of TEOS, followed by a spacer etch as illustrated in FIG. 8. According to this embodiment, the oxide spacer <b>52</b> is formed under low-pressure chemical vapor deposition (CVD) conditions that cause the lateral cavity <b>34</b> to remain partially void. Although no particular theory of deposition is required, it is the low pressure that may cause longer mean-free paths of depositing oxide spacer material that leaves a partially void lateral cavity <b>34</b>.

P-0058[0058] In another embodiment illustrated in FIG. 8, an oxide spacer <b>52</b> is blanket deposited by physical vapor deposition (PVD) under conditions that also cause the lateral cavity <b>34</b> to remain partially or totally void, followed by a spacer etch. In this embodiment, substantially no minifield oxidation is carried out before the blanket deposition and spacer etch of the oxide spacer <b>52</b>. Thereby, the lateral cavity <b>34</b> retains its faceted surfaces <b>36</b>, <b>38</b>, <b>40</b>, and <b>42</b> (depicted in FIG. 6). However, unless the isotropic etch is followed by a micro-atmospheric- or oxygen-excluding process, a thin native oxide film <b>46</b>, represented herein by the oxidation <b>46</b> in FIG. 8, will be present over the faceted surfaces <b>36</b>, <b>38</b>, <b>40</b>, and <b>42</b> (depicted in FIG. 6). This native oxide film <b>46</b> in some embodiments is substantially monatomic, or a few atomic layers thick in a range from about 2 Angstrom to about 8 Angstrom.

P-0059[0059]FIG. 9 illustrates an embodiment that relates to an oxidation that has a thickness intermediate to the previous two embodiments. In this embodiment, a process is carried out that partially fills the lateral cavity <b>34</b> with oxide material. The extent of fill into the lateral cavity <b>34</b> of the oxidation <b>46</b> is more than the extent of fill for the embodiment depicted in FIG. 8, and less than the extent of fill for the embodiment depicted in FIG. 7. Dimensions achieved by this embodiment are intermediate to the dimensions that are achieved in the embodiment depicted in FIGS. 8 and 7. In one embodiment, the amount of the substrate <b>10</b> that is consumed sideways, for example, is approximately 0.06 micron on each side of the stem <b>50</b>. That oxidation process leaves the stem <b>50</b> that connects the substrate that will become the active area <b>32</b> to the bulk of the substrate <b>10</b>. In this embodiment, the stem <b>50</b> is on the order of 0.05 microns by 0.05 microns.

P-0060[0060] The thickness of the stem <b>50</b> is set forth herein as about 0.05 micron for each given embodiment depicted in FIGS. 7, 8 and <b>9</b>. This thickness is controllable by the extent of the lateral etch that forms the lateral cavity <b>34</b>, in concert with the degree of growth of the oxidation <b>46</b>. It can be appreciated that other thicknesses of the stem <b>50</b> can be achieved, by controlling these parameters. Table 1 illustrates various geometries based upon lateral etches for a 0.25 micron lithography. The first three embodiments are depicted in FIGS. 7, 9, and <b>8</b>, respectively. The fourth embodiment is an example of a native oxide oxidation <b>46</b>, wherein after fabrication, the facets <b>36</b>, <b>38</b>, <b>40</b>, and <b>42</b> (FIG. 6) are visible by photomicrography. <tables id="TABLE-US-00001" num="1"><table frame="none" colsep="0" rowsep="0"><tgroup align="left" colsep="0" rowsep="0" cols="1"><colspec colname="1" colwidth="217PT" align="center" /><thead><row><entry namest="1" nameend="1" align="center">TABLE 1</entry></row></thead><tbody valign="top"><row><entry /></row><row><entry namest="1" nameend="1" align="center" rowsep="1" /></row><row><entry>0.25 Micron Process Geometries</entry></row></tbody></tgroup><tgroup align="left" colsep="0" rowsep="0" cols="4"><colspec colname="1" colwidth="42PT" align="center" /><colspec colname="2" colwidth="49PT" align="center" /><colspec colname="3" colwidth="63PT" align="center" /><colspec colname="4" colwidth="63PT" align="center" /><tbody valign="top"><row><entry /><entry>Void Depth,</entry><entry /><entry /></row><row><entry>Example</entry><entry>micron</entry><entry>Oxide 46, micron</entry><entry>Stem 50, micron</entry></row><row><entry namest="1" nameend="4" align="center" rowsep="1" /></row></tbody></tgroup><tgroup align="left" colsep="0" rowsep="0" cols="4"><colspec colname="1" colwidth="42PT" align="char" char="." /><colspec colname="2" colwidth="49PT" align="char" char="." /><colspec colname="3" colwidth="63PT" align="char" char="." /><colspec colname="4" colwidth="63PT" align="char" char="." /><tbody valign="top"><row><entry>1</entry><entry>0</entry><entry>0.1</entry><entry>.05</entry></row><row><entry>2</entry><entry>.03</entry><entry>.07</entry><entry>.05</entry></row><row><entry>3</entry><entry>.07</entry><entry>.03</entry><entry>.05</entry></row><row><entry>4</entry><entry>.0995</entry><entry>.0005</entry><entry>.05</entry></row><row><entry>5</entry><entry>.035</entry><entry>.06</entry><entry>.06</entry></row><row><entry>6</entry><entry>.065</entry><entry>.03</entry><entry>.06</entry></row><row><entry>7</entry><entry>.0945</entry><entry>.0005</entry><entry>.06</entry></row><row><entry>8</entry><entry>0</entry><entry>.09</entry><entry>.07</entry></row><row><entry>9</entry><entry>.03</entry><entry>.06</entry><entry>.07</entry></row><row><entry>10</entry><entry>.06</entry><entry>.03</entry><entry>.07</entry></row><row><entry>11</entry><entry>.0895</entry><entry>.0005</entry><entry>.07</entry></row><row><entry namest="1" nameend="4" align="center" rowsep="1" /></row></tbody></tgroup></table></tables>

P-0061[0061] Table 2 illustrates various geometries based upon varied lateral etches for a 0.15 micron geometry. <tables id="TABLE-US-00002" num="2"><table frame="none" colsep="0" rowsep="0"><tgroup align="left" colsep="0" rowsep="0" cols="1"><colspec colname="1" colwidth="217PT" align="center" /><thead><row><entry namest="1" nameend="1" align="center">TABLE 2</entry></row></thead><tbody valign="top"><row><entry /></row><row><entry namest="1" nameend="1" align="center" rowsep="1" /></row><row><entry>0.15 Micron Process Geometries</entry></row></tbody></tgroup><tgroup align="left" colsep="0" rowsep="0" cols="4"><colspec colname="1" colwidth="42PT" align="center" /><colspec colname="2" colwidth="49PT" align="center" /><colspec colname="3" colwidth="63PT" align="center" /><colspec colname="4" colwidth="63PT" align="center" /><tbody valign="top"><row><entry /><entry>Void Depth,</entry><entry /><entry /></row><row><entry>Example</entry><entry>micron</entry><entry>Oxide 46, micron</entry><entry>Stem 50, micron</entry></row><row><entry namest="1" nameend="4" align="center" rowsep="1" /></row></tbody></tgroup><tgroup align="left" colsep="0" rowsep="0" cols="4"><colspec colname="1" colwidth="42PT" align="char" char="." /><colspec colname="2" colwidth="49PT" align="char" char="." /><colspec colname="3" colwidth="63PT" align="char" char="." /><colspec colname="4" colwidth="63PT" align="char" char="." /><tbody valign="top"><row><entry>1</entry><entry>0</entry><entry>0.06</entry><entry>.03</entry></row><row><entry>2</entry><entry>.02</entry><entry>.04</entry><entry>.03</entry></row><row><entry>3</entry><entry>.04</entry><entry>.02</entry><entry>.03</entry></row><row><entry>4</entry><entry>.0595</entry><entry>.0005</entry><entry>.03</entry></row><row><entry>5</entry><entry>0</entry><entry>.055</entry><entry>.04</entry></row><row><entry>6</entry><entry>.015</entry><entry>.04</entry><entry>.04</entry></row><row><entry>7</entry><entry>.025</entry><entry>.03</entry><entry>.04</entry></row><row><entry>8</entry><entry>0</entry><entry>.05</entry><entry>.05</entry></row><row><entry>9</entry><entry>.02</entry><entry>.03</entry><entry>.05</entry></row><row><entry>10</entry><entry>.03</entry><entry>.02</entry><entry>.05</entry></row><row><entry>11</entry><entry>.0495</entry><entry>.0005</entry><entry>.05</entry></row><row><entry namest="1" nameend="4" align="center" rowsep="1" /></row></tbody></tgroup></table></tables>

P-0062[0062]FIGS. 10 and 11 illustrate further processing according to an embodiment taken from the structure depicted in FIG. 9 by way of non-limiting example. FIG. 10 depicts structures constructed with the undercut that formed the lateral cavity <b>34</b>. In FIG. 10, a larger portion of the substrate <b>10</b> is illustrated so that adjacent partially isolated structures of active areas <b>32</b> may be seen. The partially isolated active areas <b>32</b> are separated by the recess <b>18</b> that, in this embodiment, acts as a shallow trench isolation (STI) trench. According to an embodiment, the recess <b>18</b> is filled with a material such as oxide by a known process such as a high-density plasma (HDP) technique. In one embodiment, the substrate <b>10</b> is blanket HDP deposited with an oxide fill <b>54</b> deposition which blankets the substrate <b>10</b> and which fills the recess <b>18</b>. Thereafter, the oxide fill <b>54</b> is etched back by a process that stops on the protective layer <b>14</b> if it is present as a polysilicon material. Where the protective layer <b>14</b> is present as a polysilicon material, overetching of the oxide fill <b>54</b> may occur. The etching back process is carried out according to process needs, such as by chemical-mechanical polishing (CMP), mechanical polishing (MP), chemical etchback, and others.

P-0063[0063] Another embodiment occurs where no protective layer <b>14</b> has remained during processing to this extent of the process. For example, where the protective layer <b>14</b> is a nitride material, it is removed simultaneously with the remnant of the nitride film <b>24</b> (FIG. 6). According to this embodiment, an oxide fill <b>54</b> is a doped or undoped material that shows a distinctive etch responsiveness in comparison to the pad oxide layer <b>12</b>, such that the pad oxide layer <b>12</b> acts as the etch stop.

P-0064[0064] As depicted in FIG. 10, the material filling the recess <b>18</b> is etched or planarized so that the top surface <b>56</b> of the oxide fill <b>54</b> is approximately even with the top surface of the pad oxide layer <b>12</b>. Where the protective layer <b>14</b> is present such as a polysilicon material, the remnants of the protective layer <b>14</b> is stripped in a manner so as not to damage the remnants of the pad oxide layer <b>12</b>. In one embodiment, the remnant of the pad oxide layer <b>12</b> is used as a gate oxide for the fabrication of active devices above the active area <b>32</b>.

P-0065[0065] Total isolation between devices on the active areas <b>32</b> can be as much as 0.65 microns (0.2 microns of the oxide fill <b>54</b>, plus 0.25 microns of the active are <b>32</b>, plus 0.2 microns of the oxide fill <b>54</b>) for a given 0.25-micron lithography. Furthermore, the field oxide regions are comprised of both thermal oxide and deposited oxide so that the advantages of each type of oxide can be gained.

P-0066[0066] The structure depicted in FIG. 10 is also depicted in FIG. 11 as a storage device, wherein two dynamic random access (DRAM) memory cells are formed thereon. Active devices in the form of a digit line junction <b>58</b> and storage node junctions <b>60</b> and <b>62</b> are formed in the partially isolated active area <b>32</b>. A word line <b>64</b> overlays the active area <b>32</b>. The storage node junctions <b>60</b> and <b>62</b> are in electrical contact with respective capacitors <b>66</b> and <b>68</b> through polysilicon plugs <b>70</b>. The digit line junction <b>58</b> is in electrical contact with a polysilicon plug <b>72</b>. The polysilicon plug <b>72</b> is a contact that touches the active area <b>32</b>. The polysilicon plug <b>72</b> is in further contact with a digit line <b>74</b> through a metal plug <b>76</b>.

P-0067[0067] A substrate <b>10</b> carrying a partially isolated active area <b>32</b> provides a vehicle for the fabrication of a storage device such as a DRAM cell, or virtually any type of logic circuit that employs a MOSFET.

P-0068[0068] While the structure depicted in FIG. 11 illustrates one type of device which might be fabricated upon the workpiece of the substrate <b>10</b> and with the use of the partially isolated active area <b>32</b>, those of ordinary skill in the art will recognize the advantages of fabricating other types of devices according to various embodiments and their equivalents. In particular, active devices formed in the partially isolated active area <b>32</b> will be substantially isolated from the bulk of the substrate <b>10</b>.

P-0069[0069]FIG. 12 illustrates another process embodiment in which a deep implantation region is first implanted into the substrate. In this embodiment, the substrate <b>110</b> has a deep implantation region <b>130</b> that has been blanket implanted to a depth that is qualitatively equivalent to the location of the deep implantation region <b>30</b> depicted in FIG. 4. In one embodiment, the deep implantation region <b>130</b> is made of materials that are identical to the bulk semiconductive material in the substrate <b>110</b>. At the level of the recess second bottom <b>26</b>, a deep implantation region <b>30</b> is formed. In one embodiment, the deep implantation region <b>30</b> is made of materials that are substantially identical to the bulk semiconductive material in the substrate <b>10</b>. Implantation is carried out at an energy level that achieves self-interstitial implantation, and that causes the implantation region <b>30</b> to become amorphous enough to have an etch responsiveness that is different from the bulk semiconductive material in the substrate <b>10</b>. In one embodiment, implantation conditions use a silicon source that is implanted to a monocrystalline-to-self interstitial ratio of about 3:1. By “silicon source” it is meant that silicon or another Group IV element is used, or a combination such as silicon and germanium. In one embodiment, the implanted concentration is from about 5E14 atoms/cm²to about 5E15 atoms/cm²at process conditions of ambient temperature (20 C. to about 30 C.) and an implantation energy from about 20 KeV to about 30 KeV. In one embodiment, a silicon source that is substantially equivalent to the silicon chemistry of the bulk of the semiconductive substrate <b>10</b>, is implanted to a concentration of about 25E14 atoms/cm²and process conditions are about 25 C. and an implantation energy of about 25 KeV. The vertical implantation profile is controlled to be narrow with respect to the specific process geometry. In one embodiment, the vertical implantation profile has a height of about 0.05 microns when measured upwardly, beginning at the level that will make up the recess second bottom <b>126</b> (see FIG. 15).

P-0070[0070] A pad oxide layer <b>112</b> is also deposited on the substrate <b>110</b>, as well as a protective layer <b>114</b> on top of the pad oxide layer <b>112</b> to act as a buffer during subsequent etch steps and other processing. In one embodiment, the protective layer <b>114</b> is polysilicon. In one embodiment, the protective layer <b>114</b> is a nitride material. In another embodiment, the protective layer <b>114</b> is a polysilicon layer that is covered with a nitride material. The specific combination is selected depending upon process integration choices.

P-0071[0071] A mask <b>116</b> is formed and patterned upon the protective layer <b>114</b>. In one embodiment, the mask <b>116</b> is a photoresist material or a hard mask material such as a nitride or oxide according to embodiments set forth herein. The area protected by the mask <b>116</b> defines what will become a partially isolated active area in a partial SOI structure.

P-0072[0072]FIG. 13 illustrates an embodiment after an etch process that has exposed the regions unprotected by the mask <b>116</b>. In the etch process, the protective layer <b>114</b> and the pad oxide layer <b>112</b> have also been patterned, and a recess <b>118</b> has been formed with a recess first bottom <b>120</b> and a recess first wall <b>122</b>.

P-0073[0073]FIG. 14 illustrates the structure depicted in FIG. 13 after further processing in which the mask <b>116</b> has been removed and a nitride film <b>124</b> has been grown onto the exposed semiconductive material of the substrate <b>110</b>. In one embodiment, the exposed semiconductive material of the substrate <b>110</b> is exposed silicon. The nitride film <b>124</b> is depicted as covering the recess first bottom <b>120</b> and the recess first wall <b>122</b>. The nitride film <b>124</b> may be grown by known process under conditions that deposit only upon semiconductive material such as exposed silicon as set forth herein for the embodiments depicted in FIG. 3 such as RPN, RTN, RPO, and RTO.

P-0074[0074]FIG. 15 illustrates processing of the substrate <b>110</b> in which an etch has formed a recess second wall <b>128</b> and a recess second bottom <b>126</b> below the level of the recess first bottom <b>120</b>. Because of the presence of the nitride film <b>124</b>, the recess first wall <b>112</b> is protected, and the recess second wall <b>128</b> has been formed that is approximately coplanar with the lateral extremity of the nitride film <b>124</b>. In one embodiment, an anisotropic etch, such as a reactive ion etch, is used such that the nitride film <b>124</b> is left standing upon what is left of the recess first bottom <b>120</b>. For a 0.25-micron CD process, the remnant of the nitride film <b>124</b> has a height, H, in a range from about 0.1 micron to about 0.15 microns. In this dimension, the distance from the remnant of the recess first bottom <b>120</b> to the recess second bottom <b>126</b> is in a range from about 0.1 micron to about 0.3 microns.

P-0075[0075] At the level of the recess second bottom <b>126</b>, the deep implantation region <b>130</b> is exposed. According to an embodiment, the deep implantation region <b>130</b> acts as an etch stop. In one example, an anisotropic etch is carried out that has an etch recipe selective to the deep implantation region <b>130</b>.

P-0076[0076] In another embodiment, external process control is used to stop the etch at the level of the deep implantation region <b>130</b>. After the etch that either stops on the deep implantation region <b>130</b> by chemical selectivity, or by external process control, an isotropic etch recipe is used in subsequent processing that is selective to the amorphous material of the deep implantation region <b>130</b>, but the etch recipe removes bulk semiconductive material in the substrate <b>110</b>. In one embodiment, the etch recipe is a wet TMAH etch as set forth herein for other embodiments. In another embodiment, the wet etch uses a KOH etch chemistry as set forth herein for other embodiments. The isotropic etch may also be combined with an anisotropic etch, either before or after the isotropic etch. By using both an isotropic and an anisotropic etch, both the downward etching and the undercutting of the nitride film <b>124</b> may be varied to suit particular applications.

P-0077[0077] Various wet TMAH etch recipes are known that are selective to amorphous silicon and to nitride films, and that isotropically etch bulk monocrystalline silicon along crystallographic planes. FIG. 16 illustrates the results of a TMAH etch that has formed a lateral cavity <b>134</b> that has undercut the active area <b>132</b>. By this undercutting etch, the active area <b>132</b> has been mostly separated from the bulk semiconductive material in the substrate <b>110</b> and substantially no etching through the deep implantation region <b>130</b> has occurred.

P-0078[0078] Under the etch conditions, and due to the scale of the lateral cavity <b>134</b>, a distinctive contour may appear therein. The TMAH etch has an effect along crystallographic planes such that a faceted contour may appear within the lateral cavity <b>134</b>. It can be seen that faceted surfaces <b>136</b>, <b>138</b>, <b>140</b>, and <b>142</b> are illustrated. However, these are depicted in arbitrary shape, angle and size for illustrative purposes, and the specific shapes, angles, and sizes of the faceted surfaces will depend upon the crystallographic orientation of the bulk semiconductive material in the substrate <b>110</b> and the specific etch conditions. According to the specific etch conditions, a photomicrographic view of the lateral cavity <b>134</b> will depict substended crystallographic planes of bulk semiconductive material in the substrate <b>110</b> that have been exposed by the TMAH etch.

P-0079[0079] After formation of the lateral cavity <b>134</b>, the deep implantation region <b>130</b> is treated to form an annealed deep implantation region <b>144</b> as illustrated in FIG. 17. Particularly at free surfaces, the annealed deep implantation region <b>144</b> has been return to substantially the same semiconductive quality as the bulk semiconductive material in the substrate <b>110</b> by repairing at least some of the monocrystalline lattice in what was the deep implantation region <b>130</b> (FIG. 16). Further processing, including oxidation, oxide spacer formation, STI oxide fill processing, planarization, and device construction, among other processes are carried out as set forth in embodiments in this disclosure.

P-0080[0080]FIG. 18 illustrates another embodiment in which two implantation regions are first implanted into the substrate. In one embodiment, the substrate <b>210</b> has a deep implantation region <b>230</b> that has been first blanket implanted to a qualitative depth that is equivalent to the location of the deep implantation region <b>30</b> depicted in FIG. 4, or the deep implantation region <b>130</b> depicted in FIG. 14. A shallow implantation region <b>278</b> is second blanket implanted into the substrate <b>210</b>. The shallow implantation region <b>278</b> is implanted to a qualitative depth that is equivalent to the location of the recess first bottom <b>20</b> depicted in FIG. 4, or the recess first bottom <b>120</b> depicted in FIG. 14. As in other embodiments set forth herein, the deep implantation region <b>230</b> and the shallow implantation region <b>278</b> are implanted with materials that are substantially identical to the bulk semiconductive material in the substrate <b>210</b>. Implantation is carried out at an energy level that achieves self-interstitial implantation, and that causes the implantation regions <b>230</b> and <b>278</b> to become amorphous enough to have an etch responsiveness that is different from the bulk semiconductive material in the substrate <b>210</b>. The achievement of the implantation regions <b>230</b> and <b>278</b> is done according to processing conditions known in the art, and as set forth herein. The implantation profiles are controlled to be narrow with respect to the specific process geometry. In one embodiment, the implantation profiles each have a height of about 0.05 microns.

P-0081[0081] A pad oxide layer <b>212</b> is also deposited on the substrate <b>210</b>, as well as a protective layer <b>214</b> on top of the pad oxide layer <b>212</b> to act as a buffer during subsequent etch steps and other processing. In one embodiment, the protective layer <b>214</b> is polysilicon. In one embodiment, the protective layer <b>214</b> is a nitride material. In another embodiment, the protective layer <b>214</b> is a polysilicon layer that is covered with a nitride material. The specific combination is selected depending upon process integration choices.

P-0082[0082] A mask <b>216</b> is formed and patterned upon the protective layer <b>214</b>. As set forth herein for other embodiments, the mask <b>216</b> is either a photoresist material or a hard-mask material such as a nitride or oxide. The area protected by the mask <b>116</b> defines what will become a partially isolated active area in a partial SOI structure.

P-0083[0083]FIG. 19 illustrates an embodiment after an etch process that has exposed the regions unprotected by the mask <b>216</b>. In the etch process, the protective layer <b>214</b> and the pad oxide layer <b>212</b> have also been patterned, and a recess <b>218</b> has been formed with a recess first bottom <b>220</b> and a recess first wall <b>222</b>. It is noted that the first etch has also stopped at or below the level of the shallow implantation region <b>278</b>.

P-0084[0084]FIG. 20 illustrates the structure depicted in FIG. 19 after further processing in which the mask <b>216</b> has been removed and a nitride film <b>224</b> has been grown onto the exposed semiconductive material of the substrate <b>210</b>. In one embodiment, the exposed semiconductive material of the substrate <b>210</b> is exposed silicon. The nitride film <b>224</b> is depicted as covering the recess first bottom <b>220</b> and the recess first wall <b>222</b>. The nitride film <b>224</b> may be grown by known process under conditions that deposit only upon semiconductive material such as exposed silicon as set forth herein for the embodiments depicted in FIG. 3 and FIG. 14. The nitride film <b>224</b> may be grown by known process under conditions that deposit only upon semiconductive material such as exposed silicon as set forth herein for the embodiments depicted in FIG. 3 such as RPN, RTN, RPO, and RTO.

P-0085[0085]FIG. 21 illustrates processing of the substrate <b>210</b> in which an etch has formed a recess second wall <b>228</b> and a recess second bottom <b>226</b> below the level of the recess first bottom <b>220</b>. Because of the presence of the nitride film <b>224</b>, the recess first wall <b>222</b> is protected, and the recess second wall <b>228</b> has been formed that is approximately coplanar with the lateral extremity of the nitride film <b>224</b>. In one embodiment, an anisotropic etch, such as a reactive ion etch, is used such that the nitride film <b>224</b> is left standing upon what is left of the recess first bottom <b>220</b>. For a 0.25-micron CD process, the remnant of the nitride film <b>224</b> has a height, H, in a range from about 0.1 microns to about 0.15 microns. In this dimension, the distance from the remnant of the recess first bottom <b>220</b> to the recess second bottom <b>226</b> is in a range from about 0.1 microns to about 0.3 microns. According to an embodiment, the deep implantation region <b>230</b> acts as an etch stop. In one example, an anisotropic etch is carried out that has an etch recipe selective to the deep implantation region <b>230</b>.

P-0086[0086]FIG. 22 illustrates further processing according to an embodiment. After the etch that either stops on the deep implantation region <b>230</b> by chemical selectivity, or by external control, an isotropic etch recipe is used in subsequent processing that is selective to the amorphous material of the shallow implantation region <b>278</b> and the deep implantation region <b>230</b>. The etch recipe removes bulk semiconductive material in the substrate <b>110</b> that lies between the shallow implantation region <b>278</b> and the deep implantation region <b>230</b>. In this embodiment, the formation of a lateral cavity <b>234</b> is restricted by the presence of the shallow implantation region <b>278</b> above, and the deep implantation region <b>230</b> below. Accordingly, the height <b>280</b> of the lateral cavity <b>234</b> is controllable, subject to process restrictions such as the depths of the respective the shallow- and deep implantation regions <b>278</b> and <b>230</b> and their spacing apart one from the other. In one embodiment, the height <b>280</b> is in a range from about 0.01 microns to about 0.1 microns. In another embodiment, the height <b>280</b> is about 0.02 microns. This embodiment is useful wherein a voided lateral cavity <b>234</b> will have a dielectric constant essentially that of air because any oxidation or subsequent fill of the recess <b>218</b> may not penetrate into the lateral cavity <b>234</b>.

P-0087[0087] In one embodiment, the etch recipe for forming the lateral cavity <b>234</b> is a wet TMAH etch as set forth herein for other embodiments. In another embodiment, the wet etch uses a KOH etch chemistry as set forth herein for other embodiments. The isotropic etch may also be combined with an anisotropic etch, either before or after the isotropic etch.

P-0088[0088]FIG. 22 illustrates the results of a TMAH etch that has formed the lateral cavity <b>234</b> that has undercut the active area <b>232</b>. By this undercutting etch, the active area <b>232</b> has been mostly separated from the bulk semiconductive material in the substrate <b>210</b>.

P-0089[0089] Under the etch conditions, and due to the scale of the lateral cavity <b>234</b>, a distinctive contour may appear therein. The TMAH etch has an effect along crystallographic planes such that a faceted contour may appear within the lateral cavity <b>234</b> as discussed for embodiments depicted in FIGS. 5 and 16. As set forth for other embodiments, the specific shapes, angles, and sizes of the faceted surfaces will depend upon the crystallographic orientation of the bulk semiconductive material in the substrate <b>210</b>. According to the specific etch conditions, a photomicrographic view of the lateral cavity <b>234</b> will depict substended crystallographic planes of bulk semiconductive material in the substrate <b>210</b> that have been exposed by the TMAH etch.

P-0090[0090] After formation of the lateral cavity <b>234</b>, the implantation regions <b>278</b> and <b>230</b> are treated by a process such as solid-phase epitaxy to form annealed implantation regions <b>282</b> and <b>224</b>, respectively, as illustrated in FIG. 23. Particularly at the free surfaces, the annealed implantation regions <b>282</b> and <b>224</b> have been returned to substantially the same semiconductive quality as the bulk semiconductive material in the substrate <b>110</b> by repairing the monocrystalline lattice in what was the implantation region <b>278</b> and <b>230</b> (FIG. 22). In one embodiment, although some portions of the implantation regions <b>278</b> and <b>230</b> (FIG. 22) may not totally return to substantially the same semiconductive quality as the bulk semiconductive material in the substrate <b>210</b> and in the active area <b>232</b>, the depth <b>224</b> of the active area <b>232</b> (also measured by the height, H, of the nitride film) may be controlled such that the amorphous portions, if any, that remain will be significantly far from the final channel and junctions of the active area <b>232</b> such that they are operative. Further processing, including minifield oxidation, oxide spacer formation, STI oxide fill processing, planarization, and device construction, among other processes are carried out as set forth in embodiments in this disclosure. In one embodiment, the minifield oxidation consumes significant remaining implantation regions <b>282</b> and <b>244</b>.

P-0091[0091] To one of ordinary skill in the art, it now becomes clear that other processing variations are possible. For example (referring to FIG. 2 and <b>4</b> as a guide), the deep implantation region <b>30</b> may be first formed after the first etch by implanting through the recess first bottom <b>20</b> to what will become the level of the recess second bottom <b>26</b>. In this example, the deep implantation region <b>30</b> may be formed in a reactive ion etch (RIE) chamber that also carries out the second etch, and the conditions can proceed after the first etch and growth of the nitride film <b>24</b> by an ion implantation to form the deep implantation region <b>30</b> through the first bottom, and a second etch that stops on the deep implantation region <b>30</b>.

P-0092[0092] The processes and structures that are achieve in the various embodiments are inventively applicable to a variety of devices and apparatuses. Preferred systems may be made by process embodiments, or that include an embodiment or embodiments of the structure. For example, a chip package may contain a partially isolated structure such as an active area set forth in this disclosure. In one embodiment, an array of active areas is included such as a line of sense amplifiers that use the active areas, or a 2-dimensional array of storage devices such as a DRAM array. In another embodiment, the partially isolated structure is part of an electrical device that includes the semiconductor substrate in a chip package and the chip package is part of a memory module or part of a chipset. In another embodiment, the memory module is part of a dynamic random access memory module that is inserted into a host such as a motherboard or a digital computer. In another embodiment, preferred systems may be made that include the partially isolated structure. For example, a chip package may contain a substrate such as one set forth in this disclosure. In another embodiment, the partially isolated structure is part of an electrical device that includes the semiconductor substrate in a chip package and the chip package is part of a memory module or part of a chipset. In another embodiment, the memory module is part of a dynamic random access memory module that is inserted into a host such as a motherboard or a digital computer. In another embodiment, the partially isolated structure is part of an electronic system. In another embodiment, the partially isolated structure is fabricated with a floating gate. In another embodiment, the partially isolated structure is fabricated with a floating gate that is part of a flash memory device that in turn is part of a chipset such as a basic input-output system (BIOS) for an electrical device.

P-0093[0093] In another embodiment, preferred systems may be made that include the partially isolated structure. With reference to FIG. 24, a semiconductor die <b>2410</b> may be produced from a silicon wafer <b>2400</b> that may contain the partially isolated active area structures <b>32</b>, <b>132</b>, and <b>232</b> respectively, such as are depicted in FIGS. 7, 8, and <b>9</b>. A die <b>2410</b> is an individual pattern, typically rectangular, on a substrate such as substrate <b>10</b>, substrate <b>110</b>, and substrate <b>210</b>, that contains circuitry to perform a specific function. A semiconductor wafer <b>2400</b> will typically contain a repeated pattern of such dies <b>2410</b> containing the same functionality. Die <b>2410</b> may further contain additional circuitry to extend to such complex devices as a monolithic processor with multiple functionality. Die <b>2410</b> is typically packaged in a protective casing (not shown) with leads extending therefrom (not shown) providing access to the circuitry of the die <b>2410</b> for unilateral or bilateral communication and control. In one embodiment, die <b>2410</b> is incased in a host such as a chip package (not shown) such as a chip-scale package (CSP).

P-0094[0094] As shown in FIG. 25, two or more dies <b>2410</b> at least one of which contains at least one partially isolated structure such as is depicted in FIGS. 7, 8, and <b>9</b>, in accordance with various embodiments may be combined, with or without protective casing, into a host such as a circuit module <b>2500</b> to enhance or extend the functionality of an individual die <b>2410</b>. Circuit module <b>2500</b> may be a combination of dies <b>2410</b> representing a variety of functions, or a combination of dies <b>2410</b> containing the same functionality. Some examples of a circuit module <b>2500</b> include memory modules, device drivers, power modules, communication modems, processor modules and application-specific modules and may include multi-layer, multi-chip modules. Circuit module <b>2500</b> may be a sub-component of a variety of electronic systems, such as a clock, a television, a cell phone, a personal computer, an automobile, an industrial control system, an aircraft, a hand-held, and others. Circuit module <b>2500</b> will have a variety of leads <b>2510</b> extending therefrom providing unilateral or bilateral communication and control. In another embodiment, circuit module <b>2500</b> has a storage device such as is depicted in FIG. 11.

P-0095[0095]FIG. 26 shows one embodiment of a circuit module as memory module <b>2600</b> containing a structure for the inventive partially isolated structure such as are depicted in FIGS. 7, 8, and <b>9</b>, or the storage device as is depicted in FIG. 11. Memory module <b>2600</b> is a host for that generally depicts a Single In-line Memory Module (SIMM) or Dual In-line Memory Module (DIMM). A SIMM or DIMM may generally be a printed circuit board (PCB) or other support containing a series of memory devices. While a SIMM will have a single in-line set of contacts or leads, a DIMM will have a set of leads on each side of the support with each set representing separate I/O signals. Memory module <b>2600</b> contains multiple memory devices <b>2610</b> contained on support <b>2615</b>, the number depending upon the desired bus width and the desire for parity. Memory module <b>2600</b> may contain memory devices <b>2610</b> on both sides of support <b>2615</b>. Memory module <b>2600</b> accepts a command signal from an external controller (not shown) on a command link <b>2620</b> and provides for data input and data output on data links <b>2630</b>. The command link <b>2620</b> and data links <b>2630</b> are connected to leads <b>2640</b> extending from the support <b>2615</b>. Leads <b>2640</b> are shown for conceptual purposes and are not limited to the positions shown in FIG. 26.

P-0096[0096]FIG. 27 shows another host type such as an electronic system <b>2700</b> containing one or more circuit modules <b>2500</b> as described above containing at least one of the inventive partially isolated structures or data storage devices. Electronic system <b>2700</b> generally contains a user interface <b>2710</b>. User interface <b>2710</b> provides a user of the electronic system <b>2700</b> with some form of control or observation of the results of the electronic system <b>2700</b>. Some examples of user interface <b>2710</b> include the keyboard, pointing device, monitor and printer of a personal computer; the tuning dial, display and speakers of a radio; the ignition switch of gas pedal of an automobile; and the card reader, keypad, display and currency dispenser of an automated teller machine. User interface <b>2710</b> may further describe access ports provided to electronic system <b>2700</b>. Access ports are used to connect an electronic system to the more tangible user interface components previously exemplified. One or more of the circuit modules <b>2500</b> may be a processor providing some form of manipulation, control or direction of inputs from or outputs to user interface <b>2710</b>, or of other information either preprogrammed into, or otherwise provided to, electronic system <b>2700</b>. As will be apparent from the lists of examples previously given, electronic system <b>2700</b> will often contain certain mechanical components (not shown) in addition to the circuit modules <b>2500</b> and user interface <b>2710</b>. It will be appreciated that the one or more circuit modules <b>2500</b> in electronic system <b>2700</b> can be replaced by a single integrated circuit. Furthermore, electronic system <b>2700</b> may be a sub-component of a larger electronic system.

P-0097[0097]FIG. 28 shows one embodiment of an electrical device at a system level. The electronic system depicted in FIG. 28 is a memory system <b>2800</b>. Memory system <b>2800</b> acts as a higher-level host that contains one or more memory modules <b>2600</b> as described above including at least one of the partially isolated structure or the data storage device such as set forth herein in accordance with the present invention and a memory controller <b>2810</b> that may also include circuitry for the inventive partially isolated structure or the data storage device. Memory controller <b>2810</b> provides and controls a bidirectional interface between memory system <b>2800</b> and an external system bus <b>2820</b>. Memory system <b>2800</b> accepts a command signal from the external system bus <b>2820</b> and relays it to the one or more memory modules <b>2600</b> on a command link <b>2830</b>. Memory system <b>2800</b> provides for data input and data output between the one or more memory modules <b>2600</b> and external system bus <b>2820</b> on data links <b>2840</b>.

P-0098[0098]FIG. 29 shows a further embodiment of an electronic system as a computer system <b>2900</b>. Computer system <b>2900</b> contains a processor <b>2910</b> and a memory system <b>2800</b> housed in a computer unit <b>2915</b>. Computer system <b>2900</b> is but one example of an electronic system containing another electronic system, i.e. memory system <b>2600</b>, as a sub-component. The computer system <b>2900</b> may contain an input/output (I/O) circuit <b>2920</b> that is coupled to the processor <b>2910</b> and the memory system <b>2600</b>. Computer system <b>2900</b> optionally contains user interface components that are coupled to the I/O circuit <b>2920</b>. In accordance with the present invention a plurality partially isolated structures or data storage devices may each be coupled to one of a plurality of I/O pads or pins <b>2930</b> of the I/O circuit <b>2920</b>. The I/O circuit <b>2920</b> may then be coupled a monitor <b>2940</b>, a printer <b>2950</b>, a bulk storage device <b>2960</b>, a keyboard <b>2970</b> and a pointing device <b>2980</b>. It will be appreciated that other components are often associated with computer system <b>9400</b> such as modems, device driver cards, additional storage devices, etc. It will further be appreciated that the processor <b>2910</b>, memory system <b>2600</b>, I/O circuit <b>2920</b> and partially isolated structures or data storage devices of computer system <b>2900</b> can be incorporated on a single integrated circuit. Such single package processing units reduce the communication time between the processor <b>2910</b> and the memory system <b>2900</b>.

CONCLUSION

P-0099[0099] Thus has been shown a partially isolated active area and a process of fabricating the partially isolated active area that uses at least a deep implantation region to facilitate an etch that forms a lateral cavity. Embodiments of the present invention relate to processes that facilitate the partial isolation of the active area and varying degrees of oxidation if present in the lateral cavity. The partial isolation is carried out by an etch that is selective to an deep implantation region. The deep implantation region has been temporarily made amorphous, and a silicon ledge forms above the amorphous material. The process solves the problem of achieving an etch differential quality at the bottom of a trench that was carried out by other methods such as an extra deposition. The process also results in various degrees of partial isolation, depending upon the extent of a minifield oxidation operation, if it is present. Where there is a native oxide film in the lateral recess, a faceted surface remains as a result of the specific etch conditions.

P-0100[0100] A structure is also achieved that includes a faceted lateral cavity in one embodiment. The faceted lateral cavity acts to partially isolate the active area from the bulk of the substrate.

P-0101[0101] While the present invention has been described in connection with a preferred embodiment thereof, those of ordinary skill in the art will recognize that many modifications and variations may be employed. For example, the sample dimensions and process parameters disclosed herein may be varied and are disclosed for the purpose of illustration and not limitation. The foregoing disclosure and the following claims are intended to cover all such modifications and variations.