Multistage autozero sensing for a multilevel non-volatile memory integrated circuit system

CROSS-REFERENCE TO RELATED APPLICATIONS

P-0001[0001] This is a continuation-in-part of Application Serial No. 10/211,886, filed Aug. 1, 2002, which is a continuation-in-part of Application Serial No. 09/929,542, filed Aug. 13, 2001, which is a division of Application Serial No. 09/231,928 filed Jan. 14, 1999, issued as U.S. Pat. No. 6,282,145, the subject matter of each of these applications is incorporated herein by reference.

P-0002[0002] This application is related to U.S. patent application Ser. No. ______ (Attorney Docket No. 2102397-992390), filed on even date herewith, entitled “Digital Multilevel Memory System Having Multistage Autozero Sensing”, inventor Hieu Van Tran, the disclosure of which is incorporated herein by reference, U.S. patent application Ser. No. ______ (Attorney Docket No. 2102397-992540), filed on even date herewith, entitled “Digital Multilevel Non-Volatile Memory System”, inventor Hieu Van Tran, the disclosure of which is incorporated herein by reference, and U.S. patent application Ser. No. ______ (Attorney Docket No. <b>2102397</b> - <b>992550</b> ), filed on even date herewith, entitled “Sub-Volt Sensing for Digital Multilevel Flash Memory”, inventor Hieu Van Tran, the disclosure of which is incorporated herein by reference.

FIELD OF THE INVENTION

[0003] This invention relates in general to semiconductor memories, and, in particular, to the design and operation of multilevel nonvolatile semiconductor memories.

BACKGROUND OF THE INVENTION

[0004] As the information technology progresses, the demand for high density giga bit and tera bit memory integrated circuits is insatiable in emerging applications such as data storage for photo quality digital film in multi-mega pixel digital camera, CD quality audio storage in audio silicon recorder, portable data storage for instrumentation and portable personal computers, and voice, data, and video storage for wireless and wired phones and other personal communicating assistants.

[0005] The nonvolatile memory technology such as ROM (Read Only Memory), EEPROM (Electrical Erasable Programmable Read Only Memory), or FLASH is often a technology of choice for these application due to its nonvolatile nature, meaning it still retains the data even if the power supplied to it is removed. This is in contrast with the volatile memory technology, such as DRAM (Dynamic Random Access Memory), which loses data if the power supplied to it is removed. This nonvolatile feature is very useful in saving the power from portable supplies, such as batteries. Until battery technology advances drastically to ensure typical electronic systems to function for a typical operating lifetime, e.g., <b>10</b> years, the nonvolatile technology will fill the needs for most portable applications.

[0006] The FLASH technology, due to its smallest cell size, is the highest density nonvolatile memory system currently available. The advance of the memory density is made possible by rapidly advancing the process technology into the realm of nano meter scale and possibly into the atomic scale and electron scale into the next century. At the present ;sub-micro meter scale, the other method that makes the super high-density memory system possible is through the exploitation of the analog nature of a storage element.

[0007] The analog nature of a flash or nonvolatile storage element provides, by theory, an enormous capability to store information. For example, if one electron could represent one bit of information then, for one typical conventional digital memory cell, the amount of information is equal to the number of electrons stored, or approximately a few hundred thousands. Advances in device physics exploring the quantum mechanical nature of the electronic structure will multiply the analog information manifested in the quantum information of a single electron even further.

[0008] The storage information in a storage element is hereby defined as a discrete number of storage levels for binary digital signal processing with the number of storage levels equal to <b>2</b>^Nwith N equal to the number of digital binary bits. The optimum practical number of discrete levels stored in a nonvolatile storage element depends on the innovative circuit design method and apparatus, the intrinsic and extrinsic behavior of the storage element, all within constraints of a definite performance target, such as product speed and operating lifetime, with a certain cost penalty.

[0009] At the current state of the art, all the multilevel systems are only suitable for medium density, i.e. less than a few tens of mega bits, and only suitable for a small number of storage levels per cell, i.e., less than four levels or two digital bits.

[0010] As can be seen, memories having high storage capacity and fast operating speed are highly desirable.

[0011] The signal path from the data cells to a sense amplifier may have mismatch with the signal path from the reference memory cells to the sense amplifier. The mismatch generates a current ratio error and may be caused by mismatches of the threshold voltage, the width, length, mobility, and oxide thickness of the circuit elements, such as transistors, in the signal paths. The mismatch also may be caused by mismatch in signal paths due to parasitics, such as width and length of interconnects.

SUMMARY OF THE INVENTION

[0012] A data storage system comprises a plurality of memory arrays. Each memory array comprises a plurality of memory subarrays that each include a plurality of data memory cells and a plurality of reference memory cells, and a plurality of local sense amplifiers. Each local sense amplifier is coupled to a corresponding one of the plurality of memory subarrays and reads the contents of data memory cells by comparing the contents to currents or voltages from reference memory cells within the corresponding memory subarray. The local sense amplifier equalizes an output of the local sense amplifier to a current or voltage of the corresponding reference memory cell prior to sensing of the data memory cell.

[0013] The data storage system may further comprise a plurality of global sense amplifiers that are each coupled to a group of the plurality of local sense amplifiers. The global sense amplifiers may include an autozero function to equalize an output of the global sense amplifier to an input of the global sense amplifier prior to sensing of the data memory cell.

[0014] The memory subarrays may be arranged in pages of memory cells that include both data memory cells and reference memory cells. The memory system may include segment reference cells.

[0015] The data storage system may include sub-volt sensing amplifiers and built-in byte redundancy.

[0016] The foregoing, together with other aspects of this invention, will become more apparent when referring to the following specification, claims, and accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

P-0017[0017]FIG. 1A is a cross section of a source side injection flash memory cell.

P-0018[0018]FIG. 1B is a transistor symbol corresponding to the source side injection flash memory cell shown in FIG. 1A.

P-0019[0019]FIG. 1C is a block diagram of a nonvolatile multilevel memory system.

P-0020[0020]FIG. 1D is a block diagram of an electronic camera system utilizing a nonvolatile multilevel memory system.

P-0021[0021]FIG. 1E is a block diagram of an electronic audio system utilizing a nonvolatile multilevel memory system.

P-0022[0022]FIG. 2A is a block diagram of super high-density nonvolatile multilevel memory integrated circuit system.

P-0023[0023]FIG. 2B is a block diagram of flash power management unit.

P-0024[0024]FIG. 2C shows voltage mode sensing.

P-0025[0025]FIG. 3A is a block diagram of super high-density nonvolatile multilevel array architecture.

P-0026[0026]FIG. 3B is a page select circuit, which together with the segment select decoder selects one bitline at a time for each y-driver.

P-0027[0027]FIG. 3C is a block diagram of a multilevel sub-array block.

P-0028[0028]FIG. 4A is one embodiment of a nonvolatile multilevel array unit of inhibit and select segmentation.

P-0029[0029]FIG. 4B shows an alternate embodiment of the inhibit and select segmentation scheme.

P-0030[0030]FIG. 4C shows another alternate embodiment of the inhibit and select segmentation scheme.

P-0031[0031]FIG. 4D shows another alternate embodiment of the inhibit and select segmentation scheme.

P-0032[0032]FIG. 4E shows another alternate embodiment of the inhibit and select segmentation scheme.

P-0033[0033]FIG. 4F shows another alternate embodiment of the inhibit and select segmentation scheme.

P-0034[0034]FIG. 5A is a cross section of inhibit and select segmentation interconnection.

P-0035[0035]FIG. 5B is a cross section of another embodiment of inhibit and select segmentation interconnection.

P-0036[0036]FIG. 5C is a 2-step ramp rate control and fast-slow ramp rate control.

P-0037[0037]FIG. 6 shows a block diagram of multilevel decoding.

P-0038[0038]FIG. 7 shows one segment decoder that includes segmented power supply decoder, segmented bitline select decoder, inhibit decoder, segmented predecoded common line decoder, and control gate and control line decoder.

P-0039[0039]FIG. 8 shows a segmented power supply decoder.

P-0040[0040]FIG. 9A shows a segmented bitline decoder.

P-0041[0041]FIG. 9B shows a segmented inhibit decoder.

P-0042[0042]FIG. 9C shows a segmented predecoded common line decoder.

P-0043[0043]FIG. 10 shows a sub-block decoder for control gate and common line multilevel decoder.

P-0044[0044]FIG. 11A shows a sub-block of the circuit in FIG. 10 for four control gates and one common line multilevel decoder.

P-0045[0045]FIG. 11B shows another embodiment of sub-block for four control gates and one common line multilevel decoder with winner-take-all Kelvin connection.

P-0046[0046]FIG. 11C shows a circuit for one common line driver.

P-0047[0047]FIG. 12 shows a scheme of the feedthrough-to-driver and feedthrough-to-memory multilevel precision decoding.

P-0048[0048]FIG. 13 shows a block diagram of a multilevel reference system.

P-0049[0049]FIG. 14 shows details of a block diagram of a multilevel reference system.

P-0050[0050]FIG. 15 shows a reference detection scheme.

P-0051[0051]FIG. 16 shows positional linear reference system.

P-0052[0052]FIG. 17 shows a positional geometric reference system.

P-0053[0053]FIG. 18 shows an embodiment of geometric compensation reference scheme.

P-0054[0054]FIG. 19A shows voltage levels for program verify, margin, read, and restore for one embodiment of the current invention.

P-0055[0055]FIG. 19B shows voltage levels for program verify, margin, read, and restore for an alternative embodiment of the current invention.

P-0056[0056]FIG. 20 shows an embodiment of flow diagram of the page programming cycle.

P-0057[0057]FIG. 21 shows an embodiment of flow diagram after page programming begins.

P-0058[0058]FIG. 22A shows a continuation of flow diagram after page programming begins.

P-0059[0059]FIG. 22B shows an alternative embodiment of continuation of flow diagram after page programming begins shown in FIG. 22A.

P-0060[0060]FIG. 22C shows an alternate embodiment of the flow diagram shown in FIG. 22B.

P-0061[0061]FIG. 23 shows an embodiment of flow diagram of the page read cycle.

P-0062[0062]FIG. 24 shows a continuation of flow diagram of the page read cycle in FIG. 23.

P-0063[0063]FIG. 25 shows a continuation of flow diagram of the page read cycle in FIG. 24.

P-0064[0064]FIG. 26 shows details of an embodiment of a single y-driver YDRVS <b>110</b>S.

P-0065[0065]FIG. 27 shows details of a latch block, a program/read control block, and program/program inhibit block included in the single y-driver YDRVS <b>110</b>S.

P-0066[0066]FIG. 28 is a block diagram illustrating a memory system for a multilevel memory.

P-0067[0067]FIG. 29A is a block diagram illustrating an inverter mode sensing circuit.

P-0068[0068]FIG. 29B is a block diagram illustrating a voltage mode sensing circuit.

P-0069[0069]FIG. 30 is a block diagram illustrating a wide range, high speed voltage mode sensing circuit.

P-0070[0070]FIG. 31 is a block diagram illustrating a wide range, high speed mode sensing circuit having a local source follower stage and a global common source stage.

P-0071[0071]FIG. 32 is a block diagram illustrating a wide range, high speed mode sensing circuit with a local PMOS source follower stage and a global source follower stage.

P-0072[0072]FIG. 33 is a block diagram illustrating a wide range, high speed mode sensing circuit with a local NMOS source follower stage and a global source following stage.

P-0073[0073]FIG. 34 is a block diagram illustrating a global sense amplifier having an auto zeroing function.

P-0074[0074]FIG. 35 is a block diagram illustrating an auto zero sense amplifier.

P-0075[0075]FIG. 36 is a block diagram illustrating a memory system for a multilevel memory including local autozero sense amplifiers and global autozero sense amplifiers.

P-0076[0076]FIG. 36A is a block diagram illustrating a memory system for a multilevel memory including local autozero sense amplifiers.

P-0077[0077]FIG. 37 is a block diagram illustrating a memory system including single ended autozero sense amplifiers.

P-0078[0078]FIG. 38 is a block diagram illustrating a memory system including differential autozero sense amplifiers.

P-0079[0079]FIG. 39 is a block diagram illustrating a memory system including crossed bitlines.

P-0080[0080]FIG. 40 is a block diagram illustrating a current sense amplifier including an autozero.

P-0081[0081]FIG. 41 is a block diagram including a current sense amplifier including autozero and replica loading.

P-0082[0082]FIG. 42 is a block diagram illustrating a two-stage current sense amplifier including autozero.

P-0083[0083]FIG. 43 is a block diagram illustrating a two-stage current sense amplifier including autozero.

P-0084[0084]FIG. 44 is a block diagram illustrating a two-stage indirect current sense amplifier having autozero.

P-0085[0085]FIG. 45 is a block diagram illustrating a two-stage indirect current sense amplifier having autozero.

P-0086[0086]FIG. 46 is a block diagram illustrating a memory system including a low voltage sense amplifier.

P-0087[0087]FIG. 46A is a block diagram illustrating a memory system including a low voltage sense amplifier.

P-0088[0088]FIG. 47 is a block diagram illustrating a memory system including a low voltage sense amplifier according to another embodiment.

P-0089[0089]FIG. 47A is a block diagram illustrating a memory system including a low voltage sense amplifier according to another embodiment.

P-0090[0090]FIG. 47B is a block diagram illustrating a memory system including a low voltage sense amplifier according to another embodiment.

P-0091[0091]FIG. 48 is a block diagram illustrating a memory system including a low voltage sense amplifier according to another embodiment.

P-0092[0092]FIG. 48A is a block diagram illustrating a memory system including a low voltage sense amplifier according to another embodiment.

P-0093[0093]FIG. 48B is a block diagram illustrating a memory system including a low voltage sense amplifier according to another embodiment.

P-0094[0094]FIG. 49 is a schematic diagram illustrating a shared sense amplifier segmented reference array.

P-0095[0095]FIG. 50 is a schematic diagram illustrating a memory cell replica sense amplifier.

P-0096[0096]FIG. 51 is a schematic diagram illustrating a differential current sense amplifier.

P-0097[0097]FIG. 52 is a schematic diagram illustrating a two-stage differential current sense amplifier.

P-0098[0098]FIG. 53 is a schematic diagram illustrating a current difference sense amplifier.

P-0099[0099]FIG. 54 is a schematic diagram illustrating a current difference sense amplifier.

P-0100[0100]FIG. 55 is a schematic diagram illustrating a dynamic sense amplifier.

P-0101[0101]FIG. 56 is a graph illustrating control signals and voltage levels of the dynamic sense amplifier of FIG. 55.

P-0102[0102]FIG. 57 is a schematic diagram illustrating the dynamic charge sense amplifier.

P-0103[0103]FIG. 58 is a flow diagram illustrating a single bit current sensing binary search.

P-0104[0104]FIG. 59 is a flow diagram illustrating a multiple bit current sensing bit search.

P-0105[0105]FIG. 60 is a block diagram illustrating a memory system with a built-in concurrent byte redundancy.

DESCRIPTION OF THE SPECIFIC EMBODIMENTS

P-0106[0106] Described are the design method and apparatus for a super high density nonvolatile memory system capable of giga to tera bits as applied to the array architecture, reference system, and decoding schemes to realize the optimum possible number of storage levels within specified performance constraints. Method and apparatus for multilevel program and sensing algorithm and system applied to flash memory is also described.

P-0107[0107] Array architectures and operating methods are described that are suitable for a super high density, in the giga to tera bits, for multilevel nonvolatile “green” memory integrated circuit system. “Green” refers to a system working in an efficient and low power consumption manner. The system and method solves the issues associated with super high density multilevel memory system, such as, precision voltage control in the array, severe capacitive loading from MOS transistor gates and parasitics, high leakage current due to memory cells and from cells to cells, excessive power consumption due to large number of gates and parasitics, and excessive memory cell disturbances due to large memory density.

P-0108[0108] An Inhibit and Select Segmentation Scheme uses a truly-floating-bitline scheme to greatly reduce the capacitance from junctions and parasitic interconnects to a small value.

P-0109[0109] A Multilevel Memory Decoding scheme is capable of greater than 10-bit multilevel operation. The Multilevel Memory Decoding Scheme includes the Power Supply Decoded Decoding Scheme, the Feedthrough-to-Memory Decoding Scheme, and the Feedthrough-to-Driver Decoding Scheme. The Multilevel Memory Decoding scheme also includes a “winner-take-all” Kelvin Decoding Scheme, which provides precise bias levels for the memory at a minimum cost. A constant-total-current-program scheme is described. Fast-slow and <b>2</b> -step ramp rate control programming are described. A reference system method and apparatus includes the Positional Linear Reference System, Positional Geometric Reference System, and the Geometric Compensation Reference System. An apparatus and method may provide multilevel programming, reading, and margining.

P-0110[0110] A sense amplifier system includes local sense amplifiers coupled to memory subarrays and global sense amplifiers coupled to groups of local sense amplifiers.

P-0111[0111] Method and apparatus described herein are applicable to digital multilevel as well as analog multilevel system.

P-0112[0112] Memory Cell Technology

P-0113[0113] To facilitate the understanding of the invention, a brief description of a memory cell technology is described below. In an embodiment the invention applies to Source Side Injection (SSI) flash memory cell technology, which will be referred to as SSI flash memory cell technology. The invention is equally applicable to other technologies such as drain-side channel hot electron (CHE) programming (ETOX), P-channel hot electron programming, NROM (nitride programmable read only memory), SONOS (silicon-oxide-nitride-oxide-silicon), MONOS (metal-oxide-nitride-oxide-silicon), 2-D or 3-D flash, bi-directional memory cell (e.g., two storage nodes, one near drain and one near source of a memory cell; two floating gates of same one memory cell), phase change memory, molecular memory, polymer memory, spin memory, single electron memory, nano particle memory, other hot electron programming schemes, Fowler-Nordheim (FN) tunneling, ferro-electric memory, and other types of memory technology.

P-0114[0114] A cell structure of one typical SSI flash cell is symbolically shown in FIG. 1A. Its corresponding transistor symbol is shown in FIG. 1B. The cell is made of two polysilicon gates (abbreviated as poly), a floating gate poly FG <b>100</b>F and a control gate poly CG <b>100</b>C. The control gate CG <b>100</b>C also acts as a select gate that individually select each memory cell. This has the advantage of avoiding the over erase problem which is typical of stacked gate CHE flash cell. The floating gate has a poly tip structure that points to the CG <b>100</b>C, this is to enhance the electric field from the FG <b>100</b>F to the CG <b>100</b>C which allows a much lower voltage in FN erase without using a thin interpoly oxide.

P-0115[0115] The thicker interpoly oxide leads to a higher reliability memory cell. The cell is also fabricated such that a major portion of the FG <b>100</b>F overlaps the source junction <b>100</b>S. This is to make a very high coupling ratio from the source <b>100</b>S to FG <b>100</b>F, which allows a lower erase voltage and is advantageous to the SSI programming, which will be described shortly. A structural gap between the FG <b>100</b>F and at CG <b>100</b>C is also advantageous for the efficient SSI programming.

P-0116[0116] The SSI flash memory cell enables low voltage and low power performance due to its intrinsic device physics resulting from its device structure. The SSI flash cell uses efficient FN tunneling for erase and efficient SSI for programming. The SSI flash cell programming requires a small current in hundreds of nano amps and a moderate voltage range of ˜8 to 11 volts. This is in contrast to that of a typical drain-side channel hot electron memory cell programming which requires current in hundreds of microamp to milliamp range and a voltage in the range of 11 to 13 volts.

P-0117[0117] The SSI flash memory cell erases by utilizing Fowler-Nordheim tunneling from the floating gate poly to the control gate poly by applying a high erase voltage on the control gate CG <b>100</b>C, e.g., 8-13 volts, and a low voltage on the source <b>100</b>S, e.g., <b>0</b> - <b>0</b>.<b>5</b> volts. The high erase voltage together with high coupling from the source to the floating gate creates a localized high electric field from the FG <b>100</b>F tip to the CG <b>100</b>C and causes electrons to tunnel from the FG <b>100</b>F to the CG <b>100</b>C near the tip region. The resulting effect causes a net positive charge on the FG <b>100</b>F.

P-0118[0118] The SSI flash memory cell programs by applying a high voltage on the source 100S (herein also known as common line CL), e.g., 4-13 V, a low voltage on the CG lOOC, e.g., 0.7-2.5 V, and a low voltage on the drain <b>100</b>D (herein also known as the bitline BL), e.g., 0-1 V. The high voltage on the source <b>100</b>S strongly couples to the FG to strongly turn on the channel under the FG (it will be equivalently referred to as the FG channel). This in turn couples the high voltage on the source <b>100</b>S toward the gap region. The voltage on the CG <b>100</b>C turns on the channel directly under the CG <b>100</b>C (it will be equivalently referred to as the CG channel). This in turn couples the voltage on the drain 100D toward the gap region. Hence, the electrons flow from the drain junction <b>100</b>D through the CG channel, through the gap channel, through the FG channel, and finally arrive at the source junction.

P-0119[0119] Due to the gap structure between the CG 100C and the FG <b>100</b>F, in the channel under the gap, there exists a strong lateral electric field (EGAPLAT) <b>100</b>G. As the EGAPLAT <b>100</b>G reaches a critical field, electrons flowing across the gap channel become hot electrons. A portion of these hot electrons gains enough energy to cross the interface between the silicon and silicon dioxide into the silicon dioxide. And as the vertical field Ev is very favorable for electrons to move from the channel to the FG <b>100</b>F, many of these hot electrons are swept toward the FG <b>100</b>F, thus, reducing the voltage on the FG <b>100</b>F. The reduced voltage on the FG <b>100</b>F reduces electrons flowing into the FG <b>100</b>F as programming proceeds.

P-0120[0120] Due to the coincidence of favorable Ev and high EGAPLAT <b>100</b>G in the gap region, the SSI memory cell programming is more efficient over that of the drain-side CHE programming, which only favors one field over the other. Programming efficiency is measured by how many electrons flow into the floating gate as a portion of the current flowing in the channel. High programming efficiency allows reduced power consumption and parallel programming of multiple cells in a page mode operation.

P-0121[0121] Multilevel Memory Integrated Circuit System:

P-0122[0122] The challenges associated with putting together a billion transistors on a single chip without sacrificing performance or cost are tremendous. The challenges associated with designing consistent and reliable multilevel performance for a billion transistors on a single chip without sacrificing performance or cost are significantly more difficult. The approach taken here is based on the modularization concept. Basically everything begins with a manageable optimized basic unitary block. Putting appropriate optimized unitary blocks together makes the next bigger optimized block.

P-0123[0123] A super high density nonvolatile multilevel memory integrated circuit system herein described is used to achieve the performance targets of read speed, write speed, and an operating lifetime with low cost. Read speed refers to how fast data could be extracted from a multilevel memory integrated circuit system and made available for external use such as for the system microcontroller <b>2001</b> shown in FIG. 1C which is described later. Write speed refers to how fast external data could be written into a multilevel memory integrated circuit system. Operating lifetime refers to how long a multilevel memory integrated circuit system could be used in the field reliably without losing data.

P-0124[0124] Speed is modularized based on the following concept, T=CV/I, where switching time T is proportional to capacitance C multiplied by the voltage swing V divided by the operating current I. Methods and apparatuses are provided by the invention to optimize C, V, and I to achieve the required specifications of speed, power, and optimal cost to produce a high performance high-density multilevel memory integrated circuit system. The invention described herein makes the capacitance independent of memory integrated circuit density, to the first order, and uses the necessary operating voltages and currents in an optimal manner.

P-0125[0125] A nonvolatile multilevel memory system is shown in FIG. IC. A super high density nonvolatile multilevel memory integrated circuit (IC) system <b>2000</b> is a digital multilevel nonvolatile flash memory integrated circuit capable of storing 2^Nstorage levels per one memory cell, with N=number of digital bits. A system microcontroller <b>2001</b> is a typical system controller used to control various system operations. Control signals (CONTROL SIGNALS) <b>196</b> L, input/output bus (IO BUS) <b>194</b>L, and ready busy signal (R/BB) <b>196</b> RB are for communication between the system microcontroller <b>2001</b> and the super high density nonvolatile multilevel memory integrated circuit system <b>2000</b>.

P-0126[0126] An electronic camera system (SILICONCAM) <b>2008</b> utilizing super high density nonvolatile multilevel memory IC system <b>2000</b> is shown in FIG. 1D. The system (SILICONCAM) <b>2008</b> includes an integrated circuit system (ECAM) <b>2005</b> and an optical lens block (LENS) <b>2004</b>. The integrated circuit system (ECAM) <b>2005</b> includes an image sensor (IMAGE SENSOR) <b>2003</b>, an analog to digital converter block (A/D CONVERTER) <b>2002</b>, a system microcontroller <b>2001</b>, and the multilevel memory IC system <b>2000</b>. The optical lens block (LENS) <b>2004</b> is used to focus light into the IMAGE SENSOR <b>2003</b>, which converts light into an analog electrical signal. The IMAGE SENSOR <b>2003</b> is a charge coupled device (CCD) or a CMOS sensor. The block (A/D CONVERTER) <b>2002</b> is used to digitize the analog electrical signal into digital data. The microcontroller <b>2001</b> is used to control various general functions such as system power up and down, exposure time and auto focus. The microcontroller <b>2001</b> is also used to process image algorithms such as noise reduction, white balance, image sharpening, and image compression. The digital data is stored in the multilevel memory IC system <b>2000</b>. The digital data can be down loaded to another storage media through wired or wireless means. Future advances in process and device technology can allow the optical block (LENS) <b>2004</b> to be integrated in a single chip with the ECAM <b>2005</b>.

P-0127[0127] An electronic audio system (SILICONCORDER) <b>2007</b> utilizing super high density nonvolatile multilevel memory IC system <b>2000</b> is shown in FIG. 1E. The SILICONCORDER <b>2007</b> includes an integrated circuit system (SILICONAUDIO) <b>2006</b>, a MICROPHONE <b>2012</b>, and a SPEAKER <b>2013</b>. The system (SILICONAUDIO) <b>2006</b> includes an anti-alias FILTER <b>2010</b>, an A/D CONVERTER <b>2002</b>, a smoothing FILTER <b>2011</b>, aD/A CONVERTER <b>2009</b>, a system microcontroller <b>2001</b>, and the multilevel memory IC system <b>2000</b>. The FILTER <b>2010</b> and the FILTER <b>2011</b> can be combined into one filter block if the signals are multiplexed appropriately. The microcontroller <b>2001</b> is used to control various functions such as system power up and down, play, record, message management, audio data compression, and voice recognition. In recording a sound wave, the MICROPHONE <b>2012</b> converts the sound wave into an analog electrical signal, which is filtered by the FILTER <b>2010</b> to reduce non-audio signals. The filtered analog signal is then digitized by the A/D CONVERTER <b>2002</b> into digital data. The digital data is then stored in compressed or uncompressed form in the multilevel memory IC system <b>2000</b>. In playing back the stored audio signal, the microcontroller <b>2001</b> first uncompresses the digital data if the data is in compressed form. The D/A CONVERTER <b>2009</b> then converts the digital data into an analog signal which is filtered by a smoothing filter (FILTER) <b>2011</b>. The filtered output analog signal then goes to the SPEAKER <b>2013</b> to be converted into a sound wave. The signal filtering can be done by digital filtering by the microcontroller <b>2001</b>. External digital data can be loaded into the multilevel memory IC system <b>2000</b> through wired or wireless means. Future advances in process and device technology can allow the MICROPHONE <b>2012</b> and the SPEAKER <b>2013</b> to be integrated in a single chip with the SILICONAUDIO <b>2006</b>.

P-0128[0128] A circuit block diagram of the super high density nonvolatile multilevel memory integrated circuit system <b>2000</b> based on the concepts described above and also on ideas described below, is shown in FIG. 2A. For the purpose of discussion, a giga bit nonvolatile multilevel memory chip is described.

P-0129[0129] A circuit block <b>100</b> includes a regular memory array.

P-0130[0130] It includes a total of for example, 256 million nonvolatile memory cells for a <b>4</b> -bit digital multilevel memory cell technology or 128 million cells for a 8-bit digital multilevel memory cell technology. An N-bit digital multilevel cell is defined as a memory cell capable of storing 2^Nlevels. A reference array (MFLASHREF) <b>106</b> is used for the reference system. A redundancy array (MFLASHRED) <b>102</b> is used to increase production yield by replacing bad portions of the regular memory array of the circuit block <b>100</b>. An optional spare array (MFLASHSPARE) <b>104</b> can be used for extra data overhead storage such as for error correction.

P-0131[0131] A y-driver block (YDRV) <b>110</b> including a plurality of single y-drivers (YDRVS) <b>110</b>S is used for controlling the bitlines during write, read, and erase operation. Block YDRVS <b>110</b>S will be described in detail below in the description of the multilevel algorithm. Multiples of y-driver block (YDRV) <b>110</b> are used for parallel multilevel page writing and reading to speed up the data rate during write to and read from the multilevel memory IC system <b>2000</b>. A reference y-driver block (REFYDRV) <b>116</b> including a plurality of single reference y-drivers (REFYDRVS) <b>116</b>S is used for the reference array block (MFLASHREF) <b>106</b>. A redundant y-driver block (RYDRV) <b>112</b> including a plurality of single redundant y-drivers (RYDRVS) <b>112</b>S is used for the redundant array (MFLASHRED) <b>102</b>. The function of block (RYDRVS) <b>112</b>S is similar to that of block (YDRVS) <b>110</b>S. A spare y-driver block (SYDRV) <b>114</b> including a plurality of single spare y-drivers (SYDRVS) <b>114</b>S is used for the spare array (MFLASHSPARE) <b>104</b>. The function of block (SYDRVS) <b>114</b>S is similar to that of block (YDRVS) <b>110</b>S. A page select block (PSEL) <b>120</b> is used to select one bitline out of multiple bitlines for each single y-driver (YDRVS) <b>110</b>S inside the block (YDRV) <b>110</b>. Corresponding select circuit blocks for reference array, redundant array, and spare array are a reference page select block (PRSEL) <b>126</b>, a redundant page select block <b>122</b>, and a spare page select block <b>124</b>. A byte select block (BYTESEL) <b>140</b> is used to enable one byte data in or one byte data out of the blocks (YDRV) <b>110</b> at a time. Corresponding blocks for reference array, redundant array, and spare array are a reference byte select block <b>146</b>, a redundant byte select block <b>142</b>, and a spare byte select block <b>144</b>. The control signals for circuit blocks <b>116</b>, <b>126</b>, <b>146</b>, <b>112</b>, <b>122</b>, <b>142</b>, <b>114</b>, <b>124</b>, and <b>144</b> are in general different from the control signals for circuit blocks <b>110</b>, <b>120</b>, and <b>140</b> of the regular memory array of the circuit block <b>100</b>. The control signals are not shown in the figures.

P-0132[0132] A multilevel memory precision decoder block (MLMDEC) <b>130</b> is used for address selection and to provide precise multilevel bias levels over temperature, process comers, and power supply as required for consistent multilevel memory operation for the regular memory array of the circuit block <b>100</b> and for the redundant array <b>102</b>. A multilevel memory precision decoder block (MLMSDEC) <b>134</b> is used for address selection and to provide precise multilevel bias levels over temperature, process comers, and power supply as required for consistent multilevel memory operation for the spare array <b>104</b>.

P-0133[0133] An address pre-decoding circuit block (XPREDEC) <b>154</b> is used to provide decoding of addresses A<16: AN>. The term AN denotes the most significant bit of addresses depending on the size of the memory array. The outputs of block (XPREDEC) <b>154</b> couple to blocks (MLMDEC) <b>130</b> and block (MLMSDEC) <b>134</b>. An address pre-decoding block (XCGCLPRED) <b>156</b> is used to provide decoding of addresses A<11:15>. The outputs of block <b>156</b> also couple to blocks (MLMDEC) <b>130</b> and block (MLMSDEC) <b>134</b>.

P-0134[0134] A page address decoding block (PGDEC) <b>150</b> is used to provide decoding of addresses A<<b>9</b>:<b>10</b> >. The outputs of block (PGDEC) <b>150</b> couple to blocks (PSEL) <b>120</b>. A byte address decoding block (BYTEDEC) <b>152</b> is used to provide decoding of addresses A<0:8>. The outputs of block (BYTEDEC) <b>152</b> couple to blocks (BYTESEL) <b>140</b>. An address counter block (ADDRCTR) <b>162</b> provides addresses A<11:AN>, A<9:10>, and A<0:8> for row, page, and byte addresses, respectively. The outputs of the block (ADDRCTR) <b>162</b> couple to blocks (XPREDEC) <b>154</b>, (XCGCLPRED) <b>156</b>, (PGDEC) <b>150</b>, and (BYTEDEC) <b>152</b>. The inputs of the block (ADDRCTR) <b>162</b> are coupled from the outputs of an input interface logic block (INPUTLOGIC) <b>160</b>.

P-0135[0135] The input interface logic block (INPUTLOGIC) <b>160</b> is used to provide external interface to systems off-chip such as the microcontroller <b>2001</b>. Typical external interface for memory operation are read, write, erase, status read, identification (ID) read, ready busy status, reset, and other general purpose tasks. Serial interface can be used for the input interface to reduce pin counts for high-density chip due to a large number of addresses. Control signals <b>196</b>L are used to couple the INPUTLOGIC <b>160</b> to the system microcontroller <b>2001</b>. The INPUTLOGIC <b>160</b> includes a status register that is indicative of the status of the memory chip operation such as pass or fail in program or erase, ready or busy, write protected or unprotected, cell margin good or bad, restore or no restore, etc. The margin and restore concepts are described more in detail in the multilevel algorithm description.

P-0136[0136] An algorithm controller block (ALGOCNTRL) <b>164</b> is used to handshake the input commands from the block (INPUTLOGIC) <b>160</b> and to execute the multilevel erase, programming and sensing algorithms as needed for multilevel nonvolatile operation. The ALGOCNTRL <b>164</b> is also used to algorithmically control the precise bias and timing conditions as required for multilevel precision programming.

P-0137[0137] A test logic block (TESTLOGIC) <b>180</b> is used to test various electrical features of the digital circuits, analog circuits, memory circuits, high voltage circuits, and memory array. The inputs of the block (TESTLOGIC) <b>180</b> are coupled from the outputs of the INPUTLOGIC <b>160</b>. The block (TESTLOGIC) <b>180</b> also provides timing speed-up in production testing such as faster write/read and mass modes. The TESTLOGIC <b>180</b> is also used to provide screening tests associated with memory technology such as various disturb and reliability tests. The TESTLOGIC <b>180</b> also allows an off-chip memory tester to directly take over the control of various on-chip logic and circuit bias blocks to provide various external voltages and currents and external timing. This feature permits, for example, screening with external voltage and external timing or permits accelerated production testing with fast external timing.

P-0138[0138] A fuse circuit block (FUSECKT) <b>182</b> is a set of nonvolatile memory cells configured at the external system level, at the tester, at the user, or on chip on-the-fly to achieve various settings. These settings can include precision bias levels, precision on-chip oscillator, programmable logic features such as write-lockout feature for portions of an array, redundancy fuses, multilevel erase, program and read algorithm parameters, or chip performance parameters such as write or read speed and accuracy.

P-0139[0139] A reference control circuit block (REFCNTRL) <b>184</b> is used to provide precision reference levels for precision voltage levels as required for multilevel programming and sensing.

P-0140[0140] A redundancy controller block (REDCNTRL) <b>186</b> is for redundancy control logic.

P-0141[0141] A voltage algorithm controller block (VALGGEN) <b>176</b> provides various specifically shaped voltage signals of amplitude and duration as required for multilevel nonvolatile operation and to provide precise voltage levels with tight tolerance, as required for precision multilevel programming, erasing, and sensing.

P-0142[0142] A circuit block (BGAP) <b>170</b> is a bandgap voltage generator based on the bandgap circuit principle to provide a precise voltage level over process, temperature, and supply as required for multilevel programming and sensing.

P-0143[0143] A voltage and current bias generator block (V&amp;IREF) <b>172</b> is an on-chip programmable bias generator. The bias levels are programmable by the settings of the control signals from the FUSECKT <b>182</b> and also by various metal options. A precision oscillator block (PRECISIONOSC) <b>174</b> provides accurate timing as required for multilevel programming and sensing.

P-0144[0144] Input buffer blocks <b>196</b> are typical input buffer circuits, for example, TTL input buffers or CMOS input buffers. Input/output (io) buffer blocks <b>194</b> includes typical input buffers and typical output buffers. A typical output buffer is, for example, an output buffer with slew rate control, or an output buffer with level feedback control. A circuit block <b>196</b>R is an open drained output buffer and is used for ready busy handshake signal (R/BB) <b>196</b>RB.

P-0145[0145] A voltage multiplier (also known as charge pump) block (VMULCKT) <b>190</b> provides voltage levels above the external power supply required for erase, program, read, and production tests. A voltage multiplying regulator block (VMULREG) <b>192</b> provides regulation for the block (VMULCKT) <b>190</b> for power efficiency and for transistor reliability such as to avoid various breakdown mechanisms.

P-0146[0146] A flash power management block (FPMU) <b>198</b> is used to efficiently manage power on-chip such as powering up only the circuit blocks in use. The FPMU <b>198</b> also provides isolation between sensitive circuit blocks from the less sensitive circuit blocks by using different regulators for digital power (VDDD) <b>1032</b>/(VSSD) <b>1033</b>, analog power (VDDA) <b>1030</b>/(VSSA) <b>1031</b>, and IO buffer power (VDDIO) <b>1034</b>/(VSSIO) <b>1035</b>. The FPMU <b>198</b> also provides better process reliability by stepping down power supply VDD to lower levels required by transistor oxide thickness. The FPMU <b>198</b> allows the regulation to be optimized for each circuit type. For example, an open loop regulation could be used for digital power since highly accurate regulation is not required; and a closed loop regulation could be used for analog power since analog precision is normally required. The flash power management also enables creation of a “green” memory system since power is efficiently managed.

P-0147[0147] Block diagram of the FPMU <b>198</b> is shown in FIG. 2B. A VDD <b>1111</b> and a VSS <b>1000</b> are externally applied power supply and ground lines, respectively. A block (ANALOG POWER REGULATOR) <b>198</b>A is an analog power supply regulator, which uses closed loop regulation. The closed loop regulation is provided by negative feedback action of an operational amplifier (op amp) <b>1003</b> configured in a voltage buffer mode with a reference voltage (VREF <b>1</b>) <b>1002</b> on the positive input of the op amp <b>1003</b>. A filter capacitor (CFILL) <b>1004</b> is used for smoothing transient response of the analog power (VDDA) <b>1030</b>. A ground line (VSSA) <b>1031</b> is for analog power supply. A block (DIGITAL POWER REGULATOR) <b>198</b>B is a digital power supply regulator, which uses open loop regulation. The open loop regulation is provided by source follower action of a transistor <b>1006</b> with a reference voltage (VREF<b>2</b>) <b>1005</b> on its gate. A pair of filter capacitor (CFIL<b>4</b>) <b>1009</b> and (CFIL<b>2</b>) <b>1007</b> are used for smoothing transient response of digital power (VDDD) <b>1032</b>. A loading element (LOAD <b>1</b>) <b>1008</b> is for the transistor <b>1006</b>. A ground line (VSSD) <b>1033</b> is for digital power supply. A block (IO POWER REGULATOR) <b>198</b>C is an IO power supply regulator, which uses open loop regulation similar to that of the digital power supply <b>198</b>B. The open loop regulation is provided by a transistor <b>1011</b> with a reference voltage (VREF<b>3</b>) <b>1010</b> on its gate. A loading element (LOAD<b>2</b>) <b>1013</b> is for transistor <b>1011</b>. A pair of capacitors (CFIL<b>5</b>) <b>1014</b> and (CFIL<b>3</b>) <b>1012</b> are used for smoothing transient response of <b>10</b> power (VDDIO) <b>1034</b>. A ground line (VSSIO) <b>1035</b> is for IO power supply. A block <b>198</b>D includes various circuits that require unregulated power supply such as transmission switches, high voltage circuits, ESD structures, and the like.

P-0148[0148] A block (PORK) <b>1040</b> is a power on reset circuit which provides a logic signal (PON) <b>1041</b> indicating that the power supply being applied to the chip is higher than a certain voltage. The signal (PON) <b>1041</b> is typically used to initialize logic circuits before chip operation begins.

P-0149[0149] A block (VDDDET) <b>1050</b> is a power supply detection circuit, which provides a logic signal (VDDON) <b>1051</b> indicating that the operating power supply is higher than a certain voltage. The block (VDDDET) <b>1050</b> is normally used to detect whether the power supply is stable to allow the chip to take certain actions such as stopping the programming if the power supply is too low.

P-0150[0150] A block (FPMUCNTRL) <b>1060</b> is a power supply logic controller, that receives control signals from blocks (PORK) <b>104</b>, (VDDDET) <b>1050</b>, (INPUTLOGIC) <b>160</b>, (ALGOCNTRL) <b>164</b>, and other logic control blocks to power up and power down appropriately power supplies and circuit blocks. The FPMUCNTRL <b>1060</b> is also used to reduce the power drive ability of appropriate circuit blocks to save power. A line (PDDEEP) <b>1021</b> is used to power down all regulators. Lines (PDAPOW) <b>1020</b>, (PDDPOW) <b>1022</b>, and (PDIOPOW) <b>1023</b> are used to power down blocks <b>198</b>A, <b>198</b>B, and <b>198</b>C, respectively. Lines (PDDEEP) <b>1021</b>, (PDAPOW) <b>1020</b>, (PDDPOW) <b>1022</b>, and (PDIOPOW) <b>1023</b> come from block (FPMUCNTRL) <b>1060</b>.

P-0151[0151] It is possible that either closed or open loop regulation could be used for any type of power supply regulation. It is also possible that any power supply could couple directly to the applied power supply (VDD) <b>1111</b> without any regulation with appropriate consideration. For example, VDDA <b>1030</b> or VDDIO <b>1034</b> could couple directly to VDD <b>1111</b> if high voltage transistors with thick enough oxide are used for analog circuits or IO buffer circuits, respectively.

P-0152[0152] A typical memory system operation is as follows: a host such as the microcontroller <b>2001</b> sends an instruction, also referred to as a command, such as a program instruction via the CONTROL SIGNALS <b>196</b>L and the IO BUS <b>194</b>L to the multilevel memory chip <b>2000</b> (see FIG. 1C). The INPUTLOGIC <b>160</b> interprets the incoming command as a valid command and initiates the program operation internally. The ALGOCNTRL <b>164</b> receives the instruction from the INPUTLOGIC <b>160</b> to initiate the multilevel programming algorithmic action by outputting various control signals for the chip. A handshake signal such as the ready busy signal R/BB <b>196</b>RB then signals to the microcontroller <b>2001</b> that the multilevel memory chip <b>2000</b> is internally operating. The microcontroller <b>2001</b> is now free to do other tasks until the handshake signal R/BB <b>196</b>RB signals again that the multilevel memory chip <b>2000</b> is ready to receive the next command. A timeout could also be specified to allow the microcontroller <b>2001</b> to send the commands in appropriate times.

P-0153[0153] Read Operation:

P-0154[0154] A read command including a read operational code and addresses is sent by the microcontroller <b>2001</b> via the CONTROL SIGNALS <b>196</b>L and IO BUS <b>194</b>L. The INPUTLOGIC <b>160</b> decodes and validates the read command. If it is valid, then incoming addresses are latched in the ADDRCTR <b>162</b>. The ready busy signal (R/BB) <b>196</b>RB now goes low to indicate that the multilevel memory device <b>2000</b> has begun read operation internally. The outputs of ADDRCTR <b>162</b> couple to blocks (XPREDEC) <b>154</b>, (XCGCLPRED) <b>156</b>, (PGDEC) <b>150</b>, (BYTEDEC) <b>152</b>, and (REDCNTRL) <b>186</b>. The outputs of blocks <b>154</b>, <b>156</b>, <b>150</b>, <b>152</b>, and <b>186</b> couple to blocks (MLMDEC) <b>130</b>, (MLSMDEC) <b>134</b>, and block <b>100</b> to enable appropriate memory cells. Then the ALGOCNTRL <b>164</b> executes a read algorithm. The read algorithm will be described in detail later in the multilevel algorithm description. The read algorithm enables blocks (BGAP) <b>170</b>, (V&amp;IREF) <b>172</b>, (PRECISIONOSC) <b>174</b>, (VALGGEN) <b>176</b>, and (REFCNTRL) <b>184</b> to output various precision shaped voltage and current bias levels and algorithmic read timing for read operation, which will be described in detail later in the description of the multilevel array architecture. The precision bias levels are coupled to the memory cells through blocks (MLMDEC) <b>130</b>, (MLMSDEC) <b>134</b>, and block <b>100</b>.

P-0155[0155] In an embodiment, the read algorithm operates upon one selected page of memory cells at a time to speed up the read data rate. A page includes a plurality of memory cells, e.g., 1024 cells. The number of memory cells within a page can be made programmable by fuses, e.g., <b>512</b> or <b>1024</b> to optimize power consumption and data rate. Blocks (PGDEC) <b>150</b>, (MLMDEC) <b>130</b>, (MLMSDEC) <b>134</b>, <b>100</b>, and (PSEL) <b>120</b> select a page. All memory cells in the selected page are put in read operating bias condition through blocks (MLMDEC) <b>130</b>, (MLMSDEC) <b>134</b>, <b>100</b>, (PSEL) <b>120</b>, and (XCGCLPRED) <b>156</b>. After the readout voltage levels are stable, a read transfer cycle is initiated by the block (ALGOCNTRL) <b>164</b>. All the readout voltages from the memory cells in the selected page are then available at the y-drivers (YDRVS) <b>110</b>S, (RYDRVS) <b>112</b>S, and (SYDRVS) <b>114</b>S inside block (YDRV) <b>110</b>, (RYDRV) <b>112</b>, and (SYDRV) <b>114</b>, respectively.

P-0156[0156] Next, in the read transfer cycle the ALGOCNTR <b>164</b> executes a multilevel read algorithm to extract the binary data out of the multilevel cells and latches them inside the YDRVS <b>110</b>S, RYDRVS <b>112</b>S, and SYDRVS <b>114</b>S. This finishes the read transfer cycle. A restore flag is now set or reset in the status register inside the INPUTLOGIC <b>160</b>. The restore flag indicates whether the voltage levels of the multilevel memory cells being read have been changed and whether they need to be restored to the original voltage levels. The restore concept will be described more in detail in the multilevel algorithm description. Now the ready busy signal (R/BB) <b>196</b>RB goes high to indicate that the internal read operation is completed and the multilevel memory device <b>2000</b> is ready to transfer out the data or chip status. The microcontroller <b>2001</b> now can execute a status read command to monitor the restore flag or execute a data out sequence. The data out sequence begins with an external read data clock provided by the microcontroller <b>2001</b> via the CONTROL SIGNAL <b>196</b>L coupled to an input buffer <b>196</b> to transfer the data out. The external read data clock couples to the blocks (BYTEDEC) <b>152</b> and (BYTESEL) <b>140</b>, <b>142</b>, and <b>144</b> to enable the outputs of the latches inside blocks (YDRV) <b>110</b> or (RYDRV) <b>112</b> or (SYDRV) <b>114</b> to output one byte of data at a time into the bus IO<0:7> <b>1001</b>. The external read data clock keeps clocking until all the desired bytes of the selected page are outputted. The data on bus IO<0:7> <b>1001</b> is coupled to the microcontroller <b>2001</b> via IO BUS <b>194</b>L through IO buffers <b>194</b>.

P-0157[0157] Program Operation:

P-0158[0158] A program command including a program operational code, addresses, and data is sent by the microcontroller <b>2001</b> via CONTROL SIGNALS <b>196</b>L and IO BUS <b>194</b>L. The INPUTLOGIC <b>160</b> decodes and validates the command. If it is valid, then incoming addresses are latched in the ADDRCTR <b>162</b>. The data is latched in the latches inside YDRV <b>110</b>, RYDRV <b>112</b>, and SYDRV <b>114</b> via blocks (BYTEDEC) <b>152</b>, (BYTESEL) <b>140</b>, <b>142</b>, and <b>144</b>, respectively. The ready busy signal (R/BB) <b>196</b>RB now goes low to indicate that the memory device has begun program operation internally. The outputs of ADDRCTR <b>162</b> couple to blocks (XPREDEC) <b>154</b>, (XCGCLPRED) <b>156</b>, (PGDEC) <b>150</b>, (BYTEDEC) <b>152</b>, and (REDCNTRL) <b>186</b>. The outputs of blocks <b>154</b>, <b>156</b>, <b>150</b>, <b>152</b>, and <b>186</b> couple to blocks (MLMDEC) <b>130</b>, (MLSMDEC) <b>134</b>, and <b>100</b> to enable appropriate memory cells. Then the (ALGOCNTRL) <b>164</b> executes a program algorithm, which will be described in detail later in the multilevel algorithm description. The (ALGOCNTRL) <b>164</b> enables blocks (BGAP) <b>170</b>, (V&amp;IREF) <b>172</b>, (PRECISIONOSC) <b>174</b>, (VALGGEN) <b>176</b>, and (REFCNTRL) <b>184</b> to output various precision shaped voltage and current bias levels and algorithmic program timing for the program operation, which will be described in detail later in the description of the multilevel array architecture. The precision bias levels are coupled to the memory cells through blocks (MLMDEC) <b>130</b>, (MLMSDEC) <b>134</b>, and block <b>100</b>.

P-0159[0159] In an embodiment, the program algorithm operates upon one selected page of memory cells at a time to speed up the program data rate. Blocks (PGDEC) <b>150</b>, (MLMDEC) <b>130</b>, (MLMSDEC) <b>134</b>, <b>100</b>, and (PSEL) <b>120</b> select a page. All memory cells in the selected page are put in appropriate program operating bias condition through blocks (MLMDEC) <b>130</b>, (MLMSDEC) <b>134</b>, <b>100</b>, (PSEL) <b>120</b>, and (XCGCLPRED) <b>156</b>. Once the program algorithm finishes, program flags are set in the status register inside the block (INPUTLOGIC) <b>160</b> to indicate whether the program has been successful. That is, all the cells in the selected page have been programmed correctly without failure and with enough voltage margins. The program flags are described more in detail in the multilevel algorithm description. Now the ready busy signal (R/BB) <b>196</b>RB goes high to indicate that the internal program operation is completed and the memory device is ready to receive the next command.

P-0160[0160] Erase Operation:

P-0161[0161] An erase command including an erase operational code and addresses is sent by the microcontroller <b>2001</b> via CONTROL SIGNALS <b>196</b>L and IO BUS <b>194</b>L. The INPUTLOGIC <b>160</b> decodes and validates the command. If it is valid, then incoming addresses are latched in the ADDRCTR <b>162</b>. The ready busy signal (R/BB) <b>196</b>RB now goes low to indicate that the memory device has begun erase operation internally. The outputs of ADDRCTR <b>162</b> couple to blocks (XPREDEC) <b>154</b>, (XCGCLPRED) <b>156</b>, (PGDEC) <b>150</b>, (BYTEDEC) <b>152</b>, and (REDCNTRL) <b>186</b>. The outputs of blocks <b>154</b>, <b>156</b>, <b>150</b>, <b>152</b>, and <b>186</b> couple to blocks (MLMDEC) <b>130</b>, (MLSMDEC) <b>134</b>, and <b>100</b> to enable appropriate memory cells. Then the ALGOCNTRL <b>164</b> executes an erase algorithm. The ALGOCNTRL <b>164</b> enables blocks (BGAP) <b>170</b>, (V&amp;IREF) <b>172</b>, (PRECISIONOSC) <b>174</b>, (VALGGEN) <b>176</b>, and (REFCNTRL) <b>184</b> to output various precision shaped voltage and current bias levels and algorithmic erase timing for erase operation. The shaped voltage for erase is to minimize electric field coupled to memory cells, which minimizes the damage to memory cells during erasing. The precision bias levels are coupled to the memory cells through blocks (MLMDEC) <b>130</b>, (MLMSDEC) <b>134</b>, and block <b>100</b>.

P-0162[0162] In an embodiment, the erase algorithm operates upon one selected erase block of memory cells at a time to speed up the erase time. An erase block includes a plurality of pages of memory cells, e.g., 32 pages. The number of pages within an erase block can be made programmable by fuses to suit different user requirements and applications. Blocks (PGDEC) <b>150</b>, (MLMDEC) <b>130</b>, (MLMSDEC) <b>134</b>, <b>100</b>, and (PSEL) <b>120</b> select a block. All memory cells in the selected block are put in erase operating bias condition through blocks (MLMDEC) <b>130</b>, (MLMSDEC) <b>134</b>, <b>100</b>, (PSEL) <b>120</b>, and (XCGCLPRED) <b>156</b>. Once the erase algorithm finishes, the erase flags are set in the status register inside the block (INPUTLOGIC) <b>160</b> to indicate whether the erase has been successful. That is, all the cells in the selected page have been erased correctly to desired voltage levels without failure and with enough voltage margins. Now the ready busy signal (R/BB) <b>196</b>RB goes high to indicate that the internal erase operation is completed and the multilevel memory device <b>2000</b> is ready to receive the next command.

P-0163[0163] Multilevel Array Architecture:

P-0164[0164] The demanding requirements associated with putting together a billion transistors on a single chip with the ability to store multiple precision levels per cell and operating at a very high speed are contradictory. These requirements need innovative approaches and careful tradeoffs to achieve the objective. Examples of tradeoffs and problems with prior art implementation are discussed below. In conventional prior art architectures, a voltage drop along a metal line of a few tens of millivolts could be easily tolerated. Here, in a super high density nonvolatile multilevel memory integrated circuit system such a voltage drop can cause unacceptable performance degradation in precision levels due to the high number of levels stored per memory cell. In conventional array architectures, a bit line capacitance in the order of <b>10</b> pico farads would be a non-issue. Here it may be unworkable due to the high data rate required. In prior art array architectures a bias level variation from one memory cell to another in the order of +/−30 percent would be a typical situation. Here such a bias variation would be a serious performance problem. In prior art array architectures, the total resistance of a memory source line in the order of a few hundreds of ohms would be a typical situation, here a few tens of ohms is a serious problem. The huge number of memory cells of the giga to tera bit high-density memory system compounds the matter even further by making the memory source line longer. Another challenge facing the multilevel system is maintaining high speed sensing and programming with low power, again requiring tradeoffs. Another challenge facing the multilevel system is high speed sensing and programming with very high precision voltages due to a high number of levels stored per digital multilevel memory cell, again a conflicting demand. Another challenge facing the multilevel system is high speed sensing and programming consistently every time over many years, process comers, temperature, and power supply variation.

P-0165[0165] To get an appreciation of the order of magnitude of the difficulty involved in the super high density multilevel nonvolatile memory system, numerical examples will be given corresponding to a one giga bit array architecture system suitable for 256 levels, i.e., <b>8</b> bits. The array is then organized as <b>8192</b> bitlines or columns and 16384 rows or wordlines for a total of 134,217,730 physical cells.

P-0166[0166] One sensing level, V<b>1</b>level,=multilevel sensing range/2^N, N=number of digital bits stored per memory cell. Multilevel sensing range is the readout voltage range from sensing a multilevel memory cell. Assuming the multilevel sensing range from the multilevel memory cell available is <b>2048</b> millivolts, then V<b>1</b>level=<b>2048</b>/<b>256</b>=<b>8</b> millivolts.

P-0167[0167] A very high data rate is required for applications such as image or high density data storage. For example, write and read rates of a mega byte per second are required. To achieve this high data rate, parallel writing and sensing is required for the super high density nonvolatile multilevel memory integrated circuit system. In the present embodiment, a total of 1024 y-drivers (YDRVS) <b>110</b>S inside blocks (YDRV) <b>110</b> are used. This allows 1024 memory cells to be written and sensed at the same time in a page mode manner, effectively increasing the speed by a factor of <b>1024</b> over single cell operation. The number of bitlines multiplexed into one single y-driver (YDRVS) <b>110</b>S is=8192/1024=8 bitlines.

P-0168[0168] A program algorithm described in more detail elsewhere in this specification is able to achieve desired multilevel resolution. The read or program multilevel resolution is the smallest voltage range in read or program, respectively, needed to operate the multilevel memory cells correctly. An erase algorithm first erases the memory cells to make the cell readout voltage reaching a certain desired voltage level. Then the iterative program algorithm is applied to the memory cells. The program algorithm includes a plurality of verify-program cycles. A verify-program cycle includes a verify cycle followed by a program cycle. A verify cycle is done first to inhibit the cell from the first programming pulse if the cell is verified, therefore preventing possible over-programming. Over-programming means that after a programming pulse the cell sensing level passes a desired voltage level by more than a desired voltage amount. A verify cycle is used to determine whether the desired readout sensing level has been reached. If the desired readout sensing level is reached, the cell is inhibited from further programming. Otherwise, the cell is enabled for the next program cycle. A program cycle is used to change incrementally the charge stored in the cell and the corresponding cell sensing readout voltage. Instead of a verify-program cycle, a program-verify cycle can be used. A program-verify cycle begins with a program cycle followed by a verify cycle. In this case, care should be taken to ensure that the first programming pulse does not cause over-programming.

P-0169[0169] In an embodiment the program cycle includes applying a voltage on the source line, (interchangeably referred to as common line [CL]) (VCL), with a predetermined program pulsewidth (TPPWD) and a predetermined program bias cell current (Ipcell). The verify cycle makes use of the voltage mode sensing as shown in FIG. 2C, which applies a reference voltage (VCLRD) on the source line (CL), another reference voltage (VCGRD) on the control gate, and a predetermined read bias current (Ircell) on the bitline and through the memory cell. The current (Ircell) is applied to the bitline and the memory cell through select transistors which are not shown. The resulting voltage on the bitline is the sensing readout voltage (VR), which has a unique relationship to the charge on the floating gate. The voltage mode sensing is also used during read. In another embodiment of voltage mode sensing, the source line (CL) and the bitline are interchanged, and thus a reference voltage is applied on the bitline and a predetermined read bias current (Ircell) is applied on the source line through the memory cell. The resulting voltage on the source line is the sensing readout voltage (VR). In this case, the array architecture uses only one source line in read at a given time, for example, by multiplexing through decoder circuitry or over time. This is to be known as Inverse Voltage Mode sensing. In another embodiment of the voltage mode sensing, there is no predetermined read current (Ircell), or the predetermined read current equals to zero. This mode is to be known as No Current (Digital) Multilevel Mode Sensing. In another embodiment of the voltage mode sensing, the predetermined read bias current is replaced by a resistor or an equivalent resistance (like a MOS operated as a resistor). To change incrementally the readout sensing voltage to the next value (VR+dVR), with dVR equals to the incremental readout sensing voltage change, the next program cycle is repeated with the common line voltage increased incrementally to (VCL+dVCLP), with dVCLP equals to the incremental programming voltage change.

P-0170[0170] The number of verify-program cycles (NC) is dependent on the number of voltage levels and various margins of the memory system. For example, for an equivalent 8-bit digital multilevel cell, there are 2^N=2⁸=256 levels, with N=8. The minimum possible number of verify- program cycles (NC) required would be 256. To cover variations due to cell-to-cell variation, temperature, process corners, an algorithm may require, for example, approximately 1.4×256=360 verify-program cycles. To cover various margins needed such as for data retention and programming distribution, the number of verify-program cycles required is actually higher. Assuming a factor of 2 due to various margin coverage, the number of verify-program cycles is approximately equal to 720. The exact number of verify-program cycles is typically varied depending on various memory technologies and particular desired performance targets.

P-0171[0171] For write data rate of 1 mega byte per second and for 8-bit digital multilevel operation with 1024 bytes per page, the write timing per page is, TWRT=# of bytes written in parallel/data rate=1024 bytes per page/I mega bytes/second=1024 μs=1.024 ms per page.

P-0172[0172] Hence the time to execute each program-verify cycle (TPV) must be less than TWRT/NC=1.024 ms/720=1.42 μs. This fast timing coupled with parallel operation of <b>1024</b> cells has important implication on memory cell program speed, capacitance loading, power consumption and other effects as will be described below.

P-0173[0173] Typical process parameters of a sub-micron memory cell are as follows. A typical diffused source line resistance per cell is 100 ohms. A typical bitline resistance per cell is 80 milliohms. A typical silicided row line resistance per cell is 20 ohms. A typical source line capacitance per cell is 2 fF. A typical bitline capacitance per cell is 1.5 fF. And a typical row line capacitance per cell is 3 fF.

P-0174[0174] Hence for the 8192×16384 array, the total bitline capacitance is CBL=˜16384×1.5 fF=25 pF, where “=˜” is defined as approximately equal to. The total metal bitline resistance RBL=˜16384×0.08=1330 ohms. The total diffused source line resistance is RSL=8192×100=819 K ohms. The total row line resistance is RWL=8192×20=164 K ohms. For a typical memory system, the diffused source line is strapped by metal along the source line, with approximately <b>80</b> milliohms per cell, in this case RSL=8192×0.08=655 ohms.

P-0175[0175] In conventional stacked gate drain-side CHE programming (abbreviated as CHE flash program), the single cell current is typically 1 μa, which causes a voltage drop along a single metal bitline of =˜1 maxRBL=˜1 max×1330 ohms=1330 millivolts, which is unacceptable since it is much greater than 1 level=8 millivolts. In SSI flash programming (abbreviated as SSI flash program), the typical cell current can be lowered to 1 μa, which causes a voltage drop along a single metal bitline of =˜1 μa×1330 ohms=1.33 millivolts, which is acceptable.

P-0176[0176] For 1024 cells drawing the cell current (Icell) continuously, the voltage drop (DVCL) along the source line from the driver to the other end follows the geometric equation:

DVCL=0.5^*P^*(P+1)^*R 8 cell^*Icell,tm   ( <b>1</b> )

P-0177[0177] where R8 cell=the metal source line resistance for 8 cells in series=0.08 ohms×8=0.64 ohms, and P=1024.

P-0178[0178] Along the source line, for 1024 cells programming simultaneously, the total current is 1024×1 ma=1.024 A for the CHE flash program and=1024×1 μa=1.024 ma for the SSI flash program. The power needed for the drain side CHE flash programming for parallel page mode operation is unsustainable due to very high current. Additionally, the voltage drop along the metal source line by equation (1) is =˜0.5×1024*1025*0.64*1 ma=336 Volts for CHE. This is unworkable for CHE flash technology. Similarly, the source line voltage drop for the SSI flash =˜336 millivolts. This is also unworkable in the multilevel program for the following reasons.

P-0179[0179] For a multilevel nonvolatile system, in one program cycle, the cell sensing voltage can only shift (dVR) a maximum of &lt;(Q*V<b>1</b>level) for reliable sensing, where Q was 0.5 in the prior example. However Q could vary from ⅓ to <b>{fraction (1/8)} for long term reliability. This is needed, for example, to allow for sensing margin, verify margin, program disturb, data retention, and endurance. The number of cells programming simultaneously within a selected page can vary between as many as 1024 to as few as only one from one program cycle to the next. Thus the total program current flowing through the common line CL could change by a factor of 1024 from one program cycle to the next. The resulting worst case voltage change in the source line VCL from one program cycle to the next is dVCL=˜</b>336 millivolts for SSI flash. This voltage jump in VCL causes the only remaining programming cell to over program, which causes the cell sensing voltage to shift much greater than the (Q*V<b>1</b>level). Hence, the challenge is to bring the voltage drop dVCL to an acceptable level during programming.

P-0180[0180] For verifying after programming multilevel memory cells, conventional methods would shut off the read cell currents for cells that have already reached their desired verifying levels, this would cause the voltage shift dVCL in verify as much as in programming as described above. This voltage jump dVCL would couple to the memory cells and cause a large jump in cell sensing voltage. This undesired large jump in cell sensing voltage causes an error in sensing, herein called a sense error VRerr. This sense error should be much less than (Q*V<b>1</b> level). Hence this large jump is unacceptable. The invention solves the problem by enabling the total current all the time whether the cells have been verified or not. This mitigates the change in the source line voltage. However a new problem surfaces as compared to that in programming. As temperature changes from −45C. to +85C. the resistance of the source line metal line changes by about 40%, hence the source line voltage drop changes by about 40%, which causes an additional sense error VRerr in read. This sense error should be much less than (Q*V<b>1</b>level) to prevent overall read margin degradation. Therefore, an array architecture is needed to achieve this, as will be described in detail below.

P-0181[0181] With <b>1024</b> cells operating simultaneously, assuming sense current Ircell=10 μa, the total sense current is=1024×10 μa=10.24 ma flowing into the source line. This presents several problems. With power specification for a typical memory chip ICC=˜20-30 ma. This 10.24 ma is a big percentage of the power specification. To deliver 10.24 ma while maintaining a precise voltage level VCLRD, VCLRD is defined as the voltage in read on CL line, requires a challenging decoding and driver scheme, which will be addressed in the description of the multilevel decoding scheme. Large current flowing across the source line also causes the voltage drop as described above.

P-0182[0182] High data rate, meaning high sense speed and write speed, is required for data intensive application. The speed is proportional to capacitance and voltage swing and inversely proportional to the current,

T=C*V/I   (2).

P-0183[0183] For typical bitline capacitance as calculated above, CBL=<b>25</b> pF and assuming voltage swing V=1V, and assuming available current I=10 μa, the time it takes to charge or discharge a bitline as needed in verify or program cycle is, TBL=25 pF* IV/10 μa=2.5 μs. This is greater than the TPV=1.42 μs as calculated above. At least a <b>2</b> × or better timing is required for TBL to allow for various settling time, sensing time, and programming time. Increasing the current would cause higher power consumption, large decoding driver, and voltage problems as described above.

P-0184[0184] Further, in programming 1024 cells in parallel, the programming current is supplied from an on-chip voltage multiplier, also known as a charge pump. The on-chip voltage multiplier multiplies the low voltage power supply, e.g., 2.5 V to the required higher voltages. Allowing a reasonable area penalty from the on-chip voltage multiplier, a total current of 100 μa is allowed for programming. The programming current per cell is 100 μa/1024=0.1 μa. This causes a TBL=25 pF*1V/0.1 μa=250 μs, which is even more severe of a timing problem. Here an improvement of more than 2 order of magnitude or better in speed is needed. The invention describes array architectures with suitable operating methods to achieve this improvement and will be described below.

P-0185[0185]FIG. 3A is the block diagram of a super high-density digital nonvolatile multilevel memory array architecture which is capable of >8-bit multilevel operation. The block <b>100</b> has been expanded from FIG. 2A to show the sub-blocks inside. A multilevel precision memory decoder MLMDECS <b>132</b> is used for delivering bias voltage levels with tight tolerance over temperature, process, and power supply variation for multilevel memory cells. A multilevel memory sub-array MFLSUBARY <b>101</b> includes a plurality of single multilevel memory cells. Other blocks in FIG. 3A have already been described in association with the description of FIG. 2A.

P-0186[0186] A block (PSEL) <b>120</b> includes a plurality of circuit blocks (PSELS) <b>120</b>S. FIG. 3B shows details of a page select circuit (PSELS) <b>120</b>S that selects a pair of bitlines at a time. Transistors <b>120</b>A-D are select transistors. Transistors <b>120</b>E-H are inhibit transistors. Lines (PP<b>0</b>) <b>120</b>K, (PP<b>1</b>) <b>120</b>M, (PP<b>2</b>) <b>1200</b>, and (PP<b>3</b>) <b>120</b>Q are complementary signals of lines (PPOB) <b>120</b>L, (PP<b>1</b>B) <b>120</b>N, (PP<b>2</b>B) <b>120</b>P, and (PP<b>3</b>B) <b>120</b>R, respectively. Line (BLYDRV) <b>120</b>Y goes to one y-driver (YDRVS) <b>110</b>S inside the block (YDRV) <b>110</b>. Block (YDRVS) <b>110</b>S will be described in detail later in the description of the multilevel algorithm. Lines (BLTPO) <b>240</b>P, (BLTP<b>1</b>) <b>241</b>P, (BLTP<b>2</b>) <b>242</b>P, and (BLTP<b>3</b>) <b>243</b>P couple to the bitlines in block <b>101</b> and couple to a set of lines (BLPO) <b>240</b>, (BLP<b>1</b>) <b>241</b>, (BLP<b>2</b>) <b>242</b>, and (BLP<b>3</b>) <b>243</b> of the circuit block <b>290</b> in FIG. 4A.

P-0187[0187]FIG. 3C shows a block diagram of a block (MFLSUBARY) <b>101</b>. A block (MFLSUBARY) <b>101</b> includes a plurality of blocks (ARYSEGO) <b>290</b>. Blocks (ARYSEGO) <b>290</b> are first tiled horizontally NH times and then the horizontally tiled blocks <b>290</b> are tiled vertically NV times. For a page with 1024 memory cells, NH is equal to 1024. NV is determined such that the total number of memory cells is equal to the size of the desired physical memory.array.

P-0188[0188]FIG. 4A shows a basic array unit (ARYSEGO) <b>290</b>. A block (RDlSEG) <b>300</b> is a multilevel decoding block. A plurality of the blocks RDLSEG makes up the circuit block (MLMDEC) <b>130</b>. In the block (ARYSEGO) <b>290</b>, there are 8 columns and FIG. 4A shows only <b>8</b> rows of memory cells, while other rows, e.g., 120 rows, are not shown for clarity. Each ARYSEGO <b>290</b> includes a plurality, e.g. 8, of array blocks (ARYLBLK) <b>290</b>A tiled vertically. A set of transistors <b>220</b>, <b>221</b>, <b>222</b>, <b>223</b>, <b>224</b>, <b>225</b>, <b>226</b>, <b>227</b> couples respectively a set of segment bitlines (SBLO) <b>240</b>A and (SBL<b>1</b>) <b>240</b>B, (SBL<b>2</b>) <b>241</b>A and (SBL<b>3</b>) <b>241</b>B, (SBL<b>4</b>) <b>242</b>A and (SBL<b>5</b>) <b>242</b>B, (SBL<b>6</b>) <b>243</b>A and (SBL<b>7</b>) <b>243</b>B to a set of top bitlines (BLPO) <b>240</b>, (BLP<b>1</b>) <b>242</b>, (BLP<b>2</b>) <b>242</b>, and (BLP<b>3</b>) <b>243</b>, respectively. Top bitlines refer to bitlines running on top of the whole array and running the length of the MFLSUBARY <b>101</b>. Segment bitlines refer to bitlines running locally within a basic array unit ARYSEGO <b>290</b>. A set of transistors <b>230</b>, <b>231</b>, <b>232</b>, <b>233</b>, <b>234</b>, <b>235</b>, <b>236</b>, <b>237</b> couples respectively segment bitlines (SBL<b>0</b>O) <b>240</b>A and (SBL<b>1</b>) <b>240</b>B, (SBL<b>2</b>) <b>241</b>A and (SBL<b>3</b>) <b>241</b>B, (SBL<b>4</b>) <b>242</b>A and (SBL<b>5</b>) <b>242</b>B, (SBL<b>6</b>) <b>243</b>A and (SBL<b>7</b>) <b>243</b>B to an inhibit line (VINHSEGO) <b>274</b>. A line (CL<b>0</b>) <b>264</b> is the common line coupled to common lines of the first four rows of memory cells. A line (CL<b>3</b>) <b>269</b> couples to common lines of the last four rows of memory cells. A set of control gates (CGO) <b>262</b>, (CG<b>1</b>) <b>263</b>, (CG<b>2</b>) <b>265</b>, (CG<b>3</b>) <b>266</b> couples to control gates of memory cells of the first four rows respectively. A set of control gates (CG<b>12</b>) <b>267</b>, (CG<b>13</b>) <b>268</b>, (CG<b>14</b>) <b>270</b>, (CG<b>15</b>) <b>271</b> couples to control gates of memory cells of the last four rows, respectively. A pair of inhibit select lines INHBLBO <b>272</b> and INHBLB<b>1</b><b>273</b> couples to gates of transistors <b>231</b>, <b>233</b>, <b>235</b>, <b>237</b> and transistors <b>230</b>, <b>232</b>, <b>234</b>, <b>236</b> respectively. A pair of bitline select lines (ENBLBO) <b>260</b> and (ENBLAO) <b>261</b> couples to gates of transistors <b>221</b>, <b>223</b>, <b>225</b>, <b>227</b> and transistors <b>220</b>, <b>222</b>, <b>224</b>, <b>226</b>, respectively.

P-0189[0189] Multiple units of the basic array unit (ARYSEGO) <b>290</b> are tiled together to make up one sub-array (MFLSUBARY) <b>101</b> as shown in FIG. 3C. And multiples of such (MFLSUBARY) <b>101</b> are tiled horizontally to make up the final 8192 columns for a total of 32768×8192=268,435,460 physical memory cells, or called 256 mega cells. The logical array size is 256 mega cells×4 bits per cell=1 giga bits if 4-bit digital multilevel memory cell is used or 256 mega cells×8 bits per cell=2 giga bits if 8-bit digital multilevel memory cell is used. The top bitlines (BLPO) <b>240</b>, (BLP <b>1</b>) <b>241</b>, (BLP<b>2</b>) <b>242</b>, and (BLP<b>3</b>) <b>243</b> run from the top of the array to the bottom of the array. The segment bitlines (SBLO) <b>240</b>A, (SBL<b>1</b>) <b>240</b>B, (SBL<b>2</b>) <b>241</b>A, (SBL<b>3</b>) <b>241</b>B, (SBL<b>4</b>) <b>242</b>A, (SBL<b>5</b>) <b>242</b>B, (SBL<b>6</b>) <b>243</b>A, and (SBL<b>7</b>) <b>243</b>B only run as long as the number of rows within a segment, for example, <b>128</b> rows. Hence the capacitance contributed from each segment bitline is very small, e.g., 0.15 pF.

P-0190[0190] The layout arrangement of the top bitlines <b>240</b>-<b>243</b> in relative position with each other and with respect to the segment bitlines (SBLO) <b>240</b>A, (SBL<b>1</b>) <b>240</b>B, (SBL<b>2</b>) <b>241</b>A, (SBL<b>3</b>) <b>241</b>B, (SBL<b>4</b>) <b>242</b>A, (SBL<b>5</b>) <b>242</b>B, (SBL<b>6</b>) <b>243</b>A, (SBL<b>7</b>) <b>243</b>B are especially advantageous in reducing the bitline capacitance. The purpose is to make the top bitlines as truly floating as possible, hence the name of truly-floating-bitline scheme.

P-0191[0191] In an embodiment as shown in FIG. 5A, lines <b>240</b>, <b>241</b>, and <b>242</b> are in the middle, sandwiched between lines <b>240</b>A, <b>240</b>B, <b>241</b>A and <b>241</b>B in the bottom and lines (CLO) <b>264</b> in the top. Furthermore, line <b>240</b> is on top of the spacing between lines <b>240</b>A and <b>240</b>B and line <b>241</b> is on top of the spacing between lines <b>241</b>A and <b>241</b>B. This has the benefit of reducing significantly the bottom plane capacitance of line <b>240</b> and line <b>241</b> since the oxide below each line is almost doubled. The lines <b>240</b> and <b>241</b> could be positioned on top of lines <b>240</b>A and <b>241</b>A, respectively, when the sidewall capacitance reduction outweighs the benefit of the bottom plane capacitance reduction. The sidewall capacitance refers to the capacitance resulting from the vertical walls of a line, the bottom plane capacitance refers to the capacitance from the bottom of a line, and the top plane capacitance refers to the capacitance from the top of a line.

P-0192[0192] In another embodiment, as shown in FIG. 5B, the top bitlines <b>240</b>-<b>242</b> have been positioned all the way to the top metal of a multi-layer metal integrated circuit system. For example, for a 5-layer metal integrated circuit system, the top bitlines are metal <b>5</b> layer. This avoids the top plane capacitance of the top bitlines <b>240</b>-<b>242</b>. This also reduces the bottom plane capacitance of the top bitlines <b>240</b>-<b>242</b> by a factor of as much as 4 if metal <b>5</b> is used. The reduction factor of 4 is due to the oxide below the line increasing by a factor of about as much as 4. Also since the top bitlines <b>240</b>-<b>242</b> are spaced further apart as compared to the segment bitlines, the sidewall capacitance is reduced significantly. The top bitlines are now almost floating on top of the array. The end effect is more than on order of magnitude reduction in bitline capacitance. Also since the top bitlines <b>240</b>-<b>242</b> spacing are relaxed, the width of the top metal lines can be made larger to reduce the metal bitline resistance.

P-0193[0193] The reduction in bitline capacitance results in a corresponding increase in speed. To help increase the speed in programming, a bitline-stabilization-assisted operating method can be applied and is described as follows. At the beginning of the programming cycle, a bitline stabilization control signal is used to set all the bitlines to a predetermined voltage VBLPRE, e.g., 0.4-0.8 V. Then high voltage VCL is applied to selected memory common lines for programming. Now the bitlines only have to move partially to a final voltage. This speeds up the TBL timing.

P-0194[0194] There is an important transient effect related to bitline capacitance in programming. For high speed writing, each program cycle takes time in the microsecond range. The program bias condition for a memory cell is control gate voltage VCGP,=˜0.7-2.5 V, bitline cell current Ipcell,=˜50-500 nA, and common line voltage VCL going from a low,=˜0 V, to a high programming voltage,=˜8-13 V. As the VCL ramps from a low to a high voltage, there is a transient current flowing through the memory cell to charge up the bitline node capacitance. This transient current flowing through the cell contributes to the cell programming in addition to the programming current Ipcell. Prior art CHE programming would not be bothered with this effect since the additional transient programming current is small compared to the actual programming current. However, for a very fine programming voltage level control as required for high bits per cell, this effect will cause the programming level to be uncontrollable, making the multilevel memory system useless. The following example is given to appreciate the magnitude of this transient current. Assuming program VCL ramp time=1 μs, CBL=1 pF, the voltage the bitline has to slew=1 V, then, by equation (2), I=CV/T=1 pF×1V/1 μs=1 μA, which can be 10× the programming current. Hence a method is needed to reduce the transient programming current.

P-0195[0195] Two approaches are shown in FIG. 5C to reduce this transient phenomenon. In one embodiment, 2-step ramp rate control approach greatly reduces this transient effect without prolonging the programming time as follows. First VCL ramps fast during TRP<b>1</b> to an intermediate voltage VCLINT, e.g., 2-6 V, then VCL stays at an intermediate voltage for a finite time TVCLINT, then VCL ramps slow during TRP <b>2</b> to a final voltage VCLFIN. The first fast ramp with the flat intermediate time TVCLINT will let transient current flowing through the cell to stabilize most of the cell capacitances such as CBL in a short time and at sufficiently low VCL voltage so that insignificant programming takes place while the transient current is flowing. The TRP<b>1</b> is made fast to consume little programming time. The second slow ramp then brings the cell to a final programming voltage without affecting the programming rate since very little current is flowing through the cell in the second ramp.

P-0196[0196] Another embodiment of the ramp rate control is a fast-slow ramp rate control approach. VCL first ramps fast during TRP<b>1</b> to an intermediate voltage VCLINT, then VCL ramps slow during TRP<b>2</b> to a final voltage VCLFFN. The first ramp TRP<b>1</b> is faster than that of the TRP<b>2</b> ramp to allow the transient current during the first ramp TRP I to stabilize quickly all the cell capacitances while VCL is low enough to not cause significant programming.

P-0197[0197] The ramp rate can be generated by a RC network, meaning the rate is controlled by a certain capacitance multiplied by a certain resistance, or by a CV/I network, meaning the rate is controlled by a certain capacitance multiplied by a voltage swing divided by a certain bias current. Further, the ramp rate can be programmable by programmable fuses as a function of bitline capacitance to optimize the programming time without introducing adverse transient current. That is the ramp rate is made to be faster for smaller bitline capacitance.

P-0198[0198] The common line CL<b>0</b><b>264</b> is common to four rows of memory cells for the following reason. Allowing 4 mV voltage drop along the CL line during programming to avoid programming error as described previously, with 1024 cells operating simultaneously with <b>0</b>.<b>1</b> μa drawn per cell, the voltage drop by equation (1) is, dVCLP=4 mV=0.5*(1024) (1025) R8cell*0.1 μa, hence R8 cell=76 milliohms. For a typical CL line with the line width half as wide as the memory cell, the CL resistance per cell is =˜80 milliohms, for 8 cells in series, R <b>8</b> cell is 8×80=640 milliohms, which is much greater than 76 milliohms. Hence by making CL line <b>264</b> four memory cells wide, R <b>8</b> cells is=˜<b>80</b> milliohms. The reason the width of the line CL <b>264</b> cannot be made arbitrarily large is due to the program disturb. As the high voltage is applied to CL line <b>264</b> in programming, all the cells connected to the CL line <b>264</b> will see the VCL voltage whether they are selected for programming or not. The more cells connected to the same CL line, the longer time for the disturb for the unselected cells.

P-0199[0199] Shown in FIG. 4A are the metal strapping lines (CLOSTRAP) <b>264</b>S and (CL<b>3</b>STRAP) <b>269</b>S of the common lines that connect the diffusion common lines to the metal common lines. The metal strapping could be done every 8, 16, or 32 memory cells depending on an allowable voltage drop along the common line diffusion inside the strapping. This voltage drop depends on the diffusion common line resistance for a given operating current.

P-0200[0200] An alternative method that mitigates the voltage drop problem along the common line in the program cycle is by the constant-total-current-program scheme. Namely by keeping the same total current flowing all the time independent of whether the cells have been verified or not, the common line voltage drop is kept constant during programming. This could be done for example, by adding additional switching transistors in the array every 8, 16, 32, or 64 memory cells and switching into the CL line the current equivalent to the current from verified cells.

P-0201[0201] Table 1 shows the operating conditions for the memory array in read, erase, and program. The array operating conditions are shown for the cell <b>200</b> of the block ARY<b>1</b>BLK <b>290</b>A in FIG. 4A, of a selected page for read and program. The selected cell <b>200</b> is one cell out of <b>1024</b> selected cells within a selected page. The other <b>1023</b> selected cells belong to the other <b>1023</b> ARYSEGO <b>290</b> connected horizontally. The array operating conditions are also shown for all cells connected to CL<b>0</b><b>264</b> for erase.

P-0202[0202] As shown in Table 1, the operating conditions are such that all the unselected memory cells see no voltage other than 0 volts. This reduces significantly the power consumption. This is also particularly advantageous for improved speed in very high-density memory chips since all the necessary driver circuits only see the loading from the selected memory cells. The loading from the whole array is tremendous due to large number of transistors in array, e.g., 256 million transistors, with its tremendous diffusion, metal and poly interconnect parasitics. For example, one bitline capacitance, CBL is 25 pF, with 8192 bitlines the total bitline capacitance is 8192×25 pF=204 nF. This would require a tremendous amount of power during signal switching, for example, to inhibit all the bitlines during programming. Also not shown in Table 1, the unselected control signals ENBLAs, ENBLBs, INHBLAs, and INHBLBs for unselected array units ARYSEG<b>0</b><b>290</b> only see 0 or VDD but not the multiplied high voltage. This again saves significant power and increases speed due to no loading from unselected control circuits.

P-0203[0203] Another factor that is reduced greatly is the excessive leakage current from the bitline to ground due to junction leakage, bitline to bitline leakage, band-to-band tunneling, and cell subthreshold conduction. For example, for a typical leakage of 10 pA per cell, with 16,384 cells per bitline, the total leakage is 164 nA, which is greater than Ipcell=100 nA. This implies that the multilevel programming will be uncontrolled due to the uncontrollable excessive leakage current contributing to the controlled programming current Ipcell. With the inhibit and segmentation scheme, the total leakage current is reduced to 128×10 pA=1.28 nA, which is much less than Ipcell=100 nA.

P-0204[0204]FIG. 4B shows an alternative array architecture in which the decoded inhibit line VINHSEGO<b>1</b><b>274</b>B is shared between any two adjacent segments. This has the benefit of reducing the number of inhibit lines in the array.

P-0205[0205]FIG. 4C shows an alternative array architecture in which the inhibit line VINH <b>999</b> is shared for all the segments. This has the benefit of sharing one inhibit line for the whole array.

P-0206[0206]FIG. 4D shows an alternative array architecture in which a set of inhibit select line INHBLA<b>1</b>-<b>3</b> and INHBLB<b>1</b>-<b>3</b><b>275</b> to <b>280</b> are used to inhibit all segment bitlines except the selected segment bitline. VINH <b>999</b> is shared for all the segments. The operating method makes use of a segment cascading scheme that is described as follows. To even isolate the bitline capacitance further, bitline select transistors <b>220</b>-<b>227</b> are also used as cascading transistors in programming in addition to the select and inhibit function. In programming, cell <b>200</b> for example, the voltage on line <b>261</b> is initially pulsed high to pass inhibit voltage VINH <b>999</b> from a page select (PSELS) <b>120</b>S into the selected segment bitline (SBL<b>0</b>) <b>240</b>A. Then the voltage on line ENBLA<b>0</b><b>261</b> is pulsed to a cascading voltage (VPBCAS), e.g., 1 V. A precharge signal then charges the selected top bitline (BLP<b>0</b>) 240 to 0.3 V. The final voltage on the top bitline (BLP<b>0</b>) <b>240</b> is=˜0.3 V since 1V-VT=˜0.3 V. Hence the voltage on line BLP<b>0</b><b>240</b> no longer changes during programming. The voltage on the segment bitline, however, still changes as VCL is applied and stabilized. But the capacitance on the segment bitline is minimal,=˜0.15 pF. Here the operating method just described could also apply to the array shown in FIG. 4A but the inhibit voltages on the unselected segment bitlines are floating. The array shown in FIG. 4D just makes sure all the unselected segment bitlines are kept at a constant inhibit voltage (VINH) <b>999</b>.

P-0207[0207]FIG. 4E shows another array suitable for the method just described above. It needs a set of 4 additional lines (INHBLAB<b>0</b>-<b>3</b>) <b>281</b>-<b>284</b> and a set of 8 additional transistors <b>2401</b>-<b>2471</b> for inhibit decoding. However additional transistors <b>2401</b>-<b>2471</b> occupy less die area than that required for additional inhibit decoding lines <b>275</b>-<b>280</b> in FIG. 4D.

P-0208[0208]FIG. 4F shows an array architecture similar to that in FIG. 4A with the inhibit transistors physically at the top of the segment array.

P-0209[0209] Note that it is possible to do one top bitline per one segmented bitline in the ARYSEGO <b>290</b>. In this case, the sidewall capacitance from one top bitline to adjacent top bitlines increases due to reduced spacing between the top bitline and the adjacent top bitlines.

P-0210[0210] Note that it is also possible to do one top bitline per more than two segmented bitlines in the ARYSEGO <b>290</b>. In this case, more decoding transistors are needed in the array to select one segmented bitline out of more than two segmented bitlines, which leads to more die size. However the sidewall capacitance from one top bitline to adjacent top bitlines decreases due to increased spacing between the top bitline and the adjacent top bitlines. This reduction of capacitance may not be significant if the spacing is already wide enough.

P-0211[0211] An alternative embodiment of reducing the bitline capacitance is by hierarchical interconnect segmentation that is an extension over the previous concept as follows. A first segment bitline running in first layer of metal couples to a plurality of memory cells. A second segment bitline running in second layer of metal is coupled to a plurality of first segment bitlines by bitline segment transistors through vias between metal <b>1</b> and metal <b>2</b>. Third segment bitline running in third layer of metal is coupled to a plurality of second segment bitlines by other bitline segment transistors through vias between metal <b>1</b> and metal <b>2</b> and metal <b>3</b>. This can continue to higher metal layers. This approach allows optimization of horizontal spacing, vertical spacing, interconnect width, and interconnect length between different layers of interconnect metals for minimum capacitive coupling between metal interconnect lines. This results in further reduced bitline capacitance. <tables id="TABLE-US-00001" num="1"><table frame="none" colsep="0" rowsep="0"><tgroup align="left" colsep="0" rowsep="0" cols="1"><colspec colname="1" colwidth="217PT" align="center" /><thead><row><entry namest="1" nameend="1" align="center">TABLE 1</entry></row></thead><tbody valign="top"><row><entry /></row><row><entry namest="1" nameend="1" align="center" rowsep="1" /></row><row><entry>Array Operating Conditions</entry></row></tbody></tgroup><tgroup align="left" colsep="0" rowsep="0" cols="4"><colspec colname="OFFSET" colwidth="77PT" align="left" /><colspec colname="1" colwidth="49PT" align="left" /><colspec colname="2" colwidth="42PT" align="left" /><colspec colname="3" colwidth="49PT" align="left" /><tbody valign="top"><row><entry /><entry>READ</entry><entry>ERASE</entry><entry>PROGRAM</entry></row><row><entry /><entry namest="OFFSET" nameend="3" align="center" rowsep="1" /></row></tbody></tgroup><tgroup align="left" colsep="0" rowsep="0" cols="4"><colspec colname="1" colwidth="77PT" align="left" /><colspec colname="2" colwidth="49PT" align="left" /><colspec colname="3" colwidth="42PT" align="left" /><colspec colname="4" colwidth="49PT" align="left" /><tbody valign="top"><row><entry>SELECTED</entry><entry /><entry /><entry /></row><row><entry>SEGMENTS:</entry></row><row><entry>CG0</entry><entry>3-6 V</entry><entry>8-13 V</entry><entry>0.7-2.5 V</entry></row><row><entry>CG1, 2, 3</entry><entry>0</entry><entry /><entry>8-13 V</entry></row><row><entry>CG4-15</entry><entry>0</entry><entry>0</entry><entry>0</entry></row><row><entry>Rest of all</entry><entry>0</entry><entry>0</entry><entry>0</entry></row><row><entry>CG lines</entry></row><row><entry>CL0</entry><entry>2-3 V</entry><entry>0</entry><entry>4-13 V</entry></row><row><entry>CL1, 2, 3</entry><entry>0</entry><entry>0</entry><entry>0</entry></row><row><entry>Rest of all</entry><entry>0</entry><entry>0</entry><entry>0</entry></row><row><entry>CL lines</entry></row><row><entry>BL0, 8, 16 . . .</entry><entry>0 T0 2-3 V</entry><entry>FL or 0 V</entry><entry>0-0.8 V</entry></row><row><entry>BL1-7, 9-15,</entry><entry>VINH</entry><entry>VINH</entry><entry>VINH</entry></row><row><entry>17-23, . . .</entry></row><row><entry>UNSELECTED</entry></row><row><entry>SEGMENTS:</entry></row><row><entry>All CG lines</entry><entry>0 V</entry><entry>0 V</entry><entry>0 V</entry></row><row><entry>All CL lines</entry><entry>0 V</entry><entry>0 V</entry><entry>0 V</entry></row><row><entry>All BL lines</entry><entry>0 V</entry><entry>0 V</entry><entry>0 V</entry></row><row><entry namest="1" nameend="4" align="center" rowsep="1" /></row></tbody></tgroup></table></tables>

P-0212[0212] Multilevel Memory Decoding:

P-0213[0213]FIG. 6 shows the block diagram of the multilevel decoding scheme. The invention provides precision voltages with millivolt control tolerances to the memory array over temperature, process comers, and power supply variation. The invention provides these voltages in an efficient manner, meaning deliver power where it is needed and reducing the output loading through circuit configuration. The invention also provides a multilevel precision decoding circuit with minimum area overhead.

P-0214[0214] As discussed in the array architecture section, the voltage drop along the common line would cause a programming error as well as sense error in read. Hence the drop is brought down to a manageable level. By partitioning a common line into small line sections, with drivers on both sides of each of the line sections, the voltage drop is reduced. However, prior art partition would cause a tremendous area penalty due to the large amount of decoding lines and circuits. This invention provides an enhanced decoding circuit by routing the interconnect in the higher metal layers and by using circuit configurations suitable for multilevel decoding.

P-0215[0215] The block (VCGCLPRED) <b>156</b> has been expanded to include sub-blocks inside. Common line predecoder and driver (XCLPREDRV) <b>950</b> provide predecoded common lines with precision voltages to regular memory common lines in block <b>130</b> and <b>132</b>. A common line predecoder and driver (XCLSPREDRV) <b>954</b> provides predecoded common lines with precision voltages to spare memory common lines in block <b>134</b>. The circuit block <b>954</b> is functional equivalent to circuit <b>950</b>. A control gate predecoder (XCGPREDEC) <b>951</b> provides predecoded control gate lines to block <b>130</b>. A spare control gate predecoder (XCGSPREDEC) <b>952</b> provides predecoded control gate lines to block <b>134</b>. A bitline predecoder (BLXDEC) <b>953</b> provides predecoded bitlines to block (MLMDEC) <b>130</b>. All other circuit blocks have been described in association with FIG. 2A.

P-0216[0216]FIG. 7 shows one segmented decoder (RD<b>1</b> SEG) <b>300</b>. The RDI SEG <b>300</b> selects or deselects a plurality of basic array unit (ARYSEGO) <b>290</b> connected horizontally. The RD<b>1</b>SEG <b>300</b> includes a circuit segmented supply decoder (RDSGPSDEC) <b>301</b>, a segmented bitline decoder (RDSGBLDEC) <b>302</b>, a segmented common line pre-decoder (RDSGCLPDEC) <b>302</b>B, a segmented inhibit decoder (RDSGINHDEC) <b>303</b>, and multiples of a sub-block decoder (RDISUBBLK) <b>304</b>. The RDSGPSDEC <b>301</b> decodes the high voltage supply for each segmented decoder (RDLSEG <b>300</b>). The high voltage supplies for the unselected segmented decoders (RD<b>1</b> SEG) <b>300</b> are disabled and hence power is minimized due to much less loading and die size is reduced due to a smaller voltage multiplier. The RDSGBLDEC <b>302</b> couples the segment bitlines to the top bitlines when selected. The RDSGINHDEC <b>303</b> couples the inhibit voltage (VINH) <b>999</b> to the appropriate bitlines of the selected array units (ARYSEG) <b>290</b> when selected or unselected as described later in FIG. 9B. The RDISUBBLK <b>304</b> enables appropriate control gates and common lines for the memory cells.

P-0217[0217]FIG. 8 shows details of the power supply decoder (RDSGPSDEC) <b>301</b>. Line (NI) <b>310</b> and (OI) <b>311</b> are predecoded address lines coming from the address predecoder block (XPREDEC) <b>154</b>. Line ENVSUPDEC <b>312</b> is a global enable signal for disabling or enabling all the supply decoders. A NAND gate <b>315</b> is a typical 3-input NAND gate with an output line (ENB) <b>313</b>. An inverter <b>316</b> is a typical inverter with input line (ENB) <b>313</b> and an output line <b>314</b>. A high voltage level shifter (HVLS<b>1</b>) <b>317</b> shifts logic signal EN <b>314</b> into high voltage complementary output signal lines (ENVSUPB) <b>318</b> and (ENVSUP) <b>319</b>. A line (VXRGND) <b>333</b> is a low voltage line for (HVLS<b>1</b>) <b>317</b>. A line (VHSUPPLY) <b>777</b> is a precisely regulated high voltage supply for the decoding. A line (VMSUPPLY) <b>666</b> is another precisely regulated high voltage supply. A transistor PMOS <b>322</b> couples the high voltage supply (VHSUPPLY) <b>777</b> into line (VHSUPPLYSG) <b>328</b> when the RDSGPSDEC <b>301</b> is selected. Transistors PMOS <b>323</b> and <b>324</b> couple regular voltage supply (VDD) <b>1111</b> into line (VHSUPPLYSG) <b>328</b> when the RDSGPSDEC <b>301</b> is deselected. A transistor PMOS <b>325</b> couples another high voltage supply (VMSUPPLY) <b>666</b> into line (VMSUPPLYSG) <b>329</b> when the RDSGPSDEC <b>301</b> is selected. The voltage level on line (VMSUPPLY) <b>666</b>, e.g., 5-10 V, is such that in read the bitline select transistors in the memory array are heavily overdriven to reduce their on resistance, which results in insignificant sense error. Transistors PMOS <b>326</b> and <b>327</b> couple regular voltage supply (VDD) <b>1111</b> into line (VMSUPPLYSG) <b>329</b> when the RDSGPSDEC <b>301</b> is deselected. The PMOS <b>323</b> and <b>326</b> have their wells connected to line (VDD) <b>1111</b>. The PMOS <b>324</b> and <b>327</b> have their wells connected to the VHSUPPLYSG <b>328</b> and VMSUPPLYSG <b>329</b>, respectively. The connection of their wells is done to avoid source and drain junction diodes turning on during the switching.

P-0218[0218]FIG. 9A shows details of the segmented bitline select decoder (RDSGBLDEC) <b>302</b>. Line (ENVSUP) <b>319</b> and line (ENBLAVH) <b>341</b> connected to the gates of transistors <b>360</b> and <b>361</b>, respectively, are used to couple voltage on line VMSUPPLYSG <b>329</b> into line ENBLA <b>369</b>. Either transistor <b>362</b> with line (ENB) <b>313</b> on its gate or transistor <b>363</b> with line (ENBLBVL) <b>342</b> on its gate is used to couple line (ENBLA) <b>369</b> to line (VXRGND) <b>333</b>. Similarly transistors <b>364</b> and <b>365</b> together with lines (ENVSUP) <b>319</b> and line (ENBLBVH) <b>343</b>, respectively, on their gates are used to couple voltage on line (VMSUPPLYSG) <b>329</b> into line (ENBLB) <b>371</b>. Either transistor <b>366</b> with line (ENB) <b>313</b> on its gate or transistor <b>367</b> with line ENBLAVL <b>340</b> on its gate are used to couple line (ENBLB) <b>371</b> to line (VXRGND) <b>333</b>. The voltage level on line (VHSUPPLY) <b>777</b> in the block (RDSGPSDEC) <b>301</b>, e.g., 7-12 V, is such that the transistors <b>360</b>, <b>361</b>, <b>364</b>, <b>365</b> couple, with minimal loss, the voltage from VMSUPPLYSG <b>329</b> into lines (ENBLA) <b>369</b> and (ENBLB) <b>371</b>. The deselect transistors <b>362</b>, <b>363</b>, <b>366</b>, and <b>367</b> have their gates coupled only to the low voltage signals instead of the high voltage control signals as conventionally done. This circuit configuration has the benefit of reducing significantly the loading for the high voltage supply (VHSUPPLY) <b>777</b>. This circuit configuration is applied throughout all the decoding circuits.

P-0219[0219]FIG. 9B shows details of the segmented inhibit select decoder (RDSGINHDEC) <b>303</b>. Either transistor <b>350</b> with line (ENVSUPB) <b>318</b> on its gate or transistor <b>353</b> with line (ENBLBVH) <b>343</b> on its gate couples the voltage on line (VMSUPPLYSG) <b>329</b> to line (INHBLA) <b>345</b>. Transistors <b>351</b> and <b>352</b> together with lines (EN) <b>314</b> and (ENBLAVL) <b>340</b>, respectively, on their gates are used to couple line (INHBLA) <b>345</b> to line (VXRGND) <b>333</b>. Similarly either transistor <b>354</b> with line (ENVSUPB) <b>318</b> on its gate or transistor <b>357</b> with line (ENBLAVH) <b>341</b> on its gate is used to couple the voltage on line (VMSUPPLYSG) <b>329</b> to line (INHBLB) <b>347</b>. Transistors <b>355</b> and <b>356</b> together with lines (EN) <b>314</b> and line (ENBLBVL) <b>342</b> respectively on their gates are used to couple line (INHBLB) <b>347</b> to line (VXRGND) <b>333</b>. Transistor <b>358</b> with line (ENVSUP) <b>319</b> on its gate is used to couple the inhibit voltage on line (VINH) <b>999</b> to line (VINHSEG) <b>349</b>. Transistor <b>359</b> with line (ENB) <b>313</b> on its gate is used to couple the voltage on line (VINHSEG) <b>349</b> to line (VXRGND) <b>333</b>. Similar to the circuit configuration in the RDSGBLDEC <b>302</b>, the low voltage signals are used for signal deselection.

P-0220[0220] The circuit blocks RDSGPSDEC <b>301</b>, RDSGBLDEC <b>302</b>, RDSGINHDEC <b>303</b>, and RDISUBBLK <b>304</b> are used in the array as shown in FIG. 4A for array selection and inhibit decoding.

P-0221[0221]FIG. 9C shows a predecoded common line segmented decoder (RDSGCLPDEC) <b>302</b>B for lines (CLP<b>0</b>-<b>3</b>) <b>445</b>A-D. Lines (CLP<b>0</b>-<b>3</b>) <b>445</b>A-D come from a common line pre-decoder (XCLPREDRV) <b>950</b>. The purpose of this circuit (RDSGCLPDEC) <b>302</b>B is to greatly reduce the capacitive loading on lines CLP<b>0</b>-<b>3</b> seen by the common line pre-decoder (XCLPREDRV) <b>950</b>. Lines (CLPS<b>0</b>-<b>3</b>) <b>456</b>A-D are the output lines. Transistors <b>438</b>A-D with line (ENVSUP) <b>319</b> on their gates are used to couple lines (CLP<b>0</b>-<b>3</b>) <b>445</b>A-D to lines (CLPS<b>0</b>-<b>3</b>) <b>456</b>A-D, respectively. Transistors <b>439</b>A-D with line (ENB) <b>313</b> on their gates are used to couple lines (CLPS<b>0</b>-<b>3</b>) <b>456</b>A-D to line (VXCLGND) <b>5555</b>. This concept of segmented loading could also be applied to predecoded control gates CGP<b>0</b>-<b>15</b>.

P-0222[0222]FIG. 10 shows details of the sub-block decoder (RD<b>1</b>SUBLK) <b>304</b>, that includes a circuit block <b>304</b>A and a circuit block <b>304</b>B. The bloc<b>6</b>tgk <b>304</b>A includes a NAND gate <b>412</b>, an inverter <b>413</b>, and a high voltage level shifter (HVLSX) <b>418</b>. The 3-input NAND gate <b>412</b> is used for address decoding. Line (ENB<b>4</b>) <b>414</b> is its output. Lines (MI) <b>410</b>, (NI) <b>310</b>, and (OI) <b>311</b> are predecoded address lines coming from the address pre-decoder (XPREDEC) <b>154</b>. The inverter <b>413</b> inverts line (ENB<b>4</b>) <b>414</b> into line (EN<b>4</b>) <b>415</b>. The high voltage level shift (HVLSX) <b>418</b> is used to shift the logic signal EN<b>4</b><b>415</b> into the high voltage output signal (ENHV<b>4</b>BLK) <b>417</b>. Line (VHSUP) <b>770</b> supplies high voltage for the level shifter (HVLSX) <b>418</b>. Line (VHSUP) <b>770</b> couples to line (VHSUPLYSG) <b>328</b> of circuit block (RDSGPSDEC) <b>301</b>. The circuit block <b>304</b>B including a set of four circuit blocks (RD<b>4</b>CG<b>1</b>CL) <b>416</b> provides control signals for control gates (CG) and common lines (CL). Lines CG[<b>0</b>:<b>15</b>] <b>422</b>A-P couple to 16 rows of memory cells, for example, lines <b>262</b>, <b>263</b>, <b>265</b>-<b>268</b>, <b>270</b>, <b>271</b> of the block (ARY<b>1</b>BLK) <b>290</b>A in FIG. 4A. Lines CL[<b>0</b>:<b>3</b>] <b>423</b>A-D couple to 4 shared common lines of memory cells, for example, lines <b>264</b> and <b>269</b> of the block ARY<b>1</b>BLK <b>290</b>A in FIG. 4A. Lines CGP[<b>0</b>:<b>15</b>] <b>420</b>A-P are predecoded control gate lines coming from the control gate pre-decoder (XCGPREDEC) <b>951</b>. Lines CLPS[<b>0</b>:<b>3</b>] <b>456</b>A-D are predecoded common lines coming from block RDSGCLPDEC <b>302</b>B. Line (VXCGGND) <b>444</b> is a line for control gate (CG) deselection. Line (VXCLGND) <b>5555</b> is a line for common line (CL) deselection.

P-0223[0223]FIG. 11A shows details of circuit block (RD<b>4</b>CG<b>1</b>CL) <b>416</b>. Transistors <b>430</b>, <b>432</b>, <b>434</b>, <b>436</b> together with lines (CGPO) <b>440</b>, line (CGP<b>1</b>) <b>441</b>, line (CGP<b>2</b>) <b>442</b>, line (CGP<b>3</b>) <b>443</b>, respectively, on their drains are used to couple these lines <b>440</b>-<b>443</b> to output line (CGO) <b>450</b>, line (CG<b>1</b>) <b>451</b>, line (CG<b>2</b>) <b>452</b>, and line (CG<b>3</b>) <b>453</b>, respectively. Lines (CGPO-CGP <b>3</b> ) <b>440</b> - <b>443</b> come from a control gate predecoder (XCGPREDEC) <b>951</b>. Transistor <b>438</b> is used to couple line (CLPS<b>0</b>) <b>456</b>A to line (CLO) <b>454</b>. Transistor <b>439</b> is used to couple line (CLO) <b>454</b> to line (VXCLGND) <b>5555</b>. Line (ENHVLBLK) <b>446</b> couples high voltage into the gates of transistors <b>430</b>, <b>432</b>, <b>434</b>, and <b>436</b>. Line (ENB<b>1</b>BLK) <b>447</b> couples lines (CGO-<b>3</b>) <b>450</b>-<b>453</b> to the line (VXCGGND) <b>444</b> through transistors <b>431</b>, <b>433</b>, <b>435</b>, and <b>437</b>, respectively, and couples line (CLO) <b>454</b> to line (VXCLGND) <b>5555</b> through transistor <b>439</b>. The lines (ENHV<b>1</b>BLK) <b>446</b> and (ENB<b>1</b>BLK) <b>447</b> are coupled respectively to lines (ENHV<b>4</b>BLK) <b>417</b> and (ENB<b>4</b>) <b>414</b> generated by circuit block <b>304</b>.

P-0224[0224] Four common lines of memory cells are coupled together to one decoded common line CL as shown in the block (ARYSEG<b>0</b>) <b>290</b> in FIG. 4A. Four blocks of the RD<b>4</b>CG<b>1</b>CL <b>416</b> are used to provide array block selection as shown in the block (ARYSEGO) <b>290</b> in FIG. 10. One array block is defined as including 16 rows and 4 common lines of memory cells. One array block includes a plurality of blocks (ARY<b>1</b>BLK) <b>290</b>A connected horizontally.

P-0225[0225] The lines (VXRGND)<b>333</b>, (VXCLGND) <b>5555</b>, and (VXCGGND) <b>444</b> could be individually controlled to be biased at different voltage levels during erase, read, and program to optimize circuit functionality, for instance, to increase the breakdown or to reduce the leakage of MOS decoding transistors.

P-0226[0226] Note that the same transistors are used for decoding in erase, read, and program operation. In conventional decoding, read decoding is isolated from erase and program decoding since read decoding requires only low voltage and hence the decoding size can be optimized for read speed. Here all decoding is combined together to minimize the die size. Further all decoding is done by NMOS transistors instead of by both PMOS and NMOS transistors as conventionally done. This has the benefit of reducing the capacitive loading. This is so because in deselection one PMOS presents itself as a gate capacitor load while one NMOS only presents itself as a source or drain overlap capacitor load, which is much smaller than a gate capacitor load. Low capacitive loading leads to less power consumption for NMOS decoding. This is against conventional wisdom, which holds that a CMOS circuit is more power efficient than a NMOS circuit.

P-0227[0227]FIG. 11B shows an alternative circuit block (RD<b>4</b>CG<b>1</b>CL) <b>416</b> with a diode-connected transistor <b>438</b>F. The transistor <b>438</b>F provides feedback signal (CLK) <b>445</b>F for a Kelvin type connection to a circuit driver inside the block (XCLPREDRV) <b>950</b>. A Kelvin connection line consumes minimal (or no) DC current. A Kelvin connection allows a circuit driver such as a common line circuit driver to stabilize its output signal at a desired voltage level based on feedback voltage from the Kelvin connection line. This Kelvin connection line (CLK) <b>445</b>F is connected to other Kelvin connection lines vertically. This is possible since only one common line is on at any given time. Once a common line is selected, this common line will take control of the CLK <b>445</b>F line since the diode-connected transistor will be forward biased and other diode-connected transistors on the rest of the common lines will be reverse biased. This will be known as winner-take-all Kelvin decoder. This winner-take-all Kelvin decoder will ensure a predetermined voltage on the line (CL<b>0</b>) <b>454</b> will be stable all the time over varying load, process comers, temperature, and power supply variation with minimum cost. The stable voltage on the common line is required to not introduce significant voltage error in program or in read as described previously in the description of the multilevel array architecture.

P-0228[0228]FIG. 11C shows a circuit block (RD<b>1</b>CL) <b>304</b>C, which is used in a common line segmentation scheme with the array partitioning shown in FIG. 12 to reduce the voltage drop along the common lines. In an embodiment, one common line (CL) is connected together across the full array with a plurality of blocks (RD<b>1</b>CL) <b>304</b>C driving the same common line (CL). Transistor <b>438</b>S with line (ENHV<b>1</b>BLK) <b>446</b> on its gate couples line (CLPS<b>0</b>S) <b>456</b> AS to line (CL<b>0</b>) <b>454</b>. Line (CL<b>0</b>) <b>454</b> of this circuit block <b>304</b>C is the same line (CL<b>0</b>) <b>454</b> of the circuit block (RD<b>4</b>CG<b>1</b>CL) <b>416</b>. A deselect transistor <b>439</b>S with line (ENB<b>1</b>BLK) <b>447</b> couples line (CL<b>0</b>) <b>454</b> to line (VXCLGND) <b>5555</b>. The transistor <b>439</b>S is optional in this circuit since the function of coupling line (CL<b>0</b>) <b>454</b> to line (VXCLGND) <b>5555</b> is already provided by the transistor <b>439</b> in the RD<b>4</b>CG<b>1</b>CL <b>416</b>. The transistor <b>439</b>S provides additional drive ability in addition to that of the transistor <b>439</b>. Line (CLPS<b>0</b>S) <b>456</b>AS couples to a common line pre- decoder (XCLPREDRV) <b>950</b>. The winner-take-all Kelvin decoding can also be used here. The control signals (ENHV<b>4</b>BLK) <b>417</b> and (ENB<b>4</b>) <b>414</b> shown in the block (RD<b>1</b>SUBBLK) <b>304</b> couple to control signals (ENHVLBLK) <b>446</b> and (ENB<b>1</b>BLK) <b>447</b>, respectively. The control signals (ENHV<b>4</b>BLK) <b>417</b> and (ENB<b>4</b>) <b>414</b> are fed through the memory array as shown in FIG. 12. In an alternate embodiment, one common line is divided into many separate common lines across the full array. These separate common lines are not connected to each other. In this case, each separate common line is driven on both sides by two blocks (RD<b>1</b>CL) <b>304</b>C or by a (RD<b>1</b>CL) <b>304</b>C and a (RD<b>4</b>CG<b>1</b>CL) <b>416</b>. Common line segmentation is described more in detail below in description associated with FIG. 12.

P-0229[0229]FIG. 12 shows a feedthrough-to-memory and feedthrough-to-driver scheme together with the common line segmentation to deliver precise voltages for memory cells as described in the following. The feedthrough scheme exploits the multi-layer metal interconnect to reduce the circuit complexity and die size and to enable innovative circuit configurations. A conventional flash memory system typically only uses up to a maximum of 2 metal layers and hence is limited in core interconnect scheme possibilities. This feedthrough scheme is made possible by three or more metal layers.

P-0230[0230] The block (MLMDECS) <b>132</b>, shown in FIG. 12 and also in FIG. 3A, includes a plurality of the blocks (RDSGCLPDEC) <b>302</b>B and a plurality of the blocks (RD<b>1</b>CL) <b>304</b>C. Only one block (RDSGCLPDEC) <b>302</b>B and one block (RD<b>1</b>CL) <b>304</b>C per block <b>132</b> are shown in FIG. 12 for clarity. Other blocks have similar connections. The block (MLMDEC) <b>130</b>, shown in FIG. 12 and also in FIG. 3A, includes a plurality of the blocks (RD<b>1</b>SEG) <b>300</b>. The block RD<b>1</b>SEG <b>300</b> includes a block (RDSGPSDEC) <b>301</b> and a plurality of blocks (RDlSUBBLK) <b>304</b>. Only the block (RDSGPSDEC) <b>301</b> and one block (RD<b>1</b>SUBBLK) <b>304</b> inside one block RDLSEG <b>300</b> are shown in FIG. 12 for clarity. Other blocks have similar connections.

P-0231[0231] The feedthrough-to-memory uses a single driver to drive both left and right sides of a memory array. The layout of row decoding circuits such as of the block (RD<b>1</b>SUBBLK) <b>304</b> is very dense because of the limited height of a typical advanced memory cell, e.g., 0.5-1 μm per cell height, and the very wide width of each decoding transistor, e.g., 20-50 μm, due to their required precision multilevel drive ability. This makes it extremely difficult to route the required lines from the right side across the active circuit of this row decoding circuit to the left side with limited layers of metal interconnect. As shown in FIG. 10, the control lines CG[<b>0</b>:<b>15</b> ] <b>422</b> A-P and common lines CL [<b>0</b>:<b>3</b> ] <b>423</b> A-D provides the control signals to the memory cells on the right side as well as the memory cells on the left side. This is also shown in FIG. 12 in block <b>304</b>B with lines pointing to the right as well as to the left. Similarly it also shows the control lines from circuit block <b>304</b>A and <b>304</b>C driving both sides. The feedthrough-to-memory scheme also shows predecoded high voltage lines (ENHV<b>4</b>BLK) <b>417</b> and (ENVSUP) <b>319</b> and predecoded low voltage lines (ENB) <b>313</b> and (ENB<b>4</b>) <b>414</b> being fed through the memory by running on top of the memory, for example, in metal <b>4</b>, without interfering with the memory cells underneath. Other control lines could also be fed through the memory. Again this is achievable by three or more metal layers which allow a different circuit configuration with minimal active area. The circuit block <b>304</b>C is the precision voltage driver for the common lines CL of the memory cells in addition to the circuit block <b>304</b>B. The feedthrough-to-driver scheme shows control signals from circuit blocks <b>304</b>B and <b>304</b>A being fed through the memory array to the precision voltage drivers <b>304</b>C.

P-0232[0232] The common line segmentation is also shown in FIG. 12. Each metal common line runs the length of the memory core horizontally across the full array with seven circuit blocks (RD<b>1</b>CL) <b>304</b>C and two circuit blocks (RD<b>1</b>SUBBLK) <b>304</b> driving the same common line. The voltage drop across one common line is thus divided into eight voltage drop segments. Each voltage drop segment belongs to each common line of each sub-array block (MFLSUBARY) <b>101</b>. Within each voltage drop segment, the voltage value on the left side is same as the voltage value on the right side of the voltage drop segment and the lowest voltage value is in the middle of the voltage drop segment. This is because there is a precision circuit driver (RDLCL) <b>304</b>C or (RD<b>4</b>CG<b>1</b>CL) <b>416</b> on each side of the voltage drop segment. One alternative embodiment of the common line segmentation scheme is to have these common lines physically divided into eight separate common lines. That is, each sub-array block (MFLSUBARY) <b>101</b> shown in FIG. 12 has its separate common line. However, in this case, the deselect transistor <b>439</b>S in the block (RD<b>1</b>CL) <b>304</b>C is no longer optional but necessary to deselect each separated common line.

P-0233[0233] The voltage level on the control gates is controlled by the voltage on the lines (CGP[<b>0</b>:<b>15</b> ]) <b>420</b> A-P in circuit block <b>304</b>. The voltage on lines (CGP[<b>0</b>:<b>15</b> ]) <b>420</b> A-P are in turn controlled by a precise bandgap-referred regulated voltage. Hence precision voltage level is provided at the memory control gates. The voltage level on the common lines is controlled by the voltage on the predecoded common lines (CLP[<b>0</b>:<b>3</b> ]) <b>421</b> A-D in circuit block <b>304</b>. The voltage on lines (CLP[<b>0</b>:<b>3</b> ]) <b>421</b> A-D are in turn controlled by a precise bandgap-referred regulated voltage for each common line driver. Hence precision voltage level is provided at the memory common lines. The programming and sensing current bias are also bandgap-referred; hence they are highly stable.

P-0234[0234] Note that in FIG. 12 an alternative embodiment is to share one block (RDSGPSDEC) <b>301</b> or <b>304</b>A across the full array by doing feedthrough of the outputs of (RDSGPSDEC) <b>301</b> or <b>304</b> A across the full memory array. In this case the drive ability of the driver circuit inside block (RDSGPSDEC) <b>301</b> or <b>304</b>A should be adequately designed to drive the long interconnect lines.

P-0235[0235] Note that in FIG. 10 an alternative embodiment is to have a separate block (RD<b>4</b>CG<b>1</b>CL) <b>416</b> for driving the right side of an array and another separate block (RD<b>4</b>CG<b>1</b>CL) <b>416</b> for driving the left side of an array. Another alternative embodiment is to share just one CL driver for both left and right sides but to have separate control gate CG drivers for the left side and the right side.

P-0236[0236] Multilevel Reference System:

P-0237[0237]FIG. 13 shows a block diagram for a multilevel digital memory reference system. All the relevant blocks have been described in association with previous figures. The highlighted blocks <b>106</b>, <b>116</b>, <b>126</b>, and <b>146</b> with the highlighted lines (VREF<b>0</b>-<b>15</b>) <b>760</b>-<b>775</b> are shown to show the reference system in relation to the physical position of the array and y-drivers. The physical position of the reference array corresponding to various schemes is explained in the following description.

P-0238[0238]FIG. 14 shows details of a multilevel digital memory reference system. A reference circuit block (VREFGEN) <b>719</b> is used to provide all reference voltage levels for erasing, programming, sensing, margin tests, and production tests. Shown are reference levels for reference cells (VREFR<b>0</b>-<b>15</b>) <b>700</b>-<b>715</b> and reference levels for data cells (VREFD<b>0</b>-<b>15</b>) <b>720</b> -<b>735</b>. Data cells refer to memory cells that store digital data. A 16 level multilevel flash cell is assumed for this discussion. A flash reference array (MFLASHREF) <b>106</b> includes a plurality of blocks (MFLASHREFS) <b>106</b>A. A block (MFLASHREFS) <b>106</b>A includes a plurality of reference memory cells. A reference page select <b>126</b>A is used to select the reference cells in the blocks (MFLASHREFS) <b>106</b>A associated with a selected page. Each block <b>126</b>A selects one reference cell in one corresponding block (MFLASHREFS) <b>106</b>A. For each selected page, there are <b>16</b> blocks <b>126</b>A selecting 16 reference cells in 16 corresponding blocks (MFLASHREFS) <b>106</b>A. The 16 selected reference cells makes up one page reference.

P-0239[0239] A buffer (VRBUFFER) <b>750</b> and a comparator <b>801</b> are inside a block (REFYDRVS) <b>116</b>S. The buffer (VRBUFFER) <b>750</b> is used to drive each reference level of (VREF<b>0</b>-<b>15</b>) <b>760</b>-<b>775</b> for all the y-drivers. A buffer circuit without offset auto zero <b>750</b>A is used to isolate the reference cell from all capacitance from auxiliary circuits. The offset auto zero cancels out the voltage offset of an analog buffer. The voltage offset of an analog buffer is typically uncontrollable and is caused by threshold voltage mismatch, transistor transconductance mismatch, and systematic offset. This voltage offset would cause an uncertainty in the reference voltage, which would degrade the margin of one voltage level with respect to another voltage level. Line (VBUFO) <b>781</b> is used to verify a reference cell is programmed to one desired reference level out of 16 possible reference levels. Line (VBUFO) <b>781</b> is used instead of the direct memory cell output for verifying in the verify cycle. This is to include the buffer offset from buffer <b>750</b>A in the verifying process. The comparator <b>801</b> is used to do the actual comparison in verify. A buffer with offset auto zero <b>750</b>B is used to drive a reference level. Various voltage levels needed for multilevel algorithm are also generated by the buffer <b>750</b> B with switch capacitor technique. The auto zero is needed to zero out the offset of this buffer since a typical buffer offset is 10-20 mV. This voltage amount if not canceled out would degrade the margin of a reference level, which effectively reduces the voltage margin for each level. Capacitors are needed to accomplish the auto zero and level shifting operation in the buffer <b>750</b>B. However as described in the array architecture description, any additional capacitance would adversely degrade the write and read speed. Hence buffer <b>750</b>A is inserted between the reference cell and the buffer <b>750</b>B so that the reference cell only sees one gate capacitance inside a typical buffer as a capacitor load.

P-0240[0240] Lines (VREF<b>0</b>-<b>15</b>) <b>760</b>-<b>775</b> are the final reference lines driving into all the y-drivers as needed for verify-program cycles and read cycles. Switch S <b>750</b>D couples line (VREFD) <b>720</b> to the input terminal of buffer <b>750</b>B when one selected page programs for the first time. Switch S <b>750</b>C couples line (VBUFO) <b>781</b> to input terminal of buffer <b>750</b>B when the same selected page programs for the second time or more without an erase in between program. The reason is that for first time programming, reference levels for data cells come from a reference generator VREFGEN <b>719</b> and for subsequent programming reference levels come from the reference cells in MFLASHREFS <b>106</b>A.

P-0241[0241] For the memory system described herein, there are 8 pages for each row, 4 rows for each block, and 512 bytes per page with a 4-bit digital multilevel memory cell. Since any one page is written or read at any time a complete reference set of 16 levels is reserved for each page instead of for each row. This is done to preserve the operating conditions through the lifetime of a memory system exactly the same for reference cells as regular data cells. This is done for example to make the reference and data cells have the same voltage readout drift over time. For each row, there are <b>8</b> x <b>16</b> =<b>128</b> reference cells. This has some small die size penalty. The reference cells are written at the same time as the regular data cells.

P-0242[0242] After the reference cells are written with the first programming sequence, if subsequent programming cycles are allowed to write other data cells in the same page, the previously programmed reference cells stay in the program inhibit mode. This is accomplished as shown in FIG. 15. A comparator <b>850</b> is used to compare a reference voltage from a bandgap VREF <b>851</b>, e.g., 1.2 V, versus a readout voltage from a reference memory cell VREFOUT <b>852</b>, for example, level <b>0</b>, e.g., 0.5 V. If the reference cell has not been written, VREF <b>851</b><VREFOUT <b>852</b>, then line (REFON) <b>853</b> would be low. If the reference cell has been written, VREF <b>851</b>>VREFOUT <b>852</b>, then line (REFON) <b>853</b> would be high indicating that the reference cells have been previously written and the reference cells are inhibited in programming.

P-0243[0243] For subsequent programming cycles after the first programming cycle, the reference voltages for the data cells come from the reference cells and the reference voltages are shifted appropriately to place the data voltages in between the adjacent reference voltages.

P-0244[0244] The voltage drop along the common line poses a particular problem for a multilevel reference system. Reference cells are needed to track the data cells over temperature, process, or power supply. But as temperature changes, the voltage drop along the common line changes, which causes a sense error. The voltage drop along the line from one end to the other end follows geometrically as described earlier. That is depending on position along the common line, the cells experience different amounts of common line voltage changes, which cause different voltage readout shifts due to different voltage amounts being coupled into the cells. This cannot be corrected by a conventional reference system.

P-0245[0245]FIG. 16 shows a positional linear reference system that corrects this error. Assuming the voltage drop along a line is linear and assuming an acceptable voltage shift is DVREF/2, by dividing the voltage drop DVTOTAL <b>859</b>=VBEG <b>855</b>-VEND <b>856</b>, into different voltage segments with equal voltage drop DVREF <b>858</b> and by positioning the reference cells <b>857</b> in the middle of a divided array segment (ARYVSUB<b>1</b>-<b>3</b>) <b>888</b>A-C corresponding to a voltage segment, the maximum voltage difference from a reference cell to a data cell in the beginning or at the end of the voltage segment is=&lt;DVREF/2. Hence reference correction over temperature is achieved. It is possible to place the reference cells <b>857</b> at the beginning or the end of a divided array segment (ARYVSUB<b>1</b>-<b>3</b>) <b>888</b>A-C. In this case the maximum voltage difference from a reference cell to a data cell is DVREF instead of DVREF/2 as in the case of positioning the reference array in middle of a divided segment array. Another advantage of placing the reference cells in the middle of a divided array segment is to minimize the electrical variation due to the edge interface from the memory array to peripheral circuits.

P-0246[0246]FIG. 17 shows a positional reference geometric system basing on the concepts similar to FIG. 16. In this embodiment, the reference cells <b>857</b> are not symmetrically but geometrically positioned to correct for the geometric effect of the voltage drop.

P-0247[0247] In FIGS. 16 and 17, each full array is divided into three sub-arrays (ARYVSUB<b>1</b>-<b>3</b>) <b>888</b>A-C and (ARYVSUB<b>4</b>-<b>6</b>) <b>888</b>D-F respectively. It should be noted that the array could be divided into as many sub-arrays as needed to reduce the voltage error. Also shown in FIGS. 16 and 17, each sub-array of ARYVSUB<b>1</b>-<b>6</b><b>888</b>A-F includes its own complete set of reference cells in the middle. A complete set of reference cells provides all the reference levels, e.g., 16 levels for 4-bit digital multilevel cell per page, for all the pages. One row of reference cells includes 128 reference cells if each row has 8 pages and each reference cell provides one reference level. An alternative embodiment is to have more than one reference cell per level, e.g., 4-16 cells per level. This averages out the electrical variation of multiple cells.

P-0248[0248]FIG. 18 shows a geometric compensation reference system. The objective is to simulate the voltage drop in the common line into the reference readout voltage by attaching similar loading currents to the reference readout voltage. A resistance R <b>862</b> in the reference line is made equivalent to a resistance R <b>866</b> in the common line. A reference loading current (ICELLR) <b>868</b>R is made the same as that of ICELL <b>868</b>. Hence the total voltage drop in reference DVREFTOTAL <b>863</b>,=REFB <b>860</b>-REFE <b>861</b>, is equal to DVCLTOTAL <b>867</b>,=VCLB <b>864</b>-VCLE <b>865</b>. It is not necessary to attach the same number of loading reference currents ICELLR <b>868</b>R to the number of ICELL <b>868</b>. It is only necessary to attach the approximate amount of the current loading at appropriate positions to minimize the error to an acceptable level.

P-0249[0249] One alternative embodiment of the reference system is, instead of using 16 reference cells for a <b>4</b> -bit digital multilevel cell, to use 2 or 4 or 8 reference cells to generate <b>16</b> reference levels with level interpolation. That is from reference levels coming from reference cells, the other reference levels are interpolated by using linear or any other interpolation.

P-0250[0250] Multilevel Algorithm:

P-0251[0251]FIG. 19A shows various voltages generated and used in one embodiment of the invention for program verifying, program upper and lower margin verifying, read sensing and restore high or restore low margin verifying during read sensing. The read sensing is advantageously performed in the voltage-mode but other modes of read sensing are also applicable. All the voltages are generated by the V&amp;IREF block <b>172</b>. VREFR(L) is the program verify voltage used to verify program level (L) of a reference cell. VREFD(L) is the program verify voltage used to verify program level (L) of a data cell. For example, in a 4 bit per cell storage embodiment there are 16 levels used. It is also possible to use 15 levels instead of <b>16</b> levels since the extreme low or high levels not need to be constrained to exact low or high levels but can go to ground or power supply respectively. VREFR<b>0</b> through VREFR<b>15</b> are program verify voltages used for verifying programming of the reference cells. VREFD<b>0</b> through VREFD <b>15</b> are program verify voltages used for verifying programming of the data cells. VUM(L) and VLM(L) are upper and lower program margin voltages respectively for level L. Each level L may have its own VUM(L) and VLM(L) voltage values. VUM(L) and VLM(L) can each be of different value also for each level L. On the other hand, VUM(L) and VLM(L) can be of the same voltage value for all the levels. VUM(L) and VLM(L) voltages are generated by the block V&amp;IREF <b>172</b>. VRSTH(L) and VRSTL(L) are RESTORE HIGH and RESTORE LOW margin voltages respectively for level L. Each level L may have its own VRSTH(L) and VRSTL(L) voltage value. VRSTH(L) and VRSTL(L) can each be of different value also for each level L. On the other hand, VRSTH(L) and VRSTL(L) can be of the same voltage value for all the levels. VRSTH(L) and VRSTL(L) voltages are generated by the V&amp;IREF <b>172</b> block. VCELLR(L) is the voltage read back from a reference cell during read sensing. VCELLD(L) is the voltage read back from a data cell during read sensing. The cross-hatched regions show the distribution of possible read back voltages during read sensing after reference cells or data cells have been programmed to a certain level L, while using VREFR(L) or VREFD(L) as the program verify voltage, respectively. The distributions occur because every cell does not have the same programming or read sensing characteristics.

P-0252[0252] Page Programming Cycle:

P-0253[0253]FIG. 20 shows the flow diagram for one embodiment of the page programming cycle. During a page programming cycle a plurality of memory cells are programmed in parallel. However this algorithm is equally applicable for single cell programming. As an example, 4 bit per cell is programmed in each cell. First the program command is issued and the address of the page to be programmed is loaded. The data count NC is initialized. The address loading may be performed through a single or a plurality of address cycles. Program data is input during the DATAIN step and is selectively loaded in the internal latches of a YDRVS <b>110</b>S or SYDRVS <b>114</b>S or RYDRV <b>112</b>S. Block YDRV <b>110</b>, SYDRV <b>114</b>, (RYDRV) <b>112</b> includes a plurality of YDRVS <b>110</b>S, SYDRVS <b>114</b>S, RYDRVS <b>112</b>S respectively. Block YDRVS <b>110</b>S will be described in detail later in the description associated with FIG. 26. Data gets loaded into the data latches of the current YDRVS <b>110</b>S or SYDRVS <b>114</b>S selected from the ADDRCTR <b>162</b> and the BYTEDEC <b>152</b>. The redundancy control block REDCNTRL <b>186</b> asserts RED_ADD₁₃TRUE true (YES or Y) or false (NO or N) to signify whether the current YDRVS <b>110</b>S or SYDRVS <b>114</b>S is GOOD or BAD. A YDRVS <b>110</b>S or SYDRVS <b>114</b>S is GOOD if it has not been flagged as one that cannot be used to load input data on its data latches. A YDRVS <b>10</b>S or SYDRVS <b>114</b>S is BAD if it has been flagged as one that cannot be used to load input data on its data latches. GOOD or BAD YDRVSs or SYDRVSs are flagged during manufacturing testing and the flags are internally stored on non-volatile latches. If RED_ADD_TRUE=NO, meaning current YDRVS <b>110</b> S or SYDRVS <b>114</b> S is GOOD, then a data nibble on the IO[<b>0</b>:<b>3</b>] or IO[<b>4</b>:<b>7</b>] bus is placed at the input of the data latches of the current YDRVS <b>110</b> S or SYDRVS <b>114</b> S. A data byte consists of 8 digital bits and a data nibble consists of 4 digital bits. If RED_ADD_TRUE=Y, meaning current YDRVS <b>110</b>S or SYDRVS <b>114</b>S is BAD, then the data nibble on the IO[<b>0</b>:<b>3</b> ] or IO[<b>4</b>:<b>7</b> ] bus is placed at the data latches of the selected RYDRVS <b>112</b>S. Next, if NEXTDATAIN=Y, the data at the input of the data latches of the respective YDRVS <b>110</b>S, SYDRVS <b>114</b>S or RDYRVS <b>112</b>S is latched. If NEXTDATAIN=N then the flow waits for the program start command PRG. Next, if the data count NC>MAXNC=not true (N), then NC=NC+1 and the flow loops back to DATAIN step to load in the next data byte. If the data count NC>MAXNC true (Y), then the flow goes out of the loop and waits for the program start command PRG. The data count MAXNC signifies the number of data bytes that are simultaneously programmed in a page. Next, if command PRG is received then page programming begins. If command PRG is not received then the flow loops back to check for NEXTDATAIN. No data loading is required for blocks (REFYDRVS) <b>116</b>S because their latches are internally set. A block (REFDRV) <b>116</b> includes a plurality of blocks (REFYDRVS) <b>116</b>S.

P-0254[0254]FIG. 21 shows the flow diagram after page programming begins. The Program flag=Pass is set and the BUSY signal is set. In another embodiment a configuration (fuse) bit initialization is executed to load in data from fuse non-volatile memory cells to volatile latches located in the fuse circuit block (FUSECKT) <b>182</b> at this step. The program inhibit mode of all cells in the page being programmed are reset to enable programming. Based on the output B[<b>0</b>:<b>3</b>] of the data latches of each YDRVS <b>110</b>S, SYDRVS <b>114</b>S or RYDRVS <b>112</b>S a program verify voltage VREFD(L) is set at the input of the comparator in each of the respective YDRVS <b>110</b>S, SYDRVS <b>114</b>S or RYDRVS <b>112</b>S. Based on the output B[<b>0</b>:<b>3</b>] of the data latches of each REFYDRVS <b>116</b>S a program verify voltage VREFR(L) is set at the input of the comparator in each REFYDRVS <b>116</b>S. For each reference cell and data cell in the page being programmed, the cell voltage VCELLD(L) or VCELLR(L) is read. Depending on the output B[<b>0</b>:<b>3</b>] of the data latches (a) for each REFYDRVS <b>116</b>S the appropriate program verify voltage VREFR(L) is compared to the reference cell read back voltage VCELLR(L) and (b) for each YDRVS <b>110</b>S, SYDRVS <b>114</b>S, RYDRVS <b>112</b>S, the appropriate program verify voltage VREFD(L) is compared with data cell read back voltage VCELLD(L) to indicate whether further programming is required. If no further programming is required for a particular reference cell or data cell, it is put in the program inhibit mode. If the Program Pulse Count=MAXPC is not true, then the cells are placed in the program mode and another programming pulse is applied to all the cells in the page, including the reference cells. Cells which are in the program inhibit mode do not get any additional programming. Cells which are not in the program inhibit mode get additional programming. After the programming pulse is applied, the program pulse count is incremented and the cells are placed in the voltage-mode read to verify if further programming is required. This iterative verify-program loop is continued until either all the cells in the page including the reference cells are in the program inhibit mode or when the program pulse count=MAXPC is true. If program pulse count=MAXPC true condition is reached, before all cells in the page including the reference cells are all in program inhibit mode, then the program flag=fail condition is set, BUSY signal is reset and the programming cycle is done. Whenever the All Cells in Program Inhibit Mode=true condition is reached, the flow moves to the next step as shown in FIG. 22A.

P-0255[0255] As shown in FIG. 22A, next, for each level L, upper program margin verify voltage UMV(L)=VCELLR(L)-VUM(L) is generated, where VUM(L) is the upper margin voltage for level L. Depending on the data latch output B[<b>0</b>:<b>3</b> ] of the data latches in the respective YDRVS <b>110</b>S, SYDRVS <b>114</b>S, RYDRVS <b>112</b>S the appropriate voltage UMV(L) is compared with read back cell voltage VCELLD(L) for all the data cells. If the result of comparison indicates that all upper cell margins are not within limits then a program flag=fail condition is set; BUSY signal is reset and programming cycle is done. If the result of comparison indicates that all the upper cell margins are within limits then a program flag=fail condition is not set and then, for each level L, lower program margin verify voltage LMV(L)=VCELLR(L-<b>1</b>)+VLM(L) is generated, where VLM(L) is the lower margin voltage for level L. Depending on the data latch output B[<b>0</b>:<b>3</b>] of the data latches in the respective YDRVS <b>110</b>S, SYDRVS <b>114</b>S, RYDRVS <b>112</b>S the appropriate voltage LMV(L) is compared with read back cell voltage VCELLD(L). If the result of comparison indicates that all lower cell margins are not within limits then a program flag=fail condition is set; BUSY signal is reset and programming cycle is done. If the result of comparison indicates that all the lower cell margins are within limits then a program flag=fail condition is not set and BUSY signal is reset and programming cycle is done. The program flag=fail indicates the programming cycle has been unsuccessful to program the current page. It does not indicate specifically which cell or cells caused the unsuccessful programming.

P-0256[0256] Page Read Cycle:

P-0257[0257]FIG. 23 shows the flow diagram for the page read cycle. During a page read cycle a plurality of memory cells are read in parallel. However this algorithm is equally applicable for single cell read. After the page read command is issued along with the address of the page to be read, the BUSY signal is set, RESTOREL and RESTOREH flags are reset, the data latches in the YDRVS <b>110</b>S, SYDRVS <b>114</b>S, RYDRVS <b>112</b>S are set to output B[<b>0</b>:<b>3</b>]=1111 and N is set to 3. N represents the number of bits stored per memory cell. In another embodiment a configuration (fuse) bit initialization is executed to load in data from fuse non-volatile memory cells to volatile latches located in the fuse circuit block (FUSECKT) <b>182</b> at this step. All the cells in the addressed page are placed in the voltage-mode read and the cell voltages, VCELLR(L) for reference cells and VCELLD(L) for data cells are read. BN is forced to “0” and the read verify voltage VCELLR(L), which is one of the reference read back voltages dependent on B<b>3</b>, B<b>2</b>, B<b>1</b>, B<b>0</b>, is compared with the cell read back voltage VCELLD(L). For each cell, if the VCELLD(L)>VCELLR(L) then BN is latched as “1”, otherwise BN is latched as “0”. The loop continues until all the bits B<b>3</b>, B<b>2</b>, BE<b>1</b>, B<b>0</b> are latched and N=0. Next, as shown in FIG. 24, for each level L, a MARGIN RESTORE LOW Voltage VRSTRL(L)=VCELLR(L)-VRSTL(L) is generated, where VRSTL(L) is the restore low margin voltage. Depending on the latched bits B<b>3</b>, B<b>2</b>, B<b>1</b>, B<b>0</b> on each of the YDRVS <b>110</b>S, SYDRVS <b>114</b>S, RYDRVS <b>112</b>S, the voltage VRSTRL(L) is compared with the respective data cell read back voltage VCELLD(L). If VCELLD(L)>VRSTRL(L) for any one of the cells, then the RESTOREL flag is set. Next, for each level L a MARGIN RESTORE HIGH Voltage VRSTRH(L)=VCELLR(L-1)+VRSTH(L) is generated, where VRSTH(L) is the restore high margin voltage. Depending on the latched bits B<b>3</b>, B<b>2</b>, B<b>1</b>, B<b>0</b> on each of the YDRVS <b>110</b>S, SYDRVS <b>114</b>S, RYDRVS <b>112</b>S, the voltage VRSTRH(L) is compared with the respective data cell read back voltage VCELLD(L). If VCELLD(L)<VRSTRH(L) for any one of the cells, then the RESTOREH flag is set, otherwise RESTOREH flag is not set. Next, as shown in FIG. 25, BUSY signal is reset and the byte count ND is initialized to NDI. NDI is the byte count of the existing byte address location. All bits in the respective YDRVSs, SYDRVSs, or RYDRVSs data latches are ready to be sequentially read. Whenever READ CLOCK=Y, the RED_ADD_TRUE is checked for that byte address location. If RED_ADD_TRUE=Y, then data from RYDRVS <b>112</b>S is output to the IO port IO[<b>0</b>:<b>7</b>] <b>1001</b>, otherwise data from YDRVS <b>110</b>S is output to the io port IO[<b>0</b>:<b>7</b>] <b>1001</b>. If READ CLOCK=N and ENABLE=Y then the flow loops back until READ CLOCK=Y or ENABLE=N. After all the data is output i.e. ND>MAXND=Y or if ENABLE=N, the Page read cycle is done. If ND>MAXND is=N, then ND is incremented and the flow loops back to check the READ CLOCK.

P-0258[0258]FIG. 26 shows the details of an embodiment of YDRVS <b>110</b>S. SYDRVS <b>114</b>S and RYDRVS <b>112</b> S have similar details. The description given for YDRVS <b>110</b>S is equally applicable for SYDRVS <b>114</b>S and RYDRVS <b>112</b>S. In this embodiment 4 bits are stored per memory cell, hence four data latches are required per YDRVS <b>110</b>S. A set of four data latches (DATALAT<b>3</b>) <b>10</b>, (DATALAT<b>2</b>) <b>11</b>, (DATALAT<b>1</b>) <b>12</b>, (DATALAT<b>0</b>) <b>13</b> holds the data during the DATAIN step of a page programming cycle or holds the data during a LATCH EN=<b>1</b> or=O step during a page read cycle. Data is loaded into DATALAT<b>3</b><b>10</b>, DATALAT<b>2</b><b>11</b>, DATALAT<b>1</b><b>12</b>, DATALAT<b>0</b><b>13</b> through the DIN<b>3</b><b>14</b>, DIN<b>2</b><b>15</b>, DIN<b>1</b><b>16</b>, DIN<b>0</b><b>17</b> lines respectively and read out from the DATALAT<b>3</b><b>10</b>, DATALAT<b>2</b><b>11</b>, DATALAT<b>1</b><b>12</b>, DATALAT<b>0</b><b>13</b> through the DOUT<b>3</b><b>18</b>, DOUT<b>2</b><b>19</b>, DOUT<b>1</b><b>20</b>, DOUT<b>0</b><b>21</b> lines respectively. Lines (DIN<b>3</b>) <b>14</b>, (DIN<b>2</b>) <b>15</b>, (DIN<b>1</b>) <b>16</b>, (DIN<b>0</b>) <b>17</b>, (DOUT<b>3</b>) <b>18</b>, (DOUT<b>2</b>) <b>19</b>, (DOUT<b>1</b>) <b>20</b>, (DOUT<b>0</b>) <b>21</b> connect to BYTESEL <b>140</b> for YDRV <b>110</b> and connect to blocks <b>144</b>, <b>142</b> for SYDRV <b>114</b>, RDYRV <b>112</b> respectively. During page program cycle, lines (B<b>3</b>) <b>22</b>, (B<b>2</b>) <b>23</b>, (B<b>1</b>) <b>24</b>, (B<b>0</b>) <b>25</b> are outputs of DATALAT<b>3</b><b>10</b>, DATALAT<b>2</b><b>11</b>, DATALAT<b>1</b><b>12</b>, DATALAT<b>0</b><b>13</b>, respectively, and have a latched logical relationship to the lines (DIN<b>3</b>) <b>14</b>, (DIN<b>2</b>) <b>15</b>, (DIN<b>1</b>) <b>16</b>, (DIN<b>0</b>) <b>17</b>, respectively. During page read cycle lines B<b>3</b><b>22</b>, B<b>2</b><b>23</b>, B<b>1</b><b>24</b>, B<b>0</b><b>25</b> are output of DATALAT<b>3</b><b>10</b>, DATALAT<b>2</b><b>11</b>, DATALAT<b>1</b><b>12</b>, DATALAT<b>0</b><b>13</b> respectively and represent the 4 bits read out of the cell. Depending on the status of lines (B<b>3</b>) <b>22</b>, (B<b>2</b>) <b>23</b>, (B<b>1</b>) <b>24</b>, and (B<b>0</b>) <b>25</b>, the REFERENCE MULTIPLEXER <b>26</b> couples one of the lines VR<b>0</b> through VR<b>15</b> to one input of the VOLTAGE COMPARATOR <b>27</b>. The output of the VOLTAGE COMPARATOR <b>27</b> connects to the input of the LATCH <b>28</b>. Under the control of ALGOCNTRL <b>164</b>, the line ENLATCOMP <b>29</b> functions as a strobe signal to enable the LATCH <b>28</b> during a certain time to latch the output of the VOLTAGE COMPARATOR <b>27</b>. Line RBYLATCOMP <b>30</b> resets the LATCH <b>28</b> at suitable times under the control of ALGOCNTRL <b>164</b>. The PROGRAM/READ CONTROL <b>31</b> outputs lines COMPOR <b>32</b> and COMPORB <b>33</b>. COMPOR <b>32</b> and COMPORB <b>33</b> lines are connected together in a wire-OR manner for all YDRV <b>110</b>, SYDRV <b>114</b>, and RYDRV <b>112</b>. The PROGRAM/PROGRAM INHIBIT SWITCH <b>34</b> puts the memory cell coupled to it indirectly through line BLIN <b>35</b> into a program or program inhibit mode under the control of PROGRAM/READ CONTROL <b>31</b>. Line BLIN <b>35</b> goes to the PSEL <b>120</b> for YDRV <b>110</b> and to blocks <b>124</b>, <b>122</b> for SYDRV <b>114</b>, RYDRV <b>112</b> respectively. The lines VR<b>0</b> through VR<b>15</b> individually are coupled to the output of a VRBUFFER <b>750</b>.

P-0259[0259]FIG. 27 shows the details of a LATCH <b>28</b> block, a PROGRAM/READ CONTROL <b>31</b> block and a PROGRAM/PROGRAM INHIBIT <b>34</b> block. The VROUT line <b>55</b> couples the output of REFERENCE MULTIPLEXER <b>26</b> to the positive input of a VOLTAGE COMPARATOR <b>27</b>. The line COMPOUT <b>58</b> couples the output of the VOLTAGE COMPARATOR <b>27</b> to the D input of a latch <b>59</b>. ENLATCOMP <b>29</b> goes to the EN input of the latch <b>59</b>. ENLATCOMP <b>29</b> acts as a strobe signal for the latch. When ENLATCOMP <b>29</b> is at logic high the latch <b>59</b> outputs the logic level on D input to the Q output. QB is the inverted logic level of Q. When ENLATCOMP <b>29</b> goes to logic low, the latch <b>59</b> latches the logic level on D input. RBYLATCOMP <b>30</b> goes to the reset R input of the latch <b>59</b>. When RBYLATCOMP <b>30</b> is logic low latch <b>59</b> is reset, whereby Q is at logic low and QB is at logic high. Line COMLATQ <b>40</b> couples the Q output of the latch <b>59</b> to the gate of a NMOS transistor N<b>1</b><b>43</b>. Line COMLATQB <b>41</b> couples the QB output of the latch <b>59</b> to the gate of a NMOS transistor N<b>2</b><b>44</b>. Line COMLATQ <b>40</b> also couples to the data latches DATALAT<b>3</b><b>10</b>, DATALAT<b>2</b><b>11</b>, DATALAT<b>1</b><b>12</b>, DATALAT<b>0</b><b>13</b>. COMLATQ <b>40</b> also couples to one input of a 2 input NAND gate NAND <b>49</b>. The other input of the NAND <b>49</b> is coupled to the signal READ<b>2</b>B. READ<b>2</b>B is at logic high during page programming cycle and at logic low during page read cycle. The line NDO <b>52</b> couples the output of NAND <b>49</b> to the input of an inverter INV <b>48</b> and also to the gate inputs of PMOS transistor P<b>1</b><b>45</b> and NMOS transistor N<b>3</b><b>47</b>. The line INVO <b>53</b> couples the output of INV <b>48</b> to the gate of a PMOS transistor P <b>2</b><b>46</b>. Line BLIN <b>35</b> connects to one terminal of each of P<b>1</b><b>45</b>, N<b>3</b><b>47</b> and P<b>2</b><b>46</b>. BLIN <b>35</b> also connects to the negative input of VOLTAGE COMPARATOR <b>27</b>. The other terminal of P<b>1</b><b>45</b> is connected to inhibit voltage input VIH <b>57</b>. Line N<b>4</b>D <b>54</b> connects the other terminals of N<b>3</b><b>47</b> and P<b>2</b><b>46</b> to one terminal of NMOS transistor N<b>4</b><b>50</b>. Line N<b>5</b>D <b>60</b> connects the other terminal of N<b>4</b><b>50</b> to one terminal of NMOS transistor N<b>5</b><b>51</b>. The other terminal of N<b>5</b><b>51</b> is connected to ground. The gates of N<b>4</b><b>50</b> and N<b>5</b><b>51</b> are connected to inputs VBIYDRVCAS <b>56</b> and VBIYDRV <b>57</b> respectively. N<b>4</b><b>50</b> and N<b>5</b><b>51</b> form a current bias circuit whereby a constant current load is placed on the BLIN <b>35</b> when INVO <b>53</b> is at logic low and NDO <b>52</b> is at logic high. N<b>4</b><b>50</b> and N<b>5</b><b>51</b> together represent the predetermined bias current for the voltage mode sensing as shown in FIG. 2C.

P-0260[0260] After the page program command and the address of the page to be program is issued, the data to be programmed is loaded in the data latches DATALAT<b>3</b><b>10</b>, DATALAT <b>2</b><b>11</b>, DATALAT<b>1</b><b>12</b>, DATALAT<b>0</b><b>13</b> of each of the YDRVS <b>110</b>S, SYDRVS <b>114</b>S or RYDRVS <b>112</b>S. The REFERENCE MULTIPLEXER <b>26</b> then couples one of the inputs VR<b>0</b> through VR<b>15</b> to its output VROUT<b>55</b>. During a program verify cycle VREFD(<b>0</b>) through VREFD(<b>15</b>) are available on the VR<b>0</b> through VR<b>15</b> lines respectively. VR<b>0</b> through VR<b>15</b> are commonly coupled to REFERENCE MULTIPLEXER <b>26</b> of all the YDRV <b>110</b>, SYDRV <b>112</b>, RYDRV <b>14</b>. The REFYDRVS <b>116</b>S have the data latches internally set. In this embodiment there are 16 REFYDRVS <b>116</b>S. Each REFYDRVS <b>116</b>S is used for a specific level. For example, the data latches of a REFYDRVS <b>116</b>S used for level <b>5</b> will be internally set to program level <b>5</b> into reference cells coupled to it. VRO through VR<b>15</b> are commonly coupled to REFERENCE MULTIPLEXER <b>26</b> of all the REFYDRVS <b>116</b>S. During a program verify cycle, VREFR(<b>0</b>) through VREFR(<b>15</b>) are respectively available at the VR<b>0</b> through VR<b>15</b> lines of a REFYDRVS <b>116</b>S. Depending on the output B<b>3</b>, B<b>2</b>, B<b>1</b>, B<b>0</b> of the data latches DATALAT<b>3</b><b>10</b>, DATALAT<b>2</b><b>11</b>, DATALAT<b>1</b><b>12</b>, DATALATO <b>13</b> within each YDRVS <b>110</b>S, SYDRVS <b>114</b>S, SYDRVS <b>112</b>S one specific voltage VREFD(<b>0</b>) through VREFD(<b>15</b>) is output to the input of the VOLTAGE COMPARATOR <b>27</b>. Depending on the output B<b>3</b>, B<b>2</b>, B<b>1</b>, B<b>0</b> of the data latches DATALAT<b>3</b><b>10</b>, DATALAT<b>2</b><b>11</b>, DATALAT<b>1</b><b>12</b>, DATALAT<b>0</b><b>13</b> within each REFYDRV <b>116</b> one specific voltage VREFR(<b>0</b>) through VREFR(<b>15</b>) is output to the input of the VOLTAGE COMPARATOR <b>27</b>.

P-0261[0261] The latch <b>59</b> within each REFYDRVS <b>116</b>S, YDRVS <b>110</b>S, SYDRVS <b>114</b>S and RYDRVS <b>112</b>S are all reset by pulsing line RBYLATCOMP <b>30</b>. RBYLATCOMP <b>30</b> is commonly connected to the reset input of the latch <b>59</b> within each REFYDRVS <b>116</b>S,YDRVS <b>110</b>S, SYDRVS <b>114</b>S, and RYDRVS <b>112</b>S. After latch <b>59</b> is reset, COMLATQ <b>40</b> is at logic low. The NAND <b>49</b> then outputs logic high to line NDO <b>52</b>. Output of INV <b>48</b> then is at logic low on line INVO <b>53</b>. With NDO <b>52</b> at logic high and INVO <b>53</b> at logic low transistors N <b>3</b><b>47</b> and P <b>246</b> couple BLIN <b>35</b> to N<b>4</b><b>50</b>. P<b>1</b><b>45</b> de-couples the inhibit voltage VIH <b>57</b> from BLIN <b>35</b>. The memory cell is placed in the voltage read mode and the cell read back voltage VCELLR(L) or VCELLD(L) is available on BLIN <b>35</b>. At this point, the VOLTAGE COMPARATOR <b>27</b> compares the voltages at its inputs. If voltage on BLIN <b>35</b> is higher then voltage on VROUT <b>55</b> the output COMPOUT <b>58</b> is low, otherwise it is high. At this time a positive going strobe pulse is applied to the ENLATCOMP <b>29</b> common to all the latches <b>59</b> in REFYDRVS <b>116</b> S, YDRVS <b>110</b>S, SYDRVS <b>114</b>S and RYDRVS <b>112</b>S, to latch the status of line COMPOUT <b>58</b>. If COMPOUT <b>58</b> is low, then the COMLATQ <b>40</b> remains at logic low.

P-0262[0262] If COMPOUT <b>58</b> is high, then the COMLATQ <b>40</b> switches to logic high. If during an iteration of verify-program cycles any one of the latches <b>59</b> latches a logic high on COMLATQ <b>40</b>, called a program inhibit state, then for that specific REFYDRVS <b>116</b>S, YDRVS <b>110</b>S, SYDRVS <b>114</b>S or RYDRVS <b>112</b>S, the line NDO <b>52</b> is at low and the line INVO <b>53</b> is at logic high. With latch <b>59</b> in a program inhibit state, BLIN <b>35</b> is de-coupled from N<b>4</b>D <b>54</b> and there is no current load, whereas, BLIN <b>35</b> is coupled to the inhibit voltage VIH <b>57</b> through P<b>1</b><b>45</b>. With latch <b>59</b> in the program inhibit state, further programming pulses do not cause programming.

P-0263[0263] The line COMPOR <b>32</b> is connected in a wire-OR fashion to all the COMPOR <b>32</b> lines of each REFYDRVS <b>116</b>S, YDRVS <b>110</b>S, SYDRVS <b>114</b>S or RYDRVS <b>112</b>S. There is a pull up load coupling the COMPOR <b>32</b> line to the power supply. Similarly, the line COMPORB <b>33</b> is connected in a wire-OR fashion to all the COMPORB <b>33</b> lines of each REFYDRVS <b>116</b> S, DRVS <b>110</b>S, SYDRVS <b>114</b>S or RYDRVS <b>112</b>S. There is a pull up load coupling the COMPORB <b>33</b> line to the power supply. The COMPORB line <b>33</b> goes high whenever all the latches <b>59</b> have reached the program inhibit mode. When the Program Pulse Count=MAXPC is reached, the ALGOCNTRL <b>164</b> latches the status of COMPORB line <b>33</b> in a status latch in block INPUT LOGIC <b>160</b>. The status latch can be read at one of the IO[<b>0</b>:<b>7</b>] <b>1001</b> lines by the external host. If ALGOCNTRL <b>164</b> latches a logic low in the status latch in block INPUT LOGIC <b>160</b> then a program fail condition is reached and the ALGOCNTRL <b>164</b> goes out of the page programming cycle.

P-0264[0264] If at the end of any verify-program iteration, the COMPOR <b>32</b> line goes high, the ALGOCNTRL <b>164</b> sequences to the margin verify mode. All latches <b>59</b> are reset. All cells are placed in the voltage read mode by READB <b>52</b> at logic low. At this time inhibit voltage is de- coupled from BLIN <b>35</b> and current bias transistor N<b>4</b><b>50</b> is coupled to BLIN <b>35</b>. Cell voltages VCELLR(L) or VCELLD(L) are respectively available on BLIN <b>35</b> of a REFYDRVS <b>116</b>S or BLIN <b>35</b> of YDRVS <b>110</b>S, SYDRVS <b>114</b>S, or RYDRVS <b>112</b>S. During program margin verify the voltages read back from the data cells are checked for adequate margin from voltages read back from reference cells for each programmed level L. In the Upper Program Margin Verify mode, voltages UMV(<b>0</b>) through UMV(<b>15</b>) are placed on the VR<b>0</b> through VR(<b>15</b>). Depending on the output B<b>3</b>, B<b>2</b>, B<b>1</b>, B<b>0</b> of the data latches DATALAT<b>3</b><b>10</b>, DATALAT<b>2</b><b>11</b>, DATALAT<b>1</b><b>12</b>, DATALATO <b>13</b> within each YDRVS <b>110</b>S, SYDRVS <b>114</b>S, RYDRVS <b>112</b>S one specific voltage UMV(O) through UMV(<b>15</b>) is output to the input VROUT <b>55</b> of the VOLTAGE COMPARATOR <b>27</b>. At this time the VOLTAGE COMPARATOR <b>27</b> compares the voltages at its inputs. If voltage on BLIN <b>35</b> is higher then voltage on VROUT <b>55</b> the output COMPOUT <b>58</b> is low, otherwise it is high. At this time a positive going strobe pulse is applied to the ENLATCOMP <b>29</b> common to all the latches <b>59</b> in YDRVS <b>110</b>S, SYDRVS <b>114</b>S and RYDRVS <b>112</b>S, to latch the status of line COMPOUT <b>58</b>. If COMPOUT <b>58</b> is low, then the COMLATQ <b>40</b> remains at logic low. If COMPOUT <b>58</b> is high, then the COMLATQ <b>40</b> switches to logic high. At this time, if LGOCNTRL <b>164</b> latches a logic low in the status latch in INPUT LOGIC <b>160</b> block by looking at the status of the COMPORB <b>33</b> line, then a program fail condition is reached and the ALGOCNTRL <b>164</b> goes out of the page programming cycle. Otherwise, ALGOCNTRL <b>164</b> sequences to the Lower Program Margin Verify mode.

P-0265[0265] In the Lower Program Margin Verify mode, all latches <b>59</b> are reset. Voltages LMV(<b>0</b>) through LMV(<b>15</b>) are placed on the VR<b>0</b> through VR(<b>15</b>). Depending on the output B<b>3</b>, B<b>2</b>, B<b>1</b>, B<b>0</b> of the data latches (DATALAT <b>3</b>) <b>10</b>, (DATALAT<b>2</b>) <b>11</b>, (DATALAT<b>1</b>) <b>12</b>, (DATALAT<b>0</b>) <b>13</b> within each YDRVS <b>110</b>S, SYDRVS <b>114</b>S, RYDRVS <b>112</b>S one specific voltage LMV(<b>0</b>) through LMV(<b>15</b>) is output to the input VROUT <b>55</b> of the VOLTAGE COMPARATOR <b>27</b>. At this time the VOLTAGE COMPARATOR <b>27</b> compares the voltages at its inputs. If voltage on BLIN <b>55</b> is higher then voltage on VROUT <b>55</b> the output COMPOUT <b>58</b> is low, otherwise is high. At this time a positive going strobe pulse is applied to the ENLATCOMP <b>29</b> common to all the latches <b>59</b> in YDRVS <b>110</b>S, SYDRVS <b>114</b>S and RYDRVS <b>112</b>S, to latch the status on line COMPOUT <b>58</b>. If COMPOUT <b>58</b> is low, then the COMLATQ <b>40</b> remains at logic low. If COMPOUT <b>58</b> is high, then the COMLATQ <b>40</b> switches to logic high. At this time, if ALGOCNTRL <b>164</b> latches a logic low in the status latch in INPUT LOGIC <b>160</b> block by looking at the status of the COMPOR line <b>32</b>, then a program fail condition is reached and the ALGOCNTRL <b>164</b> goes out of the page programming cycle.

P-0266[0266] During page read cycle, after page read command and the page address is issued, the reference and the data cells are placed in the voltage read mode. At this time all the B<b>3</b> [<b>0</b>:<b>3</b>] lines output <b>1111</b>. VR<b>0</b> through VR<b>15</b> have VCELLR(<b>0</b>) through VCELLR(<b>15</b>). VCELLR(<b>0</b>) through VCELLR(<b>15</b>) are the voltages read out of the reference cells of the page being read. Under the control of the ALGOCNTRL <b>164</b> block 4 bits are sequentially read into the data latches (DATALAT<b>3</b>) <b>10</b>, (DATALAT<b>2</b>) <b>11</b>, (DATALAT<b>1</b>) <b>12</b>, (DATALAT<b>0</b>) <b>13</b>. For example, B <b>3</b> is read by forcing the output of DATALAT<b>3</b> to output B<b>3</b>=<b>0</b>. At this time B[<b>0</b>:<b>3</b>]=1110. The REFERENCE MULTIPLEXER <b>26</b> then outputs VCELLR(<b>7</b>) on the VROUT <b>55</b> in each of the YDRVS <b>110</b>S, SYDRVS <b>114</b>S and RYDRVS <b>112</b>S. The output COMPOUT <b>58</b> of the VOLTAGE COMPARATOR <b>27</b> is high or low depending on whether voltage VCELLD(L) on the BLIN <b>35</b> is lower or higher relative to voltage VCELLR(<b>7</b>) on line VROUT <b>55</b>. If COMPOUT <b>58</b> is high then a logic high is latched into DATALAT<b>3</b><b>10</b> and B<b>3</b>=0, otherwise logic low is latched and B<b>3</b>=1. Next, B<b>2</b> is read by forcing the output of DATALAT<b>2</b><b>11</b> to output B<b>2</b>=0. At this time B[<b>0</b>:<b>3</b>]=<b>110</b>B<b>3</b>. B<b>3</b> is the output of DATALAT<b>3</b><b>10</b> from previous sequence. The REFERENCE MULTIPLEXER <b>26</b> then outputs VCELLR(L), depending on <b>110</b>B<b>3</b> on the VROUT <b>55</b> line in each of the YDRVS <b>110</b>S, SYDRVS <b>114</b>S and RYDRVS <b>112</b>S. The output COMPOUT <b>58</b> of the VOLTAGE COMPARATOR <b>27</b> is high or low depending on whether voltage VCELLD(L) on the BLIN <b>35</b> is lower or higher relative to voltage VRCELL(L) on line VROUT <b>55</b>. If COMPOUT <b>58</b> is high then a logic high is latched into DATALAT<b>2</b><b>11</b> and B<b>2</b>=0, otherwise logic low is latched and B<b>2</b>=1. In this manner, the next two sequences latch two bits into the DATALAT<b>1</b><b>12</b> and DATALAT<b>0</b><b>13</b>.

P-0267[0267] After all 4 bit from the cell are latched into the DATALAT<b>3</b><b>10</b>, DATALAT<b>2</b><b>11</b>, DATALAT <b>1</b><b>12</b>, DATALATO <b>13</b> for all the YDRVS <b>110</b>S, SYDRVS <b>114</b>S and RYDRVS <b>112</b>S, the restore margins are checked. All latches <b>59</b> are reset. First the RESTORE LOW margin is checked. At this time, for each level <b>0</b> through <b>15</b>, MARGIN RESTORE LOW Voltage VRSTRL(<b>0</b>) through VRSTRL(<b>15</b>) is placed at the VRO through VR<b>15</b> lines respectively. Depending on each outputs B<b>3</b>, B<b>2</b>, B<b>1</b>, B<b>0</b> of the data latches DATALAT<b>3</b><b>10</b>, DATALAT<b>2</b><b>11</b>, DATALAT<b>1</b><b>12</b>, DATALAT<b>0</b><b>13</b> within each YDRVS <b>110</b>S, SYDRVS <b>114</b>S and RYDRVS <b>112</b>S, the REFERENCE MULTIPLEXER <b>26</b> outputs one of VRSTRL(<b>0</b>) through VRSTRL(<b>15</b>) on line VROUT <b>55</b> going into the positive input of the VOLTAGE COMPARATOR <b>27</b>. ENLATCOMP <b>29</b> is strobed with the positive pulse to latch the status of the COMPOUT <b>58</b> line. If data cell read out voltage VCELLD(L) on BLIN <b>35</b> line is higher than voltage VRSTRL(L) on VROUT <b>55</b> line then COMLATQ <b>40</b> remains at logic low and COMLATQB <b>41</b> at logic high. Otherwise, COMLAT <b>40</b> is at logic high and COMLATQB <b>41</b> at logic low. At this time, if ALGOCNTRL <b>164</b> latches a logic low in the RESTORE LOW latch in INPUT LOGIC <b>160</b> block by looking at the status of the COMPORB line <b>33</b>, then a restore low flag condition is reached. Next, all latches <b>59</b> are reset.

P-0268[0268] Next the RESTORE HIGH margin is checked. At this time, for each level <b>0</b> through <b>15</b>, MARGIN RESTORE HIGH Voltage VRSTRH(<b>0</b>) through VRSTRH(<b>15</b>) is placed at the VR<b>0</b> through VR <b>15</b> lines respectively. Depending on each outputs B<b>3</b>, B<b>2</b>, B<b>1</b>, B<b>0</b> of the data latches DATALAT<b>3</b><b>10</b>, DATALAT<b>2</b><b>11</b>, DATALAT<b>1</b><b>12</b>, DATALAT<b>0</b><b>13</b> within each YDRVS <b>110</b>S, SYDRVS <b>114</b>S and RYDRVS <b>112</b>S, the REFERENCE MULTIPLEXER <b>26</b> outputs one of VRSTRH(<b>0</b>) through VRSTRH(<b>15</b>) on line VROUT <b>55</b> going into the positive input of the VOLTAGE COMPARATOR <b>27</b>. ENLATCOMP <b>29</b> is strobed with the positive pulse to latch the status of the COMPOUT <b>58</b> line. If data cell read out voltage VCELLD(L) on BLIN <b>35</b> line is higher than voltage VRSTRH(L) on VROUT <b>55</b> line then COMLATQ <b>40</b> remains at logic low and COMLATQB <b>41</b> at logic high. Otherwise, COMLAT <b>40</b> is at logic high and COMLATQB <b>41</b> at logic low. At this time, if ALGOCNTRL <b>164</b> latches a logic low in the RESTORE HIGH latch in INPUT LOGIC <b>160</b> block by looking at the status of the COMPOR line <b>32</b>, then a restore high flag condition is reached.

P-0269[0269] At this time, 4 bits from every cell with the page being read are latched into the respective data latches within each YDRVS <b>110</b>S, SYDRVS <b>114</b>S and RYDRVS <b>112</b>S. Next under the control of the READ CLOCK data is sequentially read on IO[<b>0</b>:<b>7</b>]. If after READ CLOCK the RED_ADD_TRUE=Y condition is true then the data is read from the addressed RYDRVS <b>112</b>S otherwise data is read from the addressed YDRVS <b>110</b>S or SYDRVS <b>114</b>S.

P-0270[0270]FIG. 19B shows various voltages generated and used in another embodiment of the current invention for program verifying, program margin verifying, read sensing and restore high or low margin verifying. In this embodiment the program margin verify voltage VREFR(L)-VRM(L) and VREFD(L)-DM(L) for a level L of a reference cell and a data cell respectively, are generated by the block V&amp;IREF <b>172</b> independent of the voltages VCEF LR(L) and VCELLD(L) programmed into the reference cell and data cell respectively. The voltage VRM(L) for a level L of the reference cells can be unique for each level or the same for all levels. The voltage VDM(L) for a level L of the data cells can be unique for each level or the same for all levels.

P-0271[0271]FIG. 22B shows the portion of the flow for the page programming cycle that uses the voltages as shown in FIG. 19B. In the flow shown in FIG. 22B, only one program margin verify comparison is made instead of two as shown in FIG. 22A. This has the advantage of reducing the total time for completion of a page programming cycle.

P-0272[0272]FIG. 22C shows an alternative embodiment of the flow shown in FIG. 22B. At the end of the programming, a BSERV operation is done to verify that the read operation is operational versus the data in The BSERV operation is a binary search read verification operation that is substantially the same as described in FIGS. 23 and 24 with the additional step of comparing resulting digital bits BR<<b>3</b>:<b>0</b>> from the binary search with a stored digital bits B<<b>3</b>:<b>0</b>> from loading data in. If the comparison is not true, the program flag is set to indicate program failure. The operation further ensures that all cells are within an operational range, for example not out of range due to programming overshoot to the next levels.

P-0273[0273] The embodiment shown in FIGS. 19B and 22B can be used in combination with the embodiment shown in FIGS. 19A and 22A. As discussed in the multilevel reference system section above, the embodiment shown in FIGS. 19B and 22B can be used when a selected page programs for the first time after block erase. For subsequent page programming cycles on the same page, the embodiment shown in FIGS. 19A and 22A is advantageous since the VCELLR(L) values may shift between initial page programming and subsequent page programming.

P-0274[0274]FIG. 28 is a block diagram illustrating a memory system <b>2800</b> for a multilevel memory.

P-0275[0275] The memory system <b>2800</b> comprises a plurality of memory arrays <b>2801</b> arranged in rows and columns of memory arrays <b>2801</b>. Each memory array <b>2801</b> comprises a plurality of memory subarrays <b>2802</b>, a plurality of local sense amplifiers <b>2804</b>, and a plurality of global sense amplifiers <b>2806</b>. In one embodiment, a local sense amplifier <b>2804</b> is disposed adjacent to a memory subarray <b>2802</b>. In another embodiment, the local sense amplifier <b>2804</b> is shared between a plurality of memory subarrays <b>2802</b>. The local sense amplifier <b>2804</b> reads the contents of the memory cells within the corresponding memory subarray <b>2802</b>. The memory subarrays <b>2802</b> are arranged in rows and columns. The local sense amplifiers <b>2804</b> coupled to a column of memory subarrays <b>2802</b> are coupled to a global sense amplifier <b>2806</b>. The memory cells may include redundant cells, reference cells or spare cells.

P-0276[0276]FIG. 29A is a block diagram illustrating an inverter mode sensing circuit <b>2900</b>.

P-0277[0277] The inverter mode sensing circuit <b>2900</b> comprises a PMOS transistor <b>2902</b>, a plurality of NMOS transistors <b>2904</b> and <b>2906</b>, a feedback circuit <b>2908</b>, a plurality of memory cells <b>2910</b>, and a comparator <b>2912</b>. For clarity, only one memory cell <b>2910</b> and one NMOS transistor <b>2906</b> are shown for a subarray, but the subarray comprises a plurality of memory cells <b>2910</b> arranged in columns. Each column has a corresponding NMOS transistor <b>2906</b> or a plurality of NMOS transistors <b>2906</b> arranged in series. Only one column with one memory cell <b>2910</b> is shown.

P-0278[0278] The comparator <b>2912</b> determines the voltage of the memory cell by comparing the cell voltage (VCELL) <b>2914</b> to a reference voltage (VREF) <b>2916</b> in a manner described above. The PMOS transistor <b>2902</b>, the NMOS transistors <b>2904</b> and <b>2906</b> and the memory cells <b>2910</b> are coupled in series between the supply voltage and ground. The selected memory cell <b>2910</b> is read by applying a control gate reference voltage (VCGRD) <b>2917</b> on the control gate of the memory cell <b>2910</b>. The column of memory cells <b>2910</b> and an associated bit line has a capacitance <b>2918</b> that slows the sensing of the memory cells <b>2910</b>. The NMOS transistor <b>2906</b> functions as a switch to couple the column of memory cells <b>2910</b> to the sensing portion of the circuit. The feedback circuit <b>2908</b> controls biasing of the NMOS transistor <b>2904</b> to stabilize the cell voltage <b>2914</b>. The drain of the diode connected PMOS transistor <b>2902</b> is coupled to the cell voltage <b>2914</b>. Inverter mode sensing may also be referred to as current mode sensing or common source sensing. In another embodiment of current mode sensing, the source line (CL) (as shown coupled to ground) and the bitline are interchanged, and thus the voltage on the source line is coupled to the readout voltage <b>2914</b>. In this case, the array architecture uses only one source line in read at a given time, for example by multiplexing through decoder circuitry or over time. This mode is to be known as Inverse Current Mode sensing.

P-0279[0279]FIG. 29B is a block diagram illustrating a voltage mode sensing circuit <b>2950</b>.

P-0280[0280] The voltage sensing circuit <b>2950</b> is similar to the inverter mode sensing circuit <b>2900</b> except that a current source <b>2952</b> replaces the PMOS transistor <b>2902</b> and is coupled to ground, the memory cell <b>2910</b> is coupled to a reference bias, and the NMOS transistor <b>2904</b> and the feedback circuit <b>2908</b> are omitted. The voltage mode sensing may also be referred to as source follower sensing.

P-0281[0281]FIG. 30 is a block diagram illustrating a wide range, high speed voltage mode sensing circuit <b>3000</b>.

P-0282[0282] The memory array <b>2800</b> includes a plurality of voltage mode sensing circuits <b>3000</b>. The voltage mode sensing circuit <b>3000</b> comprises a PMOS transistor <b>3002</b>, a plurality of NMOS transistors <b>3004</b>, <b>3006</b>, <b>3007</b>, a feedback circuit <b>3008</b>, a plurality of memory cells <b>3010</b>, a current source (IRCELL) <b>3011</b>, and a comparator <b>3012</b>. For clarity, only one memory cell <b>3010</b>, one NMOS transistor <b>3006</b>, and one NMOS transistor <b>3007</b> are shown for a subarray, but the subarray comprises a plurality of memory cells <b>3010</b> arranged in columns. Each colun has a corresponding NMOS transistor <b>3006</b>. Only one column with one memory cell <b>3010</b> is shown. Possible decoding circuitry between the current source <b>3011</b> and the memory cell <b>301</b><b>0</b> and between the current source <b>3011</b> and the NMOS transistor <b>3007</b> is not shown. [<b>0271</b> ] The comparator <b>3012</b> determines the voltage of the memory cell by comparing a cell voltage (VCELL) <b>3014</b> to a reference voltage (VREF) <b>3016</b> in a manner described above. The PMOS transistor <b>3002</b>, the NMOS transistors <b>3004</b>, <b>3006</b> and <b>3007</b> are coupled in series between the supply voltage and ground. The current source <b>3011</b> is coupled between the gate of the NMOS transistor <b>3002</b> and ground. The memory cell <b>3010</b> is coupled between a reference voltage (VCLRD) and the common node formed of the current source <b>3011</b> and the gate of the NMOS transistor <b>3007</b>.

P-0283[0283] The selected memory cell <b>3010</b> is read by applying a control gate reference voltage (VCGRD) <b>3017</b> on the control gate of the memory cell <b>3010</b>. The biasing ofthe gate of the NMOS transistor <b>3007</b> by the current source <b>3011</b> and the memory cell <b>3010</b> controls the voltage on the bit line.

P-0284[0284] The NMOS transistor <b>3006</b> functions as a switch to couple the column of NMOS transistors <b>3007</b> and the associated memory cells <b>3010</b> to the sensing portion of the circuit. The feedback circuit <b>3008</b> controls biasing of the NMOS transistor <b>3004</b> to stabilize the cell voltage <b>3014</b>. The drain of the diode connected PMOS transistor <b>3002</b> is coupled to the cell voltage <b>3014</b>.

P-0285[0285]FIG. 31 is a block diagram illustrating a voltage mode sensing circuit <b>3100</b>.

P-0286[0286] The voltage mode sensing circuit <b>3100</b> comprises a plurality of memory subarrays <b>3150</b>, a plurality of local sense amplifiers <b>3152</b>, and a plurality of global sense amplifiers <b>3154</b>. The local sense amplifier <b>3152</b> includes a local source follower stage. The global sense amplifier <b>3154</b> includes a common source stage.

P-0287[0287] The memory array <b>3150</b> includes columns of memory cells <b>3110</b> coupled to first bitlines <b>3151</b>.

P-0288[0288] Each local sense amplifier <b>3152</b> is coupled to a memory subarray <b>3150</b>. In one embodiment, the local sense amplifier <b>3152</b> is disposed adjacent the memory subarray <b>3150</b>. The local sense amplifier <b>3152</b> includes a selection circuit <b>3153</b> that couples a selected bitline <b>3151</b> to a bitline <b>3155</b>. In one embodiment, the selection circuit <b>3153</b> comprises transistors. The local sense amplifier <b>3152</b> senses the selected memory cell on the bitline <b>3151</b> and provides a voltage to a global sense amplifier <b>3154</b>.

P-0289[0289] The local sense amplifier <b>3152</b> comprises an NMOS transistor <b>3107</b> coupled between the bittine <b>3155</b> and ground, and includes a gate coupled to the bitline <b>3151</b>. A current source <b>3111</b> is coupled between the gate of the NMOS transistor <b>3107</b> and ground.

P-0290[0290] The global sense amplifier <b>3154</b> comprises a comparator <b>3112</b>, a PMOS transistor <b>3102</b> and a selection circuit <b>3158</b>. The selection circuit <b>3158</b> couples the selected one of the bitlines <b>3155</b> to a common node formed of a voltage cell input <b>3114</b> of the comparator <b>3112</b> and the drain of the diode connected PMOS transistor <b>3102</b>. A reference voltage <b>3116</b> is applied to the second input of the comparator <b>3112</b>.

P-0291[0291] The local sense amplifier <b>3152</b> provides a larger voltage range by using optimally low current bias. The global sense amplifier <b>3154</b> includes a common source stage with a PMOS transistor <b>3114</b> as a load, and buffers the column capacitance.

P-0292[0292] The voltage mode sensing circuit <b>3100</b> further comprises a plurality of reference subarrays <b>3170</b>, a plurality of local sense amplifiers <b>3172</b>, and a plurality of global sense amplifiers <b>3174</b>. The reference subarrays <b>3170</b> comprise a plurality of reference cells for storing reference signals. In one embodiment, the reference subarrays <b>3170</b> are similar to the memory subarrays <b>3150</b>. The local sense amplifiers <b>3172</b> read the reference subarrays <b>3170</b>. In one embodiment, the local sense amplifiers <b>3172</b> are similar to the local sense amplifiers <b>3152</b>. The global sense amplifiers <b>3174</b> detect and amplify the voltage from the local sense amplifiers <b>3172</b>.

P-0293[0293] The global sense amplifier <b>3174</b> comprises a comparator <b>3173</b>, a PMOS transistor <b>3176</b> and a selection circuit <b>3178</b>, which are arranged in similar manner as the comparator <b>3112</b>, the PMOS transistor <b>3102</b> and the selection circuit <b>3158</b> of the global sense amplifier <b>3154</b>, except the comparator <b>3173</b> is configured as a buffer. The comparator <b>3173</b> serves as a comparator in sensing the reference cells and serves as a buffer for driving the reference level.

P-0294[0294]FIG. 32 is a block diagram illustrating a voltage mode sensing circuit <b>3200</b>.

P-0295[0295] The voltage mode sensing circuit <b>3200</b> includes like elements as the voltage mode sensing circuit <b>3100</b> (FIG. 31) and are given like reference numbers. The voltage mode sensing circuit <b>3200</b> comprises a memory array <b>3150</b>, a plurality of local sense amplifiers <b>3252</b> and a plurality of global sense amplifiers <b>3254</b>. The local sense amplifier <b>3252</b> includes a local source follower stage and includes a PMOS source follower as part of the global sense amplifier. The global sense amplifier <b>3254</b> includes a source follower stage.

P-0296[0296] Each local sense amplifier <b>3252</b> is coupled to a memory subarray <b>3150</b>. In one embodiment, the local sense amplifier <b>3252</b> is disposed adjacent the memory subarray <b>3150</b>. The local sense amplifier <b>3252</b> includes a selection circuit <b>3253</b> that couples a selected bitline <b>3151</b> to a bitline <b>3255</b>. In one embodiment, the selection circuit <b>3253</b> comprises transistors. The local sense amplifier <b>3252</b> senses the selected memory cell on the bitline <b>3151</b> and provides a voltage to a global sense amplifier <b>3254</b>.

P-0297[0297] The local sense amplifier <b>3252</b> comprises a PMOS transistor <b>3207</b> coupled between the bitline <b>3255</b> and ground, and includes a gate coupled to the bitline <b>3151</b>. A current source <b>3211</b> is coupled between the gate of the PMOS transistor <b>3207</b> and ground. The local sense amplifier <b>3252</b> provides a maximum voltage range by using low current bias.

P-0298[0298] The global sense amplifier <b>3254</b> comprises a comparator <b>3212</b>, a current source <b>3202</b> and a selection circuit <b>3258</b>. The current source <b>3202</b> couples the supply voltage to the cell voltage terminal <b>3214</b> of the comparator <b>3212</b> to ground. The selection circuit <b>3258</b> couples the selected one of the bitlines <b>3255</b> to a common node formed of a voltage cell input <b>3214</b> of the comparator <b>3212</b> and the current source <b>3202</b>. A reference voltage <b>3216</b> is applied to the second input of the comparator <b>3212</b>.

P-0299[0299] The global sense amplifier <b>3254</b> buffers the column capacitance.

P-0300[0300] The voltage mode sensing circuit <b>3200</b> further comprises a plurality of reference subarrays <b>3170</b>, a plurality of local sense amplifiers <b>3282</b>, and a plurality of global sense amplifiers <b>3274</b>. The reference subarrays <b>3170</b> comprise a plurality of reference cells for storing reference signals. In one embodiment, the reference subarrays <b>3170</b> are similar to the memory subarrays <b>3150</b>. The local sense amplifiers <b>3282</b> read the reference subarrays <b>3170</b>. In one embodiment, the local sense amplifiers <b>3282</b> are similar to the local sense amplifiers <b>3252</b>. The global sense amplifiers <b>3274</b> detect and amplify the voltage from the local sense amplifiers <b>3282</b>.

P-0301[0301] The global sense amplifier <b>3274</b> comprises a comparator <b>3292</b>, a current source <b>3272</b> and a selection circuit <b>3278</b>, which are arranged in similar manner as the comparator <b>3212</b>, the current source <b>3202</b> and the selection circuit <b>3258</b> of the global sense amplifier <b>3254</b>, except the comparator <b>3292</b> is configured as a buffer. The comparator <b>3292</b> serves as a comparator in sensing the reference cells and serves as a buffer for driving the reference level.

P-0302[0302]FIG. 33 is a block diagram illustrating voltage mode sensing circuit <b>3300</b>.

P-0303[0303] The voltage mode sensing circuit <b>3300</b> includes like elements as the voltage mode sensing circuit <b>3200</b> (FIG. 32) and are given like reference numbers. The voltage mode sensing circuit <b>3300</b> comprises a memory array <b>3150</b>, a plurality of local sense amplifiers <b>3352</b> and a plurality of global sense amplifiers <b>3354</b>. The local sense amplifier <b>3352</b> includes a local source follower stage and includes an NMOS source follower as part of the global sense amplifier. The global sense amplifier <b>3354</b> includes a source follower stage.

P-0304[0304] Each local sense amplifier <b>3352</b> is coupled to a memory subarray <b>3150</b>. In one embodiment, the local sense amplifier <b>3352</b> is disposed adjacent the memory subarray <b>3150</b>. The local sense amplifier <b>3352</b> includes a selection circuit <b>3253</b> that couples a selected bitline <b>3151</b> to a bitline <b>3355</b>. In one embodiment, the selection circuit <b>3253</b> comprises transistors. The local sense amplifier <b>3252</b> senses the selected memory cell on the bitline <b>3151</b> and provides a voltage to a global sense amplifier <b>3254</b>.

P-0305[0305] The local sense amplifier <b>3352</b> comprises an NMOS transistor <b>3307</b> coupled between the bitline <b>3355</b> and a supply voltage terminal, and includes a gate coupled to the bitline <b>3151</b>. A current source <b>3311</b> is coupled between the gate of the NMOS transistor <b>3307</b> and ground. The local sense amplifier <b>3252</b> provides a maximum voltage range by using low current bias.

P-0306[0306] The global sense amplifier <b>3354</b> comprises a comparator <b>3312</b>, a current source <b>3302</b> and a selection circuit <b>3358</b>. The current source <b>3302</b> couples the voltage terminal <b>3314</b> of the comparator <b>3312</b> to a ground terminal. The selection circuit <b>3358</b> couples the selected one of the bitlines <b>3355</b> to a common node formed of a voltage cell input <b>3314</b> of the comparator <b>3312</b> and the current source <b>3302</b>. A reference voltage <b>3316</b> is applied to the second input of the comparator <b>3312</b>. The global sense amplifier <b>3354</b> is selectively coupled to the bitline to compare the cell voltage to a reference voltage <b>3316</b>. The global sense amplifier <b>3354</b> buffers the column capacitance.

P-0307[0307] The voltage mode sensing circuit <b>3300</b> further comprises a plurality of reference subarrays <b>3170</b>, a plurality of local sense amplifiers <b>3382</b>, and a plurality of global sense amplifiers <b>3374</b>. The reference subarrays <b>3170</b> comprise a plurality of reference cells for storing reference signals. In one embodiment, the reference subarrays <b>3170</b> are similar to the memory subarrays <b>3150</b>. The local sense amplifiers <b>3382</b> read the reference subarrays <b>3170</b>. In one embodiment, the local sense amplifiers <b>3382</b> are similar to the local sense amplifiers <b>3352</b>. The global sense amplifiers <b>3374</b> detect and amplify the voltage from the local sense amplifiers <b>3382</b>.

P-0308[0308] The global sense amplifier <b>3374</b> comprises a comparator <b>3392</b>, a current source <b>3372</b> and a selection circuit <b>3378</b>, which are arranged in similar manner as the comparator <b>3312</b>, the current source <b>3302</b> and the selection circuit <b>3358</b> of the global sense amplifier <b>3354</b>, except the comparator <b>3392</b> is configured as a buffer. The comparator <b>3392</b> serves as a comparator in sensing the reference cells and serves as a buffer for driving the reference level.

P-0309[0309] In another embodiment, the local sense amplifier is a common source amplifier, and the global sense amplifiers are NMOS source follower stages or PMOS source follower stages.

P-0310[0310] In another embodiment, the local sense amplifier is a common source amplifier, and the global sense amplifiers are common source amplifiers.

P-0311[0311]FIG. 34 is a block diagram illustrating a global sense amplifier <b>3400</b> having an auto zeroing function.

P-0312[0312] The comparators <b>3012</b>, <b>3112</b>, <b>3212</b>, and <b>3312</b> of FIGS. <b>30</b>-<b>33</b> may be the global sense amplifier <b>3400</b>.

P-0313[0313] The sense amplifier <b>3400</b> comprises an operational amplifier <b>3402</b>, a pair of capacitors <b>3404</b> and <b>3405</b>, and a plurality of switches <b>3406</b> and <b>3407</b>.

P-0314[0314] The capacitors <b>3404</b> and <b>3405</b> couples respective inputs <b>3408</b> and <b>3410</b> of the operational amplifier <b>3402</b> to the switch <b>3406</b>.

P-0315[0315] In response to an auto zero (AZ) command <b>3416</b>, the switches <b>3407</b> selectively couples an output <b>3412</b> of the operational amplifier <b>3402</b> to the input <b>3408</b> to equalize the voltages on the output <b>3412</b> and input <b>3408</b>, and selectively couples an output <b>3414</b> of the operational amplifier <b>3402</b> to the input <b>3410</b> to equalize the output <b>3414</b> and the input <b>3410</b>. In the auto zero mode, the voltage on A terminals of the capacitors <b>3404</b> and <b>3405</b> are set equal to the reference voltage (VREF) <b>3418</b>, and the B terminals of the capacitors <b>3404</b> and <b>3405</b> are equalized to the complementary outputs of the operational amplifier <b>3402</b>. The switch <b>3406</b> is switched by an evaluation (EVA) command <b>3422</b> to connect the cell voltage (VCELL) <b>3420</b> to the other end of the capacitor <b>3405</b> for comparison from the operational amplifier <b>3402</b>.

P-0316[0316] The switch <b>3406</b> selectively applies the reference voltage (VREF) <b>3418</b> to the capacitor <b>3404</b> in response to the evaluation (EVA) command <b>3422</b>. The switch <b>3406</b> also selectively applies either the reference voltage (VREF) <b>3418</b> or a cell voltage (VCELL) <b>3420</b> to the capacitor <b>3405</b> in response to the evaluation (EVA) command <b>3422</b>. The evaluation command <b>3422</b> equalizes the signals on terminals <b>3404</b>A and <b>3505</b>A of the capacitors <b>3404</b> and <b>3405</b>.

P-0317[0317] In an alternate embodiment, the nodes <b>3404</b>B and <b>3405</b>B of the capacitors <b>3404</b> and <b>3405</b> are reset to a fixed bias voltage. In another embodiment, the nodes <b>3404</b>B and <b>3405</b>B of the capacitors <b>3404</b> and <b>3405</b> are shorted together.

P-0318[0318] By using a capacitor for sensing, the input common load range to the operational amplifier (or comparator) is substantially constant and independent of the memory cell voltage or current.

P-0319[0319]FIG. 35 is a block diagram illustrating an auto zero sense amplifier <b>3500</b>.

P-0320[0320] The autozero sense amplifier <b>3500</b> comprises a plurality of PMOS transistors <b>3502</b> and <b>3504</b>, a plurality of NZ NMOS transistors <b>3506</b> and <b>3507</b>, a plurality of NMOS transistors <b>3508</b> through <b>3516</b>, a plurality of capacitors <b>3518</b> and <b>3519</b> and a plurality of transfer gates <b>3522</b> through <b>3528</b>.

P-0321[0321] The PMOS transistors <b>3502</b> and <b>3504</b> and the NMOS transistors <b>3508</b>, <b>3509</b> and <b>3513</b> and the NZ NMOS transistor <b>3507</b> are arranged as a differential pair. The NMOS transistors <b>3508</b> and <b>3509</b> provide the differential input pair. The NZ NMOS transistor <b>3507</b> and the NMOS transistor <b>3513</b> provide bias for the NMOS transistor <b>3508</b> and <b>3509</b>. The PMOS transistors <b>3502</b> and <b>3504</b> are coupled for cross-coupled loading. The PMOS transistor <b>3502</b> is coupled between the supply voltage and an output terminal <b>3530</b>. A bias voltage <b>3529</b> is applied to the gates of the NZ NMOS transistors <b>3506</b> and <b>3507</b> and the NMOS transistors <b>3513</b> and <b>3514</b>.

P-0322[0322] The NMOS transistors <b>3510</b> and <b>3511</b> provide an NMOS coupled internal latch, which is active while the differential input pair is on. The drain of the NMOS transistor <b>3510</b> is coupled to the drain of the NMOS transistor <b>3509</b> and the gate of the NMOS transistor <b>3511</b>. The drain of the NMOS transistor <b>3511</b> is coupled to a common node formed of the drain of the NMOS transistor <b>3508</b> and gate of the NMOS transistor <b>3510</b>. The NZ NMOS transistor <b>3506</b> and the NMOS transistor <b>3514</b> provide bias for the NMOS transistors <b>3510</b> and <b>3511</b> and are coupled between the common node formed of the sources of the NMOS transistors <b>3510</b> and <b>3511</b>, and ground.

P-0323[0323] The transfer gate <b>3522</b> couples the drains of the PMOS transistors <b>3502</b> and <b>3504</b> and the output <b>3530</b> to each other for equalization and quick recovery for the next comparison in response to a release signal <b>3531</b> and an inverted release signal <b>3532</b>.

P-0324[0324] The capacitor <b>3519</b> couples the gate of the NMOS transistor <b>3509</b> to first terminals of the transfer gates <b>3525</b> and <b>3526</b> which include a second terminal coupled to a reference voltage <b>3534</b>. The capacitor <b>3518</b> couples the gate of the NMOS transistor <b>3508</b> into first terminals of the transfer gates <b>3527</b> and <b>3528</b>, which have second terminals coupled to the reference voltage <b>3534</b> and a cell voltage <b>3535</b>, respectively. The transfer gates <b>3525</b> and <b>3527</b> are controlled by a auto zero signal <b>3537</b> and an inverted auto zero signal <b>3538</b>. The transfer gates <b>3526</b> and <b>3528</b> are controlled by evaluation signals <b>3539</b> and <b>3540</b>.

P-0325[0325] The transfer gates <b>3523</b> and <b>3524</b> couple the drains of the PMOS transistors <b>3504</b> and <b>3502</b>, respectively, to the gates of the NMOS transistors <b>3509</b> and <b>3508</b>, respectively, in response to the auto zero signal <b>3537</b> and inverted auto zero signal <b>3538</b>. The NMOS transistors <b>3512</b> and <b>3516</b> couple the gates of the NMOS transistors <b>3509</b> and <b>3508</b>, respectively, to ground in response to a strobe signal <b>3542</b> to pull down the transistors <b>3509</b> and <b>3508</b> to turn off the differential pair. The NMOS transistor <b>3515</b> couples the sources ofthe NMOS transistors <b>3510</b> and <b>3511</b> to the ground in response to the strobe signal <b>3542</b> for full level latching.

P-0326[0326] The array architectures described herein may enable multilevel parallel operation.

P-0327[0327] A pipelined read operation may be as follows. A first row is selected in a selected subarray, such as subarray <b>2802</b> or subarray <b>3150</b>/<b>3170</b>, and the content of selected memory cells are coupled to the local bitline and to the global bitlines while a second row in another subarray <b>2802</b> or <b>3150</b>/<b>3170</b> is selected and the content of the selected memory cells are coupled to the local bitlines but not yet coupled to the global bitlines. After the read operation completes processing the data of the first row, the data of the second row is enabled to couple to the global bitlines to continue the read operation, and a third row in a different subarray <b>2802</b> or <b>3150</b>/<b>3170</b> is selected to enable the content of the selected memory cells to couple to the local bitlines but not yet to the global bitlines. This cycle continues until all desired data are read out. This, for example, enables continuous read of multilevel memory cells.

P-0328[0328] In another embodiment, pipelined read operation is performed by operating on memory cells in a row in an array, such as memory array <b>2801</b>, while another row in another memory array <b>2801</b> is selected to enable the contents of the memory cells to be ready.

P-0329[0329] A read-while-read operation may be as follows. A read operation operates on both arrays, such as memory array <b>2801</b> (or memory subarrays <b>2802</b> or <b>3150</b>), simultaneously and the data are available from both arrays possibly at the same time. In this case, for example, data latches are used to latch the data from both arrays. In another embodiment, two sets of data lines may be used to transfer the data from both arrays to an on-chip controller.

P-0330[0330] A read/write-while-write/read operation may be as follows. Similarly while one operation, e.g., read, is executed on an array, such as subarray <b>2802</b> or array <b>2801</b> or subarrays <b>3150</b>/<b>3170</b>, another operation is executed, e.g., write, on another array such as subarray <b>2802</b> or <b>2801</b> or subarray <b>3150</b>/<b>3170</b>. This is possible because control circuits associated with decoding and sensing and/or writing may be embedded for each array.

P-0331[0331] A read/erase-while-erase/read may be as follows. Similarly while one operation, e.g., read, is executed on an array, such as subarray <b>2802</b> or <b>2801</b> or subarray <b>3150</b>/<b>3170</b>, another operation is executed, e.g., erase, on another array such as subarray <b>2802</b> or <b>2801</b> or subarray <b>3150</b>/<b>3170</b>. This is possible because each array may have its own decoders and embedded control circuits associated with sensing.

P-0332[0332] An erase-while-erase operation may be as follows. Similarly while one erase operation is executed on an array, such as subarray <b>2802</b> or <b>2801</b> or subarray <b>3150</b>/<b>3170</b>, another erase operation is executed on another array, such as subarray <b>2802</b> or <b>2801</b> or subarray <b>3150</b>/<b>3170</b>. This is possible because each array may have its own decoders.

P-0333[0333] A write/erase-while-erase/write operation may be as follows. Similarly while one operation, e.g., write, is executed on an array, such as subarray <b>2802</b> or array <b>2801</b> or subarrays <b>3150</b>/<b>3170</b>, another operation is executed, e.g., erase, on another array such as subarray <b>2802</b> or <b>2801</b> or subarray <b>3150</b>/<b>3170</b>. This is possible because each array may have its own decoders and embedded control circuits associated with sensing and/or writing.

P-0334[0334] A write-while-write operation may be as follows. Similarly while one write operation is executed on an array, such as subarray <b>2802</b> or <b>2801</b> or subarray <b>3150</b>/<b>3170</b>, another write operation is executed on another array, such as subarray <b>2802</b> or <b>2801</b> or subarray <b>3150</b>/<b>3170</b>. This is possible because each array may have its own decoders and embedded control circuits associated with sensing and/or writing.

P-0335[0335]FIG. 36 is a block diagram illustrating a memory system <b>3600</b> for a multilevel memory including local autozero sense amplifiers and global autozero sense amplifiers.

P-0336[0336] The memory system <b>3600</b> comprises a plurality of memory arrays <b>3601</b> arranged in rows and columns of memory arrays <b>3601</b>. Each memory array <b>3601</b> comprises a plurality of memory subarrays <b>3602</b>, a plurality of local sense amplifiers <b>3604</b>, and a plurality of global sense amplifiers <b>3606</b>. In one embodiment, the local sense amplifier <b>3604</b> is disposed adjacent to a memory subarray <b>3602</b>. In another embodiment, the local sense amplifier <b>3604</b> is shared between a plurality of memory subarrays <b>3602</b>. The local sense amplifier <b>3604</b> reads the contents of the memory cells within the corresponding memory subarray <b>3602</b>. The memory subarrays <b>3602</b> are arranged in rows and columns. The local sense amplifiers <b>3604</b> coupled to a column of memory subarrays <b>3602</b> are coupled to a global sense amplifier <b>3606</b>. The memory cells may include redundant cells, reference cells, or spare cells. The local sense amplifier <b>3604</b> may include an autozero function. In one embodiment, the global sense amplifiers <b>3606</b> include an autozero function. In another embodiment, the global sense amplifiers <b>3606</b> does not include an autozero function. In another embodiment, the memory system <b>3600</b> includes only the global sense amplifiers <b>3606</b> at the top level (at the system <b>3600</b>), which are shared between the memory arrays <b>3601</b>.

P-0337[0337]FIG. 36A is a block diagram illustrating a memory system <b>3650</b> for a multilevel memory including local autozero sense amplifiers.

P-0338[0338] The memory system <b>3650</b> is similar to memory system <b>3600</b>, but it does not include the global sense amplifiers <b>3606</b>. In this case, memory subarrays <b>3651</b> are similar to the memory subarrays <b>3601</b> without the global sense amplifiers <b>3606</b>, but include buffers <b>3652</b> that are disposed locally right after the. local sense amplifier <b>3604</b> to drive a global bus (not shown) coupled between a sensed and amplified output of the buffer <b>3652</b> to global latches (not shown) or output buffers (not shown). This architecture may be most realizable for highest speed. Alternatively, the latches instead of global latches may be disposed locally next to the local sense amplifier <b>3604</b>.

P-0339[0339] The memory subarrays <b>3602</b> of FIGS. 36 and 36 A may be segmented arrays. The memory subarray <b>3602</b> may include status cells disposed in a separate row or rows or same row which indicates status of the subarray/row such as it is used for data or code storage, whether the subarray/row is at erase or program state, whether the subarray/row is good, not-so-good or bad condition, a number of bad cells in a subarray/row, or degree of cell storage level wearing, or operational status such as bias values for erase/program/read bias for each row or page. The memory subarray <b>3602</b> may include reference cells disposed in a separate row or rows, which are enabled when a data row is enabled in a verify or a read mode.

P-0340[0340] The memory subarray <b>3602</b> may include reference cells that are read for each page, such as described above, or for each segment.

P-0341[0341] The local current sense amplifier <b>3604</b> may be a current sense amplifier <b>4000</b> (FIG. 40), the current sense amplifier <b>4100</b> (FIG. 41), the two-stage current sense amplifier <b>4200</b> (FIG. 42), a two-stage current sense amplifier <b>4300</b> (FIG. 43), a two-stage indirect current sensing amplifier <b>4400</b> (FIG. 44), and a two-stage indirect current sensing amplifier <b>4500</b> (FIG. 45).

P-0342[0342]FIG. 37 is a block diagram illustrating a memory system <b>3700</b> including single ended autozero sense amplifiers.

P-0343[0343] A memory system <b>3700</b> comprises a plurality of segmented arrays <b>3702</b>, a plurality of autozero local sense amplifiers <b>3704</b>, and a plurality of autozero global sense amplifiers <b>3706</b>. The memory system <b>3700</b> may be arranged in a manner similar to the memory system <b>3600</b> described above. For clarity, FIG. 37 shows only one segmented array <b>3702</b>, one autozero local sense amplifier <b>3704</b>, and one autozero global sense amplifier <b>3706</b>. The segmented array <b>3702</b> comprises a plurality of data memory cells <b>3708</b> and a plurality of reference memory cells <b>3710</b>. For clarity only one data memory cell <b>3708</b> and one reference memory cell <b>3710</b> are shown. The data cells <b>3708</b> and the reference memory cells <b>3710</b> are coupled to the corresponding autozero local sense amplifier <b>3704</b> for sensing the content of the data memory cell <b>3708</b> in comparison with the reference memory cell <b>3710</b>. The autozero local sense amplifier <b>3704</b> may be, for example, one of the sense amplifiers described below in conjunction with FIGS. 40 through 45. The autozero local sense amplifier and the autozero global sense amplifier are single ended amplifiers.

P-0344[0344] In another embodiment, the autozero local sense amplifier <b>3704</b> may be a current sensing autozero sense amplifier, and the autozero global sense amplifier <b>3706</b> may be a voltage sensing autozero sense amplifier, such as described above. In another embodiment, the autozero local sense amplifier <b>3704</b> may be a current sensing autozero sense amplifier, and the autozero global sense amplifier <b>3706</b> may be a current sensing autozero sense amplifier. In another embodiment, the autozero local sense amplifier <b>3704</b> may be a voltage sensing autozero sense amplifier, and the autozero global autozero sense amplifier <b>3706</b> may be a current sensing autozero sense amplifier.

P-0345[0345]FIG. 38 is a block diagram illustrating a memory system <b>3800</b> including differential autozero sense amplifiers.

P-0346[0346] The memory system <b>3800</b> comprises a plurality of segmented memory arrays <b>3802</b>, a plurality of local autozero sense amplifiers <b>3804</b>, and a plurality of global sense amplifiers <b>3806</b>. For. clarity, FIG. 38 shows only one segmented memory array <b>3802</b>, one autozero local sense amplifier <b>3804</b>, and one autozero global sense amplifier <b>3806</b>. The memory system <b>3800</b> may be arranged in a manner similar to the memory systems <b>3600</b> and <b>3700</b>, except that the autozero local sense amplifier <b>3804</b> and the autozero global sense amplifier <b>3806</b> may include a differential autozero sense amplifier such as the global sense amplifier <b>3400</b> described above in conjunction with FIG. 34. In another embodiment, the memory system <b>3800</b> does not include a global sense amplifier <b>3806</b>. In this case, a differential to single ended output and buffered stage may be coupled locally right after the local sense amplifier <b>3804</b> to drive a global bus (not shown) coupled between from a sensed and amplified output of the buffered stage to global latches (not shown) or output buffers (not shown).

P-0347[0347]FIG. 39 is a block diagram illustrating a memory system <b>3900</b> including crossed bitlines.

P-0348[0348] The memory system <b>3900</b> comprises a plurality of memory arrays <b>3902</b>, and a plurality of global sense amplifiers <b>3904</b>. For clarity and simplicity, only one memory array <b>3902</b> and one global sense amplifier <b>3904</b> are shown. The memory <b>3902</b> comprises a plurality of data cells <b>3906</b>, a plurality of reference cells <b>3908</b> and a plurality of local sense amplifiers <b>3910</b>. For clarity and simplicity, only one column of data cells <b>3906</b>, one column of reference cells <b>3908</b>, and one local sense amplifier <b>3910</b> are shown. A data bitline <b>3912</b> couples a column of data cells <b>3906</b> to the local sense amplifier <b>3910</b>. A reference bitline <b>3914</b> couples a column of reference cells <b>3908</b> to the local sense amplifier <b>3910</b>. The local sense amplifier <b>3910</b> is coupled to the global sense amplifier <b>3904</b>. The data bitline <b>3912</b> and the reference bitline <b>3914</b> are disposed in a crossed configuration with the bitlines <b>3912</b> and <b>3914</b> being disposed so the signal path goes back and forth between the physical location of the columns of data cells <b>3906</b> and reference cells <b>3908</b>. Crossing may provide similar electrical characteristics as a twisted wire pair. A global bitline <b>3916</b> couples the global sense amplifier <b>3904</b> to the local sense amplifier <b>3910</b>. Global bitlines <b>3916</b> may be arranged in a crossed configuration. One bitline <b>3912</b> or <b>3914</b> may be crossed in the same metal while the other bitline makes a crossing jump by another metal line, a poly line, or a diffusion over the first bitline.

P-0349[0349] In another embodiment, the local sense amplifiers <b>3910</b> and the global sense amplifiers <b>3904</b> may use the sense amplifiers described below in conjunction with FIGS. <b>40</b>-<b>48</b>.

P-0350[0350]FIG. 40 is a block diagram illustrating a current sense amplifier <b>4000</b> including auto-zero.

P-0351[0351] The current sense amplifier <b>4000</b> uses autozero or equalization to equalize voltages on an output terminal <b>4099</b> and a node <b>4098</b> that stores a voltage corresponding to the current on a reference cell bitline (IR) <b>4005</b> so that the signal path through the current sense amplifier <b>4000</b> is similar for both the data cell bitline (ICELL) <b>4006</b> and the reference cell bitline (IR) <b>4005</b>. The current sense amplifier <b>4000</b> may be used in the autozero local sense amplifier <b>3704</b> of FIG. 37.

P-0352[0352] The current sense amplifier <b>4000</b> comprises a plurality of inverters <b>4001</b> and <b>4002</b>, a plurality of PMOS transistors <b>4010</b> and <b>4011</b>, a plurality of NMOS transistors <b>4020</b> through <b>4023</b>, and a charge cancellation injection circuit <b>4036</b>.

P-0353[0353] The NMOS transistors <b>4021</b> and <b>4023</b> are arranged as a switch to selectively couple the reference cell bitline (IR) <b>4005</b> or the data cell bitline (ICELL) <b>4006</b> to a first node <b>4007</b>. The drain-source terminals of the NMOS transistor <b>4021</b> couple the reference cell bitline (IR) <b>4005</b> to the first node <b>4007</b> in response to a first autozero selection signal <b>4003</b> applied to a gate of the NMOS transistor <b>4021</b>. The drain-power terminals of the NMOS transistor <b>4023</b> couple the data cell bitline (ICELL) <b>4006</b> to the first node <b>4007</b> in response to a second autozero selection signal <b>4004</b> applied to a gate of the NMOS transistor <b>4023</b>. In another embodiment, PMOS transistors (not shown) may be coupled in parallel to the NMOS transistors <b>4021</b> and <b>4023</b> and controlled by the second autozero selection signal <b>4004</b> and the first autozero selection signal <b>4003</b>, respectively.

P-0354[0354] The inverters <b>4001</b> and <b>4002</b> are coupled in series to generate the second autozero selection signal <b>4004</b> and the first autozero selection signal <b>4003</b>, respectively, in response to an autozero control signal <b>4008</b> applied to the input of the inverter <b>4001</b>. In one embodiment, the timing of the generation of the first and second autoselection signals <b>4003</b> and <b>4004</b>, respectively, causes the NMOS transistors <b>4021</b> and <b>4023</b> operating as switches to break before make.

P-0355[0355] The drain-source terminals of the diode connected PMOS transistor <b>4011</b> couple a supply voltage VSUP to the first node <b>4007</b> to generate a current indicative of the voltage on the first node <b>4007</b> and correspondingly indicative of the voltage in the respective data memory cell or reference memory cell.

P-0356[0356] The drain-source terminals of the PMOS transistor <b>4010</b> and the NMOS transistor <b>4020</b> are coupled in series between the supply voltage and ground to form an output terminal <b>4099</b> formed of the common node of the drains of the transistors <b>4010</b> and <b>4020</b>. The gate of the PMOS transistor <b>4010</b> is coupled to the common node of the gate and drain of the PMOS transistor <b>4011</b> to form a current mirror with the PMOS transistor <b>4011</b>.

P-0357[0357] The NMOS transistor <b>4022</b> is arranged as a switch to selectively couple the voltage on the common node formed of the output terminal <b>4099</b> and the drain terminals of the transistors <b>4010</b> and <b>4020</b> to a second node <b>4098</b> in response to the first autozero selection signal <b>4003</b>. When the voltage on the output terminal <b>4099</b> is coupled to the second node <b>4098</b>, the voltage on the second node <b>4098</b> is indicative of the voltage on the first node <b>4007</b>, which corresponds to the data cell plus any offset through the data path and the sense amplifier <b>4000</b>. The drain-source terminals of the NMOS transistor <b>4022</b> couple the drain of the NMOS transistor <b>4020</b> to the common node formed of the second node <b>4098</b> and the gate of the NMOS transistor <b>4020</b> to diode connect the NMOS transistor <b>4020</b> in response to the first autozero selection signal <b>4003</b> applied to the gate of the NMOS transistor <b>4022</b>.

P-0358[0358] In another embodiment, a capacitor (not shown) is coupled between the second node <b>4098</b> and ground to store charge indicative of the reference memory cell current.

P-0359[0359] The charge injection cancellation circuit <b>4036</b> provides charge injection cancellation caused by the NMOS transistor <b>4022</b> switching. The charge injection cancellation circuit <b>4036</b> may be an NMOS transistor arranged as a capacitor coupled between the source of the NMOS transistor <b>4022</b> and the second autozero selection signal <b>4004</b>. In one embodiment, the NMOS transistor <b>4036</b> is one-half the size of the NMOS transistor <b>4022</b>. In another embodiment, the drain-source terminals of a PMOS transistor (not shown) may be coupled between the drain-source terminals of the NMOS transistor <b>4022</b>.

P-0360[0360] As an overview, the NMOS transistors <b>4021</b> and <b>4023</b> selectively couple the reference memory cell line (IR) <b>4005</b> and the data memory cell (Icell) <b>4006</b> to the first node <b>4007</b> in response to the first and second autozero selection signals <b>4003</b> and <b>4004</b>, respectively. The data from the reference memory cell line <b>4005</b> and the data memory cell line <b>4006</b> may be mismatched, but after the data reaches the first node <b>4007</b>, the current sense amplifier <b>4000</b> provides a similar path to eliminate mismatch of the signals from the data memory cell and the reference memory cell when they are compared. The reference level of the reference memory cell is first converted from a current to a voltage and a corresponding voltage is stored on the second data node <b>4098</b> and then the data cell is read by applying the current to the first node <b>4007</b> and comparing to the reference memory cell stored on the second node <b>4098</b> to produce an output signal on the output terminal <b>4099</b> indicative of the difference in the voltage on the first node <b>4007</b> and the second node <b>4098</b> to indicate the difference between the data memory cell and the reference voltage from the reference memory cell.

P-0361[0361] During a first operation, the current sense amplifier <b>4000</b> is operated to store a voltage on the second node <b>4098</b> indicative of the reference bitline (IR) <b>4005</b>. The first autozero selection signal <b>4003</b> is set to an enable state, and the second autozero selection signal <b>4004</b> is correspondingly set to the disabled state. When the first autozero selection signal <b>4003</b> is enabled, the NMOS transistors <b>4021</b> and <b>4022</b> are turned on. The NMOS transistor <b>4021</b> applies the reference current (IR) to the first node <b>4007</b> which is applied to the PMOS transistor <b>4011</b>. The PMOS transistor <b>4010</b> mirrors the current from the PMOS transistor <b>4011</b>. The NMOS transistor <b>4020</b> is diode connected because the enabled NMOS transistor <b>4022</b> shorts the output terminal to the second node <b>4098</b>. The voltage on the second node <b>4098</b> sustains the current in the PMOS transistor <b>4010</b> and the NMOS transistor <b>4020</b>. The voltage on the second node <b>4098</b> corresponds to the reference memory cell current IR plus any offset between the PMOS transistors <b>4011</b> and <b>4010</b>, hence the current in the PMOS transistor <b>4010</b> corresponds to the reference memory cell current IR but not necessarily exactly due to any mismatch between the PMOS transistors <b>4010</b> and <b>4011</b>.

P-0362[0362] During the second operation, the first autozero selection signal <b>4003</b> is disabled and the second autozero selection signal <b>4004</b> is enabled, to connect the data cell to the first node <b>4007</b>. The NMOS transistor <b>4023</b> is turned on and the NMOS transistors <b>4021</b> and <b>4022</b> are turned off. The NMOS transistor <b>4023</b> provides the data cell current ICELL to the PMOS transistor <b>4011</b>, which the PMOS transistor <b>4010</b> mirrors. The PMOS transistor <b>4010</b> compares this current to the current from the NMOS transistor <b>4020</b> generated in response to the voltage on the second node <b>4098</b>. The output voltage VOUT on the output terminal <b>4099</b> is the current difference between the two currents multiplied by the output impedance looking into the PMOS transistor <b>4010</b> and the NMOS transistor <b>4020</b>. In biased voltage range, the output impedance is the drain-source resistance of the PMOS transistor <b>4010</b> in parallel with the drain-source resistance of the NMOS transistor <b>4020</b>.

P-0363[0363]FIG. 41 is a block diagram illustrating a current sense amplifier <b>4100</b> including autozero and replica loading.

P-0364[0364] The current sense amplifier <b>4100</b> is similar to the current sense amplifier <b>4000</b>, and includes a replica loading circuit comprising a PMOS transistor <b>4114</b> and an NMOS transistor <b>4127</b> that are arranged to precharge the data cell reference line (ICELL) <b>4006</b>. Like numbers represent like elements. The current sense amplifier <b>4100</b> may be used in the autozero sense amplifier <b>3704</b> of FIG. 37.

P-0365[0365] The drain-source terminals of the diode connected PMOS transistor <b>4114</b> and the NMOS transistor <b>4127</b> are coupled in series between the supply voltage Vsup and the data memory cell line (ICELL) <b>4006</b>. The NMOS transistor <b>4127</b> is enabled by the first autozero selection signal <b>4003</b> applied to the gate thereof. The transistors <b>4114</b> and <b>4127</b> replicate the loading of the transistors <b>4011</b> and <b>4021</b>. In one embodiment, the PMOS transistor <b>4114</b> is the same size as the PMOS transistor <b>4011</b>. Likewise, the NMOS transistor <b>4127</b> is the same size as the NMOS transistor <b>4021</b>.

P-0366[0366] When the first autozero selection signal <b>4003</b> is enabled, both the NMOS transistors <b>4021</b> and <b>4127</b> are enabled. The first node <b>4007</b> is brought to the level of the reference memory cell line (IR) <b>4005</b> as described above, and the data cell line (ICELL) <b>4006</b> is precharged. After the second autozero selection signal <b>4004</b> is enabled, the NMOS transistor <b>4127</b> is disabled and the first node <b>4007</b> is brought to the data cell reference as described above, but at a faster speed because of the precharge.

P-0367[0367]FIG. 42 is a block diagram illustrating a two stage current sense amplifier <b>4200</b> including autozero.

P-0368[0368] The two-stage current sense amplifier <b>4200</b> is similar to the current sense amplifier <b>4100</b> of FIG. 41, but also includes an output stage. The output stage is autozeroed or equalized to the output of the current sense amplifier <b>4100</b> during a first operation. The two-stage current sense amplifier <b>4200</b> may be used in the autozero sense amplifier <b>3704</b> of FIG. 37.

P-0369[0369] The two stage current sense amplifier <b>4200</b> comprises a current sense amplifier <b>4100</b> and an output stage <b>4202</b>.

P-0370[0370] The output stage <b>4202</b> compares or amplifies the output of the current sense amplifier <b>4100</b>. The output stage <b>4202</b> comprises a PMOS transistor <b>4215</b>, NMOS transistors <b>4228</b> and <b>4229</b>, and a charge injection cancellation circuit <b>4237</b>. The drain-source terminals of the PMOS transistor <b>4215</b> and the NMOS transistor <b>4229</b> are coupled in series between the supply voltage and ground, and form an output terminal <b>4299</b> at a common node formed of the drains of the transistors <b>4215</b> and <b>4229</b>. The gate of the PMOS transistor <b>4215</b> is coupled to the gate of the PMOS transistor <b>4010</b> for biasing that is the same as the same autozero bias condition. The gate of the NMOS transistor <b>4229</b> is biased by the output <b>4199</b> of the current sense amplifier <b>4100</b>. The drain-source terminals of the NMOS transistor <b>4228</b> diode connect the NMOS transistor <b>4229</b> in response to the first autozero selection signal <b>4003</b>. In one embodiment, the transistors <b>4215</b>, <b>4229</b>, and <b>4228</b> are similar to respective transistors <b>4010</b>, <b>4020</b>, and <b>4022</b> to increase gain and speed. The charge injection cancellation circuit <b>4237</b> may be an NMOS transistor arranged as a capacitor coupled between the source of the NMOS transistor <b>4228</b> and the second autozero selection signal <b>4004</b>. In one embodiment, the NMOS transistor of the charge injection cancellation circuit <b>4237</b> is similar to the charge injection cancellation circuit <b>4036</b>.

P-0371[0371] In an alternative embodiment, a decoupling capacitor (not shown) may be coupled between the output of the current sense amplifier <b>4100</b> and the common node formed of the gate of the NMOS transistor <b>4229</b>, the source of the NMOS transistor <b>4228</b> and the charge injection cancellation circuit <b>4237</b>.

P-0372[0372]FIG. 43 is a block diagram illustrating a two-stage current sense amplifier <b>4300</b> including autozero.

P-0373[0373] The two-stage current sense amplifier <b>4300</b> is similar to the current sense amplifier <b>4000</b> of FIG. 40, but also includes an output stage. The output stage is autozeroed or equalized to the output of the current sense amplifier <b>4000</b> during a first operation. The two-stage current sense amplifier <b>4300</b> may be used in the autozero local sense amplifier <b>3704</b> of FIG. 37.

P-0374[0374] The two-stage current sense amplifier <b>4300</b> comprises the current sense amplifier <b>4000</b> and an output stage <b>4302</b>.

P-0375[0375] The output stage <b>4302</b> inverts and amplifies the output signal from the current sense amplifier <b>4000</b>. The output stage <b>4302</b> comprises a PMOS transistor <b>4315</b>, NMOS transistors <b>4328</b> and <b>4329</b>, a charge injection cancellation circuit <b>4337</b>, and a capacitor <b>4340</b>. The drain-source terminals of the PMOS transistor <b>4315</b> and the NMOS transistor <b>4329</b> are coupled in series between the supply voltage and ground, and form an output terminal <b>4399</b> at the common node formed of the drains of the transistors <b>4315</b> and <b>4329</b>. The gates of the transistors <b>4315</b> and <b>4329</b> are coupled together to form an inverter of the transistors <b>4315</b> and <b>4329</b>. The drain-source terminals of the NMOS transistor <b>4328</b> diode connect the NMOS transistor <b>4329</b> in response to the first autozero selection signal <b>4003</b>. The charge injection cancellation circuit <b>4337</b> may be an NMOS transistor arranged as a capacitor coupled between the source of the NMOS transistor <b>4328</b> and the second autozero selection signal <b>4004</b>. The capacitor <b>4340</b> is coupled between the output <b>4099</b> of the current sense amplifier <b>4000</b> and the common node formed of the gates of the transistors <b>4315</b> and <b>4329</b>, the source of the NMOS transistor <b>4328</b> and the charge injection cancellation circuit <b>4337</b>. The capacitor <b>4340</b> decouples the output stage <b>4302</b> from the current sense amplifier <b>4000</b>.

P-0376[0376] In an alternative embodiment, the gate of the PMOS transistor <b>4315</b> may be coupled to the PMOS transistor <b>4010</b>.

P-0377[0377]FIG. 44 is a block diagram illustrating a two-stage indirect current sensing amplifier <b>4400</b> having autozero.

P-0378[0378] The two-stage indirect current sensing amplifier <b>4400</b> may be used in the autozero local sense amplifier <b>3704</b> of FIG. 37.

P-0379[0379] The two-stage indirect current sensing amplifier <b>4400</b> comprises an indirect current input stage <b>4401</b>, an indirect current sense amplifier <b>4402</b>, and an output stage <b>4403</b>. The indirect current input stage <b>4401</b> selectively switches between a reference memory cell bitline (IREF) <b>4495</b> and a data memory cell bitline (ICELL) <b>4496</b>. In a first operation, the indirect current input stage <b>4401</b> stores a voltage corresponding to the current on the reference memory cell bitline (IREF) <b>4495</b> and any offset in the circuit. The two-stage indirect current sensing amplifier <b>4400</b> autozeroes or equalizes the output of the indirect current sense amplifier <b>4402</b> and the output of the output stage <b>4403</b> with the stored voltage. During a second operation, the indirect current input stage <b>4401</b> couples the data memory cell bitline (ICELL) <b>4496</b> to an input of the indirect current sense amplifier <b>4402</b> for comparison with the reference current on the reference memory cell bitline (IREF) <b>4495</b> as adjusted by the stored voltage in the indirect current input stage <b>4401</b>. The indirect current sense amplifier <b>4402</b> amplifies the voltage difference, which is further amplified by the output stage <b>4403</b>.

P-0380[0380] The indirect current input stage <b>4401</b> comprises a plurality of NMOS transistors <b>4421</b> through <b>4424</b> and a capacitor <b>4433</b>. The indirect current sense amplifier <b>4402</b> comprises a plurality of PMOS transistors <b>4410</b> and <b>4419</b>, a plurality of NMOS transistors <b>4427</b> through <b>4429</b>, and a charge injection cancellation circuit <b>4435</b>. The output stage <b>4403</b> comprises a PMOS transistor <b>4411</b>, a plurality of NMOS transistors <b>4420</b> and <b>4426</b>, and a charge injection cancellation circuit <b>4436</b>.

P-0381[0381] The diode connected NMOS transistor <b>4421</b> couples the reference memory cell bitline (IREF) <b>4495</b> to ground. The reference memory cell bitline (IREF) <b>4495</b> is coupled to the gate of the NMOS transistor <b>4428</b> for providing a reference bias and also is coupled to the drain of the NMOS transistor <b>4423</b> for selective switching to the capacitor <b>4433</b> in response to a first autozero selection signal <b>4493</b>.

P-0382[0382] The diode connected NMOS transistor <b>4422</b> couples the data memory cell bitline (ICELL) <b>4496</b> to ground. The data memory cell bitline (ICELL) <b>4496</b> is coupled to the drain of the NMOS transistor <b>4424</b> for selective switching to the capacitor <b>4433</b> in response to a second autozero selection signal <b>4494</b>.

P-0383[0383] The drain-source terminals of the diode connected PMOS transistor <b>4419</b> and the NMOS transistor <b>4428</b> are coupled in series between the supply voltage VSUP and ground to provide a reference current in response to the reference bias applied to the gate of the NMOS transistor <b>4428</b> by the reference memory cell bitline (IREF) <b>4495</b>. The drain-source terminals of the PMOS transistor <b>4410</b> and the NMOS transistor <b>4429</b> are coupled in series between the supply voltage VSUP and ground. The gate of the PMOS transistor <b>4410</b> is coupled to the common node formed of the gate and drain of the PMOS transistor <b>4419</b> to form a current mirror with the PMOS transistor <b>4419</b>. The drain-source terminals of the NMOS transistor <b>4427</b> diode connect the NMOS transistor <b>4429</b> in response to being enabled by the first autozero selection signal <b>4493</b>. The charge injection cancellation circuit <b>4435</b> is coupled to the source of the NMOS transistor <b>4427</b> to provide charge injection cancellation in response to the second autozero selection signal <b>4494</b>. The charge injection cancellation circuit <b>4435</b> may be an NMOS transistor arranged as a capacitor coupled between the source of the NMOS transistor <b>4427</b> and the second autozero selection signal <b>4494</b>.

P-0384[0384] In the output stage <b>4403</b>, the drain-source terminals of the PMOS transistor <b>4411</b> and the NMOS transistor <b>4420</b> are coupled in series between the supply voltage VSUP and ground, and the drains of the transistors <b>4411</b> and <b>4420</b> form an output terminal <b>4499</b>. The gate of the PMOS transistor <b>4411</b> is coupled to the common node formed of the gate and drain of the PMOS transistor <b>4419</b> to form a current mirror with the PMOS transistor <b>4419</b>. The drain-source terminals of the NMOS transistor <b>4426</b> diode connect the NMOS transistor <b>4420</b> and couple the output <b>4459</b> of the indirect current sense amplifier <b>4402</b> to the output terminal <b>4499</b> of the output stage <b>4403</b> in response to being enabled by the first autozero selection signal <b>4493</b>. The charge injection cancellation circuit <b>4436</b> is coupled to the source of the NMOS transistor <b>4426</b> to provide charge injection cancellation in response to the second autozero selection signal <b>4494</b>. The charge injection cancellation circuit <b>4436</b> may be an NMOS transistor arranged as a capacitor coupled between the source of the NMOS transistor <b>4426</b> and the second autozero selection signal <b>4494</b>.

P-0385[0385] During the first operation, the first autozero selection signal <b>4493</b> is enabled, and the transistors <b>4423</b>, <b>4427</b>, and <b>4426</b> are enabled to couple the reference memory cell bitline (IREF) <b>4495</b> to the capacitor <b>4433</b> which stores the voltage corresponding to the current on the reference memory cell bitline (IREF) <b>4495</b> and any offset in the circuit, and couples the voltage to the output of the indirect current sense amplifier <b>4402</b> and the output <b>4499</b> of the output stage <b>4403</b>. During a second operation, the second autozero selection signal <b>4494</b> is enabled, which enables the NMOS transistor <b>4424</b> to couple the data memory cell bitline (ICELL) <b>4496</b> to the capacitor <b>4433</b>, which is compared to the stored voltage. The indirect current sense amplifier <b>4402</b> amplifies the voltage difference, which is further amplified by the output stage <b>4403</b>.

P-0386[0386] The mismatch between the NMOS transistors <b>4421</b> and <b>4422</b> may not be cancelled in the two-stage indirect current sense amplifier <b>4400</b>.

P-0387[0387]FIG. 45 is a block diagram illustrating a two-stage indirect current sensing amplifier <b>4500</b> having autozero.

P-0388[0388] The two-stage indirect current sensing amplifier <b>4500</b> is similar to the indirect current sensing amplifier <b>4400</b>, but instead includes an inverter arranged output stage. The output stage is autozeroed or equalized to the output of an indirect current sense amplifier during a first operation. The two-stage indirect current sensing amplifier <b>4500</b> may be used in the autozero local sense amplifier <b>3704</b> of FIG. 37.

P-0389[0389] The two-stage indirect current sense amplifier <b>4500</b> comprises an indirect current input stage <b>4401</b>, an indirect current sense amplifier <b>4402</b> and an output stage <b>4503</b>. The output stage <b>4503</b> comprises a PMOS transistor <b>4511</b>, a plurality of NMOS transistors <b>4520</b> and <b>4526</b>, a capacitor <b>4532</b>, and a charge injection cancellation circuit <b>4536</b>. The transistors <b>4511</b> and <b>4520</b> are arranged as an inverter gain stage with self bias. The drain-source terminals of the PMOS transistor <b>4511</b> and the NMOS transistor <b>4520</b> are coupled in series between the supply voltage VSUP and ground, and include gates coupled to each other. The drains of the transistors <b>4511</b> and <b>4520</b> form an output node <b>4599</b>. The capacitor <b>4532</b> couples the output of the indirect current sense amplifier <b>4402</b> to the common node formed of the gates of the transistors <b>4511</b> and <b>4520</b> to decouple the indirect current sense amplifier <b>4402</b> and the output stage <b>4503</b>. The drain-source terminals of the NMOS transistor <b>4526</b> couple the output terminal of the output stage <b>4503</b> to the common node formed of the gates of the transistors <b>4511</b> and <b>4520</b> in response to the first autozero selection signal <b>4493</b>. The charge injection cancellation circuit <b>4536</b> is coupled to the source of the NMOS transistor <b>4526</b> in response to the second autozero selection signal <b>4494</b>. The charge injection cancellation circuit <b>4536</b> may be an NMOS transistor arranged as a capacitor coupled between the source of the NMOS transistor <b>4526</b> and the second autozero selection signal <b>4494</b>.

P-0390[0390] The memory system <b>3700</b> of FIG. 37 may be configured to operate at low voltages, e.g. 0.0 to 1.2 volts. The local sense amplifier <b>3706</b> may include a readout circuit that operates to read multilevel memory cells in this voltage range, such as described below in conjunction with FIGS. <b>46</b>- <b>48</b>.

P-0391[0391]FIG. 46 is a block diagram illustrating a memory system <b>4600</b> including a low voltage sense amplifier. The sensing shown in FIGS. 46, 46A, <b>47</b>, <b>47</b>A, <b>47</b>B, <b>48</b>, <b>48</b>A, and <b>48</b>B is to be known as Direct (Memory) Cell Sensing because a sensing element (the load) is connected directly through decoding circuitry to the memory cell but not through bias (cascading transistors. The sensing elements are capable of sub-volt (less than 1 volt power supply) sensing. In one embodiment, the circuits of FIGS. 46, 46A, <b>47</b>, <b>47</b>A, <b>47</b>B, <b>48</b>, <b>48</b>A, and <b>48</b>B are coupled to a comparison circuit that uses capacitors for autozero, signal coupling, and signal comparison, such as shown in FIGS. 34, 35, <b>38</b>, and <b>57</b>.

P-0392[0392] The memory system <b>4600</b> is similar to the memory system <b>3600</b> described above in conjunction with FIG. 36, but the local sense amplifier <b>3604</b> includes a readout circuit <b>4602</b>. For clarity, FIG. 46 shows only one memory subarray <b>3602</b> and one local sense amplifier <b>3604</b>, and only one memory cell <b>4603</b> is shown in the memory subarray <b>3602</b>. The readout circuit <b>4602</b> may operate in a low voltage range. The readout circuit <b>4602</b> may read memory cells that store low voltages and may provide a read signal <b>4604</b> indicative of the content of the memory cells <b>4603</b>.

P-0393[0393] The readout circuit <b>4602</b> comprises a buffer <b>4606</b> and a resistor <b>4608</b>. The resistor <b>4608</b> provides feedback between an output and an inverting input of the buffer <b>4606</b>. The inverting input of the buffer <b>4606</b> is coupled to the bitline for coupling to the memory cells <b>4603</b>. A non-inverting input of the buffer <b>4606</b> is coupled to a reference voltage from a reference memory cell (not shown).

P-0394[0394] As an illustrative example, the voltage stored in the memory cell <b>4603</b> and the voltage (VBITLN) on the bitline may be in the range of 0.0 through 1.0 volts. The minimum supply voltage (VDD_min) equals the voltage (VBITLN) on the bitline plus a differential operating voltage (dVOP), for example 0.5 volts. A control gate voltage (VCGR) of 1.8 to 2.4 volts is applied to the control gate of the memory cell <b>4603</b>. The memory cell <b>4603</b> operates in a linear region or saturation. During a read or verify, the bitline voltage (VBITLN) may be 0.2 V or 0.6 V. The read signal <b>4604</b> output from the comparator <b>4606</b> may be in a range of 0.2 to 0.4 volts or 0.8 to 1.2 volts.

P-0395[0395]FIG. 46A is a block diagram illustrating a memory system <b>4650</b> including a low voltage sense amplifier.

P-0396[0396] The memory system <b>4650</b> is similar to the memory system <b>4600</b> described above in conjunction with FIG. 46, but the local sense amplifier <b>3604</b> includes a readout circuit <b>4652</b> that may operate in a low voltage range. The readout circuit <b>4602</b> may read memory cells that store low voltages and may provide a read signal <b>4654</b> indicative of the content of the memory cells <b>4603</b>. The readout circuit <b>4652</b> comprises a resistor <b>4608</b> coupled between the supply voltage and the output <b>4654</b>, which is coupled to the bitline coupled to the memory cell <b>4603</b>.

P-0397[0397]FIG. 47 is a block diagram illustrating a memory system <b>4700</b> including a low voltage sense amplifier.

P-0398[0398] The memory system <b>4700</b> is similar to the memory system <b>4600</b> in FIG. 46 described above. For clarity, FIG. 47 shows only one memory subarray <b>3602</b> and one local sense amplifier <b>3604</b>. The local sense amplifier <b>3604</b> includes a readout circuit <b>4702</b>, which is similar to the readout circuit <b>4602</b>, except that a PMOS transistor <b>4708</b> functions as the feedback element and replaces the resistor <b>4608</b>. The readout circuit <b>4702</b> may operate in a low voltage range. The PMOS transistor <b>4708</b> includes drain-source terminals coupled between the output and the inverting input of a buffer <b>4706</b> and includes a gate coupled to a fixed voltage, such as ground.

P-0399[0399]FIG. 47A is a block diagram illustrating a memory system <b>4750</b> including a low voltage sense amplifier.

P-0400[0400] The memory system <b>4750</b> is similar to the memory system <b>4700</b> in FIG. 47 described above, but the local sense amplifier <b>3604</b> includes a readout circuit <b>4752</b> that comprises a PMOS transistor <b>4758</b> that includes drain-source terminals coupled between a supply voltage and an output node <b>4754</b>, which is coupled to the bitline coupled to the memory cell <b>4603</b>, and includes a gate coupled to a fixed voltage, such as ground.

P-0401[0401]FIG. 47B is a block diagram illustrating a memory system <b>4770</b> including a low voltage sense amplifier.

P-0402[0402] The memory system <b>4770</b> is similar to the memory system <b>4750</b> in FIG. 47A described above, but the local sense amplifier <b>3604</b> includes a readout circuit <b>4772</b> that comprises a diode connected PMOS transistor <b>4758</b> coupled between the supply voltage and an output node <b>4774</b>.

P-0403[0403]FIG. 48 is a block diagram illustrating a memory system <b>4800</b> including a low voltage sense amplifier.

P-0404[0404] The memory system <b>4800</b> is similar to the memory system <b>4700</b> of FIG. 47. For clarity, FIG. 48 shows only one memory subarray <b>4602</b> and one local sense amplifier <b>3604</b>. The local sense amplifier <b>3604</b> includes a readout circuit <b>4802</b> that comprises a buffer <b>4806</b> and an NMOS transistor <b>4808</b>, which can be an enhancement NMOS transistor (threshold voltage VT 0.5 to 1.0V) or a native NMOS transistor (threshold voltage VT=−0.2 to 0.2). The NMOS transistor <b>4808</b> includes drain-source terminals coupled between the supply voltage VDD and an inverting input of the buffer <b>4806</b>, and includes a gate coupled to the output of the buffer <b>4806</b> for feedback. The operation of the readout circuit <b>4802</b> is similar to that described above for the readout circuit <b>4602</b>, except the minimum supply voltage VDD_minequals a fixed voltage, e.g., 0.4 volts, plus a differential operating voltage (dVOP), e.g., 0.5 volts.

P-0405[0405]FIG. 48A is a block diagram illustrating a memory system <b>4850</b> including a low voltage sense amplifier.

P-0406[0406] The memory system <b>4850</b> is similar to the memory system <b>4800</b> in FIG. 48 described above, but the local sense amplifier <b>3604</b> includes a readout circuit <b>4852</b> that comprises a NMOS transistor <b>4858</b> that includes drain-source terminals coupled between a supply voltage and an output node <b>4854</b>, which is coupled to the bitline coupled to the memory cell <b>4603</b>, and includes a gate coupled to a fixed voltage.

P-0407[0407]FIG. 48B is a block diagram illustrating a memory system <b>4870</b> including a low voltage sense amplifier.

P-0408[0408] The memory system <b>4870</b> is similar to the memory system <b>4850</b> in FIG. 48A described above, but the local sense amplifier <b>3604</b> includes a readout circuit <b>4872</b> that comprises a diode connected NMOS transistor <b>4878</b> coupled between the supply voltage and an output node <b>4874</b>.

P-0409[0409]FIG. 49 is a schematic diagram illustrating a shared sense amplifier segmented reference array <b>4900</b>. The shared sense amplifier segmented reference array <b>4900</b> may be used in the memory system <b>3800</b> described above in conjunction with FIG. 38.

P-0410[0410] The shared sense amplifier segmented reference array <b>4900</b> comprises a plurality of array segments <b>4902</b>-<b>1</b> and <b>4902</b>-<b>2</b> and a plurality of differential sense amplifiers <b>4904</b>-<b>1</b> through <b>4904</b>-<b>3</b>. As an illustrative example, the array <b>4900</b> includes two array segments <b>4902</b>. In one embodiment, the array segments <b>4902</b> are disposed above and below the differential sense amplifiers <b>4904</b>.

P-0411[0411] The array segment <b>4902</b> comprises a plurality of memory cells <b>4912</b> arranged in rows and columns. A pair of reference rows <b>4913</b> comprise two rows of memory cells that store reference levels. Word lines WLR<b>0</b> and WLR<b>1</b> are coupled to even and odd reference rows, respectively, to account for odd and even row effect. Even or odd reference rows are used for even or odd data rows respectively. Word lines WL<b>0</b> through WL<b>3</b> are coupled to the data rows.

P-0412[0412] The array segment <b>4902</b> comprises a plurality of memory columns <b>4906</b>-<b>0</b> through <b>4906</b>-<b>7</b>, a first multiplexer <b>4908</b> and a plurality of second multiplexers <b>4910</b>-<b>1</b> through <b>4910</b>-<b>3</b>. As an illustrative example, the memory cells store two bits, and accordingly, there are three reference cells for three reference levels. In this case, the memory cells <b>4912</b> of the reference rows <b>4913</b> store reference voltages in the memory cells in the three memory columns <b>4906</b>-<b>5</b>-through <b>4906</b>-<b>7</b>. The other memory cells <b>4912</b> in the reference row <b>4913</b> may be left floating, or may be connected, but not used. The first multiplexer <b>4908</b> couples each of the memory columns <b>4906</b> to a first input of each of the differential sense amplifiers <b>4904</b>. The multiplexers <b>4910</b>-<b>1</b> through <b>4910</b>-<b>3</b> couple the respective memory column <b>4906</b>-<b>5</b> through <b>4906</b>-<b>7</b> to a second input of a respective differential sense amplifier <b>4904</b>-<b>1</b> through <b>4904</b>-<b>3</b>. Each memory column <b>4906</b> comprises a column of the memory cells <b>4912</b> and a multiplexer <b>4914</b>. For clarity, reference numerals are shown only for one memory column <b>4906</b>. The multiplexer <b>4914</b> allows the memory cells <b>4912</b> to be accessed.

P-0413[0413] In one embodiment, data is stored in one of the array segments <b>4902</b>, for example, the bottom array segment <b>4902</b>, and reference voltages are stored in the memory cells <b>4912</b> of the reference rows <b>4913</b> that are in the memory columns <b>4906</b>-<b>5</b> through <b>4906</b>-<b>7</b> of the other array segment <b>4902</b>, for example, the top array segment <b>4902</b>. When memory cells <b>4912</b> in one of the array segments <b>4902</b> are selected for multiplexing to the differential sense amplifiers <b>4904</b>, memory cells <b>4912</b> in the memory columns <b>4906</b>-<b>5</b> through <b>4906</b>-<b>7</b> that function as reference memory cells of the other array segment <b>4902</b> is selected at the same time.

P-0414[0414]FIG. 50 is a schematic diagram illustrating a memory cell replica sense amplifier <b>5000</b>.

P-0415[0415] The memory cell replica sense amplifier <b>5000</b> comprises a plurality of memory cell circuits <b>5002</b>-<b>0</b> and <b>5002</b>-<b>1</b>, a plurality of replica memory cell circuits <b>5004</b>-<b>0</b> through <b>5004</b>-<b>4</b>, a differential amplifier <b>5006</b>, and a plurality of bias generators <b>5008</b>-<b>0</b> and <b>5008</b>-<b>1</b>. For clarity, the details of only the bias generator <b>5008</b>-<b>0</b> are shown. Although five replica memory cell circuits <b>5004</b> are shown, other numbers of circuits <b>5004</b> may be used. One of inputs to the differential amplifier <b>5006</b> couples to the read out voltage from a data memory cell and the other input couples to read out voltage from a reference memory cell.

P-0416[0416] The memory cell circuits <b>5002</b> comprise a memory cell circuit <b>5010</b>, a PMOS transistor <b>5012</b>, and a plurality of NMOS transistors <b>5014</b> and <b>5016</b>. For clarity, the details of only the memory cell circuit <b>5002</b>-<b>0</b> are shown. The memory cell circuit <b>5010</b> is a circuit that is an equivalent model for a source side injection (SSI) split gate flash memory cell in read mode. In one embodiment, the memory cell circuit <b>5010</b> comprises a pair of NMOS transistors, in which a bottom transistor corresponds to a floating gate transistor, and a top transistor corresponds to a select gate (control gate) transistor. The NMOS transistor <b>5016</b> operates as a switch or multiplexer to allow access to the memory cell circuit <b>5010</b> in response to a column decode (COLDEC) signal. The NMOS transistor <b>5014</b> provides column bias to the memory cell circuit <b>5002</b> in response to the bias generator <b>5008</b>, which generates a bias and includes feedback control of the bias.

P-0417[0417] The replica memory cell circuits <b>5004</b> comprise a replica memory cell circuit <b>5020</b>, a PMOS transistor <b>5022</b>, and a plurality of NMOS transistors <b>5024</b> and <b>5026</b>. For clarity, the details of only the replica memory cell circuit <b>5004</b>-<b>0</b> are shown. The replica memory circuit <b>5020</b> replicates the SSI flash memory cells. In one embodiment, the replica memory cell circuit <b>5020</b> comprises a pair of NMOS transistors. The PMOS transistor <b>5022</b> mirrors the current of the PMOS transistor <b>5012</b> of the memory cell circuit <b>5002</b>. The NMOS transistor <b>5026</b> replicates the column select decoding of the NMOS transistor <b>5016</b>. The NMOS transistor <b>5024</b> provides column bias to the replica memory cell circuit <b>5004</b>. A control gate voltage CG is applied to the memory cell circuits <b>5010</b> of both memory cell circuits <b>5002</b>-<b>0</b> and <b>5002</b>-<b>1</b>. A data floating gate voltage FCD is shown as a storage node of the data memory cell <b>5010</b> of the memory cell circuit <b>5002</b>-<b>0</b>. A reference floating gate voltage FCR is shown as a storage node of the reference memory cell <b>5010</b> of the memory cell circuit <b>5002</b>-<b>1</b>. The gate of a transistor in the replica memory cell circuit <b>5020</b> is coupled to the drain of the NMOS transistor <b>5024</b> so that the output voltage is approximately the same as the floating gate voltage because the size and operating condition of the replica memory cell circuit <b>5020</b> is equivalent to that of the memory cell circuit <b>5002</b>. The drain of the PMOS transistor <b>5022</b> of the replica memory cell circuit <b>5004</b>-<b>0</b> provides an output data voltage, and the drain of the PMOS transistor <b>5022</b> of the other replica memory circuits <b>5004</b> provides an output reference voltage. The PMOS transistors <b>5022</b> of the replica memory cell circuits <b>5004</b>-<b>1</b> through <b>5004</b>-<b>4</b> are dimensioned to a ratio to the PMOS transistor <b>5012</b> of the memory cell circuit <b>5002</b> to set different output reference voltage levels. As an illustrative example, three levels are set for two-bit cells, and a fourth level is set as an erase reference.

P-0418[0418] In one embodiment, the transistors <b>5014</b> of the memory cell circuits <b>5002</b> and the transistors <b>5024</b> of the replica memory cell circuits <b>5004</b> are the same size.

P-0419[0419] In another embodiment, the replica memory cell circuits <b>5004</b>-<b>1</b> through <b>5004</b>-<b>4</b> are coupled to a corresponding memory cell circuit <b>5002</b>. In this case each memory cell circuit <b>5010</b> of the memory circuit <b>5002</b> has a different floating gate voltage FGR to generate different levels.

P-0420[0420]FIG. 51 is a schematic diagram illustrating a differential current sense amplifier <b>5100</b>.

P-0421[0421] The differential current sense amplifier <b>5100</b> comprises a plurality of current sources <b>5101</b> through <b>5106</b>, a plurality of PMOS transistors <b>5108</b> and <b>5109</b>, and a plurality of NMOS transistors <b>5112</b> and <b>5113</b>. The current sense amplifiers <b>5101</b> through <b>5104</b> are arranged as a differential sense amplifier to form an up output (OP) node <b>5120</b> between the current sources <b>5101</b> and <b>5103</b> and to form a down output (ON) node <b>5121</b> between the current sources <b>5102</b> and <b>5104</b>. The current source <b>5105</b> is parallel to the current source <b>5104</b>, and the current source <b>5106</b> is parallel with the current source <b>5103</b>. The current source <b>5106</b> is a data current source. The current source <b>5105</b> is a reference current source. In one embodiment, the current source <b>5105</b> replicates the reference current IREF from a reference memory cell, and the current source <b>5106</b> replicates the data current IDAT from a data memory cell.

P-0422[0422] The drain-source terminals of the PMOS transistor <b>5108</b> and the diode connected NMOS transistor <b>5112</b> are coupled between the up output node <b>5120</b> and ground. The drain- source terminals of the PMOS transistor <b>5109</b> and the NMOS transistor <b>5103</b> are coupled between the down output node <b>5121</b> and ground. The drains of the transistors <b>5109</b> and <b>5113</b> form an output node <b>5136</b>. A bias voltage VPBIAS applied to the gates of the PMOS transistors <b>5108</b> and <b>5109</b> establishes a bias point on the up node <b>5120</b> and the down node <b>5121</b>. The drain of the NMOS transistor <b>5112</b> biases the gate of the NMOS transistor <b>5113</b> to mirror the current.

P-0423[0423] In one embodiment, the fixed bias currents of the current sources <b>5101</b> and <b>5102</b> are set equal (I₅₁₀₁=I₅₁₀₂). The fixed bias currents of the current sources <b>5103</b> and <b>5104</b> are set equal to each other (I₅₁₀₃=I₅₁₀₄). The current of the current source <b>5101</b> is greater than the current of the current source <b>5103</b> (I₅₁₀₁>I₅₁₀₃). As an illustrative example, the current source <b>5103</b> provides a current of 30 μa and the current source <b>5101</b> provides a bias fixed current of 60 μa. The current in the NMOS transistor <b>5113</b>, the current in the NMOS transistor <b>5112</b> and the current in the PMOS transistor <b>5108</b> are equal to each other (I₅₁₁₃=I₅₁₁₂=I₅₁₀₈), and equal the difference of the current source <b>5101</b> and the sum of the currents from the current sources <b>5103</b> and <b>5106</b> (I₅₁₃₁=I₅₁₁₂=I₅₁₀₈=I₅₁₀₁−I₅₁₀₃−IDAT). This relationship follows from the NMOS transistor <b>5113</b> mirroring the current of the NMOS transistor <b>5112</b>. The current from the PMOS transistor <b>5109</b> is the difference between the current from the current source <b>5102</b> and the sum of the currents of the current sources <b>5104</b> and <b>5105</b> (I₅₁₀₉=I₅₁₀₄−IREF). Accordingly, the output voltage equals

VOUT=ΔI*R_OUT=(I₅₁₁₃-I₅₁₀₉)*R_OUT,

P-0424[0424] where the resistance R_OUTis the equivalent resistance at the output node (VOUT) <b>5116</b>. Equivalently the output voltage equals

VOUT=(IREF-DAT)*R_OUT,

P-0425[0425] which is the difference of the data and reference currents multiplied by the output resistance. Alternatively, the output from the output terminal <b>5136</b> may be a current that is the difference of the data and reference currents multiplied by a gain factor G, or

IOUT=G (IDAT-IREF),

P-0426[0426] where the gain factor G may be provided by an additional current gain circuit (not shown) having again G.

P-0427[0427]FIG. 52 is a schematic diagram illustrating a two-stage differential current sense amplifier <b>5200</b>.

P-0428[0428] The two-stage differential current sense amplifier <b>5200</b> comprises the differential current sense amplifier <b>5100</b> and an output stage <b>5202</b>. The output stage <b>5202</b> comprises a plurality of PMOS transistors <b>5204</b> and <b>5205</b> and a plurality of NMOS transistors <b>5206</b> and <b>5207</b>. The output stage <b>5202</b> operates as another gain stage. The output stage <b>5202</b> provides an output rail to rail level at an output node VOUT.

P-0429[0429] In another embodiment, the differential current sense amplifier stage <b>5100</b> includes an NMOS transistor <b>5113</b> that has a gate that is diode connected instead of being coupled to the NMOS transistor <b>5112</b>.

P-0430[0430] The drain-source terminals of the diode connected PMOS transistor <b>5204</b> and the NMOS transistor <b>5206</b> are coupled in series between the supply voltage and ground. The gate of the NMOS transistor <b>5206</b> is coupled to the drain of the NMOS transistor <b>5112</b>. The drain-source terminals of the PMOS transistor <b>5205</b> and the NMOS transistor <b>5207</b> are coupled in series between the supply voltage and ground and form an output voltage terminal <b>5216</b> of the common node of the drains of the transistors <b>5205</b> and <b>5207</b>. The gate of the PMOS transistor <b>5205</b> is coupled to the drain of the PMOS transistor <b>5204</b> to mirror the current of the PMOS transistor <b>5204</b>. The gate of the NMOS transistor <b>5207</b> is coupled to the drain of the NMOS transistor <b>5113</b>.

P-0431[0431]FIG. 53 is a schematic diagram illustrating a current difference sense amplifier <b>5300</b>.

P-0432[0432] The differential current sense amplifier <b>5300</b> comprises a reference current source <b>5302</b> that provides a reference current IREF, a data current source <b>5304</b> that provides a data current IDAT, and an output current source <b>5306</b> that provides an output current IOUT. The reference current source <b>5302</b> and the data current source <b>5304</b> are coupled in series between a power terminal and a ground terminal and form an output node <b>5308</b> that provides an output that is a current. The output current source <b>5306</b> is coupled between the output node <b>5308</b> and ground.

P-0433[0433] If the data current IDAT is greater than the reference current IREF, the output current IOUT equals zero. Otherwise, the output current IOUT=IREF-IDAT.

P-0434[0434] In another embodiment, the reference current source <b>5302</b> and the output current source <b>5306</b> may be interchanged.

P-0435[0435] In another embodiment, the output of the sense amplifier <b>5300</b> may be an output voltage VOUT equals the difference of the data and reference current multiplied by the output resistance, or

VOUT=V(OUT<b>1</b>)=(IREF-IDAT)*ROUT,

P-0436[0436] where ROUT is the equivalent resistance at the output node <b>5308</b>.

P-0437[0437] In another embodiment, the output current IOUT may be referred to the positive rail instead of ground, coupled between the power terminal and the output node <b>5308</b>, and such the output current IOUT=IDAT-IREF.

P-0438[0438] In another embodiment, another output current source may be coupled between the power terminal and the output node <b>5308</b> to generate a positive output current IOUTP(=IDAT-IREF) in addition to a negative output current IOUTN (=IREF-IDAT) from the output current source <b>5306</b>.

P-0439[0439]FIG. 54 is a schematic diagram illustrating a current difference sense amplifier <b>5400</b>.

P-0440[0440] The current difference sense amplifier <b>5400</b> comprises a reference current source <b>5402</b> that provides a reference current IREF, a data current source <b>5404</b> that provides a data current IDAT, a PMOS transistor <b>5406</b>, and a plurality of NMOS transistors <b>5408</b> and <b>5410</b>. The NMOS transistor <b>5410</b> provides an output current IOUT. The reference current source <b>5402</b> and the data current source <b>5404</b> are coupled in series between a power terminal and a ground terminal and form an output node <b>5412</b>. The drain-source terminals of the PMOS transistor <b>5406</b> and the diode connected NMOS transistor <b>5408</b> are coupled in series between the output node <b>5412</b> and ground. The drain-source terminals of the NMOS transistor are coupled between an output note <b>5414</b> and ground, and the gate of the NMOS transistor <b>5410</b> is biased by the drain of the PMOS transistor <b>5406</b>, which has a bias voltage VPBIAS applied to the gate of the PMOS transistor <b>5406</b> to establish the bias voltage on the node <b>5412</b>. In another embodiment, the diode connected NMOS transistor <b>5408</b> is connected directly to the node <b>5412</b>, i.e., without coupling through the PMOS transistor <b>5406</b>.

P-0441[0441] The transistors <b>5406</b>, <b>5408</b>, and <b>5410</b> form an output stage to buffer the current, and amplify a current difference. The current flow in the NMOS transistor <b>5408</b> equals the difference of the reference current IREF and the data current IDAT, or <b>15408</b>=IREF-IDAT.

P-0442[0442] The output current IOUT equals the difference of the data and reference currents multiplied by a gain factor G, or

IOUT=G (IDAT-IREF).

P-0443[0443] The size of the NMOS transistor <b>5410</b> equals the gain factor G times the size of the NMOS transistor <b>5408</b>.

P-0444[0444]FIG. 55 is a schematic diagram illustrating a dynamic sense amplifier <b>5500</b>.

P-0445[0445] The dynamic sense amplifier <b>5500</b> comprises a data memory cell <b>5502</b>, a reference memory cell <b>5504</b>, a plurality of NMOS transistors <b>5506</b>, <b>5508</b>, <b>5510</b>, <b>5512</b>, <b>5514</b>, <b>5516</b>, and a comparator <b>5518</b>. For clarity, only one data memory cell <b>5502</b> and one reference memory cell <b>5504</b> are shown for subarray, but a subarray comprises a plurality of data memory cells <b>5502</b> arranged in columns and a plurality of reference cells <b>5504</b> arranged-in columns. Each column of data memory cells <b>5502</b> includes corresponding NMOS transistors <b>5506</b> and <b>5508</b> for decoding. Each reference column comprises NMOS transistors <b>5510</b> and <b>5512</b> for decoding. Only one column with one data memory cell <b>5502</b> is shown.

P-0446[0446] The comparator <b>5518</b> determines the voltage of the data memory cell <b>5502</b> by comparing the cell voltage (VCELLD) on a cell bitline <b>5520</b> to a reference voltage (VCELLR) on a reference bitline <b>5522</b>. The NMOS transistor <b>5514</b> couples a bias voltage (VBIAS) <b>5524</b> to the data cell voltage <b>5520</b> in response to an initialize bitline (INITBL) signal <b>5526</b>. The NMOS transistor <b>5516</b> couples the bias voltage signal <b>5524</b> to the reference cell voltage <b>5522</b> in response to the initialized bitline signal <b>5526</b>. The cell bitline <b>5520</b> has a capacitance shown as a capacitor <b>5528</b>. The reference bitline <b>5522</b> has a capacitance shown as a capacitor <b>5530</b>. Additional capacitance can be added to the bit lines <b>5520</b> and <b>5522</b> to achieve a desired value of capacitance. A data control gate voltage (VCGR) <b>5532</b> is applied to the control gate of the data memory cell <b>5502</b>. A reference control voltage (VCGEFR) <b>5534</b> is applied to the control gate of the reference memory cell <b>5504</b>. A comparator enable (ENBLADIFA) signal <b>5536</b> enables the comparator <b>5518</b>.

P-0447[0447]FIG. 56 is a graph illustrating the control signals and voltages of the dynamic sense amplifier <b>5500</b>.

P-0448[0448] The initialize bitline signal <b>5526</b> is set to high to enable the NMOS transistors <b>5514</b> and <b>5516</b> to initialize the bitlines <b>5520</b> and <b>5522</b>, respectively, at a bias voltage (VBIAS) <b>5524</b>. The control gate voltage of the data control gate voltage <b>5532</b> and the reference control gate voltage <b>5534</b> are applied during this time. Once sufficient voltage is developed between the data cell voltage (VCELLD) on the cell bitline <b>5520</b> and the reference cell voltage on the reference cell bitline <b>5522</b>, the comparator <b>5518</b> is enabled to amplify the difference voltage. As an illustrative example, for a difference current of 0.5 μa, a bitline capacitance of 0.5 pF, and a voltage of 10 mV is developed in 10 nanoseconds from the relationship that 10 mV equals 0.5 μa times 10 nanoseconds divided by 0.5 pF. In this embodiment, no load, such as pullup, is needed for the sensing circuitry. In another embodiment, the data cell voltage (VCELLD) <b>5520</b> and the reference cell voltage (VCELLR) <b>5522</b> go in a positive direction during the signal development period instead of a negative direction as shown in FIG. 56. Voltage mode sensing or current mode sensing may be utilized for memory cells <b>5502</b> and <b>5504</b>.

P-0449[0449]FIG. 57 is a schematic diagram illustrating a dynamic charge sense amplifier <b>5700</b>.

P-0450[0450] The dynamic charge sense amplifier <b>5700</b> comprises a data memory cell <b>5502</b>, a reference memory cell <b>5504</b>, NMOS transistors <b>5506</b>, <b>5508</b>, <b>5510</b>, <b>5512</b>, <b>5514</b> and <b>5516</b> arranged in a similar manner as the dynamic sense amplifier <b>5500</b> of FIG. 55. The dynamic charge sense amplifier <b>5700</b> further comprises a plurality of capacitors <b>5701</b> through <b>5704</b>, a comparator <b>5706</b>, and a plurality of switches <b>5708</b> and <b>5710</b>. The capacitor <b>5701</b> couples the cell voltage line <b>5520</b> to a positive input of the differential comparator <b>5706</b>. The capacitor <b>5702</b> couples the reference cell voltage <b>5522</b> to a negative input of the comparator <b>5706</b>. The switches <b>5708</b> and <b>5710</b> couple respective inverted and non-inverted outputs <b>5712</b> and <b>5713</b> to the positive and negative inputs of the comparator <b>5706</b>. The capacitors <b>5703</b> and <b>5704</b> are coupled in parallel to the switches <b>5708</b> and <b>5710</b>, respectively. An autozero signal <b>5716</b> is applied to the switches <b>5708</b> and <b>5710</b> and is an active low to enable voltage signal development of the comparator <b>5706</b>. In one embodiment, the autozero signal <b>5716</b> is buffered from, and thus is logically the same as, the initialized bitline signal <b>5526</b>. The negative and positive nodes of the comparator <b>5706</b> are initialized or autozeroed at a bias in an autozero state. The capacitors <b>5703</b> and <b>5704</b> cause the comparator <b>5706</b> to function as a gain amplifier with a gain equal to the ratio of the capacitances of the capacitors <b>5701</b> and <b>5703</b>. In another embodiment, the dynamic charge sense amplifier <b>5700</b> does not include the capacitors <b>5703</b> and <b>5704</b>, and the comparator <b>5706</b> functions as a comparator with the capacitor <b>5701</b> and <b>5702</b> providing capacitive coupling.

P-0451[0451] The systems described above may be used for Inverse Voltage Mode Sensing, No Current (Digital) Multilevel Mode Sensing, or Inverse Current Mode Sensing with appropriate modification, and may include an autozero function of the sense amplifier. The autozero function may include equalizing the input and output of the sense amplifier before sensing or the storage of the reference cell sensing before the data cell sensing to reduce signal path mismatch.

P-0452[0452]FIG. 58 is a flow diagram illustrating a single bit current sensing binary search. During the binary search, the data value of a cell being read is analyzed one bit at a time. As an illustrative example, a three-bit data memory cell for an eight value memory cell is described in which the bits are B<b>2</b>, B<b>1</b>, and B<b>0</b> with bit B<b>2</b> being the most significant bit and bit B<b>0</b> being the least significant bit. As an overview of the binary search, the data cell is set into a current sensing condition and the sensed data current is compared to a reference current from the reference memory cell. As part of the binary search, the full range of current values is divided into half and the data cells determine whether the data value is in the upper or lower half of the voltage range. After this determination, the selected one-half current range is divided into two one-quarter current ranges, and the data current is analyzed to determine which one-quarter range the data value is in. The one-quarter range is then divided into half and the data value is analyzed to determine which of the one-eighth ranges the data value is in, and likewise for each additional bit. For a three-bit data cell, three such determinations are made. For an n bit data cell, a number n determinations are made during the single bit current sensing binary search. The eight values can be arbitrary values.

P-0453[0453] The data cells are set into a sensing condition, and the data memory cell (IDAT) bitline is set into an autozero condition and the data cells are read (block <b>5802</b>). The data range being evaluated is divided into half and the data current (IDAT) is analyzed to determine whether the data current is in the upper or lower half of the current range. The data current (IDAT) is compared to a reference current from the reference memory cells corresponding to the mid-point of the entire data range (block <b>5804</b>). For example, for a three-bit system, the data current (IDAT) is compared to the reference current for the fourth memory level (IR<b>4</b>). If the sensed data current (IDAT) is greater than or equal to the fourth level reference current (IR <b>4</b> ), the first bit being detected B<b>2</b> is set to a high value (B<b>2</b>=1) (block <b>5806</b>). The data current (IDAT) is in the upper half of the data range, and the upper half of the data range is divided in half or into two one-quarter data ranges. The data current (IDAT) is compared to the midpoint reference current of the upper half which in the illustrative example corresponds to the sixth reference current (IR <b>6</b> ). If the data current (IDAT) is greater than or equal to the sixth reference current (IR<b>6</b>) (block <b>5808</b>), the second data bit, B<b>1</b>, is set high (B<b>1</b>=1) (block <b>5810</b>), and the data current (IDAT) is in the upper half of the data range. The upper quarter of the data range is again divided into half and the data current (IDAT) is compared to the bit level current of the upper quarter range, which is the seventh reference current (IR<b>7</b>). If the data current (IDAT) is greater than or equal to the seventh reference current (IR<b>7</b>) (block <b>5812</b>), the third bit BO is set high (B<b>0</b>=1) (block <b>5814</b> ). Thus in this case, the data of the cell corresponds to B<b>2</b>, B<b>1</b> and B<b>0</b> equals ‘111’. Otherwise if the data current (IDAT) is less than the seventh reference current (IR<b>7</b>) (block <b>5812</b>), the data current (IDAT) is in the bottom half of the upper quarter of the data range and the last bit B<b>0</b> is set low (B<b>0</b>=0) (block <b>5816</b>), and the data in the cell corresponds to B<b>2</b>B<b>1</b>B<b>0</b> equals ‘110’.

P-0454[0454] On the other hand, if the data current (IDAT) is less than the sixth reference current (IR<b>6</b>) (block <b>5808</b>), the data is in the quarter range that is in the bottom half of the top half of the voltage range and the second bit B<b>1</b> is set low (B<b>1</b>=0) (block <b>5818</b>). This quarter range is then divided into two sections corresponding to one-eighth of the overall data range and the data current (IDAT) is compared to the fifth reference current (IR<b>5</b>). If the data current (IDAT) is greater than or equal to the fifth reference current (block <b>5820</b>), the data current (IDAT) is in the top half of the quarter range, and the third data bit BO is set high (B<b>0</b>=1) (block <b>5822</b>), and the data in the cell corresponds to B<b>2</b>B<b>1</b>B<b>0</b> equals ‘101’. Otherwise, if the data current (IDAT) is less than the fifth reference current (block <b>5820</b>), the third bit B<b>0</b> is set low (B<b>0</b>=0) (block <b>5816</b>), and the data in the cell corresponds to B<b>2</b>B<b>1</b>B<b>0</b> equals ‘100’.

P-0455[0455] On the other hand, if the data current (IDAT) is less than the fourth reference current (IR<b>4</b>) (block <b>5804</b>), the data is in the lower half of the current range, and the first bit B <b>2</b> is set low (B<b>2</b>=0) (block <b>5824</b>). The half range is divided into two halves corresponding to one-quarter ranges of the overall data range, and the data current (IDAT) is compared to the second reference current (IR<b>2</b>). If the data current (IDAT) is greater than or equal to the second reference current (block <b>5826</b>), the data current (IDAT) is in the upper quarter range of the bottom half range, and the second data bit B<b>1</b> is set high (B<b>1</b>=1) (block <b>5828</b>). Again, the quarter range is divided into one-eighth ranges and the data current (IDAT) is compared to the third reference current (IR<b>3</b>). If the data current (IDAT) is greater than or equal to the third reference current (block <b>5830</b>), the data current (IDAT) is in the top half of this quarter range, and the third data bit B<b>0</b> is set high (B<b>0</b>=1) (block <b>5832</b>), and the data in the cell corresponds to B<b>2</b>B<b>1</b>B<b>0</b> equals ‘011’. Otherwise, if the data current (IDAT) was less than the third reference current (block <b>5830</b>), the third bit B<b>0</b> is set low (B<b>0</b>=0) (block <b>5834</b>), and the data in the cell corresponds to B<b>2</b>B<b>1</b>B<b>0</b> equals ‘010’.

P-0456[0456] On the other hand, if the data current (IDAT) is less than the second data current (IR<b>2</b>) (block <b>5826</b>), the data is in the quarter range that is in the bottom half of the range, and the second bit B<b>1</b> is set low (B<b>1</b>=0) (block <b>5836</b>). This quarter range is then divided into two sections corresponding to one-eighth of the overall data range and the data current (IDAT) is compared to the first reference current (IR<b>1</b>). If the data current (IDAT) is greater than or equal to the first reference current (block <b>5838</b>), the data current (IDAT) is in the top half of this quarter range, and the third bit B<b>0</b> is set high (B<b>0</b>=1) (block <b>5840</b>), and the data of the cell corresponds to B<b>2</b>B<b>1</b>B<b>0</b> equals ‘001’. Otherwise if the data current (IDAT) is less than the first reference current (block <b>5838</b>), the third bit B<b>0</b> is set low (B<b>0</b>=0) (block <b>5834</b>), and the data in the cell corresponds to B<b>2</b>B<b>1</b>B<b>0</b> equals ‘000’.

P-0457[0457]FIG. 59 is a flow diagram illustrating a multiple bit current sensing binary search. The data cell may be connected to multiple sense amplifiers for comparing to different reference currents at the same time to reduce the number of steps of the search. During a first search stage, the data current (IDAT) from the data memory cell is applied to a plurality of comparators, which each determine the relationship between the data current and a reference level. One of the comparators compares the data current to a reference level that is in the middle of the data range. The results of this comparison are used to determine which reference levels are applied to the comparators during a second search stage. More particularly, the reference levels in the determined data range are applied. Further, the results of some of the data determination are discarded.

P-0458[0458] As an illustrative example, the data cell is a three-bit data cell that stores bits B<b>2</b>B<b>1</b>B<b>0</b> in a manner similar to that described above for FIG. 58. Further to the illustrative example, two bits are determined per comparison stage. The three-bit system has eight data values with corresponding eight reference values. In this illustrative example, three comparators are used to compare the data current to the three different reference levels. In the first comparison, the full range is divided into eight ranges.

P-0459[0459] The data cells are put into a current sensing condition and the data memory cell (IDAT) bitline is set into an autozero condition and the data cells are read (block <b>5902</b> ). The data current (IDAT) is compared to a fourth reference level (IR<b>4</b>) (block <b>5904</b>), a sixth reference current (IR<b>6</b>) (block <b>5906</b>), and a second reference current (IR<b>2</b>) (block <b>5908</b>). The comparison of the data current (IDAT) to the fourth reference level (IR<b>4</b>) determines whether the first data bit B<b>2</b> is set high or low. If the data current (IDAT) is greater than or equal to the fourth reference current (IR<b>4</b>) (block <b>5904</b>), the first data bit B<b>2</b> is set high (B<b>2</b>=1) (block <b>5910</b>), or otherwise the first data bit B<b>2</b> is set low (B<b>2</b>=0) (block <b>5912</b>). The data current (IDAT) is compared to the sixth reference current (IR<b>6</b>) to determine the second data bit B<b>1</b>. If the data current (IDAT) is greater than or equal to the sixth reference current (IR<b>6</b>) (block <b>5906</b>), the second data bit B<b>1</b> is set high (B<b>1</b>=1) (block <b>5914</b>), or otherwise the second data bit B<b>1</b> is set low (B<b>1</b>=0) (block <b>5924</b>). The data current (IDAT) is compared to the second reference current (IR<b>2</b>). If the data current (IDAT) is greater than or equal to the second reference current (IR <b>2</b> ) (block <b>5908</b>), the second data bit B<b>1</b> is set high (B<b>1</b>=1) (block <b>5928</b>), or otherwise the second data bit B<b>1</b> is set low (B<b>1</b>=0) (block <b>5938</b> ). If the comparison at block <b>5904</b> determines that the data current (IDAT) is greater than or equal to the fourth reference current, then the data from the comparison at block <b>5908</b> is discarded (block <b>5934</b>). On the other hand, if the data current (IDAT) is less than the fourth reference current (IR<b>4</b>) (block <b>5904</b>), the comparison of block <b>5906</b> is discarded (block <b>5922</b>).

P-0460[0460] During the second stage, the third data bit B<b>0</b> is determined. If the data current (IDAT) comparison to the sixth reference current (IR<b>6</b>) (block <b>5906</b>) indicates the second bit B <b>1</b> is set high (B<b>1</b>=1) (block <b>5914</b>), the second comparison operation compares the data current (IDAT) to the seventh reference current (IR<b>7</b>). If the data current (IDAT) is greater than or equal to the seventh reference current (IR<b>7</b>) (block <b>5916</b>), the third data bit B<b>0</b> is set high (B=1) (block <b>5918</b>), and the data in the cell corresponds to B<b>2</b>B<b>1</b>B<b>0</b> equals ‘111’. On the other hand, if the data current (IDAT) is less than the seventh reference current (IR<b>7</b>) (block <b>5916</b>), the third data bit B<b>0</b> is set low (BO=0) (block <b>5920</b>), and the data in the cell corresponds to B <b>2</b> BlBO equals ‘110’.

P-0461[0461] On the other hand, if the data current (IDAT) comparison to the sixth reference current IR<b>6</b> (block <b>5906</b>) indicates the second bit B<b>1</b> is set low (B<b>1</b>=0) (block <b>5925</b>), the second comparison operation compares the data current (IDAT) to the fifth reference current (IR<b>5</b>). If the data current (IDAT) is greater than or equal to the fifth data current (block <b>5924</b>), the third data bit B<b>0</b> is set high (B<b>0</b>=1) (block <b>5926</b>), and the data in the cell corresponds to B<b>2</b>B<b>1</b>B<b>0</b> equals ‘101’. On the other hand, if the data current (IDAT) is less than the fifth reference current (IR<b>5</b>) (block <b>5924</b>), the third data bit B<b>0</b> is set low (B<b>0</b>=0) (block <b>5920</b>), and the data in the cell corresponds to B<b>2</b>B<b>1</b>B<b>0</b> equals ‘100’.

P-0462[0462] If the data current comparison to the second reference current IR<b>2</b> indicates the second bit B<b>1</b> is set high (B<b>1</b>=1) (block <b>5928</b>), the second comparison operation compares the data current to the third reference current IR<b>3</b>. If the data current (IDAT) is greater than or equal to the third reference current IR<b>3</b> (block <b>5930</b>), the third bit B<b>0</b> is set high (B<b>0</b>=1) (block <b>5932</b>), and the data in the cell corresponds to B<b>2</b>B<b>1</b>B<b>0</b> equals ‘011’. On the other hand, if the data current (IDAT) is not greater than or equal to the reference current IR<b>3</b> (block <b>5930</b>), the third bit BO is set low (BO=<b>0</b> ) (block <b>5936</b> ), and the data in the cell corresponds to B<b>2</b>B<b>1</b>B<b>0</b> equals ‘010’.

P-0463[0463] On the other hand, if the data current (IDAT) comparison to the second reference current IR<b>2</b> (block <b>5908</b>) indicates a second bit B<b>1</b> is set low (B<b>1</b>=0) (block <b>5938</b>), the second comparison operation compares the data current (IDAT) to the first reference current (IR<b>1</b>). If the data current (IDAT) is greater than or equal to the first data current (IR<b>1</b>) (block <b>5940</b>), the third data bit BO is set high (B<b>0</b>=1) (block <b>5942</b>), and the data in the cell corresponds to B<b>2</b>B<b>1</b>B<b>0</b> equals ‘001’. On the other hand, if the data current (IDAT) is less than the first reference current (IR<b>1</b>) (block <b>5940</b>), the third data bit BO is set low (B<b>0</b>=0) (block <b>5936</b>), and the data in the cell corresponds to B<b>2</b>B<b>1</b>B<b>0</b> equals ‘000’.

P-0464[0464] By increasing the number of comparisons done at one time to thereby determine multiple bits in one comparison cycle, the number of sequential comparison cycles may be reduced to increase the binary search operation.

P-0465[0465]FIG. 60 is a block diagram illustrating a memory system <b>6000</b> including built-in concurrent byte redundancy.

P-0466[0466] The memory system <b>6000</b> may be a modified version of the super-high density, non-volatile multilevel memory integrated circuit system of FIG. 2A. For clarity, FIG. 60 shows only the portions of the memory that are different. The memory system <b>6000</b> includes a byte decoder <b>6002</b>, a multiplex column decoder <b>6004</b>, and a memory array <b>6006</b>. The byte decoder <b>6002</b> replaces the byte decoder <b>152</b> of FIG. 2A. The memory array <b>6006</b> is shown as a single page of the memory array <b>100</b>. The multiplexer column decoder <b>6004</b> replaces the page select circuit <b>120</b> and the byte select circuit <b>140</b>. As an illustrative example, a page of 512 bytes is described, but other sizes of pages may be used.

P-0467[0467] The memory array <b>6006</b> includes memory cells organized as a normal data region <b>6008</b>, a redundant data region <b>6010</b>, and a bad byte locator <b>6012</b>. As an illustrative example, the memory array <b>6006</b> comprises 512 bytes of normal data in the normal data region <b>6008</b>, one redundant byte in the redundant data region <b>6010</b>, and 10 bits for the bad byte locator <b>6012</b>. The bad byte locator <b>6012</b> includes an indicator of whether a bad byte exists in the normal data region <b>6008</b> of the memory array <b>6006</b>, and includes an address of the location of the bad byte. In the illustrative embodiment, the bad byte locator <b>6012</b> includes one bit for the indicator and nine bits for the address of the bad byte. The byte decoder <b>6002</b> decodes an address <b>6014</b>, which is shown illustratively in FIG. 60 as an address <b>6016</b> for the 512 bytes of normal data, an address <b>6018</b> for one redundant byte and an address <b>6020</b> for 10-bit bad byte locator, and addresses the page of the memory array <b>6006</b>, and applies the decoded address to the multiplexer column decoder <b>6004</b> to address the memory array <b>6006</b>.

P-0468[0468] In one embodiment, the bad byte latch may be configured to store a predetermined data pattern, such as ‘FF’ to disable programming of the bad byte of the normal data region <b>6008</b>.

P-0469[0469] During byte loading, the byte decoder <b>6002</b> is addressed by the address <b>6014</b> to address the page of the memory array <b>6006</b> for loading data into the normal data region <b>6008</b>, the redundant data region <b>6010</b>, and the bad byte locator <b>6012</b>. When the bad byte locator <b>6012</b> indicates a bad byte in the normal data region <b>6008</b>, the byte data corresponding to this address is loaded into the redundant byte <b>6018</b>. In one embodiment, the bad byte latch may remain with a predetermined data pattern, e.g., ‘FF’, to disable programming. In one embodiment, the bad byte locator <b>6012</b> is programmed during testing at another location, such as the manufacturer, with the bad byte indicator and the byte address of the location in the normal data region <b>6008</b> that is bad.

P-0470[0470] During a program and verify operation, the byte decoder <b>6002</b> addresses all locations of the normal data region <b>6008</b> and the redundant data region <b>6010</b> for writing the data, for example 513 bytes, into the memory cells of the memory array <b>6006</b>. The bad byte locator <b>6012</b> is used by the byte decoder 6002 to determine whether the normal data region <b>6008</b> has a bad byte and the address of the bad byte from which the byte decoder <b>6002</b> determines the data for storing in the redundant data region <b>6010</b>. In one embodiment, the bad byte is not programmed if an indicator ‘FF’ is used to disable the program and verify for that bad byte.

P-0471[0471] During a read operation, the byte decoder <b>6002</b> addresses all addresses in the page of the memory array <b>6006</b> to read the normal data region <b>6008</b>, the redundant data region <b>6010</b>, and the bad byte locator <b>6012</b>. In the illustrative example, all 513 bytes of data and the 10 bits of the bad byte locator are read. The byte decoder <b>6002</b> decodes the bad byte locator <b>6012</b> to determine whether the byte redundancy is invoked and the address of the bad byte of the normal data region <b>6008</b>. If the byte redundancy is invoked, the address of the bad byte is used to switch the data from the redundant data region <b>6010</b>, and ignore the data read from the bad byte of the normal data region <b>6008</b>.

P-0472[0472] During an erase operation, the byte decoder <b>6014</b> addresses all memory cells in the normal data region <b>6008</b> and the redundant data region <b>6010</b>. In the illustrative embodiment, the 513 bytes are erased, but the bad byte locator <b>6012</b> is not erased. In another embodiment, the erase includes a process of storing the data in the bad byte locator <b>6020</b> in a latch, erasing the entire memory array <b>6006</b> and rewriting the data stored in the latch into the bad byte locator <b>6020</b>.

P-0473[0473] In another embodiment, the memory cells may be verified and read in different sensing modes. For example, the memory cell may be verified by placing the memory cell in a voltage mode while reading of the memory cell may be done in a current sensing mode.

P-0474[0474] In another embodiment, additional reference currents may be formed by interpolating or extrapolating the values stored in the reference memory cells. For example, the reference memory cells may store data in 0.1 μa increments in a range from 0.0 to 1.6 μa. A reference current may be interpolated from currents with adjacent values stored in the reference memory cells, such as by forming a reference current as an average value between adjacent reference values. For example, the first memory cell may store 0.1 μa and a second memory cell may store 0.2 μa. A reference level of 0.15 μa may be generated by dividing the memory range into two. A reference current outside the range may be formed by extrapolation.

P-0475[0475] In the foregoing description, various methods and apparatus, and specific embodiments are described. However it should be obvious to the one conversant in the art, various alternatives, modifications, and changes may be possible without departing from the spirit and the scope of the invention which is defined by the metes and bounds of the appended claims.