Data processor

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a data processor with data transfer control circuits such as a direct memory access controller (DMAC) and a data transfer controller(DTC), as well as peripheral circuits such as an analog-to-digital converter and a timer counter, and more particularly to a technology effective in decreasing the number of data registers in peripheral circuits incorporated into a single-chip microcomputer.

[0003] 2. Description of the Related Art

[0004] An analog-to-digital converter incorporated into a single-chip microcomputer usually has a plurality of analog input channels, converts analog signals input from the selected analog input channel to digital data, and stores the resultant digital data in its data registers adapted for the analog input channels. In other words, a plurality of data registers are provided corresponding to the number of the analog input channels. The analog-to-digital converter is similar to a free running counter with its input capture registers provided in a one-to-one correspondence with input events in that the data registers of the analog-to-digital converter are individually provided.

[0005] The analog-to-digital converter sends a data transfer request to a direct memory access controller when converted data is stored in its data register. In response to this request, the direct memory access controller performs transfer controls to transfer the converted data in the data resister to other devices such as a memory using the corresponding data transfer channel for which data transfer control conditions have been set. If data conversion is performed with other analog input channel, other data transfer channel, for which other data transfer control conditions are set, is used to transfer the converted data to a memory. The direct memory access controller comprises control registers for which a data transfer control conditions are set for each data transfer channel.

[0006] In the case of using a data transfer controller instead of a direct memory access controller, data transfer conditions are previously set in a memory, so that when a data transfer request is received, the data transfer control conditions corresponding to the request is loaded from the memory to the control register of the data transfer controller and the data transfer is performed according to the loaded conditions. Unlike a direct memory access controller, a data transfer controller doesn't need to comprise control registers for which a data transfer control conditions are set for each data transfer channel, but it is required to load data for data transfer control from the memory to its register every time a request of data transfer is received.

[0007] The single-chip microcomputers are described in “LSI HANDBOOK,” Tokyo: Ohmsha Ltd., Nov. 30, 1984, pp540-541.

SUMMARY OF THE INVENTION

[0008] From a study of the peripheral circuit such as an analog-to-digital converter and data transfer control circuit such as a direct memory access controller, we found as follows.

[0009] If a data register is provided for each input channel in peripheral circuits such as an analog-to-digital converter, an increase in a chip area occupied by data registers become considerable with an increasing number of input channels due to the extension of their functionality.

[0010] If a different data transfer request is caused in a direct memory access controller every time a peripheral circuit stores data in a data register corresponding to an input channel, the data transfer channels of the direct memory access controller must be at least as many as the input channels. Each data transfer channel of the direct memory access controller has a control register for which transfer control conditions such as a source address, a destination address, and the number of transferred words are set, so that an increase in a chip area occupied by the transfer control registers become considerable with an increasing number of data transfer channels.

[0011] If a different data transfer request is caused in a data transfer controller every time a peripheral circuit stores data in a data register corresponding to an input channel, the data transfer controller is required to internally transfer data to be transfer-controlled from the memory to a control register for each transfer request, which inevitably results in the reduction of data processing efficiency.

[0012] It is an object of the invention to provide a data processor in which the number of data registers can be reduced with respect to the number of the input channels of a peripheral circuit.

[0013] It is another object of the invention to provide a data processor not required to increase the number of data transfer channels even if the input channels of a peripheral circuit are increased.

[0014] It is a further object of the invention to provide a data processor in which the internal transfer processing to transfer data to be transfer-controlled from a memory to a transfer control register in response to a data transfer request from a peripheral circuit is reduced.

[0015] It is a still further object of the invention to provide a data processor wherein an increase in the number of data registers due to an increasing number of the input channels of peripheral circuits can be suppressed and the overhead resulting from data transfer control can be reduced.

[0016] The above and other objects and novel features of the invention will appear from the following description and the accompanying drawings herein.

[0017] The typical embodiments of the invention disclosed herein will be described in brief below.

[0018] [<b>1</b>] Destination Address Low-order Control by Peripheral Circuit

[0019] In the first embodiment of the invention, a peripheral circuit performs the processing of data input from input terminals such as input channels to the peripheral circuit, and the results are transferred to destinations, the low-order bits of which can be controlled by the peripheral circuit.

[0020] The data processor comprises a central processing unit, a data transfer control circuit for controlling data transfers under control of the central processing unit, and a peripheral circuit for requesting data transfers. The peripheral circuit selects an input terminal thereof such as an input channel, processes input data from the selected input terminal, requests the transfer of the processing result, and outputs identification information (CH<b>2</b> to CH<b>0</b>) which permits the identification of the selected input terminal. The data transfer control circuit has a destination address register (DAR) with its low-order bits variable according to the identification information from the peripheral circuit.

[0021] Therefore, the peripheral circuit is not required to comprise data registers for storing the processing results of input data according to the number of input terminals. The low-order bits of a destination address register are automatically updated based on the identification information from the peripheral circuit, so that the data transfer channels of data transfer control circuits such as a direct memory access controller are not required to be increased with respect to the number of the input channels of the peripheral circuit. It is not necessary to perform an internal transfer processing of data to be transfer-controlled from a memory to a control register each time the peripheral circuit requests data transfer to a data transfer control circuit such as a data transfer controller.

[0022] For example, the peripheral circuit is an analog-to digital converter having a converter section and a converter control section for converting analog signals to digital data. The converter section has analog input channels and a conversion data register shared for storing the results of conversion of input signals from analog input channels. The converter control section requests the transfer of conversion results stored in the conversion data register and outputs code information as an above-described identification information which permits the identification of the analog input channel corresponding to its conversion result.

[0023] In more detailed description, the converter section may be arranged to have an analog multiplexer for selecting one of analog input channels and convert analog signals from the analog input channel selected by the analog multiplexer in digital data in a successive approximation procedure.

[0024] In this case the converter control section may be arranged to have a channel-select register for holding selection information which allows the multiplexer to select an analog input channel, and output the selection information held in the channel-select register as above-described code information. Additionally, to support a scan mode for analog input channels, the converter control section may be provided with computing element for incrementing the value in the channel-select register to activate the increment operation of the computing element one per scan execution.

[0025] The data transfer control circuit is a circuit for controlling data transfers by loading transfer control conditions from a memory in response to data transfer requests, and may be arranged as a data transfer controller wherein address information set in a destination address register can be overwritten with above-described identification information according to the loaded transfer control conditions.

[0026] Also above-described data transfer control circuit is a circuit for controlling data transfers according to transfer control conditions previously set by a central processing unit, and may be arranged as a direct memory access controller wherein address information set as transfer control conditions in a destination address register can be overwritten with above-described identification information.

[0027] The data processor may have a RAM that can be addressed using address information held by the destination address register. The data processor may be formed in a single semiconductor chip with a RAM.

[0028] [<b>2</b>] Destination Address Low-order Control by Peripheral Circuit

[0029] In the second embodiment of the invention, a peripheral circuit performs the processing in response to the occurrence of events, and the results are transferred to destinations, the low-order bits of which can be controlled by the peripheral circuit.

[0030] The data processor comprises a central processing unit, a data transfer control circuit for controlling data transfers under control of central processing unit, and a peripheral circuit for requesting data transfers. The peripheral circuit performs processing in response to the occurrence of an event to be dealt with, requests the transfer of the processing result, and outputs identification information (EIT<b>1</b> to EIT<b>0</b>) which permits the identification of the event occurrence corresponding to the processing result. The data transfer control circuit has a destination address register (DAR) with its low-order bits variable according to identification information from the peripheral circuit.

[0031] Therefore, the peripheral circuit is not required to comprise data registers for storing the processing results in response to the inputs of events, one for each event input channel. The low-order bits of a destination address register are automatically updated based on the identification information from the peripheral circuit, so that the data transfer channels of data transfer control circuits such as direct memory access controllers are not required to be increased with respect to the number of the input channels of the peripheral circuit. It is not necessary to perform a internal transfer processing of data to be transfer-controlled from a memory to a control register each time the peripheral circuit requests data transfer to a data transfer control circuit such as data transfer controllers.

[0032] For example, the peripheral circuit is a free running timer having a counter section and a counter control section, wherein the counter section comprise a counting element and a data register for storing the counted values of the counting element. The counter control section stores the counted values of the counting element in the data register in response to the notice of event occurrence from event input channels to be dealt with, requests the transfers of the counted values stored in the data register, and outputs code information which enables the event input channel with such a change to be discriminated from other event input channels as above-described identification information. In this case, the data register is an input capture register shared by a plurality of event input channels.

[0033] Above-described data transfer control circuit is a circuit for controlling data transfers by loading transfer control conditions from a memory in response to data transfer requests, and may be arranged as a data transfer controller wherein address information set in the destination address register can be overwritten with above-described identification information according to the loaded transfer control conditions.

[0034] Also above-described data transfer control circuit is a circuit for controlling data transfers according to transfer control conditions previously set by a central processing unit, and may be arranged as a direct memory access controller wherein address information set as transfer control conditions in the destination address register can be overwritten with above-described identification information.

[0035] The data processor may have a RAM that can be addressed using address information held by the destination address register. The data processor may be formed in a single semiconductor chip with a RAM.

[0036] [<b>3</b>] Source and Destination Address Low-order Control by Peripheral Circuit

[0037] In the third embodiment of the invention, a peripheral circuit performs the processing of data input from input terminals such as data input channels, and the results are transferred to sources and destinations, the low-order bits of which can be controlled by the peripheral circuit.

[0038] The data processor comprises a central processing unit, a data transfer control circuit for controlling data transfers under control of central processing unit, and a peripheral circuit for requesting data transfers. The peripheral circuit selects a data input channel thereof, performs a predetermined processing for input data from the selected data input channel, requests the transfer of the processing result, and outputs identification information (CH<b>2</b> to CH<b>0</b>) which permits the identification of the data input channel corresponding to the processing result. The data transfer control circuit has a source address register (SAR) and a destination address register (DAR) with their low-order bits variable according to the identification information from the peripheral circuit.

[0039] The peripheral circuit has a plurality of data registers for storing the processing results of input data from the data input channels, the low-order bits of the source address and destination address of such data registers are automatically updated based on the identification information from the peripheral circuit, so that the data transfer channels of data transfer control circuits such as direct memory access controllers are not required to be increased with respect to the number of the input channels of the peripheral circuit. It is not necessary to perform a internal transfer processing of data to be transfer-controlled from a memory to a control register each time the peripheral circuit requests data transfer to a data transfer control circuit such as data transfer controllers. The third embodiment is more effective, for example, in the case that the data input intervals from data input channels are short in comparison with the first embodiment. In other words, it is useful when data registers provided corresponding to individual data input channels are required to act as data buffers.

[0040] [<b>4</b>] Source and Destination Address Low-order Control by Peripheral Circuit

[0041] In the fourth embodiment, a peripheral circuit performs the processing in response to the occurrence of events, and the results are transferred to sources and destinations, the low-order bits of which can be controlled by the peripheral circuit.

[0042] The data processor comprises a central processing unit, a data transfer control circuit for controlling data transfers under control of central processing unit, and a peripheral circuit for requesting data transfers. The peripheral circuit performs processing in response to the notice of event occurrence from event input channels to be dealt with, requests the transfer of the processing result, and outputs identification information (EIT<b>1</b> to EITO) which permits the identification of the event input channel corresponding to the processing result. The data transfer control circuit has a source address register (SAR) and a destination address register (DAR) with their low-order bits variable according to the identification information from the peripheral circuit.

[0043] The peripheral circuit has a plurality of data registers for storing the processing results in response to the notice of the occurrence of events, the low-order bits of the source address and destination address of such data registers are automatically updated based on the identification information from the peripheral circuit, so that the data transfer channels of data transfer control circuits such as direct memory access controllers are not required to be increased with respect to the number of the event input channels of the peripheral circuit. It is not necessary to perform a internal transfer processing of data to be transfer-controlled from a memory to a control register each time the peripheral circuit requests data transfer to a data transfer control circuit such as data transfer controllers. The fourth embodiment is more effective, for example, in the case that event occurrence intervals from event input channels are short in comparison with the second embodiment. In other words, it is useful when data registers provided corresponding to individual event input channels are required to act as data buffers.

BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The invention will be more particularly described with reference to the accompanying drawings, in which:

[0045]FIG. 1 is a block diagram of an embodiment of a data processor of the invention;

[0046]FIG. 2 is a block diagram showing a detail of an ADC of the invention;

[0047]FIG. 3 is a block diagram showing an example of an FRT in detail;

[0048]FIG. 4 is a block diagram showing an example of a DTC in detail;

[0049]FIG. 5 is a block diagram diagrammatically showing operations with respect to a destination address when A/D conversion results of the ADC are transferred to a RAM;

[0050]FIG. 6 is an explanation drawing illustrating address bits A<b>1</b>, A<b>2</b>, and A<b>3</b> which will be operated according to channel select bit string information CH<b>2</b> to CH<b>0</b>;

[0051]FIG. 7 is an address map showing the situation where the A/D conversion results with respect to analog input signals from the analog input terminals AN<b>0</b> to AN<b>7</b> is transferred from the data register ADDR to the RAM <b>5</b>;

[0052]FIG. 8 a block diagram showing a configuration example for comparison provided by adopting the ADC having a plurality of A/D conversion data registers ADDR<b>0</b> to ADDR<b>7</b> corresponding to analog input terminals AN<b>0</b> to AN<b>7</b>;

[0053]FIG. 9 is a flow chart illustrating the AID conversion operation from the analog input terminals AN<b>0</b> to AN<b>7</b> in the ADC according to the scan mode;

[0054]FIG. 10 an explanation drawing showing the sates of the channel select bit string information CH<b>2</b> to CH<b>0</b> successively updated according to the procedure of processing shown in FIG. 9 and the address bits A<b>3</b>, A<b>2</b>, and A<b>1</b> of the register DAR changed in response to the update corresponding to the A/D conversion processes with respect to the inputs of analog input terminals AN<b>0</b> to AN<b>7</b>;

[0055]FIG. 11 an explanation drawing showing the state that data is transferred form the data register ADDR of the ADC to the predetermined areas of the RAM according to the procedure of processing shown in FIG. 9 corresponding to the A/D conversion results with respect to the inputs from the analog input terminals AN<b>0</b> to AN<b>7</b>;

[0056]FIG. 12 is a block diagram diagrammatically showing the operation with respect to destination addresses when the data loaded into the input capture register ICR in the FRT by the input capture action is transferred to the RAM;

[0057]FIG. 13 is an explanation drawing illustrating the timing of input captures and the sates of the counted values of the timer counter TCNT at the time of input capture occurrence;

[0058]FIG. 14 is an address map showing the situation where the count data is transferred to different addresses on the RAM by operating the low-order two bits of the destination address register based on event input terminal identification information;

[0059]FIG. 15 is a block diagram showing a configuration example for comparison provided by adopting a FRT having a plurality of input capture registers corresponding to event input terminals;

[0060]FIG. 16 is a block diagram illustrating the configuration of a data processor <b>1</b>A with a DMAC instead of the DTC;

[0061]FIG. 17 is a flow chart illustrating the A/D conversion operation in the ADC according to the scan mode when the DMAC shown in FIG. 16 is used;

[0062]FIG. 18 is a block diagram a data processor so arranged that both source and destination addresses are controlled with analog input terminal select bit string information;

[0063]FIG. 19 is an explanation drawing illustrating address bits A<b>1</b>, A<b>2</b>, and A<b>3</b> in both of a source and a destination, which will be operated based on analog input terminal select bit string information;

[0064]FIG. 20 is an address map illustrating the situation where data is transferred according to the configuration of FIG. 18; and

[0065]FIG. 21 is a block diagram illustrating a data processor so arranged that both source and destination addresses are controlled with event input channel identification information.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Data Processor

[0066]FIG. 1 shows an example of a data processor <b>1</b> according to the invention. For example, the data processor <b>1</b> illustrated therein may be formed on a single semiconductor substrate (semiconductor chip) such as a bulk of single crystal silicon using CMOS IC fabrication techniques.

[0067] Data processor <b>1</b> has a central processing unit (CPU) <b>2</b>, a data transfer controller (DTC) <b>3</b>, a read-only memory (ROM) <b>4</b> which is a program memory for storing programs including processing programs for the CPU <b>2</b>, a random access memory (RAM) <b>5</b> used as a work area for the CPU <b>2</b> and for the temporary storage of data, a bus controller <b>7</b>, a clock pulse generator circuit (CPG) <b>8</b>, an interrupt controller <b>10</b>, a timer counter (TMR) <b>11</b>, a serial communication interface controller (SCI) <b>12</b>, a universal serial bus controller (USB) <b>13</b>, a CRC computing unit <b>14</b>, a digital-to-analog converter (DAC) <b>15</b>, an analog-to-digital converter (ADC) <b>16</b>, a memory card interface controller (MCIFC) <b>17</b>, a pulse width modulator (PWM) <b>18</b>, a keyboard buffer controller <b>19</b>, a watchdog timer (WDT) <b>20</b>, a free running timer (FRT) <b>21</b>, a data encryption standard computing unit (DES) <b>22</b>, and I/O ports <b>23</b> to <b>25</b>. The CPU <b>2</b>, DTC <b>3</b>, ROM <b>4</b>, RAM <b>5</b>, and bus controller <b>7</b> are connected to a CPU bus <b>28</b>. The CPU bus <b>28</b> is interfaced with a peripheral bus <b>29</b> through the bus controller <b>7</b>, the peripheral bus <b>29</b> is connected to peripheral circuits such as the interrupt controller <b>10</b>, TMR <b>11</b>, SCI <b>12</b>, USB <b>13</b>, CRC computing unit <b>14</b>, DAC <b>15</b>, ADC <b>16</b>, MCIFC <b>17</b>, PWM <b>18</b>, keyboard buffer controller <b>19</b>, WDT <b>20</b>, and data encryption standard computing unit <b>22</b>. The CPU bus <b>28</b> and peripheral bus <b>29</b> each include a data bus, an address bus, and a control signal bus. The peripheral bus <b>29</b> is interfaced with an external bus (not shown) through the I/O port <b>23</b>, and the CPU bus <b>28</b> is interfaced with the peripheral bus <b>29</b> through the bus controller <b>7</b>, and then interfaced with the external bus through the I/O port <b>23</b>. The I/O ports <b>24</b> and <b>25</b> may act as external interface buffers for peripheral circuits. For example, an analog input terminal for a predetermined analog input channel of the ADC <b>16</b> is allocated to a given port of the I/O port <b>24</b>.

[0068] The CPU <b>2</b> and DTC <b>3</b> are bus master modules in the data processor <b>1</b>. The CPU <b>2</b> has an instruction control section, for example, which fetches instructions from the ROM <b>4</b> and interprets the fetched instructions, and an execution section which performs computations using a device such as a general register and an arithmetic logical computing unit according to the interpretation results of instructions. The data transfer control conditions of the DTC <b>3</b> are preset in the RAM <b>5</b> by the CPU <b>2</b>, when the ADC <b>16</b> or FRT <b>21</b> causes a data transfer request, the corresponding data transfer control conditions are load from the RAM <b>5</b> into the DTC <b>3</b>, and then the DTC <b>3</b> performs data transfer control according to the loaded transfer control conditions.

[0069] The bus controller <b>7</b> arbitrates the contention of requests for the right to use a bus among two bus master modules, namely CPU <b>2</b> and DTC <b>3</b>, and an external bus master. The arbitration logic is, for example, arbitration control based on priorities. As a result of the arbitration, a bus master module provided with the right to use a bus outputs a bus command, and then the bus controller <b>7</b> controls the bus based on this command. If address signals output by a bus master module represent the external address space of the data processor <b>1</b>, the bus controller <b>7</b> outputs address signals and access strobe signals to the outside through the I/O port <b>23</b>.

[0070] The interrupt controller <b>10</b> receives internal interrupt signals output from peripheral circuits such as FRT <b>21</b> and ADC <b>16</b> connected to the peripheral bus <b>29</b>, and external interrupt signals input from the outside through the I/O port <b>25</b>. The internal interrupt signals and external interrupt signals are collectively indicated by a reference numeral <b>30</b>. The interrupt controller <b>10</b> performs the control based on priorities and mask with respect to input interrupt signals and honors an interrupt request. When the interrupt controller <b>10</b> accepts a interrupt request, it outputs an interrupt request signal IRQ to the CPU <b>2</b> depending on the type of the interrupt request signal or outputs a DTC activation request signal DTRQ to the DTC <b>3</b>.

[0071] When the CPU <b>2</b> receives an interrupt request signal IRQ, the CPU <b>2</b> suspends its current process execution to branch to a predetermined service routine depending on the interruption factor. At the end of the service routine to which the CPU <b>2</b> branches a return instruction is executed, whereby the suspended process can be resumed.

[0072] The interrupt controller <b>10</b> is provided with data transfer control enable registers (DTCER), one for each DTC channel, and arranged so as to set whether the DTC activation is enabled or disabled with respect to plural types of interruption factors. If it set to enable, the occurrence of corresponding interruption factor activates a DTC activation request signal DTRQ of the corresponding DTC channel. If it set to disable, the occurrence of corresponding interruption factor activates an interrupt request signal IRQ. The interruption factors which enable the activation of the DTC <b>3</b> include an input capture interrupt and a compare match in the FRT <b>21</b>, a conversion ending interrupt in the ADC <b>16</b>, and a completion-of-sending interrupt and a completion-of-reception interrupt in the SCI <b>12</b>, but are not particularly limited so. A DTC vector number and corresponding vector address are determined for each interruption factor which enables the activation of the DTC <b>3</b>. The vector address contains the head address of an area on the RAM, in which data transfer control conditions activated by a corresponding DTC activation request are stored. When a DTC activation request signal DTRQ is supplied to the DTC <b>3</b> from the interrupt controller <b>10</b>, the corresponding DTC vector is also supplied to the DTC <b>3</b>. The DTC <b>3</b> loads a transfer control register with the data transfer control conditions on the RAM <b>5</b> that the DCT vector indicates and performs a data transfer control according to the loaded transfer control conditions and other conditions.

[0073] The details will be described later, when the AD conversion results with respect to data input from analog input channels are obtained in the ADC <b>16</b>, the low-order bits of destination address to which the AD conversion results are transferred using the DTC <b>3</b> can be controlled by the ADC <b>16</b>. Also, when input capture processing is performed in response to the occurrence of events to obtain a count value in the FRT <b>12</b>, the low-order bits of destinations to which the count value is transferred using the DTC <b>3</b> can be controlled by the FRT <b>21</b>.

[0074] In addition, the data processor <b>1</b> has external terminals such as ground level (Vss) and source voltage level (Vcc) as power supply terminals, and other terminals of reset input (RES), standby (input STBY), mode control input (MD<b>0</b>, MD<b>1</b>), and clock input (EXTAL, XTAL) as specialized control terminals.

[0075] The CPG <b>8</b> generates system clock signals ø using a crystal resonator connected to terminals EXTAL and XTAL, or external clock signals input to the EXTAL terminal, the system clock generating method is not particularly so limited.

[0076] When the data processor <b>1</b> receives a reset signal RES, the on-chip circuit modules such as the CPU <b>2</b> become reset. When this reset state resulting from the receipt of a reset signal RES is released, the CPU <b>2</b> loads an instruction from a predetermined start address, starts the execution of a program, follows the program, for example, fetches data from the RAM <b>5</b>, performs the computation processing of the fetched data, performs the input/output of signals with respect to the outside based on the processing results using devices such as a FRT <b>21</b> and ADC <b>16</b>, and controls various equipment.

ADC

[0077]FIG. 2 shows an example of the ADC <b>16</b> in detail. The ADC <b>16</b> selects one of analog signals supplied from analog input terminals AN<b>0</b> to AN<b>7</b> using an analog multiplexer <b>40</b> and samples the selected analog signal with a sample hold circuit <b>41</b>. The sampled analog voltage signal is compared to the output voltage of a local D/A converter circuit <b>42</b> by a comparator <b>43</b>. The control circuit <b>44</b> receives the comparison results, and controls the values of a successive approximation register <b>45</b> according to the comparison results. The local D/A converter circuit <b>42</b> converts the values of the successive approximation register <b>45</b> to analog form to produce analog voltage signals to be output to the comparator <b>43</b>. If a value obtained in the successive approximation register <b>45</b> converges due to this successive approximation operation, the value is set in an AD conversion data register ADDR as digital data corresponding to an input analog signal. When the digital data is set in the AD conversion register ADDR, the control circuit <b>44</b> asserts an AD conversion ending interrupt signal ADI to the interrupt controller <b>10</b>. The control section of the ADC <b>16</b> consists of a control circuit <b>44</b>, a status control register ADCSR, and a control register ADCR. The AD conversion data register ADDR, status control register ADCSR, and control register ADCR are connected to a peripheral bus <b>29</b> through a bus interface <b>46</b>.

[0078] The control register ADCR includes A/D conversion start/stop control bits, and a clock select bit for setting a clock which determines an A/D conversion time.

[0079] The status control register ADCSR includes a selection field for analog input channels or analog input terminals and a conversion mode designation field. However, analog input channels are herein regarded as the equivalents of analog input terminals.

[0080] The conversion mode designation field sets the operation mode of the ADC <b>16</b> at a single mode, four-channels scan mode, or eight-channels scan mode depending on its setting value. The single mode is an operation mode in which an AD conversion is performed one time with respect to an analog input terminal selected in the selection field of analog input terminals and the operation is completed. The scan mode is an operation mode in which AD conversion with respect to a plurality of channels are successively performed. The four-channels scan mode is an, operation mode in which AD conversions with respect to the four channels of AN<b>0</b> to AN<b>3</b> or AN<b>4</b> to AN<b>7</b> selected in the selection field of analog input terminals, are successively performed. The eight-channels scan mode is an operation mode in which input signals from the eight terminals of AN<b>0</b> to AN<b>7</b> are converted from analog form to digital equivalents successively.

[0081] The selection field of analog input terminals is a information field which allows a multiplexer to select an input terminal according to its value. For example, the selection field of an analog input terminal is particularly limited, but consists of 3-bits channel select bit string of CH<b>2</b>, CH<b>1</b>, and CH<b>0</b>. In this case, there is a relationship such that the analog input terminal number (channel number) increases by one each time the value of (CH<b>2</b>, CH<b>1</b>, CH<b>0</b>) is incremented by one, i.e. when (CH<b>2</b>, CH<b>1</b>, CH<b>0</b>)=(0, 0, 0), (CH<b>2</b>, CH<b>1</b>, CH<b>0</b>)=(0, 0, 1), (CH<b>2</b>, CH<b>1</b>, CH<b>0</b>)=(0, 1, 0), and (CH<b>2</b>, CH<b>1</b>, CH<b>0</b>)=(0, 1, 1), the AN<b>0</b>, AN<b>1</b>, AN<b>2</b>, and AN<b>3</b> are selected respectively.

[0082] The values of the registers ADCSR and ADCR is initialized by the CPU <b>2</b>. In the scan modes, the values of the analog input terminal select bit strings CH<b>2</b> to CH<b>0</b> of the register ADCSR are incremented by the computing circuit <b>47</b> incorporated in the control circuit <b>44</b> according to the operation mode for each A/D conversion action.

[0083] The control circuit <b>44</b> supplies the DTC <b>3</b> with the values of the analog input terminal select bit string CH<b>2</b> to CH<b>0</b> of the status control register ADCSR (also hereinafter simply referred to as channel select bit string information CH<b>2</b> to CH<b>0</b>).

[0084] For example, in the case of single mode, when the results of A/D conversion are set in the data register ADDR, channel select bit string information CH<b>2</b> to CH<b>0</b>, which represents analog input channel numbers set by the CPU <b>2</b> as is subjected to the A/D conversion operation, is output. In scan modes, at the start, channel select bit string information CH<b>2</b> to CH<b>0</b> which represents analog input channel numbers set by the CPU <b>2</b> as the subjects of the A/D conversion operation is output, and then the channel select bit string information CH<b>2</b> to CH<b>0</b> incremented by the sequential computing circuit <b>47</b> is successively output. To sum up, a single data register ADDR is provided regardless of the number of the input channels, whereas the input channel (analog input terminal number) information of data corresponding to the A/D conversion results stored in the data register ADDR is output as the information of channel select bit string CH<b>2</b> to CH<b>0</b> to the DTC <b>3</b>, whereby enabling the identification of data on input channels(analog input terminals) corresponding to data of the A/D conversion results.

[0085] The control circuit <b>44</b> also supplies interrupt controller <b>10</b> with the channel select bit string information CH<b>2</b> to CH<b>0</b>, whereby the judgement of interruption factor of an AD conversion ending interrupt signal ADI is performed. In other words, the difference among data input channels (analog input terminal numbers) corresponding to A/D conversion results stored in the data register ADDR is regarded as the difference among their interruption factors, so that different interruption factors results in different vectors for the DTC <b>3</b>.

FRT

[0086]FIG. 3 shows an example of the FRT <b>21</b> in detail. The FRT <b>21</b> has a counter section comprising a free running counter FRC, output compare registers OCRa and OCRb, comparator circuits CMPa and CPMb, and an input capture register ICR. The output compare registers OCRa and OCRb, and the input capture register ICR are connected to the peripheral bus <b>29</b> through the bus interface <b>50</b>. The free running counter FRC keeps count of clock signals CLK selected by the clock selector circuit <b>51</b>. The comparator circuits CMPa and CMPb detect the agreement between the counted value of the free running counter FRC and the setting values of the output compare registers OCRa, OCRb to output compare-match signals cma and cmb. The input capture register ICR latches the counted value of the free running counter FRC when capture signals cpts are asserted.

[0087] The FRT <b>21</b> has a counter control section comprising a control logic circuit <b>52</b>, a clock selector circuit <b>51</b>, a timer control status register TCSR, and a timer control register TCR. The control logic circuit <b>52</b> has output-compare signal output terminals FTOA and FTOB for outputting the matching detection by compare-match signals cma and cmb as an event output to the outside. The control logic circuit <b>52</b> activates a capture signal cpt to cause the input capture register ICR to latch the counted values of the free running counter FRC when the occurrence of events is noticed from input-capture signal input terminals FTI<b>3</b> to FTI<b>0</b> which are event input terminals.

[0088] The timer control register TCR holds information such as control information for determining which of the rising or falling edge of input signals from input-capture signal input terminals FTI<b>3</b> to FTI<b>0</b> is used to detect an event occurrence for input capture action, and clock signal selection information of the clock selector circuit <b>51</b>. The timer control status register TCSR has four bits of input capture flags ICF<b>3</b> to ICF<b>0</b>, and two bits of output compare flags (not shown). The two bits of output compare flags show the results of the matching detection reflected on the compare-match signals cma and cmb. The input capture flags ICF<b>3</b> to ICF<b>0</b> are flags for identifying input-capture signal input terminals FTI<b>3</b> to FTI<b>0</b> used to notice of the occurrence of the events regarded as the factors of input capture action. The input capture flag corresponding to the input-capture signal input terminal used for notice of the event occurrence is set at “1”.

[0089] If any of the input capture flags ICF<b>3</b> to ICF<b>0</b> are set at “1”, the control logic circuit <b>52</b> asserts an input capture interrupt signal ICI to the interrupt controller <b>10</b>. Then, the control logic circuit <b>52</b> also encodes the input capture flags ICF<b>3</b> to ICF<b>0</b> to output two bits of event input terminal (event input channel) identification information EIT<b>1</b> and EIT<b>0</b>. As for these event input terminal identification information EIT<b>1</b> and EIT<b>0</b>, for example, FTI<b>0</b>, FTI<b>1</b>, FTI<b>2</b>, and FTI<b>3</b> correspond to (EIT<b>1</b>,EIT<b>0</b>)=(0, 0), (EITl,EIT<b>0</b>)=(0, 1), (EIT<b>1</b>,EIT<b>0</b>)=(1, 0), and (EIT<b>1</b>,EIT<b>0</b>)=(1, 1) respectively. These event input terminal identification information EIT<b>1</b> and EIT<b>0</b> are output to the DTC <b>3</b> and interrupt controller <b>10</b>. In the interrupt controller <b>10</b>, the units of event input terminal identification information EIT<b>1</b> and EIT<b>0</b> are utilized as the interruption factors of input capture interrupt signals ICIs. Regardless of plurality of input-capture signal input terminals FTI<b>3</b> to FTI<b>0</b>, a single input capture register ICR is provided, whereas information that which event (or terminal for the notice of event occurrence) may be the factor of input capture action with respect to the register ICR is provided to DTC <b>3</b> by event input terminal identification information EIT<b>1</b> and EIT<b>0</b>, whereby it becomes possible to identify which event occurrence is in correlation with latch data in the input capture register ICR.

DTC

[0090]FIG. 4 shows an example of the DTC <b>3</b> in detail. The DTC <b>3</b> has a control logic <b>60</b>, a mode register MR, a transfer count register TCR, a destination address register DAR, and a source address register SAR. The source address register SAR holds a source address and the destination address register DAR holds a destination address. In the mode register MR, information of whether or not incrementing or decrementing actions were performed with respect to the destination address register DAR and source address register SAR after transmission, a transferred data size, and a transfer mode are set. Data on the number of times of transfers is preset in the transfer count register TCR, which is utilized for control, for example, such that the preset count is decremented each time data is transferred and the transfer action is completed when the value of the counter returns to the initial value.

[0091] The interrupt controller <b>10</b> provides the control logic <b>60</b> with DTC activation request signals DTRQs and vectors VCTs depending on their activation factors. The interrupt controller <b>10</b> is provided with data transfer control enable registers DTCERS, one for each of interruption factors of ADC conversion ending interrupt signals ADIs and input capture interrupt signals ICIs. The judgement of the activation factor and interruption factor by the interrupt controller <b>10</b> is performed based on channel select bit string information CH<b>2</b> to CH<b>0</b> or event input channel identification information EIT<b>1</b> and EIT<b>0</b> when interruption is requested with an interrupt signal ADI or ICI.

[0092] The control logic <b>60</b> is supplied with channel select bit string information CH<b>2</b> to CH<b>0</b> from the ADC <b>16</b> and the event input channel identification information EIT<b>1</b> and EIT<b>0</b> from the FRT <b>21</b>. As for which of channel select bit string information CH<b>2</b> to CH<b>0</b> or event input channel identification information EIT<b>1</b> and EIT<b>0</b> is effective information, the judgement may be performed with a vector VCT provided by interrupt controller <b>10</b>.

[0093] When the interrupt controller <b>10</b> activates a DTC activation request signal DTRQ and the corresponding vector VCT is supplied, the control logic <b>60</b> loads the register information (data transfer control conditions) on the RAM <b>5</b> indicated by the vector VCT into transfer control registers MR, TCR, DAR, and SAR and data transfer control starts according to the loaded transfer control conditions.

[0094] If this data transfer is the response to an ADC conversion ending interrupt signal ADI from the ADC <b>16</b>, the low-order three bits of the destination address register DAR are determined by low-order address information <b>61</b> corresponding to channel select bit string information CH<b>2</b> to CH<b>0</b>. Therefore, when A/D conversion results are transferred from the data register ADDR of the addresses indicated by the address register SAR to the addresses on the RAM indicated by the address register DAR, the A/D conversion results in different A/D conversion channels are held in the same data register temporarily, but those results are separately stored in different areas on the RAM <b>5</b> according to the difference of channel select bit string information CH<b>2</b> to CH<b>0</b>, which protects previous A/D conversion results from being overwritten and erased with new ones undesirably.

[0095] IF the data transfer is the response to an input capture interrupt signal ICI from the FRT <b>21</b>, the low-order two bits of the destination address register DAR are determined by low-order address information <b>61</b> corresponding to event input channel identification information EIT<b>1</b> and EIT<b>0</b>. Therefore, when input capture values (counted values) are transferred from the data register ICR of the addresses indicated by the address register SAR to the addresses on the RAM indicated by the address register DAR, the counted values in response to the occurrence of different events are held in the same data register ICR temporarily, but counted values are separately stored in different areas on the RAM <b>5</b> depending on the difference of event input channel identification information EIT<b>1</b> and EIT<b>0</b>, which protects the capture counted values in response to the inputs of previous events from being overwritten and erased with new ones undesirably.

[0096]FIG. 5 diagrammatically shows the operation with respect to destination addresses when the A/D conversion results of the ADC <b>16</b> are transferred to the RAM <b>5</b>. AS is clear from FIG. 5, the low-order three bits of the destination address register DAR are determined based on channel select bit string information CH<b>2</b> to CH<b>0</b>, where the low-order three bits are different in address bit location according to data sizes. For example, if a data size is two bytes for a byte address, three bits of A<b>1</b>, A<b>2</b>, and A<b>3</b> will be operated based on channel select bit string information CH<b>2</b> to CH<b>0</b>, as shown in FIG. 6. In the embodiment shown in FIG. 5 buses and circuit blocks are partly omitted, for example, the “data bus” is the general term applied to the data buses of the buses <b>28</b> and <b>29</b> and the “address bus” is the general term applied to the address busses of the bus <b>28</b> and <b>29</b>.

[0097] The low-order three bits of the destination address register DAR are operated based on the channel select bit string information CH<b>2</b> to CH<b>0</b>, so that the A/D conversion results with respect to the analog input signals from the analog input terminals AN<b>0</b> to AN<b>7</b> are temporarily held in the same data register ADDR and then stored in different addresses on the RAM <b>5</b>, as illustrated in FIG. 7.

[0098]FIG. 8 shows a configuration example for comparison provided by adopting an ADC having a plurality of A/D conversion data registers ADDR<b>0</b> to ADDR<b>7</b> corresponding to analog input terminals AN<b>0</b> to AN<b>7</b>. In the configuration of FIG. 8 eight AD conversion data registers are required, while in FIG. 5 only one is needed. In the configuration of FIG. 8, the A/D conversion ending interrupt signals ADI<b>0</b> to ADI<b>7</b> asserted differ from one AD conversion channel to another, so that the data transfer conditions must be transferred from the RAM to the control register of the DTC every time so asserted, which results in overhead. With the configuration of FIG. 5, this overhead is not produced.

[0099]FIG. 9 illustrates a flow chart of A/D conversion operation from analog input terminals AN<b>0</b> to AN<b>7</b> in the ADC <b>16</b> according to the scan mode.

[0100] First, the DTCER is set such that DTC activation request signals are activated in response to AD conversion ending interruptions, transfer control conditions are prestored in the predetermined areas of the RAM to set the DTC (S<b>1</b>). For example, the source address set as a transfer control condition is H'FFE<b>0</b>, and the destination address is H'EC<b>80</b>. Second, the scan mode is set in the control register ADCR of the ADC <b>16</b> (S<b>2</b>), A/D conversion operation is started with respect to an analog input from the analog input terminal AN<b>0</b> (S<b>3</b>). After the A/D conversion is completed, conversion ending interruption is generated, and then the interrupt controller activates DTC activation requests in response to the interruption generation (S<b>4</b><i>a</i>). In response to this operation, the DTC <b>3</b> loads transfer control information from the predetermined area of the RAM <b>5</b>(S<b>5</b><i>a</i>), and transfers the conversion result data of the data register ADDR indicated by the source address register SAR to the address on the RAM indicated by the destination address register DAR based on the loaded transfer control information (S<b>6</b><i>a</i>). At this time, the address bits A<b>3</b> to A<b>1</b> of the destination address register DAR are determined with the values of channel select bit string information CH<b>2</b> to CH<b>0</b> provided by the ADC <b>16</b>. Then, the ADC <b>16</b> increments the values of channel select bit string information CH<b>2</b> to CH<b>0</b> on the control status register ADSCR by one using the computing circuit <b>47</b>, and starts the A/D conversion operation with respect to an analog input from the next analog input terminal ANI (S<b>7</b><i>a</i>). After the A/D conversion is completed, a conversion ending interrupt signal ADI is generated, and then the interrupt controller activates a DTC activation request signal DTRQ in response to the interrupt signal (S<b>4</b><i>b</i>). In response to this operation, the DTC <b>3</b>, wherein the scan mode has been set already, loads no transfer control information from the predetermined area of the RAM <b>5</b>, and transfers the conversion result data of the data register ADDR indicated by the source address register SAR to the address on the RAM <b>5</b> indicated by the destination address register DAR (S<b>6</b><i>b</i>). At this time, the values of channel select bit string information CH<b>2</b> to CH<b>0</b> from the ADC <b>16</b>, which determine the address bits A<b>3</b> to A<b>1</b> of the destination address register DAR, have been incremented at the step S<b>7</b><i>a </i>already, and the incremented destination address of the initial values plus two are used for data transfer (S<b>6</b><i>b</i>). Then, the ADC <b>16</b> further increments the values of channel select bit string information CH<b>2</b> to CH<b>0</b> on the control status register ADSCR by one using the computing circuit <b>47</b>, and starts the A/D conversion operation with respect to an analog input from the next analog input terminal AN<b>2</b> (S<b>7</b><i>b</i>). Thereafter, the A/D conversion according to the scan mode is continued by repeating a series of similar steps to S<b>4</b><i>b, </i>S<b>6</b><i>b, </i>and S<b>7</b><i>b </i>until the data transfer by the A/D conversion operation with respect to an analog input from the analog input terminal AN<b>7</b> is executed.

[0101]FIG. 10 shows the sates of the sequential channel select bit string information CH<b>2</b> to CH<b>0</b> updated according to the procedure of processing shown in FIG. 9 and the address bits A<b>3</b>, A<b>2</b>, and A<b>1</b> of the register DAR changed in response to the update corresponding to the A/D conversion processes with respect to the inputs of analog input terminals AN<b>0</b> to AN<b>7</b>.

[0102]FIG. 11 shows the state that data is transferred form the data register ADDR of the ADC <b>16</b> to the predetermined areas of the RAM <b>5</b> according to the procedure of processing shown in FIG. 9 corresponding to the A/D conversion results with respect to the inputs from the analog input terminals AN<b>0</b> to AN<b>7</b>. In this figure, the unit of the address space is a byte address, and it is clearly shown that the data is two bytes of data.

[0103]FIG. 12 diagrammatically shows the operation with respect to destination addresses when the data loaded into the input capture register ICR in the FRT <b>21</b> by the input capture action is transferred to the RAM <b>5</b>. As is clear from FIG. 12, the low-order two bits of the destination address register DAR are determined based on event input terminal identification information EIT<b>1</b> to EIT<b>0</b>, where the low-order two bits are different in address bit location according to data sizes. For example, if a data size is two bytes for a byte address, two bits of A<b>1</b> and A<b>2</b> among A<b>0</b>, A<b>1</b>, A<b>2</b>, A<b>3</b>, . . . An will be operated based on event input terminal identification information EIT<b>1</b> to EIT<b>0</b>. In the embodiment shown in FIG. 12, buses and circuit blocks are partly omitted, for example, the “data address bus” is the general term applied to the buses of <b>28</b> and <b>29</b>.

[0104] In FIG. 12, when the occurrence of events is noticed from the event input terminals FTI<b>0</b> to FTI<b>3</b> in successive time sequence, the counted value of the timer counter TCNT is latched by the input capture register ICR in response to the event occurrence notice. FIG. 13 illustrates the timing of input captures and the sates of the counted values of the timer counter TCNT at the time of input capture occurrence.

[0105] The low-order two bits of the destination address register DAR are operated based on the event input terminal identification information EIT<b>1</b> to EIT<b>0</b>, so that the counted values of the timer counter TCNT in response to the notices of event occurrence from the event input terminals FTI<b>0</b> to FTI<b>3</b> are temporarily held in the same data register ICR and then stored in different addresses on the RAM <b>5</b>, as illustrated in FIG. 14.

[0106]FIG. 15 shows a configuration example for comparison provided by adopting a FRT having a plurality of input capture registers ICR<b>0</b> to ICR<b>3</b> corresponding to event input terminals FTI<b>0</b> to FTI<b>3</b>. In the configuration of FIG. 15 four input capture registers are required, while in FIG. 12 only one is needed. In the configuration of FIG. 15, the input capture interrupt signals ICI<b>0</b> to ICI<b>3</b> asserted differ from one event input channel to another, so that the data transfer conditions must be transferred from the RAM to the control register of the DTC every time so asserted, which results in overhead. With the configuration of FIG. 12, this overhead is not produced.

[0107]FIG. 16 illustrates the configuration of a data processor <b>1</b>A with a DMAC (direct memory access controller) <b>32</b> instead of the DTC <b>3</b>. Unlike the DTC <b>3</b>, the DMAC <b>32</b> has a control register wherein data transfer control conditions are preset by the CPU <b>2</b>, so that the transfer control conditions doesn't have to be loaded from the RAM <b>5</b> at each transfer step. The interrupt controller <b>10</b> supplies the DMAC <b>32</b> with DMA request signal DREQ in response to an A/D conversion ending interrupt signal ADI. Consequently, the DMAC <b>32</b> obtains the right to use a bus, and performs a transfer control to transfer the conversion result data in an A/D conversion data register ADDR to the memory address indicated by the destination address register DAR of the DMAC <b>32</b>. In the DMAC <b>32</b>, the low-order three bits of the destination address register DAR is determined based on channel select bit string information CH<b>2</b> to CH<b>0</b> as in the DTC <b>3</b>. The low-order three bits of the destination address register DAR are operated based on the channel select bit string information CH<b>2</b> to CH<b>0</b>, so that the A/D conversion results with respect to the analog input signals from the analog input terminals AN<b>0</b> to AN<b>7</b> are temporarily held in the same data register ADDR and then stored in different addresses on the RAM <b>5</b>. In the configuration of FIG. 16, when a bus cycle is started, the DMAC <b>32</b> provides the ADC <b>16</b> with a bus cycle signal <b>33</b>, so that this signal may be used to produce the timing of data output from the register ADDR.

[0108]FIG. 17 illustrates a flow chart of A/D conversion operation in the ADC <b>16</b> according to the scan mode with respect to analog input terminals AN<b>0</b> to AN<b>7</b> when the DMAC <b>32</b> shown in FIG. 16 is used.

[0109] First, the DTCER is set such that DMA transfer request signals DREQ are activated in response to AD conversion ending interruptions, DMAC <b>32</b> is initialized (S<b>11</b>). For example, the source address set as transfer control condition is H'FFE<b>0</b>, and the destination address is H'EC<b>80</b>. Second, the scan mode is set in the control register ADCR of the ADC <b>16</b> (S<b>12</b>), A/D conversion operation is started with respect to an analog input from the analog input terminal AN<b>0</b> (S<b>13</b>). After the A/D conversion is completed, conversion ending interruption is generated, and then the interrupt controller activates DMA transfer request signals DREQ in response to the interruption generation (S<b>14</b><i>a</i>). In response to this operation, the DMAC <b>32</b> transfers the conversion result data of the data register ADDR indicated by the source address register SAR to the address on the RAM <b>5</b> indicated by the destination address register DAR based on the initialized transfer control information (S<b>15</b><i>a</i>). At this time, the address bits A<b>3</b> to A<b>1</b> of the destination address register DAR are determined with the values of channel select bit string information CH<b>2</b> to CH<b>0</b> provided by the ADC <b>16</b>. Then, the ADC <b>16</b> increments the values of channel select bit string information CH<b>2</b> to CH<b>0</b> on the control status register ADSCR by one using the computing circuit <b>47</b>, and starts the A/D conversion operation with respect to an analog input from the next analog input terminal AN<b>1</b> (S<b>16</b><i>a</i>). After the A/D conversion is completed, a conversion ending interrupt signal is generated, and then the interrupt controller activates a DMA transfer request signal DREQ in response to the interrupt signal (S<b>14</b><i>b</i>). The DMAC <b>32</b>, wherein the scan mode has been set already, transfers the conversion result data of the data register ADDR indicated by the source address register SAR to the address on the RAM <b>5</b> indicated by the destination address register DAR (S<b>15</b><i>b</i>). At this time, the values of channel select bit string information CH<b>2</b> to CH<b>0</b> from the ADC <b>16</b>, which determine the address bits A<b>3</b> to A<b>1</b> of the destination address register DAR, have been incremented at the step S<b>7</b><i>a </i>already, and the incremented destination address of the initial values plus <b>2</b> are used for data transfer. Then, the ADC <b>16</b> further increments the values of channel select bit string information CH<b>2</b> to CH<b>0</b> on the control status register ADSCR by one using the computing circuit <b>47</b>, and starts the A/D conversion operation with respect to an analog input from the next analog input terminal AN<b>2</b> (S<b>16</b><i>b</i>). Thereafter, the A/D conversion according to the scan mode is continued by repeating a series of similar steps to S<b>14</b><i>b, </i>S<b>15</b><i>b, </i>and S<b>16</b><i>b </i>until the data transfer by the A/D conversion operation with respect to an analog input from the analog input terminal AN<b>7</b> is executed.

[0110]FIG. 18 illustrates a configuration example of another data processor <b>1</b>B for controlling source and destination addresses using analog input terminal select bit string information CH<b>2</b> to CH<b>0</b>. The ADC <b>16</b>B has a plurality of A/D conversion data registers ADDR<b>0</b> to ADDR<b>7</b> which can be used according to individual analog input terminals, and the data register to be used is selected based on the analog input terminal select bit string information CH<b>2</b> to CH<b>0</b>. In the DTC <b>3</b>B, the low-order three bits of both address registers DAR and SAR can be changed by analog input terminal select bit string information CH<b>2</b> to CH<b>0</b>, as illustrated in FIG. 19. The data transfer form according to this configuration is illustrated in FIG. 20, the low-order bits of source addresses and destination addresses of the AD conversion data registers ADDR<b>0</b>-ADDR<b>7</b> are automatically updated based on channel select bit string information CH<b>2</b> to CH<b>0</b>. With this configuration, the data registers ADDR<b>0</b> to ADDR<b>7</b> provided corresponding to individual data input channels can be used as data buffers, so that it is more effective, for example, in the case that the data input intervals from data input channels are short in comparison with the configuration of FIG. 5.

[0111]FIG. 21 illustrates a configuration example of still other data processor <b>1</b>C for controlling source and destination addresses using event input channel identification information EIT<b>1</b> to EIT<b>0</b>. The FRT <b>21</b>C has a plurality of input capture registers ICR<b>0</b> to ICR<b>3</b> which can be used according to individual events, and the input capture register to be used is selected based on the event input channel identification information EIT<b>1</b> to EIT<b>0</b>. In the DTC <b>3</b>C, the low-order two bits of both address registers DAR and SAR can be changed by event input channel identification information EIT<b>1</b> to EIT<b>0</b>. The data transfer form according to this configuration is the same as the illustrated configuration in FIG. 20, the low-order bits of source addresses of the input capture registers ICR<b>0</b> to ICR<b>3</b> and destination addresses on the RAM are automatically updated with transfer requests. With this configuration, the data registers ICR<b>0</b> to ICR<b>3</b> provided corresponding to individual event input channels can be used as data buffers, so that it is more effective, for example, in the case that the event input intervals from event input channels are short in comparison with the configuration of FIG. 12.

[0112] While the preferred embodiments of our invention have been described specifically, it should be understood that the invention is not limited thereto and various changes and modifications may be made within the scope of the following claims.

[0113] As an example of such modifications, the peripheral circuits described herein are limited to an ADC and FRT, may be other peripheral circuits such as a peripheral circuit for communication control such as a SCI, a timer counter, and a watchdog timer.

[0114] Although transfer control information for the results of A/D conversion of succeeding channels in a scan mode is not newly loaded from the RAM at each conversion step in the embodiment shown in FIG. 9, the transfer control information may be loaded at every conversion step from the RAM to the DTC, which depends on the difference in data transfer and control methods according to both embodiments.

[0115] The invention may be also applied to a configuration with a peripheral circuit comprising a plurality of data registers provided corresponding to the number of data input channels or event input channels, wherein one of those data registers may be shared by two or more data input channels or event channels.

[0116] Typical effects according to the invention disclosed herein will be described briefly as follows:

[0117] Peripheral circuits such as an ADC are not required to comprise data registers for storing input data processing results corresponding to the number of input terminals, namely in one-to-one correspondence with the input terminals. Additionally, the peripheral circuits such as a FRT are not required to comprise data registers for processing results in response to event inputs according to the number of event input channels. Thus, the number of data register can be reduced in comparison with that of the input channels of peripheral circuits.

[0118] The low-order bits of a destination address register are automatically updated based on the identification information from the peripheral circuit, so that the data transfer channels of data transfer control circuits such as direct memory access controllers are not required to be increased with respect to the number of the input channels of the peripheral circuit. It is not necessary to perform a internal transfer processing of data to be transfer-controlled from a memory to a control register each time the peripheral circuit requests data transfer to a data transfer control circuit such as data transfer controllers.

[0119] According to the invention, it is possible to suppress an increase in the number of data registers due to an increasing number of the input channels of peripheral circuits and to reduce the overhead associated with data transfer control.