Electrical connector having differential pair terminals with equal length

FIELD OF THE INVENTION

P-0001[0001] The present invention relates to an electrical connector, and more particular to a very high-density modular connector having a pair of differential pair with equal length, thereby effectively eliminating skew during signal transmission.

DESCRIPTION OF THE PRIOR ART

P-0002[0002] High-density electrical connector for use with printed circuit boards has been increasing required by the market in light of the increasing use of the servers, and the storage box.

P-0003[0003] U.S. Pat. No. 5,993,259 discloses an electrical connector of such application. The connector disclosed in the '259 patent includes a plurality of modularized wafers bounded together. As shown in FIG. 4 of the '259 patent, the terminals are stamped from a metal sheet, then embedded within an insulative material to form the wafer. However, it can be readily seen from FIG. 4 that the length of each terminal is different from its adjacent terminal because of the right-angle arrangement. In addition, it would be unlikely to make two adjacent terminals with equal length. As long as the terminal length is different from one another, skew between terminals is therefore inevitable.

P-0004[0004] In addition, it will be difficult to have two adjacent terminals to be configured as a differential pair. By the way, because of the shape of the terminals, it is also unlikely to reach equal impedance between two adjacent terminals.

P-0005[0005] U.S. Pat. No. 6,083,047 discloses an approach to make a high-density connector by introducing the use of printed circuit board. According to teaching of the '047 patent, conductive traces are formed on surfaces of the printed circuit board in a mirror-image arrangement, typically shown in FIG. 12. Again, the conductive traces formed on the surface of the printed circuit board are unlikely to have the same length. Skew is still inevitable.

P-0006[0006] In addition, in the above-described patent, distance between two adjacent terminals is too close to intercept a ground contact or conductive trace.

P-0007[0007] In the '259 patent, even a ground bus is provided, however, the ground bus only electrically separate two adjacent wafers, while it can not separate two adjacent terminals.

P-0008[0008] In the '047 patent, since the conductive traces are exposed on the printed circuit board, arranging a ground bus between two printed circuit boards. According to the teaching of the '047, insulative spacer is arranged to two adjacent printed circuit boards, this will not doubt increase the thickness of the overall dimension of the connector, especially when ground buses are arranged therein.

P-0009[0009] In addition, when the conductive traces are formed on the printed circuit boards, connecting legs/sockets have to be attached to corresponding conductive trace. This will not doubt complicate the make of the connector.

P-0010[0010] In the '047 patent, even the conductive traces formed on both sides of the printed circuited board, since the connecting portion and tail portions are soldered thereto, the it will be unlikely to reach equal impedance between two terminals.

SUMMARY OF THE INVENTION

P-0011[0011] It is an objective of this invention to provide an electrical connector of high density in which terminal pair within an individual wafer has equal length.

P-0012[0012] It is still the objective of this invention to provide an electrical connector in which two adjacent wafers are separated by a grounding bus having ground ribs extending two adjacent terminals thereby providing excellent shielding for signal transmission.

P-0013[0013] In order to achieve the objective set forth, an electrical connector in accordance with the present invention comprises a wafer integrally formed with a pair of terminal pairs and each pair configured by first and second terminals. The first terminal includes a first base portion having a first tail portion, and a first mating portion, the first tail and mating portions extending beyond the wafer. The second terminal includes a second base portion having a second tail portion, and a second mating portion, the second tail and mating portions extending beyond the wafer; wherein the first and second base portions of the first and second terminal are spaced apart from each other in a side-by-side arrangement.

P-0014[0014] According to another embodiment of the present invention, an electrical connector in accordance with the present invention comprises at least a pair of wafers integrally formed with a plurality of terminals therein, the each wafer defining at least two openings adjacent to a terminal; and a first grounding bus is located between the wafers and forming at least a pair of grounding ribs extending into the openings of the wafer.

SUMMARY OF THE DRAWINGS

P-0015[0015] Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings, in which:

P-0016[0016]FIG. 1A is an exploded view of a wafer and a grounding bus in accordance with the present invention;

P-0017[0017]FIG. 1B is a perspective view of an insulative slab of FIG. 1A;

P-0018[0018]FIG. 1C is a front view of FIG. 1B;

P-0019[0019]FIG. 1D is a front view of a ground bus of FIG. 1B without grounding ribs removed therefrom;

P-0020[0020]FIG. 1E is a perspective view FIG. 1E;

P-0021[0021]FIG. 1F is similar to FIG. 1E and viewed from a reverse direction;

P-0022[0022]FIG. 1G is similar to FIG. 1D with grounding ribs formed thereon;

P-0023[0023]FIG. 1H is a front view first group of terminals;

P-0024[0024]FIG. 1I is a bottom view of FIG. 1H;

P-0025[0025]FIG. 1J is a front view second group of terminals;

P-0026[0026]FIG. 1K is a bottom view of FIG. 1J;

P-0027[0027]FIG. 1L is a front view showing first and second groups of terminals are arranged together without insulative slab enclosed thereon;

P-0028[0028]FIG. 2 is an assembled view of FIG. 1A;

P-0029[0029]FIG. 3A is a side view of FIG. 2;

P-0030[0030]FIG. 3B is a cross sectional view taken along line A-A of FIG. 3A;

P-0031[0031]FIG. 4A is a perspective view of an electrical connector configured by a plurality of wafers shown in FIG. 2;

P-0032[0032]FIG. 4B is similar to FIG. 4A viewed from a reverse direction;

P-0033[0033]FIG. 4C is a side view of FIG. 4A;

P-0034[0034]FIG. 4D is a cross sectional view taken along line FF-FF of FIG. 4C;

P-0035[0035]FIG. 4E is a cross sectional view of another embodiment in accordance with the present invention;

P-0036[0036]FIG. 5A is a perspective view of the electrical connector to be mated with a header;

P-0037[0037]FIG. 5B is a side view of an electrical connector assembly mounted on printed circuit boards;

P-0038[0038]FIG. 6A is a perspective view of a connector in accordance with another embodiment of the present invention;

P-0039[0039]FIG. 6B is a perspective view showing the connector of FIG. 6A is mated with the header shown in FIG. 5A; and

P-0040[0040]FIG. 6C is a front view of still another embodiment of the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

P-0041[0041] Referring to FIGS. 1A to <b>1</b>L, <b>2</b>, <b>3</b>A and <b>3</b>B, an electrical connector <b>1</b> in accordance with the present invention includes a wafer <b>10</b> in accordance with the present invention includes an insulative slab <b>11</b> and a plurality of terminals <b>12</b>, <b>13</b>, <b>14</b>, <b>15</b>, <b>16</b> and <b>17</b> integrally molded/embedded within the slab <b>11</b>. A grounding bus <b>20</b> is provided and use with the wafer <b>10</b> for EMI shielding. When a plurality of wafers <b>10</b> is used together, the grounding bus <b>20</b> provides necessary shield. The grounding bus <b>20</b> includes a plurality of grounding ribs <b>21</b> extending therefrom. An electrically shielded passage <b>22</b> is defined between two adjacent grounding ribs <b>21</b>. Detailed description will be given later.

P-0042[0042] As shown in FIG. 1A, and also FIGS. 1H, 11, and <b>1</b>J, the terminals <b>12</b> and <b>14</b> are terminal pairs, while terminals <b>13</b>, <b>15</b> are terminal pair. Since the terminals <b>12</b>, and <b>14</b> are identical except to their length, only one description is given for simplicity. In order to easy description, terminals <b>12</b> and <b>13</b> are referred to first terminal in the pair, while terminals <b>14</b> and <b>15</b> are referred to second terminal in the pair.

P-0043[0043] Each first terminal includes a first base portion <b>121</b> (<b>131</b>), a first tail portion <b>122</b> (<b>132</b>), and a first mating portion <b>123</b> (<b>133</b>). As shown in FIG. 11, the first tail portions <b>122</b> (<b>132</b>) are offset upward from the first base portion <b>121</b> (<b>131</b>).

P-0044[0044] Each second terminal includes a second base portion <b>141</b> (<b>151</b>), a second tail portion <b>142</b> (<b>152</b>), and a second mating portion <b>143</b> (<b>153</b>). As shown in FIG. 1K, the second tail portions <b>142</b> (<b>152</b>) are offset downward from the second base portion <b>141</b> (<b>151</b>). By this arrangement, when the first and second terminals <b>12</b> (<b>13</b>), and <b>14</b> (<b>15</b>) are stacked together, the first and second tail portions <b>122</b> (<b>132</b>) and <b>142</b> (<b>152</b>) are located in the same plane, such as shown in FIGS. 2 and 3B, while the first mating portions <b>123</b> (<b>133</b>) and the second mating portions <b>143</b> (<b>153</b>) are also located in the same plane.

P-0045[0045] On the other hand, the first mating portions <b>123</b> (<b>133</b>) are offset upward from the base portions <b>121</b> (<b>131</b>), while the second mating portions <b>141</b> (<b>151</b>) are offset downward from the base portions <b>141</b> (<b>151</b>). Again, when the first and second terminals <b>12</b> (<b>13</b>), and <b>14</b> (<b>15</b>) are stacked together, the sequential order of the mating portions <b>123</b> (<b>133</b>), and <b>143</b> (<b>153</b>) will become <b>123</b>, <b>143</b>, <b>133</b>, and <b>153</b>. As a matter of fact, the first and second tail portions <b>122</b> (<b>132</b>), and <b>142</b> (<b>152</b>) have the same arrangement.

P-0046[0046] Accordingly, by the offset arrangement of the mating portions <b>122</b> (<b>142</b>), and <b>132</b> (<b>152</b>), and the tail portions <b>123</b> (<b>143</b>), and <b>133</b> (<b>153</b>), the terminal <b>12</b> has the same length with the terminal <b>14</b>, while the terminal <b>13</b> has the same length with the terminal <b>15</b>. By this arrangement, the skew between the terminals <b>12</b>, <b>14</b>, and <b>13</b>, <b>15</b> are completely eliminated.

P-0047[0047] The mating portions <b>122</b> (<b>142</b>), <b>132</b> (<b>152</b>), <b>162</b>, and <b>172</b> are embodied as a socket to be mated with corresponding headers, FIG. 5A. However, it can be embodied with other configuration.

P-0048[0048] The plastic slab <b>11</b> is generally a plastic material integrally enclosing the terminals <b>12</b>, <b>13</b>, <b>14</b>, <b>15</b>, <b>16</b> and <b>17</b>. The slab <b>11</b> is defined with a plurality of openings <b>11</b><i>a </i>which are located between two adjacent terminals <b>11</b>, <b>12</b>. The slab <b>11</b> is further defined with undercut <b>11</b><i>b </i>adjacent to a mating edge <b>11</b><i>c </i>thereof. The openings <b>11</b><i>a </i>and the undercuts <b>11</b><i>b </i>are defined such that bridges <b>11</b><i>c </i>are formed therebetween. The bridges <b>11</b><i>c </i>formed thereof is use to increase the integrality of the slab <b>11</b>.

P-0049[0049] In manufacturing, the first and second group terminals <b>12</b>, <b>13</b>, <b>14</b>, <b>15</b>, <b>16</b>, and <b>17</b> are stacked together such that the tail portions <b>122</b>, <b>142</b>, <b>132</b>, <b>152</b>, <b>162</b>, and <b>172</b> are located in the same plane, while the mating portions <b>123</b>, <b>143</b>, <b>133</b>, <b>153</b>, <b>163</b>, and <b>173</b> are located in the same plane as well. Then the plastic slab <b>11</b> is over-molded over those terminals <b>12</b>, <b>13</b>, <b>14</b>, <b>15</b>, <b>16</b>, and <b>17</b> with the tail portions <b>122</b>, <b>142</b>, <b>132</b>, <b>152</b>, <b>162</b>, and <b>172</b>, the mating portions <b>123</b>, <b>143</b>, <b>133</b>, <b>153</b>, <b>163</b>, and <b>173</b> extended over the slab <b>11</b> for mating with corresponding printed circuit board and headers.

P-0050[0050] The ground bus <b>20</b> is stamped directly from a sheet metal. The grounding bus <b>20</b> is directly formed with a plurality of slots <b>20</b><i>a </i>corresponding to the contour of the terminals <b>12</b>, <b>13</b>, <b>14</b>, <b>15</b>, <b>16</b>, and <b>17</b>. Each slot <b>20</b><i>a </i>is further formed with the grounding ribs <b>21</b> through the die-cast molding. Accordingly, when a plurality of ribs <b>21</b> is formed, a plurality of passage <b>22</b> is also defined between two adjacent ribs <b>21</b>. The passage <b>22</b> is defined corresponding to the terminals <b>12</b>, <b>13</b>, <b>14</b>, <b>15</b>, <b>16</b>, and <b>17</b>. As clearly shown in FIG. 3B, each grounding rib <b>22</b> extends into the corresponding opening <b>11</b><i>a </i>of the slab <b>11</b>. Accordingly, the terminals <b>12</b>, <b>14</b> are located within the corresponding passage <b>22</b>, while the terminals <b>13</b>, <b>15</b> are located in the same passage <b>22</b>, while the terminals <b>16</b> and <b>17</b> are located within the corresponding passages <b>22</b>, respectively. By this arrangement, each terminals or terminal pair are electrically shielded from each other by the passages <b>22</b> defined by the grounding bus <b>20</b> and corresponding grounding ribs <b>21</b>.

P-0051[0051] The grounding bus <b>20</b> further defines a plurality of short ribs <b>23</b> distant to the grounding ribs <b>21</b>. As a result, gaps <b>26</b> are defined between the grounding ribs <b>21</b> and the short ribs <b>23</b>. The gaps <b>26</b> are formed to receive bridges <b>11</b><i>c </i>of the slab <b>11</b>. The short ribs <b>23</b> can be readily received in the undercut <b>11</b><i>b </i>of the slab <b>11</b>. By this arrangement, the mating portions (<b>123</b>, <b>143</b>), (<b>133</b>, <b>153</b>), <b>163</b>, and <b>173</b> are also electrically separated by the short ribs <b>23</b>. Accordingly, an excellent shield performance is achieved by the arrangement provided by the present invention.

P-0052[0052] The grounding bus <b>20</b> is further integrally formed with a plurality of grounding legs <b>24</b> for mounting to the printed circuit board, such as shown in FIG. 5B. Forming of the grounding legs <b>24</b> is only possible by the stamping process. According to the preferred embodiment of the present invention, the grounding legs <b>24</b> each has a needle-eye configuration which is electrically connected to a through hole of the printed circuit board once the grounding leg <b>24</b> is inserted therein.

P-0053[0053] The grounding bus <b>20</b> further includes peripheral walls <b>25</b> which jointly define a receiving space <b>25</b> in which the wafer <b>10</b> can be snugly received therein, such as shown in FIG. 4D. By this arrangement, the wafer <b>10</b> is completely shielded by the corresponding grounding bus <b>20</b>. In addition, as described above, the terminals <b>12</b>, <b>13</b>, <b>14</b>, <b>15</b>, <b>16</b>, and <b>17</b> within the wafer <b>10</b>

P-0054[0054]FIG. 2 is an assembled view of FIG. 1A. The arrangement shown in FIGS. 1A and 2 are just for easy understanding of the present invention. In the actual practice, the wafer <b>10</b> is completely enclosed the corresponding grounding bus <b>20</b>.

P-0055[0055]FIG. 3A is a front view of FIG. 2, while FIG. 3B is a cross sectional view taken along line A-A of FIG. 3A. It can be readily seen from FIG. 3B, the base portions <b>121</b>, <b>141</b>, and <b>131</b>, <b>151</b> are arranged in a side-by-side arrangement, thereby benefiting skew-free signal transmission.

P-0056[0056]FIGS. 4A to <b>4</b>D disclose a high density connector <b>100</b> configured by four sets of wafers <b>101</b>, <b>102</b>, <b>103</b> and <b>104</b>, and grounding buses <b>201</b>, <b>202</b>, <b>203</b>, and <b>204</b> are stacked together to define a high density electrical connector <b>100</b>. Since the wafers <b>101</b>, <b>102</b>, <b>103</b> and <b>104</b> are identical to wafer <b>10</b>, no detailed description is given. In addition, similar elements are marked with same numeral references as wafer <b>10</b>. The grounding buses <b>201</b>, <b>202</b>, <b>203</b> and <b>204</b> are also identical to grounding bus <b>20</b>, no detailed description is given. Besides, similar elements bear the same numeral references as grounding bus <b>20</b>.

P-0057[0057]FIGS. 4C is a front view of FIG. 4A, while FIG. 4D is a cross sectional view taken along line FF-FF of FIG. 4C. It can be readily seen that the wafers <b>102</b>, <b>103</b> and <b>104</b> are enclosed by the corresponding grounding buses <b>201</b>, <b>202</b>, <b>203</b>, and <b>204</b>. In addition, the base portions <b>121</b>, <b>141</b> of the terminals <b>12</b> and <b>14</b> are located within a passage <b>22</b> defined by the grounding bus <b>201</b> and the corresponding grounding ribs <b>21</b>, for example. By this arrangement, the signal transmitted by the terminals <b>12</b> and <b>14</b> is completely shielded from noise. In addition, the terminals <b>12</b>, <b>14</b> and <b>13</b>, <b>15</b> are completely and electrically isolated by the grounding ribs <b>21</b> disposed therebetween. As a result, cross-talks between the terminal pairs <b>12</b>, <b>14</b>, and <b>13</b>, <b>15</b> are completely eliminated.

P-0058[0058]FIG. 4E discloses another embodiment in accordance with the present invention. In this preferred embodiment, an electrical connector <b>200</b> configured by three wafers <b>111</b>, <b>112</b>, and <b>113</b> and the grounding buses <b>211</b>, <b>212</b>, and <b>213</b> are interlocked by a latch <b>40</b> which passes through the slots <b>20</b><i>a </i>of the grounding buses <b>211</b>, <b>212</b>, and <b>213</b>, and the openings <b>11</b><i>a </i>of the wafers <b>111</b>, <b>112</b>, and <b>113</b> is disclosed. By this arrangement, all the wafers <b>111</b>, <b>112</b>, and <b>113</b>, and the grounding buses <b>211</b>, <b>212</b>, and <b>213</b> are securely interlocked. In addition, an end plate <b>46</b> is attached to the outmost wafer <b>113</b> to completely and electrically enclosing the wafer <b>113</b> within the corresponding grounding bus <b>213</b>. Accordingly, an electrical connector <b>300</b> configured by the wafers <b>111</b>, <b>112</b>, <b>113</b> grounding buses <b>211</b>, <b>212</b>, <b>213</b>, and the end plate <b>46</b> is completely and electrically shielded.

P-0059[0059]FIG. 5A is a perspective view showing the connector <b>200</b> shown in FIG. 4A and a corresponding header <b>50</b> having an array of pin <b>51</b> extending therefrom.

P-0060[0060] The header <b>50</b> includes a base <b>50</b><i>a </i>with the pins <b>51</b> extending therefrom. The pins <b>51</b> are arranged in rows and every two adjacent rows of pins <b>51</b> are interposed with a row of grounding tabs <b>52</b>. The pins <b>51</b> are to be mated with the mating portions <b>123</b>, <b>133</b>, <b>143</b>, <b>153</b>, <b>163</b>, and <b>173</b> of the terminals <b>12</b>, <b>13</b>, <b>14</b>, <b>15</b>, <b>16</b> and <b>17</b>, while the grounding tabs <b>52</b> are electrically mated with front tabs <b>20</b><i>c </i>of the grounding buses <b>201</b>, <b>202</b>, <b>203</b> and <b>204</b>. Accordingly, when the connector <b>100</b> is mated with the header <b>50</b>, all signal transmission is free from noise and EMI shielding.

P-0061[0061]FIG. 5B is a front view showing the mating of the connector <b>100</b> and the header <b>50</b>. The doted line showing the connector <b>100</b> is mounted onto a first printed circuit board <b>60</b>, while the header <b>50</b> is mounted onto a second printed circuit board <b>70</b>. Generally, the second printed circuit board <b>70</b> is a motherboard, while the first printed circuit board <b>60</b> is a daughter board.

P-0062[0062] As clearly described above, the terminals <b>12</b> and <b>14</b> are equally and closely arranged in side-by-side arrangement, the terminals <b>12</b> and <b>14</b> can naturally serve as a differential pair to enhance signal transmission therethrough. The terminals <b>13</b> and <b>15</b> have the same advantages.

P-0063[0063] In addition, since the terminals <b>12</b> and <b>14</b> have almost the same contour, the impedance between the terminals <b>12</b> and <b>14</b> are actually equal.

P-0064[0064] In light of this, by the arrangement of the present invention, the terminals <b>12</b>, <b>14</b>, and <b>13</b>, <b>15</b> can perfectly reach the requirements to serve as differential pair as well as matched impedance, while the prior art can never reach.

P-0065[0065] It should be noted that even the terminals <b>16</b>, <b>17</b> are not incorporated with a counterpart terminals, such as terminals <b>12</b>, <b>13</b>, those counterpart terminals can be readily incorporated so as to serve as a differential pairs, such as terminals <b>12</b>, <b>14</b>; and <b>13</b>, <b>15</b>.

P-0066[0066] The wafer <b>10</b> (<b>110</b>) disclosed above includes only six terminals (<b>12</b>, <b>13</b>, <b>14</b>, <b>15</b>, <b>16</b>, <b>17</b> and <b>18</b>), however, the terminals <b>17</b> and <b>18</b> can be also incorporated with additional terminals to construct a pair.

P-0067[0067]FIG. 6A discloses an electrical connector <b>5</b> which is configured by four wafers <b>210</b> each includes eight terminals <b>212</b>, <b>213</b>, <b>214</b>, <b>215</b>, <b>216</b>, <b>217</b>, <b>218</b>, <b>219</b> and <b>220</b> in which terminals <b>212</b>, <b>214</b> is a pair, while <b>213</b>, <b>215</b> is a pair, <b>217</b>, <b>219</b> is a pair, and <b>218</b>, <b>220</b> is a pair.

P-0068[0068]FIG. 6B is a side view showing the electrical connector <b>5</b> is mated with a header <b>50</b> shown in FIG. 5A.

P-0069[0069]FIG. 6C is a front view showing that an electrical connector <b>7</b> in accordance with the present invention includes seven wafers <b>210</b> and seven grounding bus <b>20</b>. It can be readily appreciated that each pair of terminals <b>212</b>, <b>214</b>; <b>213</b>, <b>215</b>; <b>216</b>, <b>218</b>; and <b>217</b>, <b>219</b> are located in a channel defined by the grounding bus <b>20</b> and the grounding ribs <b>21</b>. By this arrangement, the signal transmission is reliably ensured.

P-0070[0070] The connector <b>7</b> shown in FIG. 6C demonstrates one of the advantages of the present invention, i.e. the connector <b>7</b> can be easily expanded by additional wafers <b>210</b>. Each wafer <b>210</b> and grounding bus <b>20</b> serves as an unit which can be selectively increased to configure an electrical connector according to the requirements. As a result, a plurality of connector can be easily derived from a single unit, the wafer <b>210</b> and the grounding bus <b>20</b>. The manufacturing cost is therefore tremendously reduced.

P-0071[0071] It will be understood that the invention may be embodied in other specific forms without departing from the spirit or central characteristics thereof. The present examples and embodiments, therefore, are to be considered in all respects as illustrative and not restrictive, and the invention is not to be limited to the details given herein.