Data communication system with self-test facility

BACKGROUND OF THE INVENTION

[0001] For several decades, integrated circuit and laser technologies have doubled in performance approximately every 18 months. These technologies have been used to support a rapidly-growing demand for global communications capacity. This demand is currently growing much faster than the underlying rate of improvement of the supporting technologies. As an example, communication traffic through the Internet has recently been doubling every nine months. The demand for additional communication bandwidth is severely stressing the capabilities of current electronic and optical technologies.

[0002] In particular, the Ethernet local area network standard has progressively increased in speed by factors of ten, starting at 10 megabit per second (Mb/s) in 1982. Proposals for a 10 gigabit/second (Gb/s) Ethernet standard were made in 1999. The most recently adopted Ethernet standard is for transmitting serial data at 1 Gb/s and uses a 8b/10b line code described by A. X. Widmer and P. A. Franaszek in <i>A DC</i>-<i>Balanced, Partitioned</i>-<i>Block, </i>8<i>b</i>/10<i>b Transmission Code</i>, 27 IBM J. R<smallcaps>ES. AND </smallcaps>D<smallcaps>EV</smallcaps>., (1983 September). In 8b/10b line code, each eight-bit input word is represented by a ten-bit code that is transmitted through the Ethernet medium. In exchange for this 25% overhead, 8b/10b coding provides DC balance, and a guaranteed transition density. The ten-bit code additionally has the ability to represent an assortment of control words used for signaling and framing.

[0003] The large overhead of 8b/10b coding imposes operational disadvantages when applied to 10 Gb/s transmissions. In U.S. patent application Ser. No. 09/522,782, the disclosure of which is incorporated herein by reference, one of the inventors of this disclosure (Walker) and others disclosed a 64b/66b encoder/66b coding scheme that provided most of the advantages of 8b/10b coding, but with a substantially smaller overhead.

[0004]FIG. 1 is a block diagram showing an example <b>10</b> of the 10 Gb/s Ethernet data communication system disclosed in the above-mentioned patent application. The data communication system receives a 4×8b/10b coded serial bitstream via the 4-lane XAUI bus <b>18</b> and outputs a 4×8b/10b coded serial bitstream via the 4-lane XAUI bus <b>19</b>.

[0005] The data communication system <b>10</b> includes the transmitter <b>20</b> and the receiver <b>22</b>. The transmitter <b>20</b> is composed of a serial arrangement of the 4×10b/8b decoder <b>32</b>, the 64b/66b encoder <b>50</b>, the scrambler <b>33</b>, the frame assembler <b>34</b> and the multiplexer <b>35</b>. The input of the 4×10b/8b decoder is connected to the XAUI bus <b>18</b>. The output of the 4×10b/8b decoder is connected to the input of the 64b/66b encoder by the 37-conductor pseudo-XGMII bus <b>42</b>.

[0006] The payload field output of the 64b/66b encoder <b>50</b> is connected to the input of the scrambler <b>33</b> by the payload field bus <b>43</b>. The master transition output of the 64b/66b encoder is connected via the master transition bus MT to the master transition input of the frame assembler <b>34</b>.

[0007] The output of the scrambler <b>33</b> is connected to the payload field input of the frame assembler <b>34</b> by the bus <b>44</b>. The output of the frame assembler is connected to the input of the multiplexer <b>35</b> by the bus <b>45</b>. The multiplexer generates a 10 Gb/s serial bitstream that is output to the Ethernet medium <b>40</b>.

[0008] The receiver <b>22</b> is composed of a serial arrangement of the demultiplexer <b>36</b>, the frame disassembler <b>37</b>, the descrambler <b>38</b>, the 66b/64b decoder <b>52</b> and the 4×8b/10b encoder <b>39</b>.

[0009] The demultiplexer <b>36</b> receives a 10 Gb/s serial bitstream from the Ethernet medium <b>40</b>. The output of the demultiplexer is connected to the input of the frame disassembler <b>37</b> by the bus <b>46</b>.

[0010] The payload field output of the frame disassembler <b>37</b> is connected to the input of the descrambler <b>38</b> by the bus <b>47</b>. The master transition output of the frame disassembler is connected to the master transition input of the 66b/64b decoder <b>52</b> by the bus MT.

[0011] The output of the descrambler <b>38</b> is connected to the payload field input of the 66b/64b decoder <b>52</b> by the bus <b>48</b>.

[0012] The output of the 66b/64b decoder <b>52</b> is connected to the input of the 4 ×8b/10b encoder <b>39</b> by the 37-conductor pseudo-XGMII bus <b>49</b>. The output of the 4×8b/10b encoder is connected to the XAUI bus <b>19</b>.

[0013] The widths of the busses <b>43</b>-<b>48</b> shown in FIG. 1 are maximum parallel widths: serial/parallel techniques may be used to reduce the parallel widths of these busses substantially.

[0014] In the transmitter <b>20</b> of the data communication system <b>10</b>, the 4×10b/8b decoder <b>32</b> is connected to the XAUI bus <b>18</b> to receive incoming serial 10-bit line code words at a bit rate of 4×3.125 Gb/s. The 4×10b/8b decoder decodes the 8b/10b coding of the 10-bit line code words to recover respective 8-bit words, and generates, a control word flag for each word that, when set, indicates that the word is a control word. The 4×10b/8b decoder sets of four of the 8-bit words and their respective control word flags to the 64b/66b encoder <b>50</b> via the pseudo-XGMII bus <b>42</b>. In this disclosure, the term quad will be used to denote a set of four 8-bit words. The pseudo-XGMII bus is composed of 37 conductors of which thirty-two are allocated to the quads, four are allocated to the control word flags for the quads, and one is allocated to a clock signal.

[0015] The 64b/66b encoder <b>50</b> determines whether any of the eight control word flags belonging to two of the quads is set. When none of the control word flags is set, the quads are composed exclusively of information words, and the 64b/66b encoder generates a payload field composed of both of the quads. The 64b/66b encoder additionally generates the two-bit master transition with bits <b>0</b> and <b>1</b> in a first state. When at least one of the control word flags is set, the quads include at least one control word, and the 64b/66b encoder generates a payload field composed of a TYPE word and seven other words. The seven other words may be information words, compressed control words or both information words and compressed control words. The 64b/66b encoder additionally generates the two-bit master transition with bits <b>0</b> and <b>1</b> in a second state, opposite to the first state. The payload field structures will be described below with reference to FIGS. <b>2</b>A-<b>2</b>C.

[0016] Regardless of the contents of the payload field and the sense of the master transition, the 64b/66b encoder <b>50</b> feeds the payload field to the scrambler <b>33</b> via its payload field output and the bus <b>43</b> and feeds the master transition, suitably pipelined, to the master transition input of the frame assembler <b>34</b>.

[0017] The scrambler <b>33</b> scrambles the payload fields of the frames so that, when the frames are transmitted, the resulting bitstream is statistically DC balanced and additionally appears to be random. Scrambling the payload fields also enables the receiver to synchronize easily on the master transitions, which are not scrambled. In an embodiment of the data communication system <b>10</b>, the scrambler scrambles the payload field using the polynomial x⁵⁸+x³⁹+x⁰. Alternative polynomials that can be used include x⁶⁵+x⁴⁷+x⁰, x⁵⁸+x¹⁹+x⁰and x⁶⁵+x¹⁸+x⁰.

[0018] The frame assembler <b>34</b> receives the scrambled payload field from the scrambler <b>33</b> and the master transition from the 64b/66b encoder <b>50</b> and forms a 66-bit frame from the scrambled payload field and the master transition.

[0019]FIG. 2A shows the basic structure of the frame <b>70</b> generated from two quads. Each quad is composed of four 8-bit words. The frame is composed of the two-bit master transition field <b>71</b> followed by the 64-bit payload field <b>72</b>. The master transition field <b>71</b> accommodates the two-bit master transition. As noted above, the payload field is scrambled by the scrambler <b>33</b> the frame <b>70</b> is formed.

[0020] Two different kinds of frame having the basic structure shown in FIG. 2A, but differing in the structure of their payload fields are generated. The structure of the payload field depends on whether or not the two quads are composed exclusively of information words. The structure of the payload field is indicated by the master transition stored in the master transition field. FIG. 2B shows the structure of the frame <b>73</b> generated when the two quads are composed exclusively of information words. In this, the master transition in the master transition field <b>71</b> is 01, and the payload field <b>72</b> is composed of the eight information words constituting the quads, i.e., 64 bits.

[0021]FIG. 2C shows the structure of the frame <b>76</b> generated when the quads include at least one control word. In this, the master transition in the master transition field <b>71</b> is 10, and the payload field <b>72</b> is composed of the eight-bit sub-field <b>77</b> and the 56-bit sub-field <b>78</b>. The eight-bit sub-field is occupied by a TYPE word and the 56-bit sub-field is occupied by a compressed version of the quads. In particular, all information words included in the quads are included unchanged in the 56-bit sub-field. The 56-bit sub-field can accommodate up to seven information words, the maximum number of information words in two quads that include at least one control word. Moreover, the start-of-packet control word S and the end-of-packet control word T, if they appear in the quads, are discarded and are not transferred to the 56-bit sub-field. Instead, the value of the TYPE word indicates the presence and position of the control word S or the control word T. Finally, all remaining control words in the quads are compressed by re-coding them using fewer than eight bits and the re-coded control words are included in the 56-bit sub-field. In an embodiment, the remaining control words are re-coded using seven-bit codes chosen to have a mutual Hamming distance of four bits.

[0022] Returning now to FIG. 1, the multiplexer <b>35</b> receives the 66-bit frames from the frame assembler <b>34</b> and serializes them for transmission through the Ethernet medium <b>40</b> at a bit rate of 10 Gb/s.

[0023] In the receiver <b>22</b> of the data communication system <b>10</b>, the demultiplexer <b>36</b> receives the serial data stream having a bit rate of 10 Gb/s from the Ethernet medium <b>40</b>. The demultiplexer partitions the bitstream into 66-bit frames, and feeds the frames to the frame disassembler <b>37</b>.

[0024] The frame disassembler <b>37</b> operates on each frame to separate the master transition from the scrambled payload field, and feeds the master transition, suitably pipelined, to the master transition input of the 66b/64b decoder <b>52</b>. The frame disassembler also feeds the scrambled payload field to the descrambler <b>38</b>.

[0025] The descrambler <b>38</b> descrambles the scrambled payload field using self-synchronizing descrambling complementary to the scrambling performed by the scrambler <b>33</b>. The descrambler feeds the resulting recovered payload field to the payload field input of the 66b/64b decoder <b>52</b>.

[0026] The 66b/64b decoder <b>52</b> decodes the recovered payload field in response to the corresponding master transition received from the frame disassembler <b>37</b>. When the master transition is in its first state, the 66b/64b decoder simply outputs the eight words in the payload field as two consecutive quads. The 66b/64b additionally outputs a control word flag for each word in the quads. When the master transition is in its second state, the 66b/64b decoder reconstitutes the two quads from which the original frame was generated before outputting them together with a control word flag for each word in the quads. The 66b/64b decoder reconstitutes the two quads by reading the TYPE word and expanding any compressed control words in the field. Additionally, when the TYPE word indicates that either the start-of-packet control word S or the end-of-packet control word T was discarded by the 64b/66b encoder <b>50</b>, the 66b/64b decoder additionally inserts a start-of-packet control word or an end-of-packet control word into the location in the quad indicated by the TYPE word.

[0027] The 66b/64b decoder <b>52</b> transfers the quads and their respective control word flags in parallel to the 4×8b/10b encoder <b>39</b> via the pseudo-XGMII bus <b>49</b>.

[0028] The 4×8b/10b encoder <b>39</b> applies 8b/10b encoding to the quads received via the pseudo-XGMII bus <b>43</b>, operating in response to the control word flag for each word constituting the quads. The 4×8b/10b encoder outputs the resulting 10-bit line code words via the XAUI bus <b>19</b>.

[0029] It is customary to equip data communication systems with a self-test facility to enable the proper operation of the data communication system to be confirmed. Conventionally, the data communication system is tested by transmitting a test sequence composed of known sequence of random bit patterns through the data communication system and detecting errors at the receiver. The receiver may be co-located with the transmitter or may be remotely located.

[0030]FIG. 3 is a block diagram showing an example <b>60</b> of a data communication system incorporating a conventional self-test facility. The data communication system <b>60</b> is based on the communication system <b>10</b> shown in FIG. 1, and elements of the data communication system <b>60</b> that correspond to elements of the data communication system <b>10</b> are indicated by the same reference numerals and will not be described again here.

[0031] The data communication system <b>60</b> additionally includes the bit error rate tester <b>61</b>, the selector <b>62</b> and the selector <b>63</b>. Bit error rate testers are known in the art. The example of the bit error rate tester <b>61</b> shown includes the test sequence generator <b>64</b> and the error detector <b>65</b>.

[0032] The selector <b>62</b> has two data inputs, a control input and a data output. One data input is connected to the output of the frame assembler <b>34</b>. The other data input is connected to the output of the test sequence generator <b>64</b>. The control input is connected to the control line <b>66</b>. The data output is connected to the input of the multiplexer <b>35</b>.

[0033] The selector <b>63</b> has a data input, a control input and two data outputs. The data input is connected to the output of the demultiplexer <b>36</b>. The control input is connected to the control line <b>66</b>. One data output is connected to the input of the frame disassembler <b>37</b>. The other data output is connected to the input of the error detector <b>65</b>.

[0034] When the self-test enable control signal STE on the control line <b>66</b> is not asserted, the selector <b>62</b> connects the output of frame assembler <b>34</b> to the input of the multiplexer <b>35</b>, and the selector <b>63</b> connects the output of the multiplexer <b>36</b> to the input of the frame disassembler <b>37</b>. In this state, the data communication system <b>60</b> operates as described above. When the STE control signal is asserted, the selector <b>62</b> connects the output of the test sequence generator <b>64</b> to the input of the multiplexer <b>35</b>, and the selector <b>63</b> connects the output of the demultiplexer <b>36</b> to the input of the error detector <b>65</b>. The error detector synchronizes automatically to the received test sequence output by the demultiplexer and generates an error signal each time the received test sequence includes an error. The error detector may count the number of errors occurring in a predetermined time or during receipt of a predetermined number of bits to generate a bit error rate.

[0035] A commonly-available test sequence generator that can be used as the test sequence generator <b>64</b> generates a test sequence composed of 2³¹-1 (about 2.14 billion) bits. With a clock speed of 10 GHz, the test sequence has a cycle time of about 0.2 seconds, which is a convenient cycle time for most testing most types of data communication system. The test sequence generator outputs the test sequence in frames of 66 bits compatible with the input of the multiplexer <b>35</b>.

[0036] However, a 2³¹-bit test sequence has a maximum run length of 31 bits. A run length of 31 bits occurs in normal 64b/66b encoded bitstreams more often than once in 10¹⁰bits. As a result, a 2³¹-bit test sequence does not adequately test the error floor. A test sequence generator that generates a longer test sequence could be used, but at the expense of a substantially longer cycle time. The cycle time of a 2⁵⁸-bit test is about 333 days. This would make it difficult to repeat a part of the test sequence that caused the data communication system to fail.

[0037] Another disadvantage of the conventional test sequence generator is that the test sequence looks like an error to any receiver in the data communication system not in self-test mode. Some receivers may require significant time to recover from such an error state.

[0038] A further disadvantage is that the test sequence is introduced into the transmitter <b>20</b> downstream of the frame assembler <b>34</b>, so that the test sequence does not test the synchronization acquisition capability of the demultiplexer <b>36</b>.

[0039] Finally, the bit error rate tester <b>61</b> and the selectors <b>62</b> and <b>63</b> collectively add substantial circuit complexity to the data communication system <b>10</b>.

[0040] Thus, what is needed is a self-test facility that employs a test sequence that has a run length long enough to test adequately the error floor of a high-quality data communication system.

[0041] What is also needed is a self-test facility that generates a test sequence having a short cycle time.

[0042] What is also needed is a self-test facility that generates a test sequence that does not appear as an error to receivers not in a self-test mode.

[0043] What is also needed is a self-test facility that generates a test sequence that additionally tests the synchronization ability of the demultiplexer.

SUMMARY OF THE INVENTION

[0044] The invention provides a method for self testing a data communication system that includes a presettable scrambler and a complementary presettable descrambler. In the method, the presettable scrambler is preset to a preset state. A seed payload field is scrambled using the presettable scrambler to generate fields of a test sequence. The fields of the test sequence are transmitted and corresponding received test sequence fields are received. The received test sequence fields are descrambled using the presettable descrambler to generate respective recovered test sequence fields. Differences between the recovered test sequence fields and the seed payload field are then detected as errors.

[0045] The combination of the preset state and the seed payload field causes the presettable scrambler to generate the test sequence to include a desired bit sequence. The seed payload field may be one of a sequence of different seed payload fields that, when scrambled, generate the test sequence to include corresponding different desired bit patterns.

[0046] The presettable scrambler may be preset to the preset state by detecting an end bit sequence in the test sequence and presetting the presettable scrambler to the preset state when the end bit sequence is detected.

[0047] The method may additionally include detecting the end bit sequence in the recovered test sequence fields and presetting the presettable descrambler to the preset state when the end bit sequence is detected.

[0048] The invention also provides a method of generating a test sequence in a data transmitter that includes a scrambler. In the method, in a normal operating mode, payload fields are scrambled using the scrambler to generate respective scrambled payload fields, and the scrambled payload fields are transmitted. Then, in a self-test operating mode, a seed payload field is scrambled using the scrambler to generate fields of the test sequence, and the fields of the test sequence are transmitted.

[0049] The scrambler may be a presettable scrambler. In this case, the presettable scrambler is preset to a preset state, and a combination of the preset state and the seed payload field causes the presettable scrambler to generate the test sequence to include a desired bit pattern.

[0050] The invention also provides a method self-testing a data receiver that includes a descrambler. In the method, in a normal operating mode, scrambled payload fields are received as received payload fields, and the received payload fields are descrambled using the descrambler. Then, in a self-test operating mode, received test sequence fields generated by scrambling a seed payload field are received, the received test sequence fields are descrambled using the descrambler to generate respective recovered test sequence fields, and differences between the recovered test sequence fields and the seed payload field are detected as errors.

[0051] The invention also provides a data communication system having a built-in self-test facility. The data communication system comprises a seed payload field source, a presettable scrambler, a presettable descrambler and an error detector. The presettable scrambler includes an input connected to the seed payload field source and an output coupled to a data transmission medium. The presettable scrambler is presettable to a preset state. The presettable descrambler includes an input coupled to the transmission medium and an output. The error detector includes an input connected to the output of the presettable descrambler, and operates to generate an error indication when a recovered test sequence field output by the presettable descrambler differs from the seed payload field.

[0052] The data communication system may additionally comprise a detector and a controller. The detector detects an end bit sequence generated by the presettable scrambler. The controller operates in response to the detector to preset the presettable scrambler to the preset state. The data communication system may additionally comprise an additional detector and an additional controller. The additional detector detects the end bit sequence at the input of the presettable descrambler. The additional controller operates in response to the detector to preset the presettable descrambler to the preset state.

[0053] The invention also provides a data transmitter having a self-test facility. The data transmitter comprises a payload field source, a seed payload field source and a scrambler. The scrambler operates in a normal operating mode to receive payload fields from the payload field source and to scramble the payload fields to generate respective scrambled payload fields for transmission, and alternatively operates in a self-test mode to receive a seed payload field from the seed payload field source and to scramble the seed payload field to generate fields of a test sequence for transmission.

[0054] The scrambler may be a presettable scrambler capable of being preset to a preset state, in which case, a combination of the preset state and the seed payload field causes the presettable scrambler to generate the test sequence to include a desired bit pattern.

[0055] Finally, the invention provides a data receiver having a self-test facility. The data receiver comprises a descrambler and an error detector. The descrambler includes an output, and operates in a normal operating mode to descramble received payload fields to generate respective recovered payload fields, and alternatively operates in a self-test operating mode to descramble received test sequence fields generated by scrambling a seed payload field to generate respective recovered test sequence fields. The error detector includes an input connected to the output of the descrambler. The error detector operates to generate error indications when the recovered test sequence fields differ from the seed payload field.

[0056] The descrambler may be a presettable descrambler, in which case, the data receiver additionally comprises a controller that operates occasionally to preset the presettable descrambler to preset state.

BRIEF DESCRIPTION OF THE DRAWINGS

[0057]FIG. 1 is a block diagram showing an example of the 10 Gb/s Ethernet data communication system disclosed in the above-mentioned patent application.

[0058]FIG. 2A shows the basic structure of the frame generated from two quads by the data communication system shown in FIG. 1.

[0059]FIG. 2B shows the structure of the frame generated when the two quads are composed exclusively of information words.

[0060]FIG. 2C shows the structure of the frame generated when the quads include at least one control word.

[0061]FIG. 3 is a block diagram showing an example of the data communication system shown in FIG. 1 incorporating a conventional self-test facility.

[0062]FIG. 4 is a block diagram showing an example of a 10 Gb/s Ethernet data communication system according to the invention. The data communication system includes a self-test facility.

[0063]FIG. 5A is a block diagram showing an example of a serial version of the presettable scrambler of the data communication system shown in FIG. 4.

[0064]FIG. 5B is a block diagram showing an example of a serial version of the presettable descrambler of the data communication system shown in FIG. 4.

[0065]FIG. 6 is a block diagram showing an example of three consecutive stages of the shift register that forms part of the presettable scrambler and the presettable descrambler shown in FIGS. 5A and 5B, respectively.

[0066]FIG. 7 is a block diagram of an example of a parallel version of the presettable scrambler of the data communication system shown in FIG. 4.

DETAILED DESCRIPTION OF THE INVENTION

[0067] The invention is based on the observation that the test sequence generator <b>64</b> of the conventional bit error rate tester <b>61</b> shown in FIG. 3 has substantial circuit commonality with the scrambler <b>33</b> used to scramble the payload fields in the data communication system <b>60</b>. The invention is based on the realization that, if the existing scrambler could be used to generate a test sequence, a self-test facility could be provided more simply and less expensively than the conventional approach shown in FIG. 3.

[0068] In a first aspect of the invention, in the self-test operating mode of the data communication system, the existing scrambler, e.g. the scrambler <b>33</b> shown in FIG. 1, is fed with a seed payload field. The existing scrambler is used in the normal operating mode to scramble the payload fields. The scrambler <b>33</b> scrambles the seed payload field to generate the fields of a test sequence. Each of the fields is filled with pseudo-random bits. A master transition is added to each field of the test sequence and the resulting 66-bit frames are transmitted.

[0069] In the receiver, the test sequence fields are extracted from the received frames as received test sequence fields and the received test sequence fields are descrambled using the existing descrambler, e.g., the descrambler <b>38</b> shown in FIG. 1. The existing scrambler is used in the normal operating mode to descramble the scrambled payload fields. Descrambling the received test sequence fields results in recovered test sequence fields that are identical to the seed payload field when there are no transmission errors. Differences between the recovered test sequence fields and the seed payload field are detected as transmission errors. Thus, the invention provides a self-test facility without the need to provide a separate test sequence generator.

[0070] In an embodiment, a 58-bit scrambler is used as the scrambler <b>33</b> to prevent malicious jamming. As noted above, the test sequence generated by a 58-bit scrambler has too long a cycle time to be practical for testing most data communication systems. A second aspect of the invention overcomes this disadvantage by using a presettable 58-bit scrambler to generate the test sequence instead of the conventional 58-bit scrambler <b>33</b>. The presettable scrambler is preset to a preset state at the start of generating the test sequence, and is again preset to the preset state after it has generated a test sequence of a predetermined number of bits. For example, the presettable scrambler can be preset to its preset state after generating a test sequence of 2³¹bits. Such a test sequence has a cycle time of about 0.21 seconds, which is an acceptable cycle time for testing most data communication systems.

[0071] The presettable scrambler can be configured to detect when it has generated the final bits that constitute the end of a test sequence composed of the predetermined number of bits. These bits will be called the end bit sequence of the test sequence. The presettable scrambler can additionally be configured to preset itself when it detects the end bit sequence.

[0072] Using a presettable scrambler as the 58-bit scrambler and repetitively presetting the presettable scrambler to the preset state in accordance with the invention overcomes additional disadvantages of conventional test sequence generators. The invention enables the test sequence to be generated with a desired bit pattern appearing at a predetermined point therein. The desired bit pattern can be used to test specific performance characteristics of the data communication system. For example, the desired bit pattern can be one that thoroughly tests the noise floor of a high-quality data communication system. Such a desired bit pattern would be one having a run-length substantially longer than 31 bits.

[0073] For example, by appropriately choosing the content of the seed payload field received by the presettable 58-bit scrambler and by additionally choosing the preset state to which the presettable scrambler is preset, the test sequence can be configured to begin with a desired bit pattern having a run length of 46 zeroes. A different preset state can make the 46-bit run length sequence appear later in the test sequence. A different seed payload field can be used to provide a run-length of ones or zeroes up to a maximum run-length equal to the length of the scrambler. A sequence of two or more different seed payload fields can be fed to the presettable scrambler during each test sequence to cause the presettable scrambler to generate the test sequence to include corresponding different desired bit patterns.

[0074] Another advantage of using a presettable scrambler as the 58-bit scrambler and using the presettable scrambler to generate the test sequence is that the test sequence fields output by the presettable scrambler are fed to the frame assembler <b>34</b> which forms 66-bit frames from the test sequence fields and their respective master transitions. As a result, the bitstream generated by the transmitter in its self-test mode appears to any receiver as a normal bitstream, regardless of whether or not the receiver is in its self-test mode. Moreover, the test sequence tests the synchronization capabilities of the demultiplexer in the receiver.

[0075] A presettable descrambler is used as the 58-bit descrambler in the receiver. The presettable descrambler locks to the received test sequence after 58 bits have been received. Once locked, the presettable descrambler descrambles the received test sequence fields using descrambling complementary to the scrambling applied by the presettable scrambler <b>133</b>. As a result, when there are no transmission errors, the output of the presettable descrambler is a sequence of recovered test sequence fields identical to the seed payload field fed to the presettable scrambler. A transmission error is identified determining whether any of the recovered test sequence fields output by the presettable descrambler differs from the seed payload field.

[0076]FIG. 4 is a block diagram showing an example <b>100</b> of a 10 Gb/s Ethernet data communication system according to the invention. The data communication system includes a self-test facility. Elements of the data communication system shown in FIG. 4 that correspond to the data communication system shown in FIG. 1 will be indicated by the same reference numerals and will not be described again.

[0077] The digital transmission system <b>100</b> includes the transmitter <b>120</b> according to the invention and the receiver <b>122</b> according to the invention. The transmitter includes the presettable scrambler <b>133</b> and the receiver includes the presettable descrambler <b>138</b> and the error detector <b>165</b>.

[0078] The input of the resettable scrambler <b>133</b> is connected to the payload field output of the 64b/66b encoder <b>50</b> by the bus <b>43</b>. The output of the resettable scrambler is connected to the payload field input of the frame assembler <b>34</b> by the bus <b>44</b>. The input of the presettable descrambler <b>138</b> is connected to the payload field output of the frame disassembler <b>37</b> by the bus <b>47</b>. The output of the presettable descrambler is connected to the payload field input of the 66b/64b decoder <b>52</b> by the bus <b>48</b>. The output of the presettable descrambler is also connected to the input of the error detector <b>165</b>.

[0079] The control line <b>66</b> is connected to control inputs on the presettable scrambler <b>133</b>, the presettable descrambler <b>138</b>, the 64b/66b encoder <b>50</b>, the 66b/64b decoder <b>52</b> and the error detector <b>165</b>.

[0080] The data communication system <b>100</b> has a normal operating mode and a self-test operating mode. In the normal operating mode, the STE control signal on the control line <b>66</b> is not asserted. This causes the 64b/66b encoder <b>50</b> to operate as described above and additionally sets the presettable scrambler <b>133</b> to its conventional operating mode in which the above-described end bit sequence does not preset the presettable scrambler. With the 64b/66b encoder and the presettable scrambler operating as just described, the 64b/66b encoder encodes blocks of data received via the XAUI bus <b>18</b> to generate payload fields, and the presettable scrambler scrambles the payload fields to generate respective scrambled payload fields. The scrambled payload fields are formed into frames that are serialized and transmitted to the Ethernet medium <b>40</b>.

[0081] In addition, non-assertion of the STE control signal causes the 66b/64b decoder <b>52</b> to operate as described above, and sets the presettable descrambler <b>138</b> to its conventional operating mode in which the above-described end bit sequence does not preset the presettable scrambler. With the 66b/64b decoder and the presettable descrambler operating as described, a serial bitstream received from the Ethernet medium <b>40</b> is segmented into frames. Scrambled payload fields and master transitions are extracted from the frames and the payload fields are descrambled by the presettable descrambler to generate respective recovered payload fields. The 66b/64b decoder decodes the recovered payload fields in response to the corresponding master transitions to generate blocks of data for output via the XAUI bus <b>19</b>. Finally, the control signal disables the error detector <b>165</b>.

[0082] In the self-test operating mode, the STE control signal on the control line <b>66</b> is asserted. The STE control signal causes the 64b/66b encoder <b>50</b> to operate as the source of a seed payload field in which all the words are set to a predetermined state. In an embodiment, the seed payload field was composed of the words 55_H00_H00_H01_H00_H00_H00_H01^Hthat collectively indicate a Local Fault. This seed payload field will be called the Local Fault payload field. Some embodiments of the 64b/66b encoder are configured to operate in response to a control signal to generate a Local Fault payload field autonomously. In this case, the STE control signal can be used to activate this feature, or a command can be transmitted via the XAUI bus to cause the 64b/66b encoder to generate the Local Fault payload field. Using the Local Fault payload field as the seed payload field has the advantage that it causes receivers not in their self-test operating mode to ignore the test sequence. An alternative seed payload field is an Idle Payload field composed of the control words that indicate an idle condition.

[0083] The 64b/66b encoder <b>50</b> additionally generates a master transition for each seed payload field and feeds the master transition to the master transition input of the frame assembler <b>34</b> via the bus MT.

[0084] During the time that the STE control signal on the control line <b>66</b> is asserted, the 64b/66b encoder repetitively outputs the seed payload field and its master transition to the presettable scrambler <b>33</b> and the frame assembler <b>34</b>, respectively. The rate as which the seed payload field and its master transition are output is the same as that at which the payload fields and their master transitions are output in the normal operating mode.

[0085] Assertion of the STE control signal additionally switches the presettable scrambler <b>133</b> to its preset operating mode. The change of state of the STE control signal additionally presets the presettable scrambler to its preset state. In its preset operating mode, the presettable scrambler monitors the test sequence to detect the end bit sequence that indicates the end of the test sequence, and presets itself to the preset state each time it detects the end bit sequence.

[0086] In an embodiment, the presettable scrambler is preset by setting the following 58-bit number into the presettable scrambler <b>133</b> as the preset state: 10101111 11111111 11100000 10111111 11111100 00000111 11111111 10 in which the left-most bit is the oldest bit of state and the right-most bit is the newest bit of state.

[0087] In this embodiment, the combination of the preset state and the seed payload field described above causes the presettable scrambler <b>133</b> to generate a test sequence that begins with a desired bit pattern composed of a 46-bit run length of zeroes. A different preset state may be used to cause the presettable scrambler to generate the test sequence with a different desired bit pattern. Different desired bit patterns may be used to test different aspects of the performance of the data communication system. For example, the desired bit pattern composed of a 46-bit run length of zeroes may be located later in the test sequence. Other values of the preset state and the seed payload field may be used to generate a desired bit pattern having any desired run-length of ones or zeroes up to the number of stages in the presettable scrambler. As a further example, the test sequence can be generated to include a desired bit pattern that invokes a specific baseline wander condition, e.g., a maximum baseline wander or a minimum baseline wander. Finally, a sequence of two or more different seed payload fields may be fed to the presettable scrambler during generation of the test sequence to generate the test sequence to include corresponding different desired bit patterns. In this disclosure, the term a seed payload field will be understood to encompass a seed payload field that is part of a sequence of two or more seed payload fields.

[0088] The seed payload field fed to the presettable scrambler may be changed to a different seed payload field when the presettable scrambler is reset in response to the end bit sequence being detected. The changed seed payload field changes the end bit sequence that occurs in the test sequence after the predetermined number of bits has been detected.

[0089] The presettable scrambler <b>133</b> feeds 64-bit fields of the test sequence to the payload field input of the frame assembler <b>34</b>. The frame assembler forms 66-bit frames from the test sequence fields received from the presettable scrambler <b>133</b> and their respective master transitions received from the 64b/66b encoder <b>50</b> and feeds the 66-bit frames to the multiplexer <b>35</b>. For example, the frame assembler may append each test sequence field to its master transition, as illustrated in FIG. 2A.

[0090] However, the master transition can be embedded in the test sequence field in an arbitrary way as long as the arbitrary way is known to the receiver. Moreover, in a data communication system that does not employ master transitions to provide information about the payload field, an arbibrary sync pattern can be embedded in, or appended to, the test sequence field in an arbitrary way as long as the receiver knows the sync pattern and the arbitrary way. The sync pattern can be any stable computably-checkable pattern. For example, a parity bit of the payload field can be used as the sync pattern. In this case, the receiver would shift the phase of the demultiplexer <b>36</b> until it found a stable bit that agreed with the parity of the payload field.

[0091] The multiplexer <b>35</b> generates a serial bit stream from the 66-bit frames and feeds the bitstream to the Ethernet medium <b>40</b>.

[0092] In the receiver <b>122</b>, the demultiplexer <b>36</b> partitions the serial bit stream received from the Ethernet medium <b>40</b> into 66-bit frames, and feeds the frames to the frame disassembler <b>37</b>. The frame disassembler <b>37</b> processes each frame to separate the master transition from the received test sequence field, and feeds the master transition to the master transition input of the 66b/64b decoder <b>52</b>. The frame disassembler also feeds the received test sequence field to the presettable descrambler <b>138</b>.

[0093] The STE control signal switches the presettable descrambler <b>138</b> into its preset operating mode. In the preset operating mode, the presettable descrambler descrambles the received test sequence fields received from the frame disassembler <b>37</b> to generate respective recovered test sequence fields. The presettable descrambler additionally monitors the received test sequence fields to detect the end bit sequence, and presets itself to the same preset state as the presettable scrambler <b>133</b> each time it detects the end bit sequence. The presettable descrambler feeds the recovered test sequence fields to the 66b/64b decoder <b>52</b> and to the error detector <b>165</b>.

[0094] The STE control signal sets the 66b/64b decoder to ignore the recovered test sequence fields output by the presettable descrambler <b>138</b>. The STE control signal also activates the error detector <b>165</b>. The error detector examines the recovered test sequence fields received from the presettable descrambler. When the data communication system is error-free, each recovered test sequence field is identical to the seed payload field described above. The error detector detects whether each recovered test sequence field is different from the seed payload field and counts the number of test sequence fields detected to be in error as bad test sequence fields to provide an estimate of the bit error rate. Alternatively, the error detector may detect and count each difference between the recovered test sequence fields and the seed payload field. When this is done, since the presettable descrambler multiplies the effect of any bit error by as many as three, the error detector divides the error count by three to estimate the bit error rate.

[0095] The FIG. 5A is a block diagram showing an example of a serial version of the presettable scrambler <b>133</b> that scrambles using the polynomial x⁵⁸+x³⁹+x⁰. Modifications to the example to implement scrambling using other polynomials will be apparent to the person of ordinary skill in the art. The presettable scrambler is composed of the shift register <b>201</b>, the exclusive-OR (XOR) gates <b>202</b> and <b>203</b>, the preset state generator <b>204</b>, the N-input AND gate <b>205</b> and the controller <b>206</b>. N is the number of stages in the shift register.

[0096] A multiplexer (not shown) forms a serial bitstream from the seed payload field received from the 64b/66b encoder <b>50</b> (FIG. 4). The serial bitstream is received at the input <b>210</b>, which is connected to one input of the XOR gate <b>202</b>. The other gate input of the XOR gate <b>202</b> is connected to the output of the XOR-gate <b>203</b>. The output of the XOR gate <b>202</b> is connected to the output <b>212</b>, and also to the data input D of the shift register <b>201</b>. The scrambled serial bitstream output at the output <b>212</b> passes via a demultiplexer (not shown) to the frame assembler <b>34</b> (FIG. 4).

[0097] The preset state generator <b>204</b> is composed of 58 state generators, each of which is set to 0 or to 1 in accordance with the corresponding digit of the 58-bit preset state. In the example of the preset state discussed above, the preset state generator sets the preset inputs P of stages <b>1</b> through <b>58</b> to 01 11111111 11100000 00111111 11111101 00000111 11111111 11110101, respectively. Circuit blocks for generating a predetermined set of states are known in the art and will not be described here.

[0098]FIG. 5A shows four exemplary stages, <b>1</b>, <b>2</b>, <b>39</b> and <b>58</b> of an example of the shift register <b>201</b> that has 58 stages. Each stage is presettable to the state set on its preset input P. Each stage has a data output Q. The preset input P of each stage of the shift register <b>201</b> is connected to a different one of the outputs of the preset state generator <b>204</b>.

[0099] The data output Q of each stage of the shift register <b>201</b> is connected to a different one of the inputs of the N-input AND gate <b>205</b>. The N-input AND gate is configured to detect when the end bit sequence appears on the outputs of the shift register. Each input of the AND gate <b>205</b> is inverting or non-inverting (indicated by the x-symbols) depending on the 1s and 0s of the end bit sequence. When the shift register has 58 stages, the N-input AND gate <b>205</b> is a 58-input gate, and the end bit sequence is the last 58 bits of the test sequence. When the end bit sequence appears on the outputs of the shift register, an input of the gate connected to an output in the 0 state is inverting and an input connected to an output in the 1 state is non-inverting. For example if bits <b>1</b>, <b>2</b> and <b>58</b> of the end bit sequence are 010, gate inputs <b>1</b> and <b>58</b> are inverting and input <b>2</b> is non-inverting.

[0100] The output of the N-input AND gate <b>205</b> is connected to one input of the controller <b>206</b>. The other input of the controller receives the self test enable control signal STE via the control line <b>66</b>. The output of the controller is connected to the preset input PS of the shift register <b>201</b>.

[0101] The data outputs Q of stages <b>39</b> and <b>58</b> of the shift register <b>201</b> are additionally connected to the inputs of the XOR gate <b>203</b>.

[0102] In the normal operating mode of the data communication system <b>100</b>, the low state of the control signal STE holds the output of controller <b>206</b> low, which holds the preset input PS of the shift register <b>201</b> low. This inhibits any presetting of the contents of the shift register <b>201</b> and the presettable scrambler <b>133</b> scrambles the payload fields received from the 64b/66b encoder <b>50</b> using the polynomial x⁵⁸+x³⁹+x⁰.

[0103] In the self-test operating mode, the seed payload field is present at the input of the presettable scrambler <b>133</b>. The control signal STE is in its high state. The change of state of the control signal STE causes the output of the controller <b>206</b> to change state for one clock cycle. The high state of the preset input PS of the shift register <b>201</b> loads the state on the preset input P of each stage into the stage, and transfers the state to the data output Q of the stage. When the preset input returns to its low state, the presettable scrambler scrambles the Local Fault payload field starting with the shift register <b>201</b> preset to the preset state. In the example described above, the first 46 digits output are all zeros.

[0104] The presettable scrambler <b>133</b> continues to scramble the Local Fault payload field until the last 58 bits output correspond to the end bit sequence described above. For example, the last 64 bits output by the presettable scrambler at the end of a test sequence of 2³¹bits is (40 2B BA 29 1E 44 6E DD)_H.

[0105] When the last 58 bits output by the presettable scrambler <b>133</b> are the end bit sequence, the end bit sequence additionally appears on the data outputs Q of the shift register <b>201</b>. This causes the output of the N-input AND gate <b>205</b>, the output of the controller <b>206</b> and the preset input PS of the shift register <b>201</b> all to go high. The high state of the preset input PS once more loads the state on the preset input P of each stage into the stage and sets the data output Q of each stage to the state of the preset input. The change in the states of the data outputs Q of the shift register causes the output of the N-input AND gate to go low. The low state of the N-input AND gate output returns the output of the controller and the preset input PS of the shift register to their low states, and the cycle repeats.

[0106] The output of the controller <b>206</b> may be used to change the seed payload field fed to the presettable scrambler <b>133</b> when the presettable scrambler is preset. This enables the test sequence generated after the preset to include a different desired bit pattern from the test sequence generated before the preset. Two different seed payload fields may alternate. Alternatively, a loop consisting of a sequence of more than two seed payload fields, at least two of which are different, may be used.

[0107] When the seed payload field is changed, the end bit sequence of the test sequence also changes. In this case, the presettable scrambler <b>133</b> may include more than one N-input gate. Each N input gate detects a different end bit sequence. The outputs of the N-input gates are fed to the controller <b>206</b> through a selector that selects the output of the N-input gate that detects the end bit sequence of the test sequence currently being generated. The presettable descrambler <b>138</b> may include a similar arrangement.

[0108]FIG. 5B is a block diagram showing an example of a serial version of the presettable descrambler <b>138</b>. Elements of the presettable descrambler <b>138</b> that correspond to elements of the presettable scrambler <b>133</b> shown in FIG. 5A are indicated by the same reference numerals and will not be described again. In the presettable descrambler, the bits of the test sequence field received from the frame disassembler <b>37</b> via the input <b>214</b> are fed into the input D of the shift register <b>201</b>. This corresponds to the test sequence field generated by the presettable scrambler shown in FIG. 5A being fed into the input D of the shift register. The recovered test sequence field is fed to the output <b>216</b> from the output of the XOR gate <b>202</b>.

[0109] The output of the N-input AND gate <b>205</b> is connected to one input of the <b>2</b>-input AND gate <b>209</b>. The other input of the AND gate <b>209</b> receives the self test enable control signal STE via the control line <b>66</b>. The output of the AND gate <b>209</b> is connected to the preset input PS of the shift register <b>201</b>.

[0110] In the normal operating mode, the low state of the control signal STE holds the output of the AND gate <b>209</b> low, which holds the preset input PS of the shift register <b>201</b> low. This inhibits any presetting of the contents of the shift register <b>201</b> and the presettable descrambler <b>138</b> descrambles the scrambled payload fields using the polynomial x⁵⁸+x³⁹+x⁰to generate respective recovered payload fields that are output to the 66b/64b decoder <b>52</b>.

[0111] In the self-test operating mode, the control signal STE changes to its high state, which enables the output of the N-input AND gate <b>209</b> to control the preset input PS of the shift register <b>201</b>. The output of the AND gate <b>209</b> is initially low, so the presettable descrambler descrambles the received test sequence fields resulting until the last 58 bits received by the presettable descrambler <b>138</b> are the end bit sequence.

[0112] When the last 58 bits received are the end bit sequence, the end bit sequence additionally appears on the data outputs Q of the shift register <b>201</b>. This causes the output of the N-input AND gate <b>205</b>, the output of the AND gate <b>209</b> and the preset input PS of the shift register <b>201</b> all to go high. The high state of the preset input loads the state on the preset input P of each stage into the stage, which changes the states of the data outputs Q of the shift register. This causes the output of the N-input AND gate <b>205</b> to go low. The low states of the outputs of the AND gates <b>205</b> and <b>209</b> return the preset input PS of the shift register to its low state. This allows the presettable descrambler to descramble the received test sequence fields starting with the shift register <b>201</b> preset in the preset state. This preset sequence repeats every time the end bit sequence is received.

[0113] It should be noted that the preset transition that takes place in the presettable descrambler <b>138</b> when the end bit sequence is receive takes place seamlessly and noiselessly.

[0114]FIG. 6 is a block diagram showing an example of three consecutive stages that form part of the shift register <b>201</b> shown in FIGS. 5A and 5B. In an embodiment, the shift register is composed of 58 identical stages. The stage <b>220</b> will be described. The stage <b>220</b> is composed of the delay element <b>222</b> and the two-input selector <b>224</b>. The output of the selector is connected to the data input D of the delay element. One input of the selector is connected to the output of the previous stage <b>226</b>. The other input is connected to the output of the preset state generator <b>204</b> corresponding to the stage <b>220</b>. The control input of the selector is connected via the preset line to the preset input PS of the shift register.

[0115] The data output Q of the delay element <b>222</b> is connected to the next stage <b>228</b> and also to an input of the N-input AND gate <b>205</b> shown in FIGS. 5A and 5B. The clock input of the delay element is connected via the clock line to the clock input C of the shift register <b>201</b>.

[0116] When the preset input PS is low, the selector <b>224</b> connects the output Q of the previous stage <b>226</b> to the data input D of the delay element <b>222</b>. On the next clock cycle, the state on the data input D is clocked to the output of the delay element <b>222</b> and thus to the next stage <b>228</b>. When the preset input PS is high, the selector <b>224</b> connects the output of the preset state generator <b>204</b> corresponding to the stage <b>220</b> to the data input D of the delay element. On the next clock cycle, the preset state corresponding to the stage <b>220</b> is clocked to the output Q of the delay element and to the input of the next stage <b>228</b>. Thus, the output of the stage <b>220</b> is set to the preset state.

[0117]FIG. 7 is a block diagram of an example of a parallel version of the presettable scrambler <b>133</b> shown in FIG. 5A. Elements of the presettable scrambler shown in FIG. 7 that correspond to those of the presettable scrambler shown in FIG. 5A are indicated using the same reference numerals and will not be described again here.

[0118] An example <b>250</b> of a 58-bit parallel presettable scrambler that scrambles a 64-bit payload field using the polynomial x⁵⁸+x³⁹+x⁰to generate a 64-bit scrambled payload field will be described. Modifications to the example shown to use a different polynomial and/or to scramble payload fields of a different size will be apparent to a person of ordinary skill in the art.

[0119] The presettable scrambler <b>250</b> is composed of the selector <b>252</b>, the scrambler register <b>254</b> and the XOR gate array <b>256</b>. The presettable scrambler additionally includes the preset state generator <b>204</b>, the N-input AND gate <b>205</b> and the controller <b>206</b>, described above.

[0120] The preset state generator is composed of 58 state generators numbered <b>1</b>-<b>58</b>. An exemplary state generator is shown at <b>258</b>. The state generator has an output P that is set to 0 or to 1 in accordance with the corresponding digit of the 58-bit preset state. The remaining 57 state generators have the same structure and operation.

[0121] The selector <b>252</b> is composed of 58 two-input change-over switches numbered <b>1</b>-<b>58</b>. An exemplary switch is shown at <b>260</b>. The switch <b>260</b> has two inputs A and B, an output M and a control input. The switch connects the input A to the output M when the preset line PS is not asserted, and connects the input B to the output M when the preset line PS is asserted. The remaining 57 switches have the same structure and operation.

[0122] The scrambler register <b>254</b> is composed of 58 latches numbered <b>1</b>-<b>58</b>. An exemplary latch is shown at <b>262</b>. The latch <b>262</b> has an input E, an output S and a control input. The latch transfers the state at its input E to its output S when the load signal on the load line L is asserted on the arrival of a new payload field at the input of the presettable scrambler <b>250</b>. The remaining 57 latches have the same structure and operation.

[0123] The XOR gate array <b>256</b> is composed of 64 three-input exclusive-OR (XOR) gates <b>1</b>-<b>64</b>. An exemplary XOR gate is shown at <b>265</b>. The XOR gate <b>265</b> has an input X, an input Y, an input Z and an output T. The remaining 63 XOR gates have the same structure and operation.

[0124] The inputs A of the switches <b>1</b>-<b>58</b>, indicated by A(<b>1</b>-<b>58</b>), of the selector <b>252</b> are connected in order to the outputs T of the XOR gates <b>1</b>-<b>58</b> of the XOR gate array <b>256</b>, indicated by T(<b>1</b>-<b>58</b>). The inputs B of the switches <b>1</b>-<b>58</b>, indicated by (B-<b>1</b>-<b>58</b>) of the selector are connected in order to the outputs P of the state generators <b>1</b>-<b>58</b>, indicated by P(<b>1</b>-<b>58</b>), of the preset state generator <b>204</b>. The control inputs of the switches <b>1</b>-<b>58</b> of the selector are all connected to the preset line PS. The preset line is connected to the output of the controller <b>206</b>. The outputs M of the switches <b>1</b>-<b>58</b>, indicated by M(<b>1</b>-<b>58</b>), of the selector are connected in order to the inputs E of the latches <b>1</b>-<b>58</b> indicated by E(<b>1</b>-<b>58</b>), of the scrambler register <b>254</b>.

[0125] The control inputs of the latches <b>1</b>-<b>58</b> of the scrambler register <b>254</b> are all connected to the load line L. The load line is asserted each time the presettable scrambler <b>250</b> receives a new payload field from the 64b/66b encoder <b>50</b>.

[0126] The outputs S of the latches <b>1</b>-<b>58</b>, indicated by S(<b>1</b>-<b>58</b>), of the scrambler register <b>254</b> are connected in order to the inputs X of the XOR gates <b>7</b>-<b>64</b>, indicated by X(<b>7</b>-<b>64</b>), of the XOR gate array <b>256</b>. In addition, the outputs S of the latches <b>1</b>-<b>39</b>, indicated by s(<b>1</b>-<b>39</b>) of the scrambler register are connected in order to the inputs Y of the XOR gates <b>26</b>-<b>64</b>, indicated by Y(<b>26</b>-<b>64</b>), of the XOR gate array <b>256</b>.

[0127] The input, indicated by I(<b>1</b>-<b>64</b>), from the payload field output of the 64b/66b encoder <b>50</b> is connected to the inputs Z of the XOR gates <b>1</b>-<b>64</b>, indicated by Z(<b>1</b>-<b>64</b>) of the XOR gate array <b>256</b>.

[0128] The outputs T of the XOR gates <b>1</b>-<b>64</b>, indicated by T(<b>1</b>-<b>64</b>) of the XOR gate array <b>256</b> are connected to the output, indicated by O(<b>1</b>-<b>64</b>), of the presettable scrambler <b>250</b>. Additionally, the outputs T of the XOR gates <b>40</b>-<b>64</b>, indicated by T(<b>40</b>-<b>64</b>), of the XOR gate array are connected to the inputs Y of the XOR gates <b>1</b>-<b>25</b>, indicated by Y(<b>1</b>-<b>25</b>), of the XOR gate array. Finally, the outputs T of the XOR gates <b>59</b>-<b>64</b>, indicated by T(<b>59</b>-<b>64</b>), of the XOR gate array are connected to the inputs X of the XOR gates <b>1</b>-<b>6</b>, indicated by X(<b>1</b>-<b>6</b>), of the XOR gate array.

[0129] In the normal operating mode of the data communication system <b>100</b>, the low state of the control signal STE holds the output of the controller <b>206</b> low, which holds the preset line PS of the selector <b>252</b> low. This connects the outputs T of the XOR gates <b>1</b>-<b>58</b> of the gate array <b>256</b> to the outputs M of switches <b>1</b>-<b>58</b>, respectively, of the selector, and thence to the inputs E of the latches <b>1</b>-<b>58</b> of the scrambler register <b>254</b>. No resetting of the presettable scrambler <b>250</b> occurs and the presettable scrambler scrambles the payload fields using the polynomial x⁵⁸+x³⁹+x⁰.

[0130] In the self-test operating mode, the presettable scrambler <b>250</b> receives the seed payload field at its input I. The control signal STE is in its high state. The change of state of the control signal STE causes the output of the controller <b>206</b> to change to its high state for one clock cycle. The high state of the preset line PS causes the selector <b>252</b> to connect the outputs P of elements <b>1</b>-<b>58</b> of the preset state generator <b>252</b> to the outputs M of switches <b>1</b>-<b>58</b>, respectively, of the selector, and thence to the inputs E of the latches <b>1</b>-<b>58</b> of the scrambler register <b>254</b>. The Load signal thus loads the outputs of the preset state generator into latches <b>1</b>-<b>58</b> of the scrambler register. This sets the states of the outputs T of the XOR gates providing the output of presettable scrambler <b>250</b>. In the example described above, the outputs are set to (00 00 00 00 00 28 FF 03)_H.

[0131] When the preset line PS returns to its low state, the outputs of the XOR gates <b>1</b>-<b>58</b> of the XOR gate array <b>256</b> are once more fed to the outputs M of switches <b>1</b>-<b>58</b>, respectively, of the selector <b>252</b>, and thence to the inputs E of the latches <b>1</b>-<b>58</b> of the scrambler register <b>254</b>. However, due to the preset operation, the outputs of the XOR gates differ from what they were before the preset. The presettable scrambler <b>250</b> scrambles the Local Fault payload field starting with the scrambler register <b>254</b> preset to the preset state.

[0132] The presettable scrambler <b>250</b> continues to scramble the Local Fault payload field to generate successive fields of the test sequence until the states of the outputs S of the scrambler register <b>254</b> correspond to the end bit sequence described above.

[0133] When the states of the outputs S of the scrambler register <b>254</b> correspond to the end bit sequence, the output of the N-input AND gate <b>205</b> changes state. This causes the output of the controller <b>206</b> and the preset line PS of the scrambler register both to go high. The high state of the preset line once more loads the preset state output by the preset state generator <b>204</b> into the scrambler register. The preset state changes the states of the outputs of the scrambler register, which causes the output of the N-input AND gate to go low. The low state of the output of the AND gate <b>205</b> returns the output of the controller and the preset input PS of the scrambler register to their low states, and the cycle repeats.

[0134] It will be apparent to the person of ordinary skill in the art that a parallel presettable descrambler can be made by rearranging the parallel presettable scrambler <b>250</b> in a manner analogous to the way the serial presettable scrambler shown in FIG. 5A is rearranged to make the serial presettable descrambler shown in FIG. 5B.

[0135] The embodiments of the data communication system <b>100</b>, transmitter <b>120</b> and receiver <b>122</b> described in this disclosure may be constructed from small-scale or large-scale integrated circuits, suitably-configured ASICs, gate arrays and other suitable hardware.

[0136] The invention has been described with reference to an example in which the 64b/66b encoder <b>50</b> serves as the source of the seed payload field. However, this is not critical to the invention. The transmitter <b>120</b> can include a source of the seed payload field independent of the 64b/66b encoder. For example, a 64-channel 2-input selector (not shown) can be located between the payload output of the 64b/66b encoder and the input of the presettable scrambler <b>133</b>. One set of inputs of the selector is connected to the output of the 64b/66b encoder, the other set of inputs is connected to receive the seed payload field, e.g., the Local Fault payload field. A generator similar to the preset state generator <b>204</b> shown in FIG. 7 can be used as the source of the seed payload field, for example. The outputs of the selector are connected to the input of the presettable scrambler. The selector is controlled by the control signal STE to feed the seed payload field to the presettable scrambler when the control signal STE is asserted.

[0137] The invention has been described with reference to examples that employ certain logic states. However, it will be apparent to the person of is ordinary skill in the art that the functions and structures described in this disclosure can be accomplished using different logic states.

[0138] Although this disclosure describes illustrative embodiments of the invention in detail, it is to be understood that the invention is not limited to practiced within the scope of the invention defined by the appended claims.