Faster image processing

BACKGROUND

P-0001[0001] 1. Field of the Invention

P-0002[0002] This invention relates to image processing.

P-0003[0003] 2. Related Technology

P-0004[0004] ANSI Standard C “memcpy” Function

P-0005[0005] A given computer hardware architecture will have an optimal means of copying a block of data from one location in a memory to another location. Complex Instruction Set Computing (CISC) architectures implement instructions that over a number of CPU cycles move a block of data. Reduced Instruction Set Computing (RISC) architectures optimize the instruction set to process each instruction in one or two CPU cycles but also included instructions that can be used to implement a short routine that will accomplish the block move in an optimal manner. An efficient routine for copying a block of data can be implemented for each specific computer architecture.

P-0006[0006] Some computer architectures include Direct Memory Access (DMA) circuitry that transfers data between memory and input/output (I/O) devices without continual central processing unit (CPU) intervention.

P-0007[0007] The ANSI standard for the C Programming Language defines a “memcpy” library function as an interface to an efficient routine for copying a block of bytes to another location.

P-0008[0008] Graphical Images

P-0009[0009] A television screen has a 4:3 aspect ratio. In the United States, television signals contain 525 scan lines of which 480 lines are visible on most televisions. When an analog video signal is digitized, each of the 480 lines are sampled 640 times, and each sample is represented by a number. Each sample point is called a picture element, or pixel. A two dimensional array is created that is 640 pixels wide and 480 pixels high. This 640×480 pixel array is a still graphical image that is considered to be full frame. The human eye can optimally perceive approximately 16.7 thousand colors. A pixel value comprised of 24 bits can represent each perceivable color. A graphical image made up of 24-bit pixels is considered to be full color. A standard Super VGA (SVGA) computer display has a screen resolution of 640 by 480 pixel. Twenty-four bits is three bytes. It is common to use a fourth byte for each pixel to specify a mask value or alpha channel. A typical image being processed may contain over 1.2 million bytes of data.

P-0010[0010] When digitizing a video signal, or when manipulating the graphics to be output as a video signal or to be displayed on a computer display it may be necessary to copy the image data to another area of memory (a buffer) for some type of image processing. However, the copied buffer takes up significant memory resources. Also the time it takes to copy the image can be significant especially when the image processing must be done in real time. Those skilled in the art realize that to improve processing performance the number of memory buffers containing a copy of the same data should be reduced to the minimum set possible.

P-0011[0011] Display Video RAM

P-0012[0012] The memory of a computer system may be physically implemented in different areas or on different boards. The main memory is used for storage of program instructions and data. A special memory area called “video RAM” may be dedicated to storing the image that is to be displayed on the computer display. The video RAM has special hardware that allows it to be accessed to update the display over 60 times a second.

P-0013[0013] Capture Video RAM

P-0014[0014] A video digitizer or video capture card may also contain a special memory area similar to display video RAM for capturing the digital samples from the video signal. This RAM may also have special hardware that allows it to be updated 60 times a second.

P-0015[0015] Cache Memory

P-0016[0016] Many computer architectures implement one or more levels of memory caching whereby blocks of memory data are stored in a cache memory that may be accessed more rapidly by the CPU. Typically input and output (I/O) memories such as video RAM, capture RAM, or hard disk buffers are not cached.

SUMMARY OF THE INVENTION

P-0017[0017] In accordance with the present invention, methods are provided of increasing performance of image processing by copying image data between I/O memory and main memory where CPU intensive processing of the image data is more efficiently performed

P-0018[0018] Objects and Advantages

P-0019[0019] Accordingly, beside the objects and advantages of the method described in the patent above, some additional objects and advantages of the present invention are:

P-0020[0020] (a) to provide efficient processing of image data prior to display on a computer display.

P-0021[0021] (b) to provide efficient processing of image data being captured in real time with a video digitizer.

P-0022[0022] (c) to reduce the time necessary to process the image data.

DRAWING FIGURES

P-0023[0023] In the drawings, closely related figures have the same number but different alphabetic suffixes.

P-0024[0024]FIG. 1A shows a basic computer architecture.

P-0025[0025]FIG. 1B shows components for video digitizing.

P-0026[0026]FIG. 1C shows components for computer display.

P-0027[0027]FIG. 2A shows a multi-level cache architecture.

P-0028[0028]FIG. 2B shows a DMA architecture.

P-0029[0029]FIG. 3A shows images copied between an I/O video RAM and main memory.

P-0030[0030]FIG. 3B shows an input image being input and encoded.

P-0031[0031]FIG. 3C shows encoded data being decoded and output.

P-0032[0032]FIG. 4 shows row by row copy of a subset image.

P-0033[0033]FIG. 5 shows a flowchart for copying a subset image from I/O RAM to a memory buffer.

P-0034[0034]FIG. 6 shows a flowchart for copying a memory buffer to a subset image in I/O RAM.

P-0035[0035]<tables id="TABLE-US-00001" num="1"><table frame="none" colsep="0" rowsep="0"><tgroup align="left" colsep="0" rowsep="0" cols="1"><colspec colname="1" colwidth="217PT" align="center" /><thead><row><entry /></row><row><entry namest="1" nameend="1" align="center" rowsep="1" /></row><row><entry>Reference Numerals in Drawings</entry></row><row><entry namest="1" nameend="1" align="center" rowsep="1" /></row></thead><tbody valign="top"><row><entry /></row></tbody></tgroup><tgroup align="left" colsep="0" rowsep="0" cols="4"><colspec colname="1" colwidth="28PT" align="left" /><colspec colname="2" colwidth="70PT" align="left" /><colspec colname="3" colwidth="21PT" align="left" /><colspec colname="4" colwidth="98PT" align="left" /><tbody valign="top"><row><entry>100</entry><entry>input</entry><entry>101</entry><entry>CPU</entry></row><row><entry>102</entry><entry>output</entry><entry>103</entry><entry>memory</entry></row><row><entry>110</entry><entry>video source</entry><entry>111</entry><entry>video digitizer</entry></row><row><entry>113</entry><entry>capture video RAM</entry><entry>120</entry><entry>display video RAM</entry></row><row><entry>121</entry><entry>video display</entry></row><row><entry>220</entry><entry>I/O RAM</entry><entry>230</entry><entry>cache</entry></row><row><entry>240</entry><entry>CPU cache</entry><entry>250</entry><entry>DMA circuitry</entry></row><row><entry>252</entry><entry>DMA control</entry><entry>254</entry><entry>DMA-Memory bus</entry></row><row><entry>256</entry><entry>DMA-I/O bus</entry></row><row><entry>300</entry><entry>buffer</entry><entry>305</entry><entry>buffer-image copy</entry></row><row><entry>310</entry><entry>image</entry><entry>320</entry><entry>encoder</entry></row><row><entry>330</entry><entry>encoded data</entry><entry>340</entry><entry>decoder</entry></row><row><entry>400</entry><entry>super-image</entry><entry>420</entry><entry>first image line</entry></row><row><entry>422</entry><entry>second image line</entry><entry>424</entry><entry>last image line</entry></row><row><entry>430</entry><entry>first buffer line</entry><entry>432</entry><entry>second buffer line</entry></row><row><entry>434</entry><entry>last buffer line</entry></row><row><entry>w</entry><entry>image width</entry><entry>h</entry><entry>image height</entry></row><row><entry>x</entry><entry>image horizontal offset</entry><entry>y</entry><entry>image vertical offset</entry></row><row><entry>500</entry><entry>image copy start</entry><entry>510</entry><entry>image copy initialization step</entry></row><row><entry>520</entry><entry>set counter step</entry><entry>530</entry><entry>image copy done decision</entry></row><row><entry>540</entry><entry>image copy step</entry><entry>550</entry><entry>update pointers step</entry></row><row><entry>560</entry><entry>increment index step</entry><entry>599</entry><entry>image copy exit</entry></row><row><entry>600</entry><entry>buffer copy start</entry><entry>610</entry><entry>buffer copy initialization step</entry></row><row><entry>620</entry><entry>set counter step</entry><entry>630</entry><entry>buffer copy done decision</entry></row><row><entry>640</entry><entry>buffer copy step</entry><entry>650</entry><entry>update pointers step</entry></row><row><entry>660</entry><entry>increment index step</entry><entry>699</entry><entry>buffer copy exit</entry></row><row><entry namest="1" nameend="4" align="center" rowsep="1" /></row></tbody></tgroup></table></tables>

DESCRIPTION OF THE INVENTION

P-0036[0036]FIGS. 1A to <b>1</b>C—Computer Architectures

P-0037[0037]FIG. 1A is a block diagram showing the basic components of a computer, comprising an input <b>100</b>, a CPU <b>101</b>, an output <b>102</b>, and memory <b>103</b>.

P-0038[0038]FIG. 1B shows an embodiment of the computer input <b>100</b> specialized to input video data. A video source <b>110</b> is connected to a video digitizer <b>111</b>. The video digitizer <b>111</b> converts the analog video signal from the video source <b>110</b> to a digital format Some video digitizers transfer the video data to memory <b>103</b> for storage. Alternatively, some video digitizers contain capture video RAM <b>113</b> which can store the captured video data on the video digitizer <b>111</b> hardware without using memory <b>103</b> for storage.

P-0039[0039]FIG. 1C shows an embodiment of the computer output <b>102</b> specialized to output video data. A video display <b>121</b> (also knows as a computer monitor) displays graphical information based on data contained in a display video RAM <b>120</b>. Programs running on the CPU <b>101</b> determine the contents of the display video RAM that is then shown by pixels on the video display <b>121</b>.

P-0040[0040] FIGS. <b>2</b>A and <b>2</b>B—Caching and DMA

P-0041[0041]FIG. 2A is a block diagram showing computer architecture where there optionally are two levels of caches. The CPU <b>101</b> has an internal cache known as a CPU cache <b>240</b> that can store copies of recently accessed memory blocks that contain program instructions or data. A cache <b>230</b> stores copies of recently accessed blocks of memory data, because the cache <b>230</b> is outside the processor it is sometimes referred to as an external cache. In an architecture where the CPU has an internal CPU cache <b>240</b>, the cache <b>230</b> may also be referred to as a level <b>2</b> cache.

P-0042[0042] If a copy of a block of memory data is in the CPU cache <b>240</b> or the memory cache <b>230</b>, the CPU <b>101</b> can access it much faster than if the data has to be fetched from memory <b>103</b>. If the data is not available to the CPU <b>101</b>, the CPU <b>101</b> stalls causing there to be cycles where no useful processing is being done. The use of caches (<b>230</b>, <b>240</b>) can have a significant impact of the speed of data processing.

P-0043[0043] It is common for input and output device registers and memories to be mapped into the memory address range. This is called memory mapped I/O. In a computer architecture that uses memory mapped I/O, the random access memory (RAM) associated with computer input <b>100</b> and output <b>102</b> devices can be accessed by programs running on the CPU as if they were memory <b>103</b> RAM. Because the I/O RAM <b>220</b> can be modified by its respective input <b>100</b> or output <b>102</b> device, special provisions are made so that the blocks of memory from I/O RAM <b>220</b> are not stored in the cache <b>230</b> or the CPU cache <b>240</b> (or if they are stored in the cache they are marked as invalid so that the CPU will fetch the current contents of the I/O RAM <b>220</b> rather than use the obsolete data in the cache). Examples of I/O RAM <b>220</b> include capture video RAM <b>113</b> and display video RAM <b>120</b>.

P-0044[0044]FIG. 2B shows a computer architecture with direct memory access (DMA) circuitry <b>250</b>. Without DMA circuitry <b>250</b>, the CPU <b>101</b> must be involved in transferring data from memory <b>103</b> to I/O RAM <b>220</b>. This CPU involvement takes the CPU <b>101</b> processing power away from executing other program instructions and adds overhead to handle the interruptions. DMA circuitry <b>250</b> is used to copy blocks of data directly between memory <b>103</b> and I/O RAM <b>220</b>. A DMA operation is initiated by the CPU <b>101</b> with a DMA control <b>252</b> sent from the CPU <b>103</b> to the DMA circuitry <b>250</b>. Once the DMA operation is initiated the CPU can return to other work. The DMA circuitry moves the data from memory <b>103</b> to I/O RAM <b>220</b> along the DMA-memory bus <b>254</b> and DMA-I/O bus <b>256</b> or from I/O RAM <b>220</b> to memory <b>103</b>. In practice, the DMA circuitry may become a secondary bus master of a system bus that interconnects the CPU <b>101</b>, I/O RAM <b>220</b>, and memory <b>103</b>. Once the data transfer is complete the DMA circuitry <b>250</b> notifies the CPU.

P-0045[0045] Processing Speed Improvement—FIGS. 3A to <b>3</b>C

P-0046[0046] When video data is being displayed or captured the storage (memory <b>103</b> or I/O RAM <b>220</b>) holding the data is continually being accessed by the video display circuitry or video digitizing circuitry. Also the capture video RAM <b>113</b> and the display video RAM <b>120</b> typically is not cached by a CPU <b>101</b> in any cache (<b>230</b> or <b>240</b>), so when processing the video data for compression, encryption, enhancement, or decompression it is significantly faster to process the data in cacheable main memory.

P-0047[0047] The present invention uses a memory copy function (similar to a memcpy function or a substantially similar set of computer instructions) to copy the desired image data from an I/O RAM <b>220</b> to a cacheable main memory <b>103</b> (FIG. 2A) where it can be more efficiently processed. After the processing is done, the processed image is then copied back to the display video RAM <b>120</b> for display on the video display <b>121</b> (FIG. 1C).

P-0048[0048]FIG. 3A shows a buffer <b>300</b> in memory <b>103</b> and an image <b>310</b> stored in I/O RAM <b>220</b>. The buffer-image copy <b>305</b> of data between the buffer <b>300</b> and the image <b>310</b> is shown as bi-directional arrows. Once the image data is copied from the image <b>310</b> to the memory buffer <b>300</b> it can be much more efficiently processed by the CPU <b>103</b>. FIG. 3B shows an encoder <b>320</b> program which accesses the buffer <b>300</b> applying enhancement, compression, or encryption algorithms as needed to produce encoded data <b>330</b>. The encoded data <b>330</b> can be stored on a storage device or transferred over a network to another computer. FIG. 3C shows a decoder <b>340</b> program processing the encoded data <b>330</b> into another instance of a memory buffer <b>300</b>. The decoder can decrypt, decompress, or enhance the encoded data as needed and place the resulting data in a memory buffer <b>300</b>.

P-0049[0049] This invention discovered that is was much more efficient to write the decoded data to a memory buffer <b>300</b> instead of writing it directly to image <b>310</b> in I/O RAM <b>220</b> as each pixel is processed. Once the decoder processing is complete, the buffer-image copy <b>305</b> is used to transfer the data from the buffer <b>300</b> to the I/O RAM <b>220</b>. The I/O RAM could be a display video RAM <b>120</b> as shown in FIG. 1C.

P-0050[0050] Not Obvious

P-0051[0051] The speed improvement yielded by this invention was not obvious to one skilled in the art of computer programming. The video data is large, up to 1.2 million bytes, and the time to copy it from one buffer to another generally is thought to be overhead that will decrease performance. This invention teaches that because of hardware lockout, collisions with the video circuitry, the lack of data caching in the CPU cache <b>240</b> or memory cache <b>230</b>, or other factors, the extra copy can significantly reduce the processing time, and thus reduce the overall time required to process the data and to display or capture the video data.

P-0052[0052] The memory copy routine used in the buffer-image copy <b>305</b> may use processor specific code, or other methods, to move blocks of data between the memory <b>103</b> (or the caches (<b>230</b>,<b>240</b>)) and the I/O RAM <b>220</b>.

P-0053[0053] The methods of this invention are much more efficient (due to I/O RAM lockouts and conflicts) than processing each pixel a byte or word at a time in place in I/O RAM <b>220</b>.

P-0054[0054] Alternatively, DMA circuitry <b>250</b> (FIG. 2B) may be used to increase the speed of transfer between memory <b>103</b> and the I/O RAM <b>220</b>.

P-0055[0055] In one embodiment of this invention the entire image is copied by a single call to the memcpy function. This has the advantage of only making one function call.

P-0056[0056]FIG. 4—Preferred Embodiment

P-0057[0057] In the preferred embodiment, only a subset image <b>310</b> of the data in I/O RAM <b>220</b> is of interest for processing, so the memory copy function is called repeatedly to copy each line of desired image data. For example if the desired subset is 320 by 240, the memory copy function is called 240 times and copies 320 pixels each time. This has the advantage of only copying the desired data. Even though there is more overhead in determining how to copy the subset and in calling the memory copy function multiple time, the time saved by copying less data more than compensates for the additional overhead. Less memory is used to hold the main memory buffer and less data must be processed.

P-0058[0058]FIG. 4 is a diagram of the buffer <b>300</b> and the image <b>310</b> that shows more detail than FIG. 3A. The subset image <b>310</b> is contained within a super-image <b>400</b>. When a television video signal is digitized there are portions of the signal that are not visible on most television displays. The video digitizer often will process all of the video signal producing a super-image <b>400</b> that contains data that surrounds the subset image <b>310</b> and the surround data typically is of no interest. If the origin of the super-image <b>400</b> is (0, 0) the image <b>310</b> of interest can be found at a coordinate (x, y) composed of the image horizontal offset x and the image vertical offset y. The image width w and the image height can be used to allocate the memory buffer <b>300</b>, rather than copying the entire super-image <b>400</b>. The coordinate of the last pixel of the desired image is (x+w, y+h).

P-0059[0059] In the preferred embodiment, the first image line <b>420</b> (starting at (x,y)) is copied (<b>305</b>) to the first buffer line <b>430</b> for the length of the image width w. Next the second image line <b>422</b> is copied to the second buffer line <b>432</b>. Each line is copied until the last image line <b>424</b> is copied to the last buffer line <b>434</b>. After the desired data is copied in this manner the buffer <b>300</b> can be efficiently processed. Buffer <b>300</b> is smaller than the super-image <b>400</b> and the data of interest is contiguous so it can be processed more efficiently. Buffer <b>300</b> can be cached and will have typically no conflict from other accesses.

P-0060[0060]FIG. 4 also illustrates the reverse process of copying a buffer <b>300</b> containing processed data to a super image <b>400</b> in an I/O RAM <b>220</b> (FIG. 3A). Each line of the buffer <b>300</b> is copied (<b>305</b>) to the image <b>310</b> in the super image <b>400</b> at the desired offset (x,y). In this reverse process the first buffer line <b>430</b> is copied to the first image line <b>420</b>. The second buffer line <b>432</b> is copied to the second image line <b>420</b>, and so forth, until the last buffer line <b>434</b> is copied to the last image line <b>424</b>. The same advantages of buffer <b>300</b> being smaller, contiguous, cacheable, and conflict free also apply to the reverse process.

P-0061[0061]FIG. 5—Image Copy Flowchart

P-0062[0062]FIG. 5 is a flow chart for the method of copying the image <b>310</b> to buffer <b>300</b> as shown in FIG. 4. The method starts at an image copy start <b>500</b> entry point. Next an image copy initialization step <b>510</b> comprising the following is executed:

P-0063[0063] the line size is set to the image width w.

P-0064[0064] the number of lines is set to the image height h.

P-0065[0065] the row size is calculated by dividing the total bytes in a row of the super image by the number of bytes per pixel.

P-0066[0066] the copy size is calculated by multiplying the line size by the number of bytes per pixel.

P-0067[0067] the source pointer is set the base address of the image <b>400</b> plus the calculation of the number of bytes to get to the (x,y) offset: ((y * row size+x) * bytes per pixel).

P-0068[0068] the destination pointer is set to the base address of the buffer <b>300</b>.

P-0069[0069] Next, in a set counter step <b>520</b>, the row index is set to 0. An image copy done decision <b>530</b> is made by comparing the row index to the number of lines. If one or more lines still need to be copied, flow continues to an image copy step <b>540</b>. In the image copy step <b>540</b>, the memory copy function is called to copy copy-size bytes from the current source pointer to the current destination pointer (effectively copying a line of the image <b>310</b> to the buffer <b>300</b>). Next, in an update pointers step <b>550</b>, the source pointer is incremented by the number of bytes in a row of the super image (effectively addressing the beginning of the next line of the image <b>310</b>), and the destination pointer is incremented by the number of bytes in a line of the buffer <b>300</b> (effectively addressing the beginning of the next line of the buffer <b>300</b>). Next in an increment index step <b>560</b>, the row index is increment. Flow continues to the image copy done decision <b>530</b>, and the loop continues until each line of the image <b>310</b> is copied. When the image has been fully copied, flow terminates at an image copy exit <b>599</b> point.

P-0070[0070]FIG. 6—Buffer Copy Flowchart

P-0071[0071]FIG. 6 is a flow chart for the method of copying the buffer <b>300</b> to the image <b>310</b> as shown in FIG. 4. The method starts at a buffer copy start <b>600</b> entry point. Next a buffer copy initialization step <b>610</b> comprising the following is executed:

P-0072[0072] the line size is set to the image width w.

P-0073[0073] the number of lines is set to the image height h.

P-0074[0074] the row size is calculated by dividing the total bytes in a row of the super image by the number of bytes per pixel.

P-0075[0075] the copy size is calculated by multiplying the line size by the number of bytes per pixel.

P-0076[0076] the destination pointer is set the base address of the image <b>400</b> plus the calculation of the number of bytes to get to the (x,y) offset: ((y * row size+x) * bytes per pixel).

P-0077[0077] the source pointer is set to the base address of the buffer <b>300</b>.

P-0078[0078] Next, in a set counter step <b>620</b>, the row index is set to 0. A buffer copy done decision <b>630</b> is made by comparing the row index to the number of lines. If one or more lines still need to be copied, flow continues to a buffer copy step <b>640</b>. In the buffer copy step <b>640</b>, the memory copy function is called to copy copy-size bytes from the current source pointer to the current destination pointer (effectively copying a line of the buffer <b>300</b> to the image <b>310</b>). Next in an update pointers step <b>650</b>, the destination pointer is incremented by the number of bytes in a row of the super image (effectively addressing the beginning of the next line of the image <b>310</b>), and the source pointer is incremented by the number of bytes in a line of the buffer <b>300</b> (effectively addressing the beginning of the next line of the buffer <b>300</b>). Next in an increment index step <b>660</b>, the row index is increment. Flow continues to the buffer copy done decision <b>630</b>, and the loop continues until each line of the buffer <b>300</b> is copied. When the buffer has been fully copied, flow terminates at a buffer copy exit <b>699</b> point.

P-0079[0079] Advantages

P-0080[0080] Execution Speed

P-0081[0081] The methods of the present invention provide a decrease in the processing time required to process images that are being input or output. This decrease in processing time allows for video images to be enhanced, compressed, and encrypted in real time. The time saved by these methods can be used to execute more efficient compression algorithms that may in turn reduce the bandwidth required to transfer the encoded data between computers or may reduce the space needed to store the encoded data.

P-0082[0082] Reduced Memory Requirements

P-0083[0083] The selection of a subset image <b>310</b> from a super image <b>400</b> (FIG. 4) reduces the amount of memory needed to hold the data being processed.

P-0084[0084] Conclusion, Ramification, and Scope

P-0085[0085] Accordingly, the reader will see that the methods the present invention provides a means of reducing the processing time and computer resources needed to process images being input or output.

P-0086[0086] Furthermore, the present invention has additional advantages in that it provides a means for reducing the space required in a storage medium.

P-0087[0087] Although the descriptions above contain many specifics, these should not be construed as limiting the scope of the invention but as merely providing illustrations of some of the preferred embodiments of this invention. For example, the memory copy algorithm can be implemented in a number of ways without limiting the scope of this invention to the use of a particular implementation.

P-0088[0088] Thus the scope of the invention should be determined by the appended claims and their legal equivalents, and not solely by the examples given.