US11552129B2

Semiconductor memory device having variable resistance elements provided between wiring lines

Summary by NHIP

Memory device with variable resistance elements

The memory device includes a substrate, first and second wirings, and variable resistance elements positioned between the wirings. Distinctive features include a third wiring crossing the first two, and five contacts extending in a second direction with specific vertical positions relative to the wirings and substrate.

Claim Score by NHIP

Read claim 1, the broadest

Abstract

According to an embodiment, a semiconductor memory device comprises first wiring lines, second wiring lines, and first variable resistance elements. The first wiring lines are arranged in a first direction and have as their longitudinal direction a second direction intersecting the first direction. The second wiring lines are arranged in the second direction and have the first direction as their longitudinal direction. The first variable resistance elements are respectively provided at intersections of the first wiring lines and the second wiring lines. In addition, this semiconductor memory device comprises a first contact extending in a third direction that intersects the first direction and second direction and having one end thereof connected to the second wiring line. The other end and a surface intersecting the first direction of this first contact are covered by a first conductive layer.

US11552129B2, drawing sheet 1 — Sheet 1 of 64

Term

9.8 yearsleft in the term

Expires 30 June 2036, including 100 days of term adjustment.

10 claims: 1 independent, 9 dependent

1
Broadest claimClaim Score 46, average(NHIP)A memory device comprising:a substrate;a first wiring extending in a first direction;a second wiring being located away from the first wiring and being located closer to the first wiring than the substrate in a second direction crossing the first direction and perpendicular to the substrate a third wiring being provided between the first wiring and the second wiring, the third wiring extending in a third direction crossing the first and the second directions;a first variable resistance element being provided between the first wiring and the third wiring;a second variable resistance element being provided between the second wiring and the third wiring;a first contact extending in the second direction, and one end of the first contact in the second direction being connected to the first wiring, the other end of the first contact in the second direction being located closer to the substrate than the third wiring in the second direction;a second contact being connected to the first contact and extending in the second direction, the second contact being located below the second wiring;a third contact extending in the second direction, and one end of the third contact being connected to the second wiring;a fourth contact extending in the second direction, and one end of the fourth contact being connected to the third wiring, the other end of the third contact being located closer to the substrate than the second wiring in the second direction;and a fifth contact being connected to the fourth contact and extending in the second direction.

117 paragraphs in 5 sections, as filed

0001This application is a continuation of and claims the benefit of priority under 35 U.S.C. § 120 from U.S. application Ser. No. 16/401,391 filed May 2, 2019, which is a continuation of U.S. application Ser. No. 16/150,321 filed Oct. 3, 2018, which is a continuation of U.S. application Ser. No. 15/791,514 filed Oct. 24, 2017 (now U.S. Pat. No. 10,115,771 issued Oct. 30, 2018), which is a continuation of U.S. application Ser. No. 15/077,026 filed Mar. 22, 2016 (now U.S. Pat. No. 9,812,502 issued Nov. 7, 2017), and claims the benefit of priority from U.S. Provisional Patent Application No. 62/212,056 filed Aug. 31, 2015, the entire contents of each of which are incorporated herein by reference.

FIELD

0002Embodiments described herein relate to a semiconductor memory device and a method of manufacturing the same.

BACKGROUND

Description of the Related Art

0003A resistance varying type memory (ReRAM: Resistive RAM), and so on, that can easily be made three-dimensional, has been receiving attention as a memory utilized for storing large capacity data. In such a memory, a variable resistance element is employed as a storage element. The following are employed as such a variable resistance element, for example, CBRAM (Conduction Bridge RAM), a storage element utilizing the likes of a chalcogenide compound or metal oxide, an MRAM element employing a resistance change due to a tunnel magnetoresistance effect, a storage element utilizing a conductive polymer (polymer ferroelectric RAM, PFRAM), and so on.

BRIEF DESCRIPTION OF THE DRAWINGS

0004<figref idref="DRAWINGS">FIG. 1</figref> is a block diagram of a nonvolatile semiconductor memory device according to a first embodiment.

0005<figref idref="DRAWINGS">FIG. 2</figref> is a circuit diagram showing a configuration of part of the same nonvolatile semiconductor memory device.

0006<figref idref="DRAWINGS">FIG. 3</figref> is a perspective view showing a configuration of part of the same nonvolatile semiconductor memory device.

0007<figref idref="DRAWINGS">FIG. 4</figref> is a cross-sectional view showing a configuration of part of the same nonvolatile semiconductor memory device.

0008<figref idref="DRAWINGS">FIG. 5</figref> is a cross-sectional view showing a configuration of part of the same nonvolatile semiconductor memory device.

0009<figref idref="DRAWINGS">FIG. 6</figref> is a plan view showing a configuration of part of the same nonvolatile semiconductor memory device.

0010<figref idref="DRAWINGS">FIGS. 7 to 12</figref> are cross-sectional views showing configuration of parts of the same nonvolatile semiconductor memory device.

0011<figref idref="DRAWINGS">FIG. 13</figref> is a flowchart showing a method of manufacturing the nonvolatile semiconductor memory device according to the first embodiment.

0012<figref idref="DRAWINGS">FIGS. 14, 17, 19, 21, 25, 30, 34, 39, 44, 47, 50, 54, 56, 60, and 62</figref> are plan views showing the same method of manufacturing.

0013<figref idref="DRAWINGS">FIGS. 15, 16, 18, 20, 22 to 24, 26 to 29, 31 to 33, 35 to 38, 40 to 43, 45, 46, 48, 49, 51 to 53, 55</figref>, 57 to 59, 61, 63, and 64 are cross-sectional views showing the same method of manufacturing.

DETAILED DESCRIPTION

0014A semiconductor memory device according to an embodiment comprises a plurality of first wiring lines, a plurality of second wiring lines, and a plurality of first variable resistance elements. The plurality of first wiring lines are arranged in a first direction and have as their longitudinal direction a second direction intersecting the first direction. The plurality of second wiring lines are arranged in the second direction and have the first direction as their longitudinal direction. The plurality of first variable resistance elements are respectively provided at intersections of the first wiring lines and the second wiring lines. In addition, this semiconductor memory device comprises a first contact extending in a third direction that intersects the first direction and second direction and having one end thereof connected to the second wiring line. The other end and a surface intersecting the first direction of this first contact are covered by a first conductive layer.

0015Next, nonvolatile semiconductor memory devices according to embodiments will be described in detail with reference to the drawings. Note that these embodiments are merely examples, and are not shown with the intention of limiting the present invention.

0016For example, a memory device employing CBRAM (Conduction Bridge RAM) is exemplified herein, but the present invention may also be applied to a memory device having another configuration. Such a memory device may be one having any configuration, for example, one employing a storage element that utilizes the likes of a chalcogenide compound or metal oxide, one employing MRAM that utilizes a resistance change due to a tunnel magnetoresistance effect, one employing a storage element that utilizes a conductive polymer (polymer ferroelectric RAM, PFRAM), and so on. Moreover, a memory cell included in the memory device may or may not include a non-linear element such as a diode or transistor.

0017In addition, a configuration having two layers of memory mats stacked is exemplified herein as a structure of a memory cell array. However, the present embodiment may also be applied to a configuration having a single layer memory mat or a configuration having three or more layers of memory mats stacked. Moreover, a configuration in which a bit line BL is shared between the stacked two layers of memory mats is exemplified herein. However, it is also possible to adopt a configuration in which a word line WL is shared between the stacked memory mats and to adopt a configuration in which wiring lines are not shared between the stacked memory mats.

0000[Semiconductor Memory Device according to First Embodiment]

0018<figref idref="DRAWINGS">FIG. 1</figref> is a block diagram of a nonvolatile semiconductor memory device according to a first embodiment. The same nonvolatile semiconductor memory device stores user data inputted from an external host 9, in a certain address in a memory cell array 1. In addition, the same nonvolatile semiconductor memory device reads user data from a certain address in the memory cell array 1, and outputs the user data to the external host 9.

0019That is, as shown in <figref idref="DRAWINGS">FIG. 1</figref>, the same nonvolatile semiconductor memory device comprises the memory cell array 1 that stores user data. The memory cell array 1 comprises a plurality of memory mats MM. As shown in <figref idref="DRAWINGS">FIG. 2</figref>, these memory mats MM comprise: a plurality of memory cells MC1 and MC2; and a bit line BL and word lines WL1 and WL2 connected to these memory cells MC1 and MC2.

0020As shown in <figref idref="DRAWINGS">FIG. 1</figref>, the same nonvolatile semiconductor memory device comprises a column control circuit 2 provided in a periphery of the memory cell array 1. When performing write of user data, the column control circuit 2 transfers a voltage generated by a voltage generating circuit 10 to a desired bit line BL, according to the user data inputted from the external host 9. Moreover, the column control circuit 2 comprises an unillustrated sense amplifier, and when performing read of user data, detects a voltage or potential of a certain bit line BL.

0021As shown in <figref idref="DRAWINGS">FIG. 1</figref>, the same nonvolatile semiconductor memory device comprises a row control circuit 3 provided in a periphery of the memory cell array 1. The row control circuit 3 transfers a voltage generated by the voltage generating circuit 10 to desired word lines WL1 and WL2, and so on, according to address data inputted from the external host 9.

0022As shown in <figref idref="DRAWINGS">FIG. 1</figref>, the same nonvolatile semiconductor memory device comprises an address register 5 that supplies address data to the column control circuit 2 and the row control circuit 3. The address register 5 stores address data inputted from a data input/output buffer 4.

0023As shown in <figref idref="DRAWINGS">FIG. 1</figref>, the same nonvolatile semiconductor memory device comprises the voltage generating circuit 10 that supplies a voltage to the memory cell array 1 via the column control circuit 2 and the row control circuit 3. The voltage generating circuit 10 generates and outputs a voltage of a certain magnitude at a certain timing, based on an internal control signal inputted from a state machine 7.

0024As shown in <figref idref="DRAWINGS">FIG. 1</figref>, the same nonvolatile semiconductor memory device comprises the state machine 7 that inputs the internal control signal to the voltage generating circuit 10, and so on. The state machine 7 receives command data from the host 9, via a command interface 6, and performs management of read, write, erase, input/output of data, and so on.

0025As shown in <figref idref="DRAWINGS">FIG. 1</figref>, the same nonvolatile semiconductor memory device comprises the data input/output buffer 4 which is connected to the external host 9 via an I/O line. The data input/output buffer 4 receives user data from the external host 9, and transfers the user data to the column control circuit 2. Moreover, the data input/output buffer 4 receives command data from the external host 9, and transfers the command data to the command interface 6. In addition, the data input/output buffer 4 receives address data from the external host 9, and transfers the address data to the address register 5. Furthermore, the data input/output buffer 4 receives user data from the column control circuit 2, and transfers the user data to the external host 9.

0026As shown in <figref idref="DRAWINGS">FIG. 1</figref>, the same nonvolatile semiconductor memory device comprises the command interface 6 that receives an external control signal from the external host 9. The command interface 6 determines which of user data, command data, and address data data inputted to the data input/output buffer 4 is, based on the external control signal inputted from the external host 9, and controls the data input/output buffer 4. In addition, the command interface 6 transfers to the state machine 7 command data received from the data input/output buffer 4.

0027Note that the column control circuit 2, the row control circuit 3, the state machine 7, the voltage generating circuit 10, and so on, configure a control circuit that controls the memory cell array 1.

0028Next, a circuit configuration of part of the memory cell array 1 according to the present embodiment will be described with reference to <figref idref="DRAWINGS">FIG. 2</figref>. <figref idref="DRAWINGS">FIG. 2</figref> is an equivalent circuit diagram showing a configuration of part of the memory cell array 1.

0029As shown in <figref idref="DRAWINGS">FIG. 2</figref>, the memory cell array 1 comprises: a plurality of the bit lines BL; a plurality of the word lines WL1 and WL2; and a plurality of the memory cells MC1 and MC2 connected to these bit lines BL and word lines WL1 and WL2. These memory cells MC1 and MC2 are connected to the row control circuit 3 via the word lines WL1 and WL2 and a word line contact CW, and are connected to the column control circuit 2 via the bit line BL and a bit line contact CB. For example, the plurality of memory cells MC1 and MC2 connected to common word lines WL1 and WL2 store a one-page portion of user data. Moreover, the plurality of memory cells MC1 and MC2 each store a one-bit portion of data, for example.

0030The memory cells MC1 and MC2 function as a variable resistance element, and have their resistance value changed according to data stored. For example, the memory cells MC11 and MC13 recording “0” are in a high-resistance state, and the memory cell MC12 recording “1” is in a low-resistance state. Therefore, when a certain voltage is applied to the word line WL11 (selected word line) connected to these memory cells MC11 to MC13, a current does not flow in the bit line BL1 and bit line BL3 connected to the memory cells MC11 and MC13, but a current does flow in the bit line BL2 connected to the memory cell MC12. Therefore, this current is detected by the column control circuit 2, whereby data of “010” is read as user data, for example. Note that the column control circuit 2 may detect a voltage, not the current, of the bit line BL.

0031In addition, the memory cells MC1 and MC2 function as a rectifier element. Therefore, practically no current flows in the word lines WL1 and WL2 (unselected word lines) other than the selected word line WL11.

0032Note that hereafter, a configuration including the plurality of bit lines BL, the plurality of word lines WL1, and the plurality of memory cells MC1 will be called a memory mat MM0. Similarly, a configuration including the plurality of bit lines BL, the plurality of word lines WL2, and the plurality of memory cells MC2 will be called a memory mat MM1.

0033Next, a schematic configuration of the memory cell array 1 will be described with reference to <figref idref="DRAWINGS">FIG. 3</figref>. <figref idref="DRAWINGS">FIG. 3</figref> is a schematic perspective view showing a configuration of part of the memory cell array 1. Note that in <figref idref="DRAWINGS">FIG. 3</figref>, part of the configuration is omitted. Moreover, the configuration shown in <figref idref="DRAWINGS">FIG. 3</figref> is merely an example, and a specific configuration may be appropriately changed.

0034As shown in <figref idref="DRAWINGS">FIG. 3</figref>, the memory cell array 1 is a so-called cross-point type memory cell array. That is, the memory cell array 1 is provided with a plurality of the word lines WL1 that are arranged in parallel in a Y direction and extend in an X direction. Moreover, provided above these plurality of word lines WL1 are a plurality of the bit lines BL that are arranged in parallel in the X direction and extend in the Y direction. Furthermore, provided above the plurality of bit lines BL are a plurality of the word lines WL2 that are arranged in parallel in the Y direction and extend in the X direction. In addition, the memory cell MC1 is provided at each of intersections of the plurality of word lines WL1 and the plurality of bit lines BL. Similarly, the memory cell MC2 is provided at each of intersections of the plurality of bit lines BL and the plurality of word lines WL2.

0035Next, the memory mat MM0 will be described with reference to <figref idref="DRAWINGS">FIG. 4</figref>. <figref idref="DRAWINGS">FIG. 4</figref> is a cross-sectional view showing a configuration of the memory mat MM0. Note that in <figref idref="DRAWINGS">FIG. 4</figref>, part of the configuration is omitted.

0036As shown in <figref idref="DRAWINGS">FIG. 4</figref>, the memory mat MM0 comprises: the word line WL1; the memory cell MC1 provided on an upper surface of the word line WL1; and the bit line BL provided on an upper surface of the memory cell MC1. The memory cell MC1 includes a filament F having conductivity, and attains the low-resistance state when this filament F contacts an electrode layer 224 and the high-resistance state when this filament F does not contact the electrode layer 224.

0037As shown in <figref idref="DRAWINGS">FIG. 4</figref>, the word line WL1 comprises the following, for example, namely: a barrier metal layer 211; and a conductive layer 212 stacked on this barrier metal layer 211. The barrier metal layer 211 is configured from a conductive layer of the likes of titanium (Ti), for example, and suppresses diffusion of an impurity when depositing the conductive layer 212, and so on. The conductive layer 212 is configured from a conductive layer of the likes of tungsten (W), for example.

0038As shown in <figref idref="DRAWINGS">FIG. 4</figref>, the memory cell MC1 comprises the following, stacked sequentially on the word line WL1, namely: a barrier metal layer 221; a metal layer 222; an insulating layer 223; the electrode layer 224; a barrier metal layer 225; and a conductive layer 226. The barrier metal layers 221 and 225 are configured from a conductive layer of the likes of titanium (Ti), for example, and suppress diffusion of an impurity when depositing the metal layer 222 or the conductive layer 226, and so on. The metal layer 222 is configured from a metal such as silver (Ag) or copper (Cu), for example, and functions as a supply source of a metal ion forming the filament F. The insulating layer 223 is configured from an insulating layer of the likes of silicon oxide (SiO2), for example, and functions as a medium in which the filament F grows. The electrode layer 224 is configured from a material such as tantalum silicon nitride (TaSiN), for example, and functions as an electrode contacting the filament F. The conductive layer 226 is configured from a conductive layer of the likes of tungsten (W), for example.

0039As shown in <figref idref="DRAWINGS">FIG. 4</figref>, the bit line BL comprises the following, for example, namely: a barrier metal layer 231; and a conductive layer 232 stacked on this barrier metal layer 231. The barrier metal layer 231 is configured from a conductive layer of the likes of titanium (Ti), for example, and suppresses diffusion of an impurity when depositing the conductive layer 232, and so on. The conductive layer 232 is configured from a conductive layer of the likes of tungsten (W), for example.

0040Note that materials of each of the configurations are merely exemplified ones, and may be appropriately changed. For example, the insulating layer 223 may be formed from a material such as silicon nitride (SiN), silicon oxynitride (SiON), aluminum oxide (Al2O3), hafnium oxide (HfO), and so on. Moreover, the electrode layer 224 may be formed from a material such as amorphous silicon, polysilicon, tantalum nitride (TaN), aluminum tantalum nitride, and so on.

0041Next, the memory mat MM1 will be described in more detail with reference to <figref idref="DRAWINGS">FIG. 5</figref>. <figref idref="DRAWINGS">FIG. 5</figref> is a cross-sectional view showing a configuration of the memory mat MM1. Note that in <figref idref="DRAWINGS">FIG. 5</figref>, part of the configuration is omitted.

0042As shown in <figref idref="DRAWINGS">FIG. 5</figref>, the memory mat MM1 comprises: the bit line BL; the memory cell MC2 provided on an upper surface of the bit line BL; and the word line WL2 provided on an upper surface of the memory cell MC2. Similarly to the memory cell MC1, the memory cell MC2 also includes a filament F having conductivity, and attains the low-resistance state when this filament F contacts an electrode layer 242 and the high-resistance state when this filament F does not contact the electrode layer 242.

0043As shown in <figref idref="DRAWINGS">FIG. 5</figref>, the memory cell MC2 comprises the following, stacked sequentially on the bit line BL, namely: a barrier metal layer 241; the electrode layer 242; an insulating layer 243; a barrier metal layer 244; a metal layer 245; a barrier metal layer 246; and a conductive layer 247. The barrier metal layers 241, 244, and 246 are configured from a conductive layer of the likes of titanium (Ti), for example, and suppress diffusion of an impurity when depositing the electrode layer 242, the metal layer 245, or the conductive layer 247, and so on. The electrode layer 242 is configured from a material such as tantalum silicon nitride (TaSiN), and functions as an electrode contacting the filament F. The insulating layer 243 is configured from an insulating layer of the likes of silicon oxide (SiO2), for example, and functions as a medium in which the filament F grows. The metal layer 245 is configured from a metal such as silver (Ag) or copper (Cu), for example, and functions as a supply source of a metal ion forming the filament F. The conductive layer 247 is configured from a conductive layer of the likes of tungsten (W), for example.

0044As shown in <figref idref="DRAWINGS">FIG. 5</figref>, the word line WL2 comprises the following, for example, namely: a barrier metal layer 251; and a conductive layer 252 stacked on this barrier metal layer 251. The barrier metal layer 251 is configured from a conductive layer of the likes of titanium (Ti), for example, and suppresses diffusion of an impurity when depositing the conductive layer 252, and so on. The conductive layer 252 is configured from a conductive layer of the likes of tungsten (W), for example.

0045Note that materials of each of the configurations are merely exemplified ones, and may be appropriately changed. For example, the electrode layer 242 may be formed from a material such as amorphous silicon, polysilicon, tantalum nitride (TaN), aluminum tantalum nitride, and so on. Moreover, the insulating layer 243 may be formed from a material such as silicon nitride (SiN), silicon oxynitride (SiON), aluminum oxide (Al2O3), hafnium oxide (HfO), and so on.

0046Next, the memory cell array 1 according to the present embodiment will be described in more detail with reference to <figref idref="DRAWINGS">FIGS. 6 to 12</figref>. <figref idref="DRAWINGS">FIG. 6</figref> is a plan view showing a configuration of part of the memory cell array 1. <figref idref="DRAWINGS">FIGS. 7 to 12</figref> are cross-sectional views showing configurations of parts of the memory cell array 1, and respectively show cross-sections corresponding to A-A through F-F of <figref idref="DRAWINGS">FIG. 6</figref>. Note that in <figref idref="DRAWINGS">FIG. 6</figref>, part of the configuration is omitted.

0047As shown in <figref idref="DRAWINGS">FIG. 6</figref>, the memory cell array 1 according to the present embodiment is provided with a plurality of memory regions MR1 and MR2. In addition, a bit line contact region BCR is provided in the Y direction of the memory regions MR1 and MR2. Moreover, word line contact regions WCR1 and WCR2 are provided in the X direction of the memory regions MR1 and MR2.

0048As shown in <figref idref="DRAWINGS">FIGS. 6 to 8</figref>, the memory regions MR1 and MR2 are provided with a plurality of the bit lines BL that are arranged in parallel in the X direction and extend in the Y direction, and a plurality of the word lines WL1 and word lines WL2 that are arranged in parallel in the Y direction and extend in the X direction (refer to <figref idref="DRAWINGS">FIGS. 7 and 8</figref>). In addition, memory cells MC1 and MC2 are provided at intersections of these plurality of bit lines BL and plurality of word lines WL1 and WL2.

0049As shown in <figref idref="DRAWINGS">FIG. 6</figref>, the bit line contact region BCR is provided with a plurality of the bit lines BL that are arranged in the X direction and extend in parallel in the Y direction. In other words, the plurality of bit lines BL are provided straddling the memory regions MR1 and MR2 and the bit line contact region BCR. Moreover, as shown in <figref idref="DRAWINGS">FIGS. 6 and 7</figref>, the bit line contact CB is connected to each of these bit lines BL. The bit line contact CB extends in the Z direction and has its upper end connected to a lower surface of the bit line BL and its lower end connected to a conductive layer 113 of a lower wiring line layer 100.

0050As shown in <figref idref="DRAWINGS">FIGS. 6 to 8</figref>, the word line contact regions WCR1 and WCR2 are each provided with a plurality of the word lines WL1 and WL2 that are arranged in the Y direction and extend in parallel in the X direction. In other words, the plurality of word lines WL1 and WL2 are provided straddling the memory regions MR1 and MR2 and the word line contact regions WCR1 and WCR2. Moreover, as shown in <figref idref="DRAWINGS">FIG. 8</figref>, in the word line contact regions WCR1 and WCR2, the word line WL1 is connected to the conductive layer 113 of the lower wiring line layer 100. In addition, as shown in <figref idref="DRAWINGS">FIGS. 6 and 8</figref>, the word line contact CW is connected to each of the word lines WL2. The word line contact CW extends in the Z direction and has its upper end connected to a lower surface of the word line WL2 and its lower end connected to the conductive layer 113 of the lower wiring line layer 100.

0051Now, as shown in <figref idref="DRAWINGS">FIGS. 6 and 9</figref>, in the present embodiment, a position and width in the X direction of the bit line BL substantially matches a position and width in the X direction of the bit line contact CB. Moreover, in the bit line contact region BCR, a plurality of the bit line contacts CB are lined up in the X direction with an identical pitch to that of the bit lines BL, and positions in the Y direction of these plurality of bit line contacts CB are substantially matched.

0052In such a configuration, a width in the X direction of the bit line contact region BCR can be suppressed to about the same width as that of the memory regions MR1 and MR2, and a width in the Y direction of the bit line contact region BCR can be suppressed to about the same width as that of the bit line contact CB. Therefore, an area occupied by the bit line contact region BCR can be reduced.

0053Moreover, in the present embodiment, the bit line contact CB is formed in an inversely tapered shape when viewed from the X direction as shown in <figref idref="DRAWINGS">FIG. 7</figref>, and is formed in a forwardly tapered shape when viewed from the Y direction as shown in <figref idref="DRAWINGS">FIG. 9</figref>. That is, as shown in <figref idref="DRAWINGS">FIG. 7</figref>, in the Y direction, a width WBY1 of the lower end of the bit line contact CB is smaller than a width WBY2 of the upper end of the bit line contact CB. On the other hand, as shown in <figref idref="DRAWINGS">FIG. 9</figref>, in the X direction, a width WBX1 of the lower end of the bit line contact CB is larger than a width WBX2 of the upper end of the bit line contact CB. Therefore, it is possible to suppress a cross-sectional area of the upper end or lower end of the contact becoming extremely small, and thereby prevent an increase in wiring line resistance.

0054Moreover, in the present embodiment, as shown in <figref idref="DRAWINGS">FIG. 7</figref>, the bit line BL and the bit line contact CB are formed integrally. Therefore, contact resistance between the bit line BL and the bit line contact CB may be ignored, and wiring line resistance can be more reduced compared to when the bit line BL and the bit line contact CB are formed separately, for example.

0055Note that in the present embodiment, as shown in <figref idref="DRAWINGS">FIG. 7</figref>, the lower surface of the bit line BL and a side surface in the Y direction (surface intersecting the Y direction) and lower surface of the bit line contact CB are covered by the barrier metal layer 231. In contrast, as shown in <figref idref="DRAWINGS">FIG. 9</figref>, side surfaces in the X direction (surface intersecting the X direction) of the bit line BL and the bit line contact CB contact a nitride layer 261. However, the nitride layer 261 may be omitted. In such a case, the side surfaces in the X direction of the bit line BL and the bit line contact CB sometimes contact an inter-layer insulating layer 228.

0056Moreover, in the present embodiment, as shown in <figref idref="DRAWINGS">FIG. 9</figref>, a side surface in the Y direction of the bit line BL and a side surface in the Y direction of the bit line contact CB are formed continuously.

0057Note that as shown in <figref idref="DRAWINGS">FIGS. 6 and 10</figref>, in the present embodiment, the word line contact CW is also formed substantially similarly to the bit line contact CB. That is, as shown in <figref idref="DRAWINGS">FIGS. 6 and 10</figref>, in the present embodiment, a position and width in the Y direction of the word line WL2 substantially matches a position and width in the Y direction of the word line contact CW. Moreover, in the word line contact regions WCR1 and WCR2, a plurality of the word line contacts CW are lined up in the Y direction with an identical pitch to that of the word lines WL, and positions in the X direction of these plurality of word line contacts CW are substantially matched.

0058Therefore, in the semiconductor memory device according to the present embodiment, not only an area of the bit line contact region BCR, but also areas of the word line contact regions WCR1 and WCR2 can be reduced.

0059In addition, the word line contact CW may be formed in an inversely tapered shape when viewed from the Y direction as shown in <figref idref="DRAWINGS">FIG. 8</figref>, and may be formed in a forwardly tapered shape when viewed from the X direction as shown in <figref idref="DRAWINGS">FIG. 10</figref>.

0060Moreover, as shown in <figref idref="DRAWINGS">FIG. 8</figref>, the word line WL2 and the word line contact CW may be formed integrally.

0061In addition, a lower surface of the word line WL2 and a side surface in the X direction and lower surface of the word line contact region WCR1 or WCR2 may be covered by the barrier metal layer 251 as shown in <figref idref="DRAWINGS">FIG. 8</figref>, and an upper surface and side surface of the word line WL2 and a side surface in the Y direction of the word line contact CW may be covered by a nitride layer 248 as shown in <figref idref="DRAWINGS">FIG. 10</figref>.

0062Moreover, as shown in <figref idref="DRAWINGS">FIG. 10</figref>, a side surface in the X direction of the word line WL2 and a side surface in the X direction of the word line contact CW may be formed continuously.

0063[Method of Manufacturing According to First Embodiment]

0064Next, a method of manufacturing the semiconductor memory device according to the present embodiment will be described with reference to <figref idref="DRAWINGS">FIGS. 13 to 64</figref>. <figref idref="DRAWINGS">FIG. 13</figref> is a flowchart for explaining the same method of manufacturing.

0065First, step S101 will be described with reference to <figref idref="DRAWINGS">FIGS. 13 to 15</figref>. <figref idref="DRAWINGS">FIG. 14</figref> is a plan view for explaining step S101. <figref idref="DRAWINGS">FIG. 15</figref> is a cross-sectional view for explaining step S101, and shows a cross-section corresponding to A-A of <figref idref="DRAWINGS">FIG. 14</figref>.

0066As shown in <figref idref="DRAWINGS">FIGS. 13 to 15</figref>, in step S101, the lower wiring line layer 100 is formed. For example, first, the likes of a CMOS circuit or wiring line layer configuring the control circuit described with reference to <figref idref="DRAWINGS">FIG. 1</figref>, are formed on an unillustrated substrate. Next, an inter-layer insulating layer 111 is formed on this substrate, and a contact hole is formed in this inter-layer insulating layer 111. The contact hole is provided at a position corresponding to the bit line contact CB and the word line contact CW. Next, a barrier metal layer 112 and the conductive layer 113 are implanted on the inside of this contact hole. The inter-layer insulating layer 111 is configured from silicon oxide (SiO2), for example. The barrier metal layer 112 is configured from a conductive layer of the likes of titanium (Ti), for example. The conductive layer 113 is configured from a conductive layer of the likes of tungsten (W), for example.

0067Next, step S102 will be described with reference to <figref idref="DRAWINGS">FIGS. 13 and 16</figref>. <figref idref="DRAWINGS">FIG. 16</figref> is a cross-sectional view for explaining step S102.

0068As shown in <figref idref="DRAWINGS">FIGS. 13 and 16</figref>, in step S102, a layer forming the word line WL1 and a layer forming the memory cell MC1, are deposited.

0069For example, first, a barrier metal layer 211A and a conductive layer 212A that form the word line WL1, are sequentially deposited. The barrier metal layer 211A is configured from a conductive layer of the likes of titanium (Ti), for example. The conductive layer 212A is configured from a conductive layer of the likes of tungsten (W), for example.

0070Next, a barrier metal layer 221A, a metal layer 222A, an insulating layer 223A, an electrode layer 224A, a barrier metal layer 225A, and a conductive layer 226A that form the memory cell MC1, are sequentially deposited. The barrier metal layers 221A and 225A are configured from a conductive layer of the likes of titanium (Ti), for example. The metal layer 222A is configured from a metal such as silver (Ag) or copper (Cu), for example. The insulating layer 223A is configured from an insulating layer of the likes of silicon oxide (SiO2), for example. The electrode layer 224A is configured from a material such as tantalum silicon nitride (TaSiN), for example. The conductive layer 226A is configured from a conductive layer of the likes of tungsten (W), for example.

0071Next, step S103 will be described with reference to FIGS. 13, 17, and 18. <figref idref="DRAWINGS">FIG. 17</figref> is a plan view for explaining step S103. <figref idref="DRAWINGS">FIG. 18</figref> is a cross-sectional view for explaining step S103, and shows a cross-section corresponding to A-A of <figref idref="DRAWINGS">FIG. 17</figref>.

0072As shown in <figref idref="DRAWINGS">FIGS. 13, 17, and 18</figref>, in step S103, formation of the word line WL1 is performed. For example, each of layers forming the word line WL1 (barrier metal layer 211A and conductive layer 212A) and each of layers forming the memory cell MC1 (barrier metal layer 221A, metal layer 222A, insulating layer 223A, electrode layer 224A, barrier metal layer 225A, and conductive layer 226A) are divided in the Y direction along a pattern of the word line WL1. As a result of this step, the word line WL1 (barrier metal layer 211 and conductive layer 212) is formed.

0073Next, step S104 will be described with reference to <figref idref="DRAWINGS">FIGS. 13, 19, and 20</figref>. <figref idref="DRAWINGS">FIG. 19</figref> is a plan view for explaining step S104. <figref idref="DRAWINGS">FIG. 20</figref> is a cross-sectional view for explaining step S104, and shows a cross-section corresponding to A-A of <figref idref="DRAWINGS">FIG. 19</figref>.

0074As shown in <figref idref="DRAWINGS">FIGS. 13, 19, and 20</figref>, in step S104, the inter-layer insulating layer 228 is formed. For example, the nitride layer 227 is deposited on sidewalls in the Y direction of each of the layers forming the word lines WL1 (barrier metal layer 211 and conductive layer 212) and the memory cells MC1 (barrier metal layer 221A, metal layer 222A, insulating layer 223A, electrode layer 224A, barrier metal layer 225A, and conductive layer 226A) adjacent in the Y direction and on an upper surface of the inter-layer insulating layer 111. The nitride layer 227 is configured from silicon nitride (SiN), for example. Next, the inter-layer insulating layer 228 is implanted between the nitride layers 227. The inter-layer insulating layer 228 is configured from silicon oxide (SiO2), for example.

0075Next, step S105 will be described with reference to <figref idref="DRAWINGS">FIG. 13</figref> and <figref idref="DRAWINGS">FIGS. 21 to 26</figref>. <figref idref="DRAWINGS">FIGS. 21 and 25</figref> are plan views for explaining step S105. <figref idref="DRAWINGS">FIGS. 22 to 24</figref> are cross-sectional views for explaining step S105, and respectively show cross-sections corresponding to A-A through C-C of <figref idref="DRAWINGS">FIG. 21</figref>. Moreover, <figref idref="DRAWINGS">FIG. 26</figref> is a cross-sectional view for explaining step S105, and shows a cross-section corresponding to A-A of <figref idref="DRAWINGS">FIG. 25</figref>.

0076As shown in <figref idref="DRAWINGS">FIG. 13</figref> and <figref idref="DRAWINGS">FIGS. 21 to 26</figref>, in step S105, a trench Slit1 is formed in the inter-layer insulating layer 228. For example, first, as shown in <figref idref="DRAWINGS">FIGS. 21 to 24</figref>, masks 301, 302, and 303 covering the memory regions MR1 and MR2 are formed. Next, as shown in <figref idref="DRAWINGS">FIGS. 25 and 26</figref>, anisotropic etching such as RIE is performed using these masks 301, 302, and 303, and the trench Slit1 is formed. The trench Slit1 extends in the X direction along the bit line contact region BCR. Moreover, the inter-layer insulating layer 111, barrier metal layer 112, and conductive layer 113 of the lower wiring line layer 100 are exposed at a lower surface of the trench Slit1.

0077Next, step S106 will be described with reference to <figref idref="DRAWINGS">FIG. 13</figref> and <figref idref="DRAWINGS">FIGS. 27 to 29</figref>. <figref idref="DRAWINGS">FIGS. 27 to 29</figref> are cross-sectional views for explaining step S106.

0078As shown in <figref idref="DRAWINGS">FIG. 13</figref> and <figref idref="DRAWINGS">FIGS. 27 to 29</figref>, in step S106, a layer forming the bit line BL and bit line contact CB and a layer forming the memory cell MC2, are deposited.

0079For example, first, a barrier metal layer 231A and a conductive layer 232A that form the bit line BL and the bit line contact CB, are sequentially deposited. The barrier metal layer 231A is configured from a conductive layer of the likes of titanium (Ti), for example. The conductive layer 232A is configured from a conductive layer of the likes of tungsten (W), for example.

0080Now, as shown in <figref idref="DRAWINGS">FIGS. 27 and 29</figref>, the barrier metal layer 231A and conductive layer 232A cover upper surfaces of the conductive layer 226A and the inter-layer insulating layer 228. Moreover, the barrier metal layer 231A and conductive layer 232A are implanted also on the inside of the trench Slit1, and contact the inter-layer insulating layer 111, barrier metal layer 112, and conductive layer 113 of the lower wiring line layer 100 at the lower surface of the trench Slit1.

0081Next, a barrier metal layer 241A, an electrode layer 242A, an insulating layer 243A, a barrier metal layer 244A, a metal layer 245A, a barrier metal layer 246A, and a conductive layer 247A that form the memory cell MC2, are sequentially deposited. The barrier metal layers 241A, 244A, and 246A are configured from a conductive layer of the likes of titanium (Ti), for example. The electrode layer 242A is configured from a material such as tantalum silicon nitride (TaSiN), for example. The insulating layer 243A is configured from an insulating layer of the likes of silicon oxide (SiO2), for example. The metal layer 245A is configured from a metal such as silver (Ag) or copper (Cu), for example. The conductive layer 247A is configured from a conductive layer of the likes of tungsten (W), for example.

0082Next, step S107 will be described with reference to <figref idref="DRAWINGS">FIG. 13</figref> and <figref idref="DRAWINGS">FIGS. 30 to 46</figref>. <figref idref="DRAWINGS">FIGS. 30, 34, 39, and 44</figref> are plan views for explaining step S107. <figref idref="DRAWINGS">FIGS. 31 to 33</figref> are cross-sectional views for explaining step S107, and respectively show cross-sections corresponding to A-A through C-C of <figref idref="DRAWINGS">FIG. 30</figref>. <figref idref="DRAWINGS">FIGS. 35 to 38</figref> are cross-sectional views for explaining step S107, and respectively show cross-sections corresponding to A-A through C-C, and E-E of <figref idref="DRAWINGS">FIG. 34</figref>. <figref idref="DRAWINGS">FIGS. 40 to 43</figref> are cross-sectional views for explaining step S107, and respectively show cross-sections corresponding to A-A through C-C, and E-E of <figref idref="DRAWINGS">FIG. 39</figref>. <figref idref="DRAWINGS">FIGS. 45 and 46</figref> are cross-sectional views for explaining step S107, and respectively show cross-sections corresponding to C-C and E-E of <figref idref="DRAWINGS">FIG. 44</figref>.

0083As shown in <figref idref="DRAWINGS">FIG. 13</figref> and <figref idref="DRAWINGS">FIGS. 30 to 46</figref>, in step S107, formation of the memory cell MC1, the bit line BL, and the bit line contact CB, are performed.

0084For example, as shown in <figref idref="DRAWINGS">FIGS. 30 to 33</figref>, first, masks 311, 312, 313, and 314 are formed. The mask 314 positioned in an uppermost layer is formed in a line-and-space pattern along a pattern of the bit line BL. Moreover, the masks 311, 312, 313, and 314 are formed straddling the memory regions MR1 and MR2 and the bit line contact region BCR.

0085Next, as shown in <figref idref="DRAWINGS">FIGS. 34 to 38</figref>, the masks 311, 312, 313, and 314 are utilized, and each of layers forming the memory cell MC1 (barrier metal layer 221A, metal layer 222A, insulating layer 223A, electrode layer 224A, barrier metal layer 225A, and conductive layer 226A), each of layers forming the bit line BL (barrier metal layer 231A and conductive layer 232A), and each of layers forming the memory cell MC2 (barrier metal layer 241A, electrode layer 242A, insulating layer 243A, barrier metal layer 244A, metal layer 245A, barrier metal layer 246A, and conductive layer 247A) are divided in the X direction along the pattern of the bit line BL. As a result, the memory cell MC1 (barrier metal layer 221, metal layer 222, insulating layer 223, electrode layer 224, barrier metal layer 225, and conductive layer 226) and the bit line BL are formed.

0086Note that as shown in <figref idref="DRAWINGS">FIGS. 36 to 38</figref>, this step is performed such that the word line WL1 (barrier metal layer 211 and conductive layer 212) is not divided in the X direction. Therefore, at this time point, each of the layers forming the bit line BL (barrier metal layer 231A and conductive layer 232A) are not completely divided, and are formed continuously in the bit line contact region BCR.

0087Next, as shown in <figref idref="DRAWINGS">FIGS. 39 to 43</figref>, a mask 321 covering the memory regions MR1 and MR2 is formed.

0088Next, as shown in <figref idref="DRAWINGS">FIGS. 44 to 46</figref>, this mask 321 and the mask 311 are utilized to divide each of the layers forming the bit line BL (barrier metal layer 231A and conductive layer 232A), in the X direction. As a result, each of the layers forming the bit line BL (barrier metal layer 231A and conductive layer 232A) are completely divided in the X direction, and the bit line contact CB (barrier metal layer 231 and conductive layer 232) is formed.

0089Next, step S108 will be described with reference to <figref idref="DRAWINGS">FIG. 13</figref> and <figref idref="DRAWINGS">FIGS. 47 to 49</figref>. <figref idref="DRAWINGS">FIG. 47</figref> is a plan view for explaining step S108. <figref idref="DRAWINGS">FIGS. 48 and 49</figref> are cross-sectional views for explaining step S108, and respectively show cross-sections corresponding to B-B and C-C of <figref idref="DRAWINGS">FIG. 47</figref>.

0090As shown in <figref idref="DRAWINGS">FIG. 13</figref> and <figref idref="DRAWINGS">FIGS. 47 to 49</figref>, in step S108, an inter-layer insulating layer 262 is formed. For example, the nitride layer 261 is deposited on sidewalls in the X direction of each of the layers forming the memory cells MC1 (barrier metal layer 221, metal layer 222, insulating layer 223, electrode layer 224, barrier metal layer 225, and conductive layer 226), the bit lines BL and bit line contacts CB (barrier metal layer 231 and conductive layer 232), and the memory cells MC2 (barrier metal layer 241A, electrode layer 242A, insulating layer 243A, barrier metal layer 244A, metal layer 245A, barrier metal layer 246A, and conductive layer 247A) adjacent in the X direction and on the upper surface of the inter-layer insulating layer 111. The nitride layer 261 is configured from silicon nitride (SiN), for example. Next, the inter-layer insulating layer 262 is implanted between the nitride layers 261. The inter-layer insulating layer 262 is configured from silicon oxide (SiO2), for example.

0091Next, step S109 will be described with reference to <figref idref="DRAWINGS">FIGS. 13, 50, and 51</figref>. <figref idref="DRAWINGS">FIG. 50</figref> is a plan view for explaining step S109. <figref idref="DRAWINGS">FIG. 51</figref> is a cross-sectional view for explaining step S109, and shows a cross-section corresponding to B-B of <figref idref="DRAWINGS">FIG. 50</figref>.

0092As shown in <figref idref="DRAWINGS">FIGS. 13, 50, and 51</figref>, in step S109, a trench Slit2 is formed in the inter-layer insulating layer 262. The trench Slit2 extends in the Y direction along the word line contact regions WCR1 and WCR2. Moreover, the inter-layer insulating layer 111, barrier metal layer 112, and conductive layer 113 of the lower wiring line layer 100 are exposed at a lower surface of the trench Slit2. Note that the trench Slit2 may be formed by a similar method to that for the trench Slit1.

0093Next, step S110 will be described with reference to <figref idref="DRAWINGS">FIGS. 13, 52, and 53</figref>. <figref idref="DRAWINGS">FIG. 52</figref> is a cross-sectional view for explaining step S110.

0094As shown in <figref idref="DRAWINGS">FIGS. 13, 52, and 53</figref>, in step S110, a layer forming the word line WL2 and word line contact CW is deposited. For example, first, a barrier metal layer 251A and a conductive layer 252A that form the word line WL2 and word line contact CW, are sequentially deposited. The barrier metal layer 251A is configured from a conductive layer of the likes of titanium (Ti), for example. The conductive layer 252A is configured from a conductive layer of the likes of tungsten (W), for example.

0095Now, as shown in <figref idref="DRAWINGS">FIGS. 52 and 53</figref>, the barrier metal layer 251A and conductive layer 252A cover upper surfaces of the conductive layer 247A and the inter-layer insulating layer 262. Moreover, the barrier metal layer 251A and conductive layer 252A are implanted also on the inside of the trench Slit2, and contact the inter-layer insulating layer 111, barrier metal layer 112, and conductive layer 113 of the lower wiring line layer 100 at the lower surface of the trench Slit2.

0096Next, step S111 will be described with reference to <figref idref="DRAWINGS">FIG. 13</figref> and <figref idref="DRAWINGS">FIGS. 54 to 64</figref>. <figref idref="DRAWINGS">FIGS. 54, 56, 60, and 62</figref> are plan views for explaining step S111. <figref idref="DRAWINGS">FIG. 55</figref> is a cross-sectional view for explaining step S111, and shows a cross-section corresponding to A-A of <figref idref="DRAWINGS">FIG. 54</figref>. <figref idref="DRAWINGS">FIGS. 57 to 59</figref> are cross-sectional views for explaining step S111, and respectively show cross-sections corresponding to A-A, D-D, and F-F of <figref idref="DRAWINGS">FIG. 56</figref>. <figref idref="DRAWINGS">FIG. 61</figref> is a cross-sectional view for explaining step S111, and shows a cross-section corresponding to F-F of <figref idref="DRAWINGS">FIG. 60</figref>. <figref idref="DRAWINGS">FIGS. 63 and 64</figref> are cross-sectional views for explaining step S111, and respectively show cross-sections corresponding to D-D and F-F of <figref idref="DRAWINGS">FIG. 62</figref>.

0097As shown in <figref idref="DRAWINGS">FIG. 13</figref> and <figref idref="DRAWINGS">FIGS. 54 to 64</figref>, in step S111, formation of the memory cell MC2, the word line WL2, and the word line contact CW, are performed.

0098For example, as shown in <figref idref="DRAWINGS">FIGS. 54 and 55</figref>, first, a mask 331 is formed. The mask 331 is formed in a line-and-space pattern along a pattern of the word line WL2. Moreover, the mask 331 is formed straddling the memory regions MR1 and MR2 and the word line contact regions WCR1 and WCR2.

0099Next, as shown in <figref idref="DRAWINGS">FIGS. 56 to 59</figref>, the mask 331 is utilized, and each of layers forming the memory cell MC2 (barrier metal layer 241A, electrode layer 242A, insulating layer 243A, barrier metal layer 244A, metal layer 245A, barrier metal layer 246A, and conductive layer 247A) and each of layers forming the word line WL2 (barrier metal layer 251A and conductive layer 252A) are divided in the Y direction along the pattern of the word line WL2. As a result, the memory cell MC2 (barrier metal layer 241, electrode layer 242, insulating layer 243, barrier metal layer 244, metal layer 245, barrier metal layer 246, and conductive layer 247) and the word line WL2 are formed.

0100Note that as shown in <figref idref="DRAWINGS">FIGS. 58 and 59</figref>, this step is performed such that the bit line BL (barrier metal layer 231 and conductive layer 232) is not divided in the Y direction. Therefore, at this time point, each of the layers forming the word line WL2 (barrier metal layer 251A and conductive layer 252A) are not completely divided, and are formed continuously in the word line contact regions WCR1 and WCR2.

0101Next, as shown in <figref idref="DRAWINGS">FIGS. 60 and 61</figref>, a mask 341 covering the memory regions MR1 and MR2 and bit line contact region BCR, is formed.

0102Next, as shown in <figref idref="DRAWINGS">FIGS. 62 to 64</figref>, this mask 341 and the mask 331 are utilized to divide each of the layers forming the word line WL2 (barrier metal layer 251A and conductive layer 252A), in the Y direction. As a result, each of the layers forming the word line WL2 (barrier metal layer 251A and conductive layer 252A) are completely divided in the Y direction, and the word line contact CW (barrier metal layer 251 and conductive layer 252) is formed.

0103Subsequently, as shown in <figref idref="DRAWINGS">FIG. 13</figref> and <figref idref="DRAWINGS">FIGS. 6 to 12</figref>, in step S112, an inter-layer insulating layer 249 is formed. For example, a nitride layer 248 is deposited on sidewalls in the Y direction of the memory cells MC2 (barrier metal layer 241, electrode layer 242, insulating layer 243, barrier metal layer 244, metal layer 245, barrier metal layer 246, and conductive layer 247) and the word lines WL2 (barrier metal layer 251 and conductive layer 252) adjacent in the Y direction and on the upper surface of the inter-layer insulating layer 111. The nitride layer 248 is configured from silicon nitride (SiN), for example. Next, the inter-layer insulating layer 249 is implanted between the nitride layers 248. The inter-layer insulating layer 249 is configured from silicon oxide (SiO2), for example.

0104The above steps make it possible to manufacture the nonvolatile semiconductor memory device described with reference to <figref idref="DRAWINGS">FIGS. 6 to 12</figref>.

0105As a result of the method of manufacturing according to the present embodiment, as described with reference to <figref idref="DRAWINGS">FIGS. 27 and 28</figref>, the conductive layer 232A is deposited inside the trench Slit1 extending in the X direction and this is utilized to form the bit line contact CB, hence positions in the Y direction of the bit line contacts CB can be substantially matched. In addition, as a result of such a method, as described with reference to <figref idref="DRAWINGS">FIGS. 30 to 33</figref>, the masks 311 to 314 of the pattern corresponding to the bit line BL is formed and this is utilized to form the bit line BL and the bit line contact CB, hence a position in the X direction of the bit line BL and a position in the X direction of the bit line contact CB can be substantially matched.

0106Similarly, as a result of the method of manufacturing according to the present embodiment, as described with reference to <figref idref="DRAWINGS">FIG. 53</figref>, the conductive layer 252A is deposited inside the trench Slit2 extending in the Y direction and this is utilized to form the word line contact CW, hence positions in the X direction of the word line contacts CW can be substantially matched. In addition, as a result of such a method, as reference to <figref idref="DRAWINGS">FIGS. 54 and 55</figref>, the mask 331 of the pattern corresponding to the word line WL is formed and this is utilized to form the word line WL and the word line contact CW, hence a position in the Y direction of the word line WL and a position in the Y direction of the word line contact CW can be substantially matched.

0107Moreover, in the method of manufacturing according to the present embodiment, as described with reference to <figref idref="DRAWINGS">FIG. 25</figref>, for example, the trench Slit1 is formed such that the inter-layer insulating layer 111, barrier metal layer 112, and conductive layer 113 of the lower wiring line layer 100 are exposed at the lower surface of the trench Slit1. Such a mode makes it possible for positions of the bit line contacts CB and each of configurations of the lower wiring line layer 100 to be aligned by adjusting a position in the Y direction of the trench Slit1. Therefore, manufacturing can be performed more easily compared to when, for example, positions in the X direction and the Y direction must be aligned.

0108Note that when the nonvolatile semiconductor memory device is manufactured by the method of manufacturing according to the present embodiment, as shown in <figref idref="DRAWINGS">FIG. 7</figref>, the lower surface of the bit line BL and the side surface in the Y direction and lower surface of the bit line contact CB are sometimes covered by the barrier metal layer 231. In contrast, as shown in <figref idref="DRAWINGS">FIG. 9</figref>, the side surfaces in the X direction of the bit line BL and bit line contact CB are sometimes covered by the nitride layer 261.

0109Moreover, when the nonvolatile semiconductor memory device is manufactured by the method of manufacturing according to the present embodiment, as shown in <figref idref="DRAWINGS">FIG. 9</figref>, the side surface in the Y direction of the bit line BL and the side surface in the Y direction of the bit line contact CB are sometimes formed continuously.

0110Moreover, in the method of manufacturing according to the present embodiment, in step S107, as described with reference to <figref idref="DRAWINGS">FIGS. 39 to 43</figref>, the mask 321 covering the memory regions MR1 and MR2 is formed, and as described with reference to <figref idref="DRAWINGS">FIGS. 44 to 46</figref>, this mask 321 and the mask 311 are utilized to divide each of the layers forming the bit line BL, in the X direction. Therefore, as shown in <figref idref="DRAWINGS">FIG. 11</figref>, an end 228a in the Y direction of the inter-layer insulating layer 228 is resultantly positioned between the bit line contact CB and the word line WL1, at a position between the bit lines BL. Moreover, as shown in <figref idref="DRAWINGS">FIG. 11</figref>, when the nitride layer 261 and the inter-layer insulating layer 262 are formed in step S108, these nitride layer 261 and inter-layer insulating layer 262 resultantly contact the end 228a in the Y direction of the inter-layer insulating layer 228.

0111Moreover, as a result of the method of manufacturing according to the present embodiment, the word line contact CW is formed similarly to the bit line contact CB, and similar advantages can be displayed in manufacturing steps of the word line contact CW.

Other Embodiments

0112Note that in the present embodiment, the bit line contact CB and the word line contact CW had substantially similar configurations. However, it is also possible for different configurations to be adopted as the bit line contact CB or the word line contact CW, for example.

0113[Others]

0114While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.

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2022-07-14	Email NotificationEML_NTR	EML_NTR
2022-07-13	Issue Notification MailedAllowedWPIR	WPIR
2022-07-13	Workflow - Informational Disclosure Statement - FinishFIDS	FIDS
2022-07-12	Information Disclosure Statement (IDS) FiledM844	M844
2022-07-12	Request for Continued Examination (RCE)RCEX	RCEX
2022-07-12	Petition EnteredPET.	PET.
2022-07-12	Information Disclosure Statement (IDS) FiledWIDS	WIDS
2022-07-12	Workflow - Request for RCE - BeginBRCE	BRCE
2022-06-28	Dispatch to FDCD1935	D1935
2022-06-28	Application Is Considered Ready for IssuePILS	PILS
2022-06-27	Issue Fee Payment VerifiedN084	N084
2022-06-27	Issue Fee Payment ReceivedIFEE	IFEE
2022-03-31	Electronic ReviewELC_RVW	ELC_RVW
2022-03-31	Email NotificationEML_NTF	EML_NTF
2022-03-31	Mail Notice of AllowanceAllowedMN/=.	MN/=.
2022-03-28	Notice of Allowance Data Verification CompletedAllowedN/=.	N/=.
2022-03-10	Date Forwarded to ExaminerFWDX	FWDX
2022-03-08	Response after Non-Final ActionA...	A...
2021-12-16	Mail Post CardPST_CRD	PST_CRD
2021-12-08	Email NotificationEML_NTF	EML_NTF
2021-12-08	Mail Non-Final RejectionNon-final rejectionMCTNF	MCTNF
2021-12-04	Non-Final RejectionNon-final rejectionCTNF	CTNF
2021-12-04	Information Disclosure Statement consideredIDSC	IDSC
2021-12-01	Date Forwarded to ExaminerFWDX	FWDX
2021-11-30	Response to Election / Restriction FiledELC.	ELC.
2021-11-30	Miscellaneous Incoming LetterLET.	LET.
2021-10-09	Mail Post CardPST_CRD	PST_CRD
2021-10-01	Email NotificationEML_NTF	EML_NTF
2021-10-01	Mail Restriction RequirementMCTRS	MCTRS
2021-09-28	Restriction/Election RequirementCTRS	CTRS
2021-09-08	Email NotificationEML_NTR	EML_NTR
2021-09-08	Email NotificationEML_NTR	EML_NTR
2021-09-08	Filing Receipt - CorrectedFLRCPT.C	FLRCPT.C
2021-09-08	Change in Power of Attorney (May Include Associate POA)PA..	PA..
2020-07-17	Email NotificationEML_NTR	EML_NTR
2020-07-16	PG-Pub Issue NotificationPG-ISSUE	PG-ISSUE
2020-04-10	Email NotificationEML_NTR	EML_NTR
2020-04-10	Application ready for PDX access by participating foreign officesCCRDY	CCRDY
2020-04-10	Application Is Now CompleteCOMP	COMP
2020-04-10	Filing ReceiptFLRCPT.O	FLRCPT.O
2020-04-09	Case Docketed to Examiner in GAUDOCK	DOCK
2020-04-09	Application Dispatched from OIPEOIPE	OIPE
2020-04-09	FITF set to YES - revise initial settingFTFS	FTFS
2020-04-06	Cleared by OIPE CSRL194	L194
2020-04-01	Oath or Declaration Filed (Including Supplemental)C602	C602
2020-04-01	Information Disclosure Statement (IDS) FiledM844	M844
2020-04-01	Patent Term Adjustment - Ready for ExaminationPTA.RFE	PTA.RFE
2020-04-01	PTO/SB/69-Authorize EPO Access to Search ResultsSREXR141	SREXR141
2020-04-01	Applicants have given acceptable permission for participating foreignAPPERMS	APPERMS
2020-04-01	IFW Scan & PACR Auto Security ReviewSCAN	SCAN
2020-04-01	Information Disclosure Statement (IDS) FiledWIDS	WIDS
2020-04-01	Entity Status Set To Undiscounted (Initial Default Setting or Status Change)BIG.	BIG.
2020-04-01	Initial Exam Team nnIEXX	IEXX

14 legal events, as the office reported them to INPADOC

Over the term

Point at a mark for the event

Events

Legal events, newest first
	Event	Code
2022-12-21	Information on status: patent grantGrantedPATENTED CASESTCF	STCF
2022-12-15	Information on status: patent application and granting procedure in generalPUBLICATIONS -- ISSUE FEE PAYMENT VERIFIEDSTPP	STPP
2022-11-15	Information on status: patent application and granting procedure in generalPUBLICATIONS -- ISSUE FEE PAYMENT RECEIVEDSTPP	STPP
2022-08-15	Information on status: patent application and granting procedure in generalNOTICE OF ALLOWANCE MAILED -- APPLICATION RECEIVED IN OFFICE OF PUBLICATIONSSTPP	STPP
2022-07-13	Information on status: patent grantGrantedPATENTED CASESTCF	STCF
2022-03-29	Information on status: patent application and granting procedure in generalNOTICE OF ALLOWANCE MAILED -- APPLICATION RECEIVED IN OFFICE OF PUBLICATIONSSTPP	STPP
2022-03-10	Information on status: patent application and granting procedure in generalRESPONSE TO NON-FINAL OFFICE ACTION ENTERED AND FORWARDED TO EXAMINERSTPP	STPP
2021-12-06	Information on status: patent application and granting procedure in generalNON FINAL ACTION MAILEDSTPP	STPP
2021-11-30	Information on status: patent application and granting procedure in generalRESPONSE TO NON-FINAL OFFICE ACTION ENTERED AND FORWARDED TO EXAMINERSTPP	STPP
2021-09-29	Information on status: patent application and granting procedure in generalNON FINAL ACTION MAILEDSTPP	STPP
2021-08-16	AssignmentAS	AS
2021-08-16	AssignmentAS	AS
2020-04-09	Information on status: patent application and granting procedure in generalDOCKETED NEW CASE - READY FOR EXAMINATIONSTPP	STPP
2020-04-01	Fee payment procedureENTITY STATUS SET TO UNDISCOUNTED (ORIGINAL EVENT CODE: BIG.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITYFEPP	FEPP

Semiconductor memory device having variable resistance elements provided between wiring lines

Summary by NHIP

Claim Score by NHIP

Abstract

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BACKGROUND

BRIEF DESCRIPTION OF THE DRAWINGS

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Members11

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Titles

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Abstract

Term

CROSS-REFERENCE TO RELATED APPLICATIONS

FIELD

BACKGROUND

BRIEF DESCRIPTION OF THE DRAWINGS

DETAILED DESCRIPTION

Members11

Over time

Transactions

Over the term

Events

Numbers

Titles

Patent term adjustment

Classification